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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / sound / pci / hda / hda_intel.c
bloba5dc7464e3b423b5015d461870037873a61456ef
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #ifdef CONFIG_X86
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
53 #endif
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include <linux/vgaarb.h>
57 #include <linux/vga_switcheroo.h>
58 #include "hda_codec.h"
59
60
61 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
62 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
63 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
64 static char *model[SNDRV_CARDS];
65 static int position_fix[SNDRV_CARDS];
66 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
67 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
68 static int probe_only[SNDRV_CARDS];
69 static bool single_cmd;
70 static int enable_msi = -1;
71 #ifdef CONFIG_SND_HDA_PATCH_LOADER
72 static char *patch[SNDRV_CARDS];
73 #endif
74 #ifdef CONFIG_SND_HDA_INPUT_BEEP
75 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
76 CONFIG_SND_HDA_INPUT_BEEP_MODE};
77 #endif
78
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
85 module_param_array(model, charp, NULL, 0444);
86 MODULE_PARM_DESC(model, "Use the given board model.");
87 module_param_array(position_fix, int, NULL, 0444);
88 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
89 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
90 module_param_array(bdl_pos_adj, int, NULL, 0644);
91 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
92 module_param_array(probe_mask, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
94 module_param_array(probe_only, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
96 module_param(single_cmd, bool, 0444);
97 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
98 "(for debugging only).");
99 module_param(enable_msi, bint, 0444);
100 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
101 #ifdef CONFIG_SND_HDA_PATCH_LOADER
102 module_param_array(patch, charp, NULL, 0444);
103 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
104 #endif
105 #ifdef CONFIG_SND_HDA_INPUT_BEEP
106 module_param_array(beep_mode, bool, NULL, 0444);
107 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
108 "(0=off, 1=on) (default=1).");
109 #endif
110
111 #ifdef CONFIG_SND_HDA_POWER_SAVE
112 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
113 module_param(power_save, int, 0644);
114 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
115 "(in second, 0 = disable).");
116
117 /* reset the HD-audio controller in power save mode.
118 * this may give more power-saving, but will take longer time to
119 * wake up.
120 */
121 static bool power_save_controller = 1;
122 module_param(power_save_controller, bool, 0644);
123 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
124 #endif
125
126 static int align_buffer_size = -1;
127 module_param(align_buffer_size, bint, 0644);
128 MODULE_PARM_DESC(align_buffer_size,
129 "Force buffer and period sizes to be multiple of 128 bytes.");
130
131 #ifdef CONFIG_X86
132 static bool hda_snoop = true;
133 module_param_named(snoop, hda_snoop, bool, 0444);
134 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
135 #define azx_snoop(chip) (chip)->snoop
136 #else
137 #define hda_snoop true
138 #define azx_snoop(chip) true
139 #endif
140
141
142 MODULE_LICENSE("GPL");
143 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
144 "{Intel, ICH6M},"
145 "{Intel, ICH7},"
146 "{Intel, ESB2},"
147 "{Intel, ICH8},"
148 "{Intel, ICH9},"
149 "{Intel, ICH10},"
150 "{Intel, PCH},"
151 "{Intel, CPT},"
152 "{Intel, PPT},"
153 "{Intel, LPT},"
154 "{Intel, LPT_LP},"
155 "{Intel, HPT},"
156 "{Intel, PBG},"
157 "{Intel, SCH},"
158 "{ATI, SB450},"
159 "{ATI, SB600},"
160 "{ATI, RS600},"
161 "{ATI, RS690},"
162 "{ATI, RS780},"
163 "{ATI, R600},"
164 "{ATI, RV630},"
165 "{ATI, RV610},"
166 "{ATI, RV670},"
167 "{ATI, RV635},"
168 "{ATI, RV620},"
169 "{ATI, RV770},"
170 "{VIA, VT8251},"
171 "{VIA, VT8237A},"
172 "{SiS, SIS966},"
173 "{ULI, M5461}}");
174 MODULE_DESCRIPTION("Intel HDA driver");
175
176 #ifdef CONFIG_SND_VERBOSE_PRINTK
177 #define SFX /* nop */
178 #else
179 #define SFX "hda-intel: "
180 #endif
181
182 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
183 #ifdef CONFIG_SND_HDA_CODEC_HDMI
184 #define SUPPORT_VGA_SWITCHEROO
185 #endif
186 #endif
187
188
189 /*
190 * registers
191 */
192 #define ICH6_REG_GCAP 0x00
193 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
194 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
195 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
196 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
197 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
198 #define ICH6_REG_VMIN 0x02
199 #define ICH6_REG_VMAJ 0x03
200 #define ICH6_REG_OUTPAY 0x04
201 #define ICH6_REG_INPAY 0x06
202 #define ICH6_REG_GCTL 0x08
203 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
204 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
205 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
206 #define ICH6_REG_WAKEEN 0x0c
207 #define ICH6_REG_STATESTS 0x0e
208 #define ICH6_REG_GSTS 0x10
209 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
210 #define ICH6_REG_INTCTL 0x20
211 #define ICH6_REG_INTSTS 0x24
212 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
213 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
214 #define ICH6_REG_SSYNC 0x38
215 #define ICH6_REG_CORBLBASE 0x40
216 #define ICH6_REG_CORBUBASE 0x44
217 #define ICH6_REG_CORBWP 0x48
218 #define ICH6_REG_CORBRP 0x4a
219 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
220 #define ICH6_REG_CORBCTL 0x4c
221 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
222 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
223 #define ICH6_REG_CORBSTS 0x4d
224 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
225 #define ICH6_REG_CORBSIZE 0x4e
226
227 #define ICH6_REG_RIRBLBASE 0x50
228 #define ICH6_REG_RIRBUBASE 0x54
229 #define ICH6_REG_RIRBWP 0x58
230 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
231 #define ICH6_REG_RINTCNT 0x5a
232 #define ICH6_REG_RIRBCTL 0x5c
233 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
234 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
235 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
236 #define ICH6_REG_RIRBSTS 0x5d
237 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
238 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
239 #define ICH6_REG_RIRBSIZE 0x5e
240
241 #define ICH6_REG_IC 0x60
242 #define ICH6_REG_IR 0x64
243 #define ICH6_REG_IRS 0x68
244 #define ICH6_IRS_VALID (1<<1)
245 #define ICH6_IRS_BUSY (1<<0)
246
247 #define ICH6_REG_DPLBASE 0x70
248 #define ICH6_REG_DPUBASE 0x74
249 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
250
251 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
252 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
253
254 /* stream register offsets from stream base */
255 #define ICH6_REG_SD_CTL 0x00
256 #define ICH6_REG_SD_STS 0x03
257 #define ICH6_REG_SD_LPIB 0x04
258 #define ICH6_REG_SD_CBL 0x08
259 #define ICH6_REG_SD_LVI 0x0c
260 #define ICH6_REG_SD_FIFOW 0x0e
261 #define ICH6_REG_SD_FIFOSIZE 0x10
262 #define ICH6_REG_SD_FORMAT 0x12
263 #define ICH6_REG_SD_BDLPL 0x18
264 #define ICH6_REG_SD_BDLPU 0x1c
265
266 /* PCI space */
267 #define ICH6_PCIREG_TCSEL 0x44
268
269 /*
270 * other constants
271 */
272
273 /* max number of SDs */
274 /* ICH, ATI and VIA have 4 playback and 4 capture */
275 #define ICH6_NUM_CAPTURE 4
276 #define ICH6_NUM_PLAYBACK 4
277
278 /* ULI has 6 playback and 5 capture */
279 #define ULI_NUM_CAPTURE 5
280 #define ULI_NUM_PLAYBACK 6
281
282 /* ATI HDMI has 1 playback and 0 capture */
283 #define ATIHDMI_NUM_CAPTURE 0
284 #define ATIHDMI_NUM_PLAYBACK 1
285
286 /* TERA has 4 playback and 3 capture */
287 #define TERA_NUM_CAPTURE 3
288 #define TERA_NUM_PLAYBACK 4
289
290 /* this number is statically defined for simplicity */
291 #define MAX_AZX_DEV 16
292
293 /* max number of fragments - we may use more if allocating more pages for BDL */
294 #define BDL_SIZE 4096
295 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
296 #define AZX_MAX_FRAG 32
297 /* max buffer size - no h/w limit, you can increase as you like */
298 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
299
300 /* RIRB int mask: overrun[2], response[0] */
301 #define RIRB_INT_RESPONSE 0x01
302 #define RIRB_INT_OVERRUN 0x04
303 #define RIRB_INT_MASK 0x05
304
305 /* STATESTS int mask: S3,SD2,SD1,SD0 */
306 #define AZX_MAX_CODECS 8
307 #define AZX_DEFAULT_CODECS 4
308 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
309
310 /* SD_CTL bits */
311 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
312 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
313 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
314 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
315 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
316 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
317 #define SD_CTL_STREAM_TAG_SHIFT 20
318
319 /* SD_CTL and SD_STS */
320 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
321 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
322 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
323 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
324 SD_INT_COMPLETE)
325
326 /* SD_STS */
327 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
328
329 /* INTCTL and INTSTS */
330 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
331 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
332 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
333
334 /* below are so far hardcoded - should read registers in future */
335 #define ICH6_MAX_CORB_ENTRIES 256
336 #define ICH6_MAX_RIRB_ENTRIES 256
337
338 /* position fix mode */
339 enum {
340 POS_FIX_AUTO,
341 POS_FIX_LPIB,
342 POS_FIX_POSBUF,
343 POS_FIX_VIACOMBO,
344 POS_FIX_COMBO,
345 };
346
347 /* Defines for ATI HD Audio support in SB450 south bridge */
348 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
349 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
350
351 /* Defines for Nvidia HDA support */
352 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
353 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
354 #define NVIDIA_HDA_ISTRM_COH 0x4d
355 #define NVIDIA_HDA_OSTRM_COH 0x4c
356 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
357
358 /* Defines for Intel SCH HDA snoop control */
359 #define INTEL_SCH_HDA_DEVC 0x78
360 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
361
362 /* Define IN stream 0 FIFO size offset in VIA controller */
363 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
364 /* Define VIA HD Audio Device ID*/
365 #define VIA_HDAC_DEVICE_ID 0x3288
366
367 /* HD Audio class code */
368 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
369
370 /*
371 */
372
373 struct azx_dev {
374 struct snd_dma_buffer bdl; /* BDL buffer */
375 u32 *posbuf; /* position buffer pointer */
376
377 unsigned int bufsize; /* size of the play buffer in bytes */
378 unsigned int period_bytes; /* size of the period in bytes */
379 unsigned int frags; /* number for period in the play buffer */
380 unsigned int fifo_size; /* FIFO size */
381 unsigned long start_wallclk; /* start + minimum wallclk */
382 unsigned long period_wallclk; /* wallclk for period */
383
384 void __iomem *sd_addr; /* stream descriptor pointer */
385
386 u32 sd_int_sta_mask; /* stream int status mask */
387
388 /* pcm support */
389 struct snd_pcm_substream *substream; /* assigned substream,
390 * set in PCM open
391 */
392 unsigned int format_val; /* format value to be set in the
393 * controller and the codec
394 */
395 unsigned char stream_tag; /* assigned stream */
396 unsigned char index; /* stream index */
397 int assigned_key; /* last device# key assigned to */
398
399 unsigned int opened :1;
400 unsigned int running :1;
401 unsigned int irq_pending :1;
402 /*
403 * For VIA:
404 * A flag to ensure DMA position is 0
405 * when link position is not greater than FIFO size
406 */
407 unsigned int insufficient :1;
408 unsigned int wc_marked:1;
409 };
410
411 /* CORB/RIRB */
412 struct azx_rb {
413 u32 *buf; /* CORB/RIRB buffer
414 * Each CORB entry is 4byte, RIRB is 8byte
415 */
416 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
417 /* for RIRB */
418 unsigned short rp, wp; /* read/write pointers */
419 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
420 u32 res[AZX_MAX_CODECS]; /* last read value */
421 };
422
423 struct azx_pcm {
424 struct azx *chip;
425 struct snd_pcm *pcm;
426 struct hda_codec *codec;
427 struct hda_pcm_stream *hinfo[2];
428 struct list_head list;
429 };
430
431 struct azx {
432 struct snd_card *card;
433 struct pci_dev *pci;
434 int dev_index;
435
436 /* chip type specific */
437 int driver_type;
438 unsigned int driver_caps;
439 int playback_streams;
440 int playback_index_offset;
441 int capture_streams;
442 int capture_index_offset;
443 int num_streams;
444
445 /* pci resources */
446 unsigned long addr;
447 void __iomem *remap_addr;
448 int irq;
449
450 /* locks */
451 spinlock_t reg_lock;
452 struct mutex open_mutex;
453
454 /* streams (x num_streams) */
455 struct azx_dev *azx_dev;
456
457 /* PCM */
458 struct list_head pcm_list; /* azx_pcm list */
459
460 /* HD codec */
461 unsigned short codec_mask;
462 int codec_probe_mask; /* copied from probe_mask option */
463 struct hda_bus *bus;
464 unsigned int beep_mode;
465
466 /* CORB/RIRB */
467 struct azx_rb corb;
468 struct azx_rb rirb;
469
470 /* CORB/RIRB and position buffers */
471 struct snd_dma_buffer rb;
472 struct snd_dma_buffer posbuf;
473
474 /* flags */
475 int position_fix[2]; /* for both playback/capture streams */
476 int poll_count;
477 unsigned int running :1;
478 unsigned int initialized :1;
479 unsigned int single_cmd :1;
480 unsigned int polling_mode :1;
481 unsigned int msi :1;
482 unsigned int irq_pending_warned :1;
483 unsigned int probing :1; /* codec probing phase */
484 unsigned int snoop:1;
485 unsigned int align_buffer_size:1;
486 unsigned int region_requested:1;
487
488 /* VGA-switcheroo setup */
489 unsigned int use_vga_switcheroo:1;
490 unsigned int vga_switcheroo_registered:1;
491 unsigned int init_failed:1; /* delayed init failed */
492 unsigned int disabled:1; /* disabled by VGA-switcher */
493
494 /* for debugging */
495 unsigned int last_cmd[AZX_MAX_CODECS];
496
497 /* for pending irqs */
498 struct work_struct irq_pending_work;
499
500 /* reboot notifier (for mysterious hangup problem at power-down) */
501 struct notifier_block reboot_notifier;
502 };
503
504 /* driver types */
505 enum {
506 AZX_DRIVER_ICH,
507 AZX_DRIVER_PCH,
508 AZX_DRIVER_SCH,
509 AZX_DRIVER_ATI,
510 AZX_DRIVER_ATIHDMI,
511 AZX_DRIVER_ATIHDMI_NS,
512 AZX_DRIVER_VIA,
513 AZX_DRIVER_SIS,
514 AZX_DRIVER_ULI,
515 AZX_DRIVER_NVIDIA,
516 AZX_DRIVER_TERA,
517 AZX_DRIVER_CTX,
518 AZX_DRIVER_CTHDA,
519 AZX_DRIVER_GENERIC,
520 AZX_NUM_DRIVERS, /* keep this as last entry */
521 };
522
523 /* driver quirks (capabilities) */
524 /* bits 0-7 are used for indicating driver type */
525 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
526 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
527 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
528 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
529 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
530 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
531 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
532 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
533 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
534 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
535 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
536 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
537 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
538 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
539 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
540 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
541 #define AZX_DCAPS_POSFIX_COMBO (1 << 24) /* Use COMBO as default */
542 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
543
544 /* quirks for ATI SB / AMD Hudson */
545 #define AZX_DCAPS_PRESET_ATI_SB \
546 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
547 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
548
549 /* quirks for ATI/AMD HDMI */
550 #define AZX_DCAPS_PRESET_ATI_HDMI \
551 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
552
553 /* quirks for Nvidia */
554 #define AZX_DCAPS_PRESET_NVIDIA \
555 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
556 AZX_DCAPS_ALIGN_BUFSIZE)
557
558 #define AZX_DCAPS_PRESET_CTHDA \
559 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
560
561 /*
562 * VGA-switcher support
563 */
564 #ifdef SUPPORT_VGA_SWITCHEROO
565 #define DELAYED_INIT_MARK
566 #define DELAYED_INITDATA_MARK
567 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
568 #else
569 #define DELAYED_INIT_MARK __devinit
570 #define DELAYED_INITDATA_MARK __devinitdata
571 #define use_vga_switcheroo(chip) 0
572 #endif
573
574 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
575 [AZX_DRIVER_ICH] = "HDA Intel",
576 [AZX_DRIVER_PCH] = "HDA Intel PCH",
577 [AZX_DRIVER_SCH] = "HDA Intel MID",
578 [AZX_DRIVER_ATI] = "HDA ATI SB",
579 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
580 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
581 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
582 [AZX_DRIVER_SIS] = "HDA SIS966",
583 [AZX_DRIVER_ULI] = "HDA ULI M5461",
584 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
585 [AZX_DRIVER_TERA] = "HDA Teradici",
586 [AZX_DRIVER_CTX] = "HDA Creative",
587 [AZX_DRIVER_CTHDA] = "HDA Creative",
588 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
589 };
590
591 /*
592 * macros for easy use
593 */
594 #define azx_writel(chip,reg,value) \
595 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
596 #define azx_readl(chip,reg) \
597 readl((chip)->remap_addr + ICH6_REG_##reg)
598 #define azx_writew(chip,reg,value) \
599 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
600 #define azx_readw(chip,reg) \
601 readw((chip)->remap_addr + ICH6_REG_##reg)
602 #define azx_writeb(chip,reg,value) \
603 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
604 #define azx_readb(chip,reg) \
605 readb((chip)->remap_addr + ICH6_REG_##reg)
606
607 #define azx_sd_writel(dev,reg,value) \
608 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
609 #define azx_sd_readl(dev,reg) \
610 readl((dev)->sd_addr + ICH6_REG_##reg)
611 #define azx_sd_writew(dev,reg,value) \
612 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
613 #define azx_sd_readw(dev,reg) \
614 readw((dev)->sd_addr + ICH6_REG_##reg)
615 #define azx_sd_writeb(dev,reg,value) \
616 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
617 #define azx_sd_readb(dev,reg) \
618 readb((dev)->sd_addr + ICH6_REG_##reg)
619
620 /* for pcm support */
621 #define get_azx_dev(substream) (substream->runtime->private_data)
622
623 #ifdef CONFIG_X86
624 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
625 {
626 if (azx_snoop(chip))
627 return;
628 if (addr && size) {
629 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
630 if (on)
631 set_memory_wc((unsigned long)addr, pages);
632 else
633 set_memory_wb((unsigned long)addr, pages);
634 }
635 }
636
637 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
638 bool on)
639 {
640 __mark_pages_wc(chip, buf->area, buf->bytes, on);
641 }
642 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
643 struct snd_pcm_runtime *runtime, bool on)
644 {
645 if (azx_dev->wc_marked != on) {
646 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
647 azx_dev->wc_marked = on;
648 }
649 }
650 #else
651 /* NOP for other archs */
652 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
653 bool on)
654 {
655 }
656 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
657 struct snd_pcm_runtime *runtime, bool on)
658 {
659 }
660 #endif
661
662 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
663 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
664 /*
665 * Interface for HD codec
666 */
667
668 /*
669 * CORB / RIRB interface
670 */
671 static int azx_alloc_cmd_io(struct azx *chip)
672 {
673 int err;
674
675 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
676 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
677 snd_dma_pci_data(chip->pci),
678 PAGE_SIZE, &chip->rb);
679 if (err < 0) {
680 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
681 return err;
682 }
683 mark_pages_wc(chip, &chip->rb, true);
684 return 0;
685 }
686
687 static void azx_init_cmd_io(struct azx *chip)
688 {
689 spin_lock_irq(&chip->reg_lock);
690 /* CORB set up */
691 chip->corb.addr = chip->rb.addr;
692 chip->corb.buf = (u32 *)chip->rb.area;
693 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
694 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
695
696 /* set the corb size to 256 entries (ULI requires explicitly) */
697 azx_writeb(chip, CORBSIZE, 0x02);
698 /* set the corb write pointer to 0 */
699 azx_writew(chip, CORBWP, 0);
700 /* reset the corb hw read pointer */
701 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
702 /* enable corb dma */
703 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
704
705 /* RIRB set up */
706 chip->rirb.addr = chip->rb.addr + 2048;
707 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
708 chip->rirb.wp = chip->rirb.rp = 0;
709 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
710 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
711 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
712
713 /* set the rirb size to 256 entries (ULI requires explicitly) */
714 azx_writeb(chip, RIRBSIZE, 0x02);
715 /* reset the rirb hw write pointer */
716 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
717 /* set N=1, get RIRB response interrupt for new entry */
718 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
719 azx_writew(chip, RINTCNT, 0xc0);
720 else
721 azx_writew(chip, RINTCNT, 1);
722 /* enable rirb dma and response irq */
723 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
724 spin_unlock_irq(&chip->reg_lock);
725 }
726
727 static void azx_free_cmd_io(struct azx *chip)
728 {
729 spin_lock_irq(&chip->reg_lock);
730 /* disable ringbuffer DMAs */
731 azx_writeb(chip, RIRBCTL, 0);
732 azx_writeb(chip, CORBCTL, 0);
733 spin_unlock_irq(&chip->reg_lock);
734 }
735
736 static unsigned int azx_command_addr(u32 cmd)
737 {
738 unsigned int addr = cmd >> 28;
739
740 if (addr >= AZX_MAX_CODECS) {
741 snd_BUG();
742 addr = 0;
743 }
744
745 return addr;
746 }
747
748 static unsigned int azx_response_addr(u32 res)
749 {
750 unsigned int addr = res & 0xf;
751
752 if (addr >= AZX_MAX_CODECS) {
753 snd_BUG();
754 addr = 0;
755 }
756
757 return addr;
758 }
759
760 /* send a command */
761 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
762 {
763 struct azx *chip = bus->private_data;
764 unsigned int addr = azx_command_addr(val);
765 unsigned int wp;
766
767 spin_lock_irq(&chip->reg_lock);
768
769 /* add command to corb */
770 wp = azx_readb(chip, CORBWP);
771 wp++;
772 wp %= ICH6_MAX_CORB_ENTRIES;
773
774 chip->rirb.cmds[addr]++;
775 chip->corb.buf[wp] = cpu_to_le32(val);
776 azx_writel(chip, CORBWP, wp);
777
778 spin_unlock_irq(&chip->reg_lock);
779
780 return 0;
781 }
782
783 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
784
785 /* retrieve RIRB entry - called from interrupt handler */
786 static void azx_update_rirb(struct azx *chip)
787 {
788 unsigned int rp, wp;
789 unsigned int addr;
790 u32 res, res_ex;
791
792 wp = azx_readb(chip, RIRBWP);
793 if (wp == chip->rirb.wp)
794 return;
795 chip->rirb.wp = wp;
796
797 while (chip->rirb.rp != wp) {
798 chip->rirb.rp++;
799 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
800
801 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
802 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
803 res = le32_to_cpu(chip->rirb.buf[rp]);
804 addr = azx_response_addr(res_ex);
805 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
806 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
807 else if (chip->rirb.cmds[addr]) {
808 chip->rirb.res[addr] = res;
809 smp_wmb();
810 chip->rirb.cmds[addr]--;
811 } else
812 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
813 "last cmd=%#08x\n",
814 res, res_ex,
815 chip->last_cmd[addr]);
816 }
817 }
818
819 /* receive a response */
820 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
821 unsigned int addr)
822 {
823 struct azx *chip = bus->private_data;
824 unsigned long timeout;
825 unsigned long loopcounter;
826 int do_poll = 0;
827
828 again:
829 timeout = jiffies + msecs_to_jiffies(1000);
830
831 for (loopcounter = 0;; loopcounter++) {
832 if (chip->polling_mode || do_poll) {
833 spin_lock_irq(&chip->reg_lock);
834 azx_update_rirb(chip);
835 spin_unlock_irq(&chip->reg_lock);
836 }
837 if (!chip->rirb.cmds[addr]) {
838 smp_rmb();
839 bus->rirb_error = 0;
840
841 if (!do_poll)
842 chip->poll_count = 0;
843 return chip->rirb.res[addr]; /* the last value */
844 }
845 if (time_after(jiffies, timeout))
846 break;
847 if (bus->needs_damn_long_delay || loopcounter > 3000)
848 msleep(2); /* temporary workaround */
849 else {
850 udelay(10);
851 cond_resched();
852 }
853 }
854
855 if (!chip->polling_mode && chip->poll_count < 2) {
856 snd_printdd(SFX "azx_get_response timeout, "
857 "polling the codec once: last cmd=0x%08x\n",
858 chip->last_cmd[addr]);
859 do_poll = 1;
860 chip->poll_count++;
861 goto again;
862 }
863
864
865 if (!chip->polling_mode) {
866 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
867 "switching to polling mode: last cmd=0x%08x\n",
868 chip->last_cmd[addr]);
869 chip->polling_mode = 1;
870 goto again;
871 }
872
873 if (chip->msi) {
874 snd_printk(KERN_WARNING SFX "No response from codec, "
875 "disabling MSI: last cmd=0x%08x\n",
876 chip->last_cmd[addr]);
877 free_irq(chip->irq, chip);
878 chip->irq = -1;
879 pci_disable_msi(chip->pci);
880 chip->msi = 0;
881 if (azx_acquire_irq(chip, 1) < 0) {
882 bus->rirb_error = 1;
883 return -1;
884 }
885 goto again;
886 }
887
888 if (chip->probing) {
889 /* If this critical timeout happens during the codec probing
890 * phase, this is likely an access to a non-existing codec
891 * slot. Better to return an error and reset the system.
892 */
893 return -1;
894 }
895
896 /* a fatal communication error; need either to reset or to fallback
897 * to the single_cmd mode
898 */
899 bus->rirb_error = 1;
900 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
901 bus->response_reset = 1;
902 return -1; /* give a chance to retry */
903 }
904
905 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
906 "switching to single_cmd mode: last cmd=0x%08x\n",
907 chip->last_cmd[addr]);
908 chip->single_cmd = 1;
909 bus->response_reset = 0;
910 /* release CORB/RIRB */
911 azx_free_cmd_io(chip);
912 /* disable unsolicited responses */
913 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
914 return -1;
915 }
916
917 /*
918 * Use the single immediate command instead of CORB/RIRB for simplicity
919 *
920 * Note: according to Intel, this is not preferred use. The command was
921 * intended for the BIOS only, and may get confused with unsolicited
922 * responses. So, we shouldn't use it for normal operation from the
923 * driver.
924 * I left the codes, however, for debugging/testing purposes.
925 */
926
927 /* receive a response */
928 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
929 {
930 int timeout = 50;
931
932 while (timeout--) {
933 /* check IRV busy bit */
934 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
935 /* reuse rirb.res as the response return value */
936 chip->rirb.res[addr] = azx_readl(chip, IR);
937 return 0;
938 }
939 udelay(1);
940 }
941 if (printk_ratelimit())
942 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
943 azx_readw(chip, IRS));
944 chip->rirb.res[addr] = -1;
945 return -EIO;
946 }
947
948 /* send a command */
949 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
950 {
951 struct azx *chip = bus->private_data;
952 unsigned int addr = azx_command_addr(val);
953 int timeout = 50;
954
955 bus->rirb_error = 0;
956 while (timeout--) {
957 /* check ICB busy bit */
958 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
959 /* Clear IRV valid bit */
960 azx_writew(chip, IRS, azx_readw(chip, IRS) |
961 ICH6_IRS_VALID);
962 azx_writel(chip, IC, val);
963 azx_writew(chip, IRS, azx_readw(chip, IRS) |
964 ICH6_IRS_BUSY);
965 return azx_single_wait_for_response(chip, addr);
966 }
967 udelay(1);
968 }
969 if (printk_ratelimit())
970 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
971 azx_readw(chip, IRS), val);
972 return -EIO;
973 }
974
975 /* receive a response */
976 static unsigned int azx_single_get_response(struct hda_bus *bus,
977 unsigned int addr)
978 {
979 struct azx *chip = bus->private_data;
980 return chip->rirb.res[addr];
981 }
982
983 /*
984 * The below are the main callbacks from hda_codec.
985 *
986 * They are just the skeleton to call sub-callbacks according to the
987 * current setting of chip->single_cmd.
988 */
989
990 /* send a command */
991 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
992 {
993 struct azx *chip = bus->private_data;
994
995 if (chip->disabled)
996 return 0;
997 chip->last_cmd[azx_command_addr(val)] = val;
998 if (chip->single_cmd)
999 return azx_single_send_cmd(bus, val);
1000 else
1001 return azx_corb_send_cmd(bus, val);
1002 }
1003
1004 /* get a response */
1005 static unsigned int azx_get_response(struct hda_bus *bus,
1006 unsigned int addr)
1007 {
1008 struct azx *chip = bus->private_data;
1009 if (chip->disabled)
1010 return 0;
1011 if (chip->single_cmd)
1012 return azx_single_get_response(bus, addr);
1013 else
1014 return azx_rirb_get_response(bus, addr);
1015 }
1016
1017 #ifdef CONFIG_SND_HDA_POWER_SAVE
1018 static void azx_power_notify(struct hda_bus *bus);
1019 #endif
1020
1021 /* reset codec link */
1022 static int azx_reset(struct azx *chip, int full_reset)
1023 {
1024 int count;
1025
1026 if (!full_reset)
1027 goto __skip;
1028
1029 /* clear STATESTS */
1030 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1031
1032 /* reset controller */
1033 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1034
1035 count = 50;
1036 while (azx_readb(chip, GCTL) && --count)
1037 msleep(1);
1038
1039 /* delay for >= 100us for codec PLL to settle per spec
1040 * Rev 0.9 section 5.5.1
1041 */
1042 msleep(1);
1043
1044 /* Bring controller out of reset */
1045 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1046
1047 count = 50;
1048 while (!azx_readb(chip, GCTL) && --count)
1049 msleep(1);
1050
1051 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1052 msleep(1);
1053
1054 __skip:
1055 /* check to see if controller is ready */
1056 if (!azx_readb(chip, GCTL)) {
1057 snd_printd(SFX "azx_reset: controller not ready!\n");
1058 return -EBUSY;
1059 }
1060
1061 /* Accept unsolicited responses */
1062 if (!chip->single_cmd)
1063 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1064 ICH6_GCTL_UNSOL);
1065
1066 /* detect codecs */
1067 if (!chip->codec_mask) {
1068 chip->codec_mask = azx_readw(chip, STATESTS);
1069 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1070 }
1071
1072 return 0;
1073 }
1074
1075
1076 /*
1077 * Lowlevel interface
1078 */
1079
1080 /* enable interrupts */
1081 static void azx_int_enable(struct azx *chip)
1082 {
1083 /* enable controller CIE and GIE */
1084 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1085 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1086 }
1087
1088 /* disable interrupts */
1089 static void azx_int_disable(struct azx *chip)
1090 {
1091 int i;
1092
1093 /* disable interrupts in stream descriptor */
1094 for (i = 0; i < chip->num_streams; i++) {
1095 struct azx_dev *azx_dev = &chip->azx_dev[i];
1096 azx_sd_writeb(azx_dev, SD_CTL,
1097 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1098 }
1099
1100 /* disable SIE for all streams */
1101 azx_writeb(chip, INTCTL, 0);
1102
1103 /* disable controller CIE and GIE */
1104 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1105 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1106 }
1107
1108 /* clear interrupts */
1109 static void azx_int_clear(struct azx *chip)
1110 {
1111 int i;
1112
1113 /* clear stream status */
1114 for (i = 0; i < chip->num_streams; i++) {
1115 struct azx_dev *azx_dev = &chip->azx_dev[i];
1116 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1117 }
1118
1119 /* clear STATESTS */
1120 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1121
1122 /* clear rirb status */
1123 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1124
1125 /* clear int status */
1126 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1127 }
1128
1129 /* start a stream */
1130 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1131 {
1132 /*
1133 * Before stream start, initialize parameter
1134 */
1135 azx_dev->insufficient = 1;
1136
1137 /* enable SIE */
1138 azx_writel(chip, INTCTL,
1139 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1140 /* set DMA start and interrupt mask */
1141 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1142 SD_CTL_DMA_START | SD_INT_MASK);
1143 }
1144
1145 /* stop DMA */
1146 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1147 {
1148 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1149 ~(SD_CTL_DMA_START | SD_INT_MASK));
1150 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1151 }
1152
1153 /* stop a stream */
1154 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1155 {
1156 azx_stream_clear(chip, azx_dev);
1157 /* disable SIE */
1158 azx_writel(chip, INTCTL,
1159 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1160 }
1161
1162
1163 /*
1164 * reset and start the controller registers
1165 */
1166 static void azx_init_chip(struct azx *chip, int full_reset)
1167 {
1168 if (chip->initialized)
1169 return;
1170
1171 /* reset controller */
1172 azx_reset(chip, full_reset);
1173
1174 /* initialize interrupts */
1175 azx_int_clear(chip);
1176 azx_int_enable(chip);
1177
1178 /* initialize the codec command I/O */
1179 if (!chip->single_cmd)
1180 azx_init_cmd_io(chip);
1181
1182 /* program the position buffer */
1183 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1184 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1185
1186 chip->initialized = 1;
1187 }
1188
1189 /*
1190 * initialize the PCI registers
1191 */
1192 /* update bits in a PCI register byte */
1193 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1194 unsigned char mask, unsigned char val)
1195 {
1196 unsigned char data;
1197
1198 pci_read_config_byte(pci, reg, &data);
1199 data &= ~mask;
1200 data |= (val & mask);
1201 pci_write_config_byte(pci, reg, data);
1202 }
1203
1204 static void azx_init_pci(struct azx *chip)
1205 {
1206 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1207 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1208 * Ensuring these bits are 0 clears playback static on some HD Audio
1209 * codecs.
1210 * The PCI register TCSEL is defined in the Intel manuals.
1211 */
1212 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1213 snd_printdd(SFX "Clearing TCSEL\n");
1214 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1215 }
1216
1217 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1218 * we need to enable snoop.
1219 */
1220 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1221 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1222 update_pci_byte(chip->pci,
1223 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1224 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1225 }
1226
1227 /* For NVIDIA HDA, enable snoop */
1228 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1229 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1230 update_pci_byte(chip->pci,
1231 NVIDIA_HDA_TRANSREG_ADDR,
1232 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1233 update_pci_byte(chip->pci,
1234 NVIDIA_HDA_ISTRM_COH,
1235 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1236 update_pci_byte(chip->pci,
1237 NVIDIA_HDA_OSTRM_COH,
1238 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1239 }
1240
1241 /* Enable SCH/PCH snoop if needed */
1242 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1243 unsigned short snoop;
1244 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1245 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1246 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1247 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1248 if (!azx_snoop(chip))
1249 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1250 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1251 pci_read_config_word(chip->pci,
1252 INTEL_SCH_HDA_DEVC, &snoop);
1253 }
1254 snd_printdd(SFX "SCH snoop: %s\n",
1255 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1256 ? "Disabled" : "Enabled");
1257 }
1258 }
1259
1260
1261 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1262
1263 /*
1264 * interrupt handler
1265 */
1266 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1267 {
1268 struct azx *chip = dev_id;
1269 struct azx_dev *azx_dev;
1270 u32 status;
1271 u8 sd_status;
1272 int i, ok;
1273
1274 spin_lock(&chip->reg_lock);
1275
1276 if (chip->disabled) {
1277 spin_unlock(&chip->reg_lock);
1278 return IRQ_NONE;
1279 }
1280
1281 status = azx_readl(chip, INTSTS);
1282 if (status == 0) {
1283 spin_unlock(&chip->reg_lock);
1284 return IRQ_NONE;
1285 }
1286
1287 for (i = 0; i < chip->num_streams; i++) {
1288 azx_dev = &chip->azx_dev[i];
1289 if (status & azx_dev->sd_int_sta_mask) {
1290 sd_status = azx_sd_readb(azx_dev, SD_STS);
1291 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1292 if (!azx_dev->substream || !azx_dev->running ||
1293 !(sd_status & SD_INT_COMPLETE))
1294 continue;
1295 /* check whether this IRQ is really acceptable */
1296 ok = azx_position_ok(chip, azx_dev);
1297 if (ok == 1) {
1298 azx_dev->irq_pending = 0;
1299 spin_unlock(&chip->reg_lock);
1300 snd_pcm_period_elapsed(azx_dev->substream);
1301 spin_lock(&chip->reg_lock);
1302 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1303 /* bogus IRQ, process it later */
1304 azx_dev->irq_pending = 1;
1305 queue_work(chip->bus->workq,
1306 &chip->irq_pending_work);
1307 }
1308 }
1309 }
1310
1311 /* clear rirb int */
1312 status = azx_readb(chip, RIRBSTS);
1313 if (status & RIRB_INT_MASK) {
1314 if (status & RIRB_INT_RESPONSE) {
1315 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1316 udelay(80);
1317 azx_update_rirb(chip);
1318 }
1319 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1320 }
1321
1322 #if 0
1323 /* clear state status int */
1324 if (azx_readb(chip, STATESTS) & 0x04)
1325 azx_writeb(chip, STATESTS, 0x04);
1326 #endif
1327 spin_unlock(&chip->reg_lock);
1328
1329 return IRQ_HANDLED;
1330 }
1331
1332
1333 /*
1334 * set up a BDL entry
1335 */
1336 static int setup_bdle(struct azx *chip,
1337 struct snd_pcm_substream *substream,
1338 struct azx_dev *azx_dev, u32 **bdlp,
1339 int ofs, int size, int with_ioc)
1340 {
1341 u32 *bdl = *bdlp;
1342
1343 while (size > 0) {
1344 dma_addr_t addr;
1345 int chunk;
1346
1347 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1348 return -EINVAL;
1349
1350 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1351 /* program the address field of the BDL entry */
1352 bdl[0] = cpu_to_le32((u32)addr);
1353 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1354 /* program the size field of the BDL entry */
1355 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1356 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1357 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1358 u32 remain = 0x1000 - (ofs & 0xfff);
1359 if (chunk > remain)
1360 chunk = remain;
1361 }
1362 bdl[2] = cpu_to_le32(chunk);
1363 /* program the IOC to enable interrupt
1364 * only when the whole fragment is processed
1365 */
1366 size -= chunk;
1367 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1368 bdl += 4;
1369 azx_dev->frags++;
1370 ofs += chunk;
1371 }
1372 *bdlp = bdl;
1373 return ofs;
1374 }
1375
1376 /*
1377 * set up BDL entries
1378 */
1379 static int azx_setup_periods(struct azx *chip,
1380 struct snd_pcm_substream *substream,
1381 struct azx_dev *azx_dev)
1382 {
1383 u32 *bdl;
1384 int i, ofs, periods, period_bytes;
1385 int pos_adj;
1386
1387 /* reset BDL address */
1388 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1389 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1390
1391 period_bytes = azx_dev->period_bytes;
1392 periods = azx_dev->bufsize / period_bytes;
1393
1394 /* program the initial BDL entries */
1395 bdl = (u32 *)azx_dev->bdl.area;
1396 ofs = 0;
1397 azx_dev->frags = 0;
1398 pos_adj = bdl_pos_adj[chip->dev_index];
1399 if (pos_adj > 0) {
1400 struct snd_pcm_runtime *runtime = substream->runtime;
1401 int pos_align = pos_adj;
1402 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1403 if (!pos_adj)
1404 pos_adj = pos_align;
1405 else
1406 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1407 pos_align;
1408 pos_adj = frames_to_bytes(runtime, pos_adj);
1409 if (pos_adj >= period_bytes) {
1410 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1411 bdl_pos_adj[chip->dev_index]);
1412 pos_adj = 0;
1413 } else {
1414 ofs = setup_bdle(chip, substream, azx_dev,
1415 &bdl, ofs, pos_adj,
1416 !substream->runtime->no_period_wakeup);
1417 if (ofs < 0)
1418 goto error;
1419 }
1420 } else
1421 pos_adj = 0;
1422 for (i = 0; i < periods; i++) {
1423 if (i == periods - 1 && pos_adj)
1424 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1425 period_bytes - pos_adj, 0);
1426 else
1427 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1428 period_bytes,
1429 !substream->runtime->no_period_wakeup);
1430 if (ofs < 0)
1431 goto error;
1432 }
1433 return 0;
1434
1435 error:
1436 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1437 azx_dev->bufsize, period_bytes);
1438 return -EINVAL;
1439 }
1440
1441 /* reset stream */
1442 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1443 {
1444 unsigned char val;
1445 int timeout;
1446
1447 azx_stream_clear(chip, azx_dev);
1448
1449 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1450 SD_CTL_STREAM_RESET);
1451 udelay(3);
1452 timeout = 300;
1453 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1454 --timeout)
1455 ;
1456 val &= ~SD_CTL_STREAM_RESET;
1457 azx_sd_writeb(azx_dev, SD_CTL, val);
1458 udelay(3);
1459
1460 timeout = 300;
1461 /* waiting for hardware to report that the stream is out of reset */
1462 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1463 --timeout)
1464 ;
1465
1466 /* reset first position - may not be synced with hw at this time */
1467 *azx_dev->posbuf = 0;
1468 }
1469
1470 /*
1471 * set up the SD for streaming
1472 */
1473 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1474 {
1475 unsigned int val;
1476 /* make sure the run bit is zero for SD */
1477 azx_stream_clear(chip, azx_dev);
1478 /* program the stream_tag */
1479 val = azx_sd_readl(azx_dev, SD_CTL);
1480 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1481 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1482 if (!azx_snoop(chip))
1483 val |= SD_CTL_TRAFFIC_PRIO;
1484 azx_sd_writel(azx_dev, SD_CTL, val);
1485
1486 /* program the length of samples in cyclic buffer */
1487 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1488
1489 /* program the stream format */
1490 /* this value needs to be the same as the one programmed */
1491 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1492
1493 /* program the stream LVI (last valid index) of the BDL */
1494 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1495
1496 /* program the BDL address */
1497 /* lower BDL address */
1498 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1499 /* upper BDL address */
1500 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1501
1502 /* enable the position buffer */
1503 if (chip->position_fix[0] != POS_FIX_LPIB ||
1504 chip->position_fix[1] != POS_FIX_LPIB) {
1505 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1506 azx_writel(chip, DPLBASE,
1507 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1508 }
1509
1510 /* set the interrupt enable bits in the descriptor control register */
1511 azx_sd_writel(azx_dev, SD_CTL,
1512 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1513
1514 return 0;
1515 }
1516
1517 /*
1518 * Probe the given codec address
1519 */
1520 static int probe_codec(struct azx *chip, int addr)
1521 {
1522 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1523 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1524 unsigned int res;
1525
1526 mutex_lock(&chip->bus->cmd_mutex);
1527 chip->probing = 1;
1528 azx_send_cmd(chip->bus, cmd);
1529 res = azx_get_response(chip->bus, addr);
1530 chip->probing = 0;
1531 mutex_unlock(&chip->bus->cmd_mutex);
1532 if (res == -1)
1533 return -EIO;
1534 snd_printdd(SFX "codec #%d probed OK\n", addr);
1535 return 0;
1536 }
1537
1538 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1539 struct hda_pcm *cpcm);
1540 static void azx_stop_chip(struct azx *chip);
1541
1542 static void azx_bus_reset(struct hda_bus *bus)
1543 {
1544 struct azx *chip = bus->private_data;
1545
1546 bus->in_reset = 1;
1547 azx_stop_chip(chip);
1548 azx_init_chip(chip, 1);
1549 #ifdef CONFIG_PM
1550 if (chip->initialized) {
1551 struct azx_pcm *p;
1552 list_for_each_entry(p, &chip->pcm_list, list)
1553 snd_pcm_suspend_all(p->pcm);
1554 snd_hda_suspend(chip->bus);
1555 snd_hda_resume(chip->bus);
1556 }
1557 #endif
1558 bus->in_reset = 0;
1559 }
1560
1561 /*
1562 * Codec initialization
1563 */
1564
1565 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1566 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1567 [AZX_DRIVER_NVIDIA] = 8,
1568 [AZX_DRIVER_TERA] = 1,
1569 };
1570
1571 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1572 {
1573 struct hda_bus_template bus_temp;
1574 int c, codecs, err;
1575 int max_slots;
1576
1577 memset(&bus_temp, 0, sizeof(bus_temp));
1578 bus_temp.private_data = chip;
1579 bus_temp.modelname = model;
1580 bus_temp.pci = chip->pci;
1581 bus_temp.ops.command = azx_send_cmd;
1582 bus_temp.ops.get_response = azx_get_response;
1583 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1584 bus_temp.ops.bus_reset = azx_bus_reset;
1585 #ifdef CONFIG_SND_HDA_POWER_SAVE
1586 bus_temp.power_save = &power_save;
1587 bus_temp.ops.pm_notify = azx_power_notify;
1588 #endif
1589
1590 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1591 if (err < 0)
1592 return err;
1593
1594 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1595 snd_printd(SFX "Enable delay in RIRB handling\n");
1596 chip->bus->needs_damn_long_delay = 1;
1597 }
1598
1599 codecs = 0;
1600 max_slots = azx_max_codecs[chip->driver_type];
1601 if (!max_slots)
1602 max_slots = AZX_DEFAULT_CODECS;
1603
1604 /* First try to probe all given codec slots */
1605 for (c = 0; c < max_slots; c++) {
1606 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1607 if (probe_codec(chip, c) < 0) {
1608 /* Some BIOSen give you wrong codec addresses
1609 * that don't exist
1610 */
1611 snd_printk(KERN_WARNING SFX
1612 "Codec #%d probe error; "
1613 "disabling it...\n", c);
1614 chip->codec_mask &= ~(1 << c);
1615 /* More badly, accessing to a non-existing
1616 * codec often screws up the controller chip,
1617 * and disturbs the further communications.
1618 * Thus if an error occurs during probing,
1619 * better to reset the controller chip to
1620 * get back to the sanity state.
1621 */
1622 azx_stop_chip(chip);
1623 azx_init_chip(chip, 1);
1624 }
1625 }
1626 }
1627
1628 /* AMD chipsets often cause the communication stalls upon certain
1629 * sequence like the pin-detection. It seems that forcing the synced
1630 * access works around the stall. Grrr...
1631 */
1632 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1633 snd_printd(SFX "Enable sync_write for stable communication\n");
1634 chip->bus->sync_write = 1;
1635 chip->bus->allow_bus_reset = 1;
1636 }
1637
1638 /* Then create codec instances */
1639 for (c = 0; c < max_slots; c++) {
1640 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1641 struct hda_codec *codec;
1642 err = snd_hda_codec_new(chip->bus, c, &codec);
1643 if (err < 0)
1644 continue;
1645 codec->beep_mode = chip->beep_mode;
1646 codecs++;
1647 }
1648 }
1649 if (!codecs) {
1650 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1651 return -ENXIO;
1652 }
1653 return 0;
1654 }
1655
1656 /* configure each codec instance */
1657 static int __devinit azx_codec_configure(struct azx *chip)
1658 {
1659 struct hda_codec *codec;
1660 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1661 snd_hda_codec_configure(codec);
1662 }
1663 return 0;
1664 }
1665
1666
1667 /*
1668 * PCM support
1669 */
1670
1671 /* assign a stream for the PCM */
1672 static inline struct azx_dev *
1673 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1674 {
1675 int dev, i, nums;
1676 struct azx_dev *res = NULL;
1677 /* make a non-zero unique key for the substream */
1678 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1679 (substream->stream + 1);
1680
1681 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1682 dev = chip->playback_index_offset;
1683 nums = chip->playback_streams;
1684 } else {
1685 dev = chip->capture_index_offset;
1686 nums = chip->capture_streams;
1687 }
1688 for (i = 0; i < nums; i++, dev++)
1689 if (!chip->azx_dev[dev].opened) {
1690 res = &chip->azx_dev[dev];
1691 if (res->assigned_key == key)
1692 break;
1693 }
1694 if (res) {
1695 res->opened = 1;
1696 res->assigned_key = key;
1697 }
1698 return res;
1699 }
1700
1701 /* release the assigned stream */
1702 static inline void azx_release_device(struct azx_dev *azx_dev)
1703 {
1704 azx_dev->opened = 0;
1705 }
1706
1707 static struct snd_pcm_hardware azx_pcm_hw = {
1708 .info = (SNDRV_PCM_INFO_MMAP |
1709 SNDRV_PCM_INFO_INTERLEAVED |
1710 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1711 SNDRV_PCM_INFO_MMAP_VALID |
1712 /* No full-resume yet implemented */
1713 /* SNDRV_PCM_INFO_RESUME |*/
1714 SNDRV_PCM_INFO_PAUSE |
1715 SNDRV_PCM_INFO_SYNC_START |
1716 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1717 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1718 .rates = SNDRV_PCM_RATE_48000,
1719 .rate_min = 48000,
1720 .rate_max = 48000,
1721 .channels_min = 2,
1722 .channels_max = 2,
1723 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1724 .period_bytes_min = 128,
1725 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1726 .periods_min = 2,
1727 .periods_max = AZX_MAX_FRAG,
1728 .fifo_size = 0,
1729 };
1730
1731 static int azx_pcm_open(struct snd_pcm_substream *substream)
1732 {
1733 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1734 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1735 struct azx *chip = apcm->chip;
1736 struct azx_dev *azx_dev;
1737 struct snd_pcm_runtime *runtime = substream->runtime;
1738 unsigned long flags;
1739 int err;
1740 int buff_step;
1741
1742 mutex_lock(&chip->open_mutex);
1743 azx_dev = azx_assign_device(chip, substream);
1744 if (azx_dev == NULL) {
1745 mutex_unlock(&chip->open_mutex);
1746 return -EBUSY;
1747 }
1748 runtime->hw = azx_pcm_hw;
1749 runtime->hw.channels_min = hinfo->channels_min;
1750 runtime->hw.channels_max = hinfo->channels_max;
1751 runtime->hw.formats = hinfo->formats;
1752 runtime->hw.rates = hinfo->rates;
1753 snd_pcm_limit_hw_rates(runtime);
1754 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1755 if (chip->align_buffer_size)
1756 /* constrain buffer sizes to be multiple of 128
1757 bytes. This is more efficient in terms of memory
1758 access but isn't required by the HDA spec and
1759 prevents users from specifying exact period/buffer
1760 sizes. For example for 44.1kHz, a period size set
1761 to 20ms will be rounded to 19.59ms. */
1762 buff_step = 128;
1763 else
1764 /* Don't enforce steps on buffer sizes, still need to
1765 be multiple of 4 bytes (HDA spec). Tested on Intel
1766 HDA controllers, may not work on all devices where
1767 option needs to be disabled */
1768 buff_step = 4;
1769
1770 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1771 buff_step);
1772 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1773 buff_step);
1774 snd_hda_power_up_d3wait(apcm->codec);
1775 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1776 if (err < 0) {
1777 azx_release_device(azx_dev);
1778 snd_hda_power_down(apcm->codec);
1779 mutex_unlock(&chip->open_mutex);
1780 return err;
1781 }
1782 snd_pcm_limit_hw_rates(runtime);
1783 /* sanity check */
1784 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1785 snd_BUG_ON(!runtime->hw.channels_max) ||
1786 snd_BUG_ON(!runtime->hw.formats) ||
1787 snd_BUG_ON(!runtime->hw.rates)) {
1788 azx_release_device(azx_dev);
1789 hinfo->ops.close(hinfo, apcm->codec, substream);
1790 snd_hda_power_down(apcm->codec);
1791 mutex_unlock(&chip->open_mutex);
1792 return -EINVAL;
1793 }
1794 spin_lock_irqsave(&chip->reg_lock, flags);
1795 azx_dev->substream = substream;
1796 azx_dev->running = 0;
1797 spin_unlock_irqrestore(&chip->reg_lock, flags);
1798
1799 runtime->private_data = azx_dev;
1800 snd_pcm_set_sync(substream);
1801 mutex_unlock(&chip->open_mutex);
1802 return 0;
1803 }
1804
1805 static int azx_pcm_close(struct snd_pcm_substream *substream)
1806 {
1807 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1808 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1809 struct azx *chip = apcm->chip;
1810 struct azx_dev *azx_dev = get_azx_dev(substream);
1811 unsigned long flags;
1812
1813 mutex_lock(&chip->open_mutex);
1814 spin_lock_irqsave(&chip->reg_lock, flags);
1815 azx_dev->substream = NULL;
1816 azx_dev->running = 0;
1817 spin_unlock_irqrestore(&chip->reg_lock, flags);
1818 azx_release_device(azx_dev);
1819 hinfo->ops.close(hinfo, apcm->codec, substream);
1820 snd_hda_power_down(apcm->codec);
1821 mutex_unlock(&chip->open_mutex);
1822 return 0;
1823 }
1824
1825 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1826 struct snd_pcm_hw_params *hw_params)
1827 {
1828 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1829 struct azx *chip = apcm->chip;
1830 struct snd_pcm_runtime *runtime = substream->runtime;
1831 struct azx_dev *azx_dev = get_azx_dev(substream);
1832 int ret;
1833
1834 mark_runtime_wc(chip, azx_dev, runtime, false);
1835 azx_dev->bufsize = 0;
1836 azx_dev->period_bytes = 0;
1837 azx_dev->format_val = 0;
1838 ret = snd_pcm_lib_malloc_pages(substream,
1839 params_buffer_bytes(hw_params));
1840 if (ret < 0)
1841 return ret;
1842 mark_runtime_wc(chip, azx_dev, runtime, true);
1843 return ret;
1844 }
1845
1846 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1847 {
1848 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1849 struct azx_dev *azx_dev = get_azx_dev(substream);
1850 struct azx *chip = apcm->chip;
1851 struct snd_pcm_runtime *runtime = substream->runtime;
1852 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1853
1854 /* reset BDL address */
1855 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1856 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1857 azx_sd_writel(azx_dev, SD_CTL, 0);
1858 azx_dev->bufsize = 0;
1859 azx_dev->period_bytes = 0;
1860 azx_dev->format_val = 0;
1861
1862 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1863
1864 mark_runtime_wc(chip, azx_dev, runtime, false);
1865 return snd_pcm_lib_free_pages(substream);
1866 }
1867
1868 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1869 {
1870 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1871 struct azx *chip = apcm->chip;
1872 struct azx_dev *azx_dev = get_azx_dev(substream);
1873 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1874 struct snd_pcm_runtime *runtime = substream->runtime;
1875 unsigned int bufsize, period_bytes, format_val, stream_tag;
1876 int err;
1877 struct hda_spdif_out *spdif =
1878 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1879 unsigned short ctls = spdif ? spdif->ctls : 0;
1880
1881 azx_stream_reset(chip, azx_dev);
1882 format_val = snd_hda_calc_stream_format(runtime->rate,
1883 runtime->channels,
1884 runtime->format,
1885 hinfo->maxbps,
1886 ctls);
1887 if (!format_val) {
1888 snd_printk(KERN_ERR SFX
1889 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1890 runtime->rate, runtime->channels, runtime->format);
1891 return -EINVAL;
1892 }
1893
1894 bufsize = snd_pcm_lib_buffer_bytes(substream);
1895 period_bytes = snd_pcm_lib_period_bytes(substream);
1896
1897 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1898 bufsize, format_val);
1899
1900 if (bufsize != azx_dev->bufsize ||
1901 period_bytes != azx_dev->period_bytes ||
1902 format_val != azx_dev->format_val) {
1903 azx_dev->bufsize = bufsize;
1904 azx_dev->period_bytes = period_bytes;
1905 azx_dev->format_val = format_val;
1906 err = azx_setup_periods(chip, substream, azx_dev);
1907 if (err < 0)
1908 return err;
1909 }
1910
1911 /* wallclk has 24Mhz clock source */
1912 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1913 runtime->rate) * 1000);
1914 azx_setup_controller(chip, azx_dev);
1915 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1916 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1917 else
1918 azx_dev->fifo_size = 0;
1919
1920 stream_tag = azx_dev->stream_tag;
1921 /* CA-IBG chips need the playback stream starting from 1 */
1922 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1923 stream_tag > chip->capture_streams)
1924 stream_tag -= chip->capture_streams;
1925 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1926 azx_dev->format_val, substream);
1927 }
1928
1929 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1930 {
1931 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1932 struct azx *chip = apcm->chip;
1933 struct azx_dev *azx_dev;
1934 struct snd_pcm_substream *s;
1935 int rstart = 0, start, nsync = 0, sbits = 0;
1936 int nwait, timeout;
1937
1938 switch (cmd) {
1939 case SNDRV_PCM_TRIGGER_START:
1940 rstart = 1;
1941 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1942 case SNDRV_PCM_TRIGGER_RESUME:
1943 start = 1;
1944 break;
1945 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1946 case SNDRV_PCM_TRIGGER_SUSPEND:
1947 case SNDRV_PCM_TRIGGER_STOP:
1948 start = 0;
1949 break;
1950 default:
1951 return -EINVAL;
1952 }
1953
1954 snd_pcm_group_for_each_entry(s, substream) {
1955 if (s->pcm->card != substream->pcm->card)
1956 continue;
1957 azx_dev = get_azx_dev(s);
1958 sbits |= 1 << azx_dev->index;
1959 nsync++;
1960 snd_pcm_trigger_done(s, substream);
1961 }
1962
1963 spin_lock(&chip->reg_lock);
1964 if (nsync > 1) {
1965 /* first, set SYNC bits of corresponding streams */
1966 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1967 azx_writel(chip, OLD_SSYNC,
1968 azx_readl(chip, OLD_SSYNC) | sbits);
1969 else
1970 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1971 }
1972 snd_pcm_group_for_each_entry(s, substream) {
1973 if (s->pcm->card != substream->pcm->card)
1974 continue;
1975 azx_dev = get_azx_dev(s);
1976 if (start) {
1977 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1978 if (!rstart)
1979 azx_dev->start_wallclk -=
1980 azx_dev->period_wallclk;
1981 azx_stream_start(chip, azx_dev);
1982 } else {
1983 azx_stream_stop(chip, azx_dev);
1984 }
1985 azx_dev->running = start;
1986 }
1987 spin_unlock(&chip->reg_lock);
1988 if (start) {
1989 if (nsync == 1)
1990 return 0;
1991 /* wait until all FIFOs get ready */
1992 for (timeout = 5000; timeout; timeout--) {
1993 nwait = 0;
1994 snd_pcm_group_for_each_entry(s, substream) {
1995 if (s->pcm->card != substream->pcm->card)
1996 continue;
1997 azx_dev = get_azx_dev(s);
1998 if (!(azx_sd_readb(azx_dev, SD_STS) &
1999 SD_STS_FIFO_READY))
2000 nwait++;
2001 }
2002 if (!nwait)
2003 break;
2004 cpu_relax();
2005 }
2006 } else {
2007 /* wait until all RUN bits are cleared */
2008 for (timeout = 5000; timeout; timeout--) {
2009 nwait = 0;
2010 snd_pcm_group_for_each_entry(s, substream) {
2011 if (s->pcm->card != substream->pcm->card)
2012 continue;
2013 azx_dev = get_azx_dev(s);
2014 if (azx_sd_readb(azx_dev, SD_CTL) &
2015 SD_CTL_DMA_START)
2016 nwait++;
2017 }
2018 if (!nwait)
2019 break;
2020 cpu_relax();
2021 }
2022 }
2023 if (nsync > 1) {
2024 spin_lock(&chip->reg_lock);
2025 /* reset SYNC bits */
2026 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2027 azx_writel(chip, OLD_SSYNC,
2028 azx_readl(chip, OLD_SSYNC) & ~sbits);
2029 else
2030 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2031 spin_unlock(&chip->reg_lock);
2032 }
2033 return 0;
2034 }
2035
2036 /* get the current DMA position with correction on VIA chips */
2037 static unsigned int azx_via_get_position(struct azx *chip,
2038 struct azx_dev *azx_dev)
2039 {
2040 unsigned int link_pos, mini_pos, bound_pos;
2041 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2042 unsigned int fifo_size;
2043
2044 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2045 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2046 /* Playback, no problem using link position */
2047 return link_pos;
2048 }
2049
2050 /* Capture */
2051 /* For new chipset,
2052 * use mod to get the DMA position just like old chipset
2053 */
2054 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2055 mod_dma_pos %= azx_dev->period_bytes;
2056
2057 /* azx_dev->fifo_size can't get FIFO size of in stream.
2058 * Get from base address + offset.
2059 */
2060 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2061
2062 if (azx_dev->insufficient) {
2063 /* Link position never gather than FIFO size */
2064 if (link_pos <= fifo_size)
2065 return 0;
2066
2067 azx_dev->insufficient = 0;
2068 }
2069
2070 if (link_pos <= fifo_size)
2071 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2072 else
2073 mini_pos = link_pos - fifo_size;
2074
2075 /* Find nearest previous boudary */
2076 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2077 mod_link_pos = link_pos % azx_dev->period_bytes;
2078 if (mod_link_pos >= fifo_size)
2079 bound_pos = link_pos - mod_link_pos;
2080 else if (mod_dma_pos >= mod_mini_pos)
2081 bound_pos = mini_pos - mod_mini_pos;
2082 else {
2083 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2084 if (bound_pos >= azx_dev->bufsize)
2085 bound_pos = 0;
2086 }
2087
2088 /* Calculate real DMA position we want */
2089 return bound_pos + mod_dma_pos;
2090 }
2091
2092 static unsigned int azx_get_position(struct azx *chip,
2093 struct azx_dev *azx_dev,
2094 bool with_check)
2095 {
2096 unsigned int pos;
2097 int stream = azx_dev->substream->stream;
2098
2099 switch (chip->position_fix[stream]) {
2100 case POS_FIX_LPIB:
2101 /* read LPIB */
2102 pos = azx_sd_readl(azx_dev, SD_LPIB);
2103 break;
2104 case POS_FIX_VIACOMBO:
2105 pos = azx_via_get_position(chip, azx_dev);
2106 break;
2107 default:
2108 /* use the position buffer */
2109 pos = le32_to_cpu(*azx_dev->posbuf);
2110 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2111 if (!pos || pos == (u32)-1) {
2112 printk(KERN_WARNING
2113 "hda-intel: Invalid position buffer, "
2114 "using LPIB read method instead.\n");
2115 chip->position_fix[stream] = POS_FIX_LPIB;
2116 pos = azx_sd_readl(azx_dev, SD_LPIB);
2117 } else
2118 chip->position_fix[stream] = POS_FIX_POSBUF;
2119 }
2120 break;
2121 }
2122
2123 if (pos >= azx_dev->bufsize)
2124 pos = 0;
2125
2126 /* calculate runtime delay from LPIB */
2127 if (azx_dev->substream->runtime &&
2128 chip->position_fix[stream] == POS_FIX_POSBUF &&
2129 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2130 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2131 int delay;
2132 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2133 delay = pos - lpib_pos;
2134 else
2135 delay = lpib_pos - pos;
2136 if (delay < 0)
2137 delay += azx_dev->bufsize;
2138 if (delay >= azx_dev->period_bytes) {
2139 snd_printk(KERN_WARNING SFX
2140 "Unstable LPIB (%d >= %d); "
2141 "disabling LPIB delay counting\n",
2142 delay, azx_dev->period_bytes);
2143 delay = 0;
2144 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2145 }
2146 azx_dev->substream->runtime->delay =
2147 bytes_to_frames(azx_dev->substream->runtime, delay);
2148 }
2149 return pos;
2150 }
2151
2152 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2153 {
2154 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2155 struct azx *chip = apcm->chip;
2156 struct azx_dev *azx_dev = get_azx_dev(substream);
2157 return bytes_to_frames(substream->runtime,
2158 azx_get_position(chip, azx_dev, false));
2159 }
2160
2161 /*
2162 * Check whether the current DMA position is acceptable for updating
2163 * periods. Returns non-zero if it's OK.
2164 *
2165 * Many HD-audio controllers appear pretty inaccurate about
2166 * the update-IRQ timing. The IRQ is issued before actually the
2167 * data is processed. So, we need to process it afterwords in a
2168 * workqueue.
2169 */
2170 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2171 {
2172 u32 wallclk;
2173 unsigned int pos;
2174 int stream;
2175
2176 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2177 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2178 return -1; /* bogus (too early) interrupt */
2179
2180 stream = azx_dev->substream->stream;
2181 pos = azx_get_position(chip, azx_dev, true);
2182
2183 if (WARN_ONCE(!azx_dev->period_bytes,
2184 "hda-intel: zero azx_dev->period_bytes"))
2185 return -1; /* this shouldn't happen! */
2186 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2187 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2188 /* NG - it's below the first next period boundary */
2189 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2190 azx_dev->start_wallclk += wallclk;
2191 return 1; /* OK, it's fine */
2192 }
2193
2194 /*
2195 * The work for pending PCM period updates.
2196 */
2197 static void azx_irq_pending_work(struct work_struct *work)
2198 {
2199 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2200 int i, pending, ok;
2201
2202 if (!chip->irq_pending_warned) {
2203 printk(KERN_WARNING
2204 "hda-intel: IRQ timing workaround is activated "
2205 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2206 chip->card->number);
2207 chip->irq_pending_warned = 1;
2208 }
2209
2210 for (;;) {
2211 pending = 0;
2212 spin_lock_irq(&chip->reg_lock);
2213 for (i = 0; i < chip->num_streams; i++) {
2214 struct azx_dev *azx_dev = &chip->azx_dev[i];
2215 if (!azx_dev->irq_pending ||
2216 !azx_dev->substream ||
2217 !azx_dev->running)
2218 continue;
2219 ok = azx_position_ok(chip, azx_dev);
2220 if (ok > 0) {
2221 azx_dev->irq_pending = 0;
2222 spin_unlock(&chip->reg_lock);
2223 snd_pcm_period_elapsed(azx_dev->substream);
2224 spin_lock(&chip->reg_lock);
2225 } else if (ok < 0) {
2226 pending = 0; /* too early */
2227 } else
2228 pending++;
2229 }
2230 spin_unlock_irq(&chip->reg_lock);
2231 if (!pending)
2232 return;
2233 msleep(1);
2234 }
2235 }
2236
2237 /* clear irq_pending flags and assure no on-going workq */
2238 static void azx_clear_irq_pending(struct azx *chip)
2239 {
2240 int i;
2241
2242 spin_lock_irq(&chip->reg_lock);
2243 for (i = 0; i < chip->num_streams; i++)
2244 chip->azx_dev[i].irq_pending = 0;
2245 spin_unlock_irq(&chip->reg_lock);
2246 }
2247
2248 #ifdef CONFIG_X86
2249 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2250 struct vm_area_struct *area)
2251 {
2252 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2253 struct azx *chip = apcm->chip;
2254 if (!azx_snoop(chip))
2255 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2256 return snd_pcm_lib_default_mmap(substream, area);
2257 }
2258 #else
2259 #define azx_pcm_mmap NULL
2260 #endif
2261
2262 static struct snd_pcm_ops azx_pcm_ops = {
2263 .open = azx_pcm_open,
2264 .close = azx_pcm_close,
2265 .ioctl = snd_pcm_lib_ioctl,
2266 .hw_params = azx_pcm_hw_params,
2267 .hw_free = azx_pcm_hw_free,
2268 .prepare = azx_pcm_prepare,
2269 .trigger = azx_pcm_trigger,
2270 .pointer = azx_pcm_pointer,
2271 .mmap = azx_pcm_mmap,
2272 .page = snd_pcm_sgbuf_ops_page,
2273 };
2274
2275 static void azx_pcm_free(struct snd_pcm *pcm)
2276 {
2277 struct azx_pcm *apcm = pcm->private_data;
2278 if (apcm) {
2279 list_del(&apcm->list);
2280 kfree(apcm);
2281 }
2282 }
2283
2284 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2285
2286 static int
2287 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2288 struct hda_pcm *cpcm)
2289 {
2290 struct azx *chip = bus->private_data;
2291 struct snd_pcm *pcm;
2292 struct azx_pcm *apcm;
2293 int pcm_dev = cpcm->device;
2294 unsigned int size;
2295 int s, err;
2296
2297 list_for_each_entry(apcm, &chip->pcm_list, list) {
2298 if (apcm->pcm->device == pcm_dev) {
2299 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2300 return -EBUSY;
2301 }
2302 }
2303 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2304 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2305 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2306 &pcm);
2307 if (err < 0)
2308 return err;
2309 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2310 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2311 if (apcm == NULL)
2312 return -ENOMEM;
2313 apcm->chip = chip;
2314 apcm->pcm = pcm;
2315 apcm->codec = codec;
2316 pcm->private_data = apcm;
2317 pcm->private_free = azx_pcm_free;
2318 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2319 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2320 list_add_tail(&apcm->list, &chip->pcm_list);
2321 cpcm->pcm = pcm;
2322 for (s = 0; s < 2; s++) {
2323 apcm->hinfo[s] = &cpcm->stream[s];
2324 if (cpcm->stream[s].substreams)
2325 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2326 }
2327 /* buffer pre-allocation */
2328 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2329 if (size > MAX_PREALLOC_SIZE)
2330 size = MAX_PREALLOC_SIZE;
2331 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2332 snd_dma_pci_data(chip->pci),
2333 size, MAX_PREALLOC_SIZE);
2334 return 0;
2335 }
2336
2337 /*
2338 * mixer creation - all stuff is implemented in hda module
2339 */
2340 static int __devinit azx_mixer_create(struct azx *chip)
2341 {
2342 return snd_hda_build_controls(chip->bus);
2343 }
2344
2345
2346 /*
2347 * initialize SD streams
2348 */
2349 static int __devinit azx_init_stream(struct azx *chip)
2350 {
2351 int i;
2352
2353 /* initialize each stream (aka device)
2354 * assign the starting bdl address to each stream (device)
2355 * and initialize
2356 */
2357 for (i = 0; i < chip->num_streams; i++) {
2358 struct azx_dev *azx_dev = &chip->azx_dev[i];
2359 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2360 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2361 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2362 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2363 azx_dev->sd_int_sta_mask = 1 << i;
2364 /* stream tag: must be non-zero and unique */
2365 azx_dev->index = i;
2366 azx_dev->stream_tag = i + 1;
2367 }
2368
2369 return 0;
2370 }
2371
2372 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2373 {
2374 if (request_irq(chip->pci->irq, azx_interrupt,
2375 chip->msi ? 0 : IRQF_SHARED,
2376 KBUILD_MODNAME, chip)) {
2377 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2378 "disabling device\n", chip->pci->irq);
2379 if (do_disconnect)
2380 snd_card_disconnect(chip->card);
2381 return -1;
2382 }
2383 chip->irq = chip->pci->irq;
2384 pci_intx(chip->pci, !chip->msi);
2385 return 0;
2386 }
2387
2388
2389 static void azx_stop_chip(struct azx *chip)
2390 {
2391 if (!chip->initialized)
2392 return;
2393
2394 /* disable interrupts */
2395 azx_int_disable(chip);
2396 azx_int_clear(chip);
2397
2398 /* disable CORB/RIRB */
2399 azx_free_cmd_io(chip);
2400
2401 /* disable position buffer */
2402 azx_writel(chip, DPLBASE, 0);
2403 azx_writel(chip, DPUBASE, 0);
2404
2405 chip->initialized = 0;
2406 }
2407
2408 #ifdef CONFIG_SND_HDA_POWER_SAVE
2409 /* power-up/down the controller */
2410 static void azx_power_notify(struct hda_bus *bus)
2411 {
2412 struct azx *chip = bus->private_data;
2413 struct hda_codec *c;
2414 int power_on = 0;
2415
2416 list_for_each_entry(c, &bus->codec_list, list) {
2417 if (c->power_on) {
2418 power_on = 1;
2419 break;
2420 }
2421 }
2422 if (power_on)
2423 azx_init_chip(chip, 1);
2424 else if (chip->running && power_save_controller &&
2425 !bus->power_keep_link_on)
2426 azx_stop_chip(chip);
2427 }
2428 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2429
2430 #ifdef CONFIG_PM
2431 /*
2432 * power management
2433 */
2434
2435 static int azx_suspend(struct device *dev)
2436 {
2437 struct pci_dev *pci = to_pci_dev(dev);
2438 struct snd_card *card = dev_get_drvdata(dev);
2439 struct azx *chip = card->private_data;
2440 struct azx_pcm *p;
2441
2442 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2443 azx_clear_irq_pending(chip);
2444 list_for_each_entry(p, &chip->pcm_list, list)
2445 snd_pcm_suspend_all(p->pcm);
2446 if (chip->initialized)
2447 snd_hda_suspend(chip->bus);
2448 azx_stop_chip(chip);
2449 if (chip->irq >= 0) {
2450 free_irq(chip->irq, chip);
2451 chip->irq = -1;
2452 }
2453 if (chip->msi)
2454 pci_disable_msi(chip->pci);
2455 pci_disable_device(pci);
2456 pci_save_state(pci);
2457 pci_set_power_state(pci, PCI_D3hot);
2458 return 0;
2459 }
2460
2461 static int azx_resume(struct device *dev)
2462 {
2463 struct pci_dev *pci = to_pci_dev(dev);
2464 struct snd_card *card = dev_get_drvdata(dev);
2465 struct azx *chip = card->private_data;
2466
2467 pci_set_power_state(pci, PCI_D0);
2468 pci_restore_state(pci);
2469 if (pci_enable_device(pci) < 0) {
2470 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2471 "disabling device\n");
2472 snd_card_disconnect(card);
2473 return -EIO;
2474 }
2475 pci_set_master(pci);
2476 if (chip->msi)
2477 if (pci_enable_msi(pci) < 0)
2478 chip->msi = 0;
2479 if (azx_acquire_irq(chip, 1) < 0)
2480 return -EIO;
2481 azx_init_pci(chip);
2482
2483 azx_init_chip(chip, 1);
2484
2485 snd_hda_resume(chip->bus);
2486 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2487 return 0;
2488 }
2489 static SIMPLE_DEV_PM_OPS(azx_pm, azx_suspend, azx_resume);
2490 #define AZX_PM_OPS &azx_pm
2491 #else
2492 #define azx_suspend(dev)
2493 #define azx_resume(dev)
2494 #define AZX_PM_OPS NULL
2495 #endif /* CONFIG_PM */
2496
2497
2498 /*
2499 * reboot notifier for hang-up problem at power-down
2500 */
2501 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2502 {
2503 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2504 snd_hda_bus_reboot_notify(chip->bus);
2505 azx_stop_chip(chip);
2506 return NOTIFY_OK;
2507 }
2508
2509 static void azx_notifier_register(struct azx *chip)
2510 {
2511 chip->reboot_notifier.notifier_call = azx_halt;
2512 register_reboot_notifier(&chip->reboot_notifier);
2513 }
2514
2515 static void azx_notifier_unregister(struct azx *chip)
2516 {
2517 if (chip->reboot_notifier.notifier_call)
2518 unregister_reboot_notifier(&chip->reboot_notifier);
2519 }
2520
2521 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2522 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2523
2524 #ifdef SUPPORT_VGA_SWITCHEROO
2525 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2526
2527 static void azx_vs_set_state(struct pci_dev *pci,
2528 enum vga_switcheroo_state state)
2529 {
2530 struct snd_card *card = pci_get_drvdata(pci);
2531 struct azx *chip = card->private_data;
2532 bool disabled;
2533
2534 if (chip->init_failed)
2535 return;
2536
2537 disabled = (state == VGA_SWITCHEROO_OFF);
2538 if (chip->disabled == disabled)
2539 return;
2540
2541 if (!chip->bus) {
2542 chip->disabled = disabled;
2543 if (!disabled) {
2544 snd_printk(KERN_INFO SFX
2545 "%s: Start delayed initialization\n",
2546 pci_name(chip->pci));
2547 if (azx_first_init(chip) < 0 ||
2548 azx_probe_continue(chip) < 0) {
2549 snd_printk(KERN_ERR SFX
2550 "%s: initialization error\n",
2551 pci_name(chip->pci));
2552 chip->init_failed = true;
2553 }
2554 }
2555 } else {
2556 snd_printk(KERN_INFO SFX
2557 "%s %s via VGA-switcheroo\n",
2558 disabled ? "Disabling" : "Enabling",
2559 pci_name(chip->pci));
2560 if (disabled) {
2561 azx_suspend(&pci->dev);
2562 chip->disabled = true;
2563 if (snd_hda_lock_devices(chip->bus))
2564 snd_printk(KERN_WARNING SFX
2565 "Cannot lock devices!\n");
2566 } else {
2567 snd_hda_unlock_devices(chip->bus);
2568 chip->disabled = false;
2569 azx_resume(&pci->dev);
2570 }
2571 }
2572 }
2573
2574 static bool azx_vs_can_switch(struct pci_dev *pci)
2575 {
2576 struct snd_card *card = pci_get_drvdata(pci);
2577 struct azx *chip = card->private_data;
2578
2579 if (chip->init_failed)
2580 return false;
2581 if (chip->disabled || !chip->bus)
2582 return true;
2583 if (snd_hda_lock_devices(chip->bus))
2584 return false;
2585 snd_hda_unlock_devices(chip->bus);
2586 return true;
2587 }
2588
2589 static void __devinit init_vga_switcheroo(struct azx *chip)
2590 {
2591 struct pci_dev *p = get_bound_vga(chip->pci);
2592 if (p) {
2593 snd_printk(KERN_INFO SFX
2594 "%s: Handle VGA-switcheroo audio client\n",
2595 pci_name(chip->pci));
2596 chip->use_vga_switcheroo = 1;
2597 pci_dev_put(p);
2598 }
2599 }
2600
2601 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2602 .set_gpu_state = azx_vs_set_state,
2603 .can_switch = azx_vs_can_switch,
2604 };
2605
2606 static int __devinit register_vga_switcheroo(struct azx *chip)
2607 {
2608 int err;
2609
2610 if (!chip->use_vga_switcheroo)
2611 return 0;
2612 /* FIXME: currently only handling DIS controller
2613 * is there any machine with two switchable HDMI audio controllers?
2614 */
2615 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2616 VGA_SWITCHEROO_DIS,
2617 chip->bus != NULL);
2618 if (err < 0)
2619 return err;
2620 chip->vga_switcheroo_registered = 1;
2621 return 0;
2622 }
2623 #else
2624 #define init_vga_switcheroo(chip) /* NOP */
2625 #define register_vga_switcheroo(chip) 0
2626 #define check_hdmi_disabled(pci) false
2627 #endif /* SUPPORT_VGA_SWITCHER */
2628
2629 /*
2630 * destructor
2631 */
2632 static int azx_free(struct azx *chip)
2633 {
2634 int i;
2635
2636 azx_notifier_unregister(chip);
2637
2638 if (use_vga_switcheroo(chip)) {
2639 if (chip->disabled && chip->bus)
2640 snd_hda_unlock_devices(chip->bus);
2641 if (chip->vga_switcheroo_registered)
2642 vga_switcheroo_unregister_client(chip->pci);
2643 }
2644
2645 if (chip->initialized) {
2646 azx_clear_irq_pending(chip);
2647 for (i = 0; i < chip->num_streams; i++)
2648 azx_stream_stop(chip, &chip->azx_dev[i]);
2649 azx_stop_chip(chip);
2650 }
2651
2652 if (chip->irq >= 0)
2653 free_irq(chip->irq, (void*)chip);
2654 if (chip->msi)
2655 pci_disable_msi(chip->pci);
2656 if (chip->remap_addr)
2657 iounmap(chip->remap_addr);
2658
2659 if (chip->azx_dev) {
2660 for (i = 0; i < chip->num_streams; i++)
2661 if (chip->azx_dev[i].bdl.area) {
2662 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2663 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2664 }
2665 }
2666 if (chip->rb.area) {
2667 mark_pages_wc(chip, &chip->rb, false);
2668 snd_dma_free_pages(&chip->rb);
2669 }
2670 if (chip->posbuf.area) {
2671 mark_pages_wc(chip, &chip->posbuf, false);
2672 snd_dma_free_pages(&chip->posbuf);
2673 }
2674 if (chip->region_requested)
2675 pci_release_regions(chip->pci);
2676 pci_disable_device(chip->pci);
2677 kfree(chip->azx_dev);
2678 kfree(chip);
2679
2680 return 0;
2681 }
2682
2683 static int azx_dev_free(struct snd_device *device)
2684 {
2685 return azx_free(device->device_data);
2686 }
2687
2688 #ifdef SUPPORT_VGA_SWITCHEROO
2689 /*
2690 * Check of disabled HDMI controller by vga-switcheroo
2691 */
2692 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2693 {
2694 struct pci_dev *p;
2695
2696 /* check only discrete GPU */
2697 switch (pci->vendor) {
2698 case PCI_VENDOR_ID_ATI:
2699 case PCI_VENDOR_ID_AMD:
2700 case PCI_VENDOR_ID_NVIDIA:
2701 if (pci->devfn == 1) {
2702 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2703 pci->bus->number, 0);
2704 if (p) {
2705 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2706 return p;
2707 pci_dev_put(p);
2708 }
2709 }
2710 break;
2711 }
2712 return NULL;
2713 }
2714
2715 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2716 {
2717 bool vga_inactive = false;
2718 struct pci_dev *p = get_bound_vga(pci);
2719
2720 if (p) {
2721 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2722 vga_inactive = true;
2723 pci_dev_put(p);
2724 }
2725 return vga_inactive;
2726 }
2727 #endif /* SUPPORT_VGA_SWITCHEROO */
2728
2729 /*
2730 * white/black-listing for position_fix
2731 */
2732 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2733 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2734 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2735 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2736 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2737 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2738 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2739 SND_PCI_QUIRK(0x1043, 0x1ac3, "ASUS X53S", POS_FIX_POSBUF),
2740 SND_PCI_QUIRK(0x1043, 0x1b43, "ASUS K53E", POS_FIX_POSBUF),
2741 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2742 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2743 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2744 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2745 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2746 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2747 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2748 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2749 {}
2750 };
2751
2752 static int __devinit check_position_fix(struct azx *chip, int fix)
2753 {
2754 const struct snd_pci_quirk *q;
2755
2756 switch (fix) {
2757 case POS_FIX_LPIB:
2758 case POS_FIX_POSBUF:
2759 case POS_FIX_VIACOMBO:
2760 case POS_FIX_COMBO:
2761 return fix;
2762 }
2763
2764 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2765 if (q) {
2766 printk(KERN_INFO
2767 "hda_intel: position_fix set to %d "
2768 "for device %04x:%04x\n",
2769 q->value, q->subvendor, q->subdevice);
2770 return q->value;
2771 }
2772
2773 /* Check VIA/ATI HD Audio Controller exist */
2774 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2775 snd_printd(SFX "Using VIACOMBO position fix\n");
2776 return POS_FIX_VIACOMBO;
2777 }
2778 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2779 snd_printd(SFX "Using LPIB position fix\n");
2780 return POS_FIX_LPIB;
2781 }
2782 if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2783 snd_printd(SFX "Using COMBO position fix\n");
2784 return POS_FIX_COMBO;
2785 }
2786 return POS_FIX_AUTO;
2787 }
2788
2789 /*
2790 * black-lists for probe_mask
2791 */
2792 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2793 /* Thinkpad often breaks the controller communication when accessing
2794 * to the non-working (or non-existing) modem codec slot.
2795 */
2796 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2797 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2798 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2799 /* broken BIOS */
2800 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2801 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2802 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2803 /* forced codec slots */
2804 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2805 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2806 /* WinFast VP200 H (Teradici) user reported broken communication */
2807 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2808 {}
2809 };
2810
2811 #define AZX_FORCE_CODEC_MASK 0x100
2812
2813 static void __devinit check_probe_mask(struct azx *chip, int dev)
2814 {
2815 const struct snd_pci_quirk *q;
2816
2817 chip->codec_probe_mask = probe_mask[dev];
2818 if (chip->codec_probe_mask == -1) {
2819 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2820 if (q) {
2821 printk(KERN_INFO
2822 "hda_intel: probe_mask set to 0x%x "
2823 "for device %04x:%04x\n",
2824 q->value, q->subvendor, q->subdevice);
2825 chip->codec_probe_mask = q->value;
2826 }
2827 }
2828
2829 /* check forced option */
2830 if (chip->codec_probe_mask != -1 &&
2831 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2832 chip->codec_mask = chip->codec_probe_mask & 0xff;
2833 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2834 chip->codec_mask);
2835 }
2836 }
2837
2838 /*
2839 * white/black-list for enable_msi
2840 */
2841 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2842 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2843 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2844 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2845 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2846 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2847 {}
2848 };
2849
2850 static void __devinit check_msi(struct azx *chip)
2851 {
2852 const struct snd_pci_quirk *q;
2853
2854 if (enable_msi >= 0) {
2855 chip->msi = !!enable_msi;
2856 return;
2857 }
2858 chip->msi = 1; /* enable MSI as default */
2859 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2860 if (q) {
2861 printk(KERN_INFO
2862 "hda_intel: msi for device %04x:%04x set to %d\n",
2863 q->subvendor, q->subdevice, q->value);
2864 chip->msi = q->value;
2865 return;
2866 }
2867
2868 /* NVidia chipsets seem to cause troubles with MSI */
2869 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2870 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2871 chip->msi = 0;
2872 }
2873 }
2874
2875 /* check the snoop mode availability */
2876 static void __devinit azx_check_snoop_available(struct azx *chip)
2877 {
2878 bool snoop = chip->snoop;
2879
2880 switch (chip->driver_type) {
2881 case AZX_DRIVER_VIA:
2882 /* force to non-snoop mode for a new VIA controller
2883 * when BIOS is set
2884 */
2885 if (snoop) {
2886 u8 val;
2887 pci_read_config_byte(chip->pci, 0x42, &val);
2888 if (!(val & 0x80) && chip->pci->revision == 0x30)
2889 snoop = false;
2890 }
2891 break;
2892 case AZX_DRIVER_ATIHDMI_NS:
2893 /* new ATI HDMI requires non-snoop */
2894 snoop = false;
2895 break;
2896 }
2897
2898 if (snoop != chip->snoop) {
2899 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2900 snoop ? "snoop" : "non-snoop");
2901 chip->snoop = snoop;
2902 }
2903 }
2904
2905 /*
2906 * constructor
2907 */
2908 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2909 int dev, unsigned int driver_caps,
2910 struct azx **rchip)
2911 {
2912 static struct snd_device_ops ops = {
2913 .dev_free = azx_dev_free,
2914 };
2915 struct azx *chip;
2916 int err;
2917
2918 *rchip = NULL;
2919
2920 err = pci_enable_device(pci);
2921 if (err < 0)
2922 return err;
2923
2924 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2925 if (!chip) {
2926 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2927 pci_disable_device(pci);
2928 return -ENOMEM;
2929 }
2930
2931 spin_lock_init(&chip->reg_lock);
2932 mutex_init(&chip->open_mutex);
2933 chip->card = card;
2934 chip->pci = pci;
2935 chip->irq = -1;
2936 chip->driver_caps = driver_caps;
2937 chip->driver_type = driver_caps & 0xff;
2938 check_msi(chip);
2939 chip->dev_index = dev;
2940 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2941 INIT_LIST_HEAD(&chip->pcm_list);
2942 init_vga_switcheroo(chip);
2943
2944 chip->position_fix[0] = chip->position_fix[1] =
2945 check_position_fix(chip, position_fix[dev]);
2946 /* combo mode uses LPIB for playback */
2947 if (chip->position_fix[0] == POS_FIX_COMBO) {
2948 chip->position_fix[0] = POS_FIX_LPIB;
2949 chip->position_fix[1] = POS_FIX_AUTO;
2950 }
2951
2952 check_probe_mask(chip, dev);
2953
2954 chip->single_cmd = single_cmd;
2955 chip->snoop = hda_snoop;
2956 azx_check_snoop_available(chip);
2957
2958 if (bdl_pos_adj[dev] < 0) {
2959 switch (chip->driver_type) {
2960 case AZX_DRIVER_ICH:
2961 case AZX_DRIVER_PCH:
2962 bdl_pos_adj[dev] = 1;
2963 break;
2964 default:
2965 bdl_pos_adj[dev] = 32;
2966 break;
2967 }
2968 }
2969
2970 if (check_hdmi_disabled(pci)) {
2971 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
2972 pci_name(pci));
2973 if (use_vga_switcheroo(chip)) {
2974 snd_printk(KERN_INFO SFX "Delaying initialization\n");
2975 chip->disabled = true;
2976 goto ok;
2977 }
2978 kfree(chip);
2979 pci_disable_device(pci);
2980 return -ENXIO;
2981 }
2982
2983 err = azx_first_init(chip);
2984 if (err < 0) {
2985 azx_free(chip);
2986 return err;
2987 }
2988
2989 ok:
2990 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2991 if (err < 0) {
2992 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2993 azx_free(chip);
2994 return err;
2995 }
2996
2997 *rchip = chip;
2998 return 0;
2999 }
3000
3001 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3002 {
3003 int dev = chip->dev_index;
3004 struct pci_dev *pci = chip->pci;
3005 struct snd_card *card = chip->card;
3006 int i, err;
3007 unsigned short gcap;
3008
3009 #if BITS_PER_LONG != 64
3010 /* Fix up base address on ULI M5461 */
3011 if (chip->driver_type == AZX_DRIVER_ULI) {
3012 u16 tmp3;
3013 pci_read_config_word(pci, 0x40, &tmp3);
3014 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3015 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3016 }
3017 #endif
3018
3019 err = pci_request_regions(pci, "ICH HD audio");
3020 if (err < 0)
3021 return err;
3022 chip->region_requested = 1;
3023
3024 chip->addr = pci_resource_start(pci, 0);
3025 chip->remap_addr = pci_ioremap_bar(pci, 0);
3026 if (chip->remap_addr == NULL) {
3027 snd_printk(KERN_ERR SFX "ioremap error\n");
3028 return -ENXIO;
3029 }
3030
3031 if (chip->msi)
3032 if (pci_enable_msi(pci) < 0)
3033 chip->msi = 0;
3034
3035 if (azx_acquire_irq(chip, 0) < 0)
3036 return -EBUSY;
3037
3038 pci_set_master(pci);
3039 synchronize_irq(chip->irq);
3040
3041 gcap = azx_readw(chip, GCAP);
3042 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3043
3044 /* disable SB600 64bit support for safety */
3045 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3046 struct pci_dev *p_smbus;
3047 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3048 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3049 NULL);
3050 if (p_smbus) {
3051 if (p_smbus->revision < 0x30)
3052 gcap &= ~ICH6_GCAP_64OK;
3053 pci_dev_put(p_smbus);
3054 }
3055 }
3056
3057 /* disable 64bit DMA address on some devices */
3058 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3059 snd_printd(SFX "Disabling 64bit DMA\n");
3060 gcap &= ~ICH6_GCAP_64OK;
3061 }
3062
3063 /* disable buffer size rounding to 128-byte multiples if supported */
3064 if (align_buffer_size >= 0)
3065 chip->align_buffer_size = !!align_buffer_size;
3066 else {
3067 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3068 chip->align_buffer_size = 0;
3069 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3070 chip->align_buffer_size = 1;
3071 else
3072 chip->align_buffer_size = 1;
3073 }
3074
3075 /* allow 64bit DMA address if supported by H/W */
3076 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3077 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3078 else {
3079 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3080 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3081 }
3082
3083 /* read number of streams from GCAP register instead of using
3084 * hardcoded value
3085 */
3086 chip->capture_streams = (gcap >> 8) & 0x0f;
3087 chip->playback_streams = (gcap >> 12) & 0x0f;
3088 if (!chip->playback_streams && !chip->capture_streams) {
3089 /* gcap didn't give any info, switching to old method */
3090
3091 switch (chip->driver_type) {
3092 case AZX_DRIVER_ULI:
3093 chip->playback_streams = ULI_NUM_PLAYBACK;
3094 chip->capture_streams = ULI_NUM_CAPTURE;
3095 break;
3096 case AZX_DRIVER_ATIHDMI:
3097 case AZX_DRIVER_ATIHDMI_NS:
3098 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3099 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3100 break;
3101 case AZX_DRIVER_GENERIC:
3102 default:
3103 chip->playback_streams = ICH6_NUM_PLAYBACK;
3104 chip->capture_streams = ICH6_NUM_CAPTURE;
3105 break;
3106 }
3107 }
3108 chip->capture_index_offset = 0;
3109 chip->playback_index_offset = chip->capture_streams;
3110 chip->num_streams = chip->playback_streams + chip->capture_streams;
3111 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3112 GFP_KERNEL);
3113 if (!chip->azx_dev) {
3114 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3115 return -ENOMEM;
3116 }
3117
3118 for (i = 0; i < chip->num_streams; i++) {
3119 /* allocate memory for the BDL for each stream */
3120 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3121 snd_dma_pci_data(chip->pci),
3122 BDL_SIZE, &chip->azx_dev[i].bdl);
3123 if (err < 0) {
3124 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3125 return -ENOMEM;
3126 }
3127 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3128 }
3129 /* allocate memory for the position buffer */
3130 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3131 snd_dma_pci_data(chip->pci),
3132 chip->num_streams * 8, &chip->posbuf);
3133 if (err < 0) {
3134 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3135 return -ENOMEM;
3136 }
3137 mark_pages_wc(chip, &chip->posbuf, true);
3138 /* allocate CORB/RIRB */
3139 err = azx_alloc_cmd_io(chip);
3140 if (err < 0)
3141 return err;
3142
3143 /* initialize streams */
3144 azx_init_stream(chip);
3145
3146 /* initialize chip */
3147 azx_init_pci(chip);
3148 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3149
3150 /* codec detection */
3151 if (!chip->codec_mask) {
3152 snd_printk(KERN_ERR SFX "no codecs found!\n");
3153 return -ENODEV;
3154 }
3155
3156 strcpy(card->driver, "HDA-Intel");
3157 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3158 sizeof(card->shortname));
3159 snprintf(card->longname, sizeof(card->longname),
3160 "%s at 0x%lx irq %i",
3161 card->shortname, chip->addr, chip->irq);
3162
3163 return 0;
3164 }
3165
3166 static void power_down_all_codecs(struct azx *chip)
3167 {
3168 #ifdef CONFIG_SND_HDA_POWER_SAVE
3169 /* The codecs were powered up in snd_hda_codec_new().
3170 * Now all initialization done, so turn them down if possible
3171 */
3172 struct hda_codec *codec;
3173 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3174 snd_hda_power_down(codec);
3175 }
3176 #endif
3177 }
3178
3179 static int __devinit azx_probe(struct pci_dev *pci,
3180 const struct pci_device_id *pci_id)
3181 {
3182 static int dev;
3183 struct snd_card *card;
3184 struct azx *chip;
3185 int err;
3186
3187 if (dev >= SNDRV_CARDS)
3188 return -ENODEV;
3189 if (!enable[dev]) {
3190 dev++;
3191 return -ENOENT;
3192 }
3193
3194 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3195 if (err < 0) {
3196 snd_printk(KERN_ERR SFX "Error creating card!\n");
3197 return err;
3198 }
3199
3200 /* set this here since it's referred in snd_hda_load_patch() */
3201 snd_card_set_dev(card, &pci->dev);
3202
3203 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3204 if (err < 0)
3205 goto out_free;
3206 card->private_data = chip;
3207
3208 if (!chip->disabled) {
3209 err = azx_probe_continue(chip);
3210 if (err < 0)
3211 goto out_free;
3212 }
3213
3214 pci_set_drvdata(pci, card);
3215
3216 err = register_vga_switcheroo(chip);
3217 if (err < 0) {
3218 snd_printk(KERN_ERR SFX
3219 "Error registering VGA-switcheroo client\n");
3220 goto out_free;
3221 }
3222
3223 dev++;
3224 return 0;
3225
3226 out_free:
3227 snd_card_free(card);
3228 return err;
3229 }
3230
3231 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3232 {
3233 int dev = chip->dev_index;
3234 int err;
3235
3236 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3237 chip->beep_mode = beep_mode[dev];
3238 #endif
3239
3240 /* create codec instances */
3241 err = azx_codec_create(chip, model[dev]);
3242 if (err < 0)
3243 goto out_free;
3244 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3245 if (patch[dev] && *patch[dev]) {
3246 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3247 patch[dev]);
3248 err = snd_hda_load_patch(chip->bus, patch[dev]);
3249 if (err < 0)
3250 goto out_free;
3251 }
3252 #endif
3253 if ((probe_only[dev] & 1) == 0) {
3254 err = azx_codec_configure(chip);
3255 if (err < 0)
3256 goto out_free;
3257 }
3258
3259 /* create PCM streams */
3260 err = snd_hda_build_pcms(chip->bus);
3261 if (err < 0)
3262 goto out_free;
3263
3264 /* create mixer controls */
3265 err = azx_mixer_create(chip);
3266 if (err < 0)
3267 goto out_free;
3268
3269 err = snd_card_register(chip->card);
3270 if (err < 0)
3271 goto out_free;
3272
3273 chip->running = 1;
3274 power_down_all_codecs(chip);
3275 azx_notifier_register(chip);
3276
3277 return 0;
3278
3279 out_free:
3280 chip->init_failed = 1;
3281 return err;
3282 }
3283
3284 static void __devexit azx_remove(struct pci_dev *pci)
3285 {
3286 struct snd_card *card = pci_get_drvdata(pci);
3287 if (card)
3288 snd_card_free(card);
3289 pci_set_drvdata(pci, NULL);
3290 }
3291
3292 /* PCI IDs */
3293 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3294 /* CPT */
3295 { PCI_DEVICE(0x8086, 0x1c20),
3296 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3297 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3298 /* PBG */
3299 { PCI_DEVICE(0x8086, 0x1d20),
3300 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3301 AZX_DCAPS_BUFSIZE},
3302 /* Panther Point */
3303 { PCI_DEVICE(0x8086, 0x1e20),
3304 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3305 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3306 /* Lynx Point */
3307 { PCI_DEVICE(0x8086, 0x8c20),
3308 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3309 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3310 /* Lynx Point-LP */
3311 { PCI_DEVICE(0x8086, 0x9c20),
3312 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3313 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3314 /* Lynx Point-LP */
3315 { PCI_DEVICE(0x8086, 0x9c21),
3316 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3317 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3318 /* Haswell */
3319 { PCI_DEVICE(0x8086, 0x0c0c),
3320 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3321 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3322 { PCI_DEVICE(0x8086, 0x0d0c),
3323 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3324 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3325 /* SCH */
3326 { PCI_DEVICE(0x8086, 0x811b),
3327 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3328 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3329 { PCI_DEVICE(0x8086, 0x080a),
3330 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3331 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3332 /* ICH */
3333 { PCI_DEVICE(0x8086, 0x2668),
3334 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3335 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3336 { PCI_DEVICE(0x8086, 0x27d8),
3337 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3338 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3339 { PCI_DEVICE(0x8086, 0x269a),
3340 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3341 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3342 { PCI_DEVICE(0x8086, 0x284b),
3343 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3344 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3345 { PCI_DEVICE(0x8086, 0x293e),
3346 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3347 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3348 { PCI_DEVICE(0x8086, 0x293f),
3349 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3350 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3351 { PCI_DEVICE(0x8086, 0x3a3e),
3352 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3353 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3354 { PCI_DEVICE(0x8086, 0x3a6e),
3355 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3356 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3357 /* Generic Intel */
3358 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3359 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3360 .class_mask = 0xffffff,
3361 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3362 /* ATI SB 450/600/700/800/900 */
3363 { PCI_DEVICE(0x1002, 0x437b),
3364 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3365 { PCI_DEVICE(0x1002, 0x4383),
3366 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3367 /* AMD Hudson */
3368 { PCI_DEVICE(0x1022, 0x780d),
3369 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3370 /* ATI HDMI */
3371 { PCI_DEVICE(0x1002, 0x793b),
3372 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3373 { PCI_DEVICE(0x1002, 0x7919),
3374 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3375 { PCI_DEVICE(0x1002, 0x960f),
3376 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3377 { PCI_DEVICE(0x1002, 0x970f),
3378 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3379 { PCI_DEVICE(0x1002, 0xaa00),
3380 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3381 { PCI_DEVICE(0x1002, 0xaa08),
3382 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3383 { PCI_DEVICE(0x1002, 0xaa10),
3384 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3385 { PCI_DEVICE(0x1002, 0xaa18),
3386 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3387 { PCI_DEVICE(0x1002, 0xaa20),
3388 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3389 { PCI_DEVICE(0x1002, 0xaa28),
3390 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3391 { PCI_DEVICE(0x1002, 0xaa30),
3392 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3393 { PCI_DEVICE(0x1002, 0xaa38),
3394 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3395 { PCI_DEVICE(0x1002, 0xaa40),
3396 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3397 { PCI_DEVICE(0x1002, 0xaa48),
3398 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3399 { PCI_DEVICE(0x1002, 0x9902),
3400 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3401 { PCI_DEVICE(0x1002, 0xaaa0),
3402 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3403 { PCI_DEVICE(0x1002, 0xaaa8),
3404 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3405 { PCI_DEVICE(0x1002, 0xaab0),
3406 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3407 /* VIA VT8251/VT8237A */
3408 { PCI_DEVICE(0x1106, 0x3288),
3409 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3410 /* VIA GFX VT7122/VX900 */
3411 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3412 /* VIA GFX VT6122/VX11 */
3413 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3414 /* SIS966 */
3415 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3416 /* ULI M5461 */
3417 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3418 /* NVIDIA MCP */
3419 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3420 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3421 .class_mask = 0xffffff,
3422 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3423 /* Teradici */
3424 { PCI_DEVICE(0x6549, 0x1200),
3425 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3426 /* Creative X-Fi (CA0110-IBG) */
3427 /* CTHDA chips */
3428 { PCI_DEVICE(0x1102, 0x0010),
3429 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3430 { PCI_DEVICE(0x1102, 0x0012),
3431 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3432 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3433 /* the following entry conflicts with snd-ctxfi driver,
3434 * as ctxfi driver mutates from HD-audio to native mode with
3435 * a special command sequence.
3436 */
3437 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3438 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3439 .class_mask = 0xffffff,
3440 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3441 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3442 #else
3443 /* this entry seems still valid -- i.e. without emu20kx chip */
3444 { PCI_DEVICE(0x1102, 0x0009),
3445 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3446 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3447 #endif
3448 /* Vortex86MX */
3449 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3450 /* VMware HDAudio */
3451 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3452 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3453 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3454 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3455 .class_mask = 0xffffff,
3456 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3457 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3458 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3459 .class_mask = 0xffffff,
3460 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3461 { 0, }
3462 };
3463 MODULE_DEVICE_TABLE(pci, azx_ids);
3464
3465 /* pci_driver definition */
3466 static struct pci_driver azx_driver = {
3467 .name = KBUILD_MODNAME,
3468 .id_table = azx_ids,
3469 .probe = azx_probe,
3470 .remove = __devexit_p(azx_remove),
3471 .driver = {
3472 .pm = AZX_PM_OPS,
3473 },
3474 };
3475
3476 module_pci_driver(azx_driver);
Linux ARM platform port for MOXA ART SoC