?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86, mrst: use a temporary variable for SFI irq
[linux-btrfs-devel.git] / drivers / ata / sata_inic162x.c
blob5c7d70c03bf00eee62d6efd4b58920c0a6a5d69b
1 /*
2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
3 *
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
6 *
7 * This file is released under GPL v2.
8 *
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
12 *
13 * This driver has interesting history. The first version was written
14 * from the documentation and a 2.4 IDE driver posted on a Taiwan
15 * company, which didn't use any IDMA features and couldn't handle
16 * LBA48. The resulting driver couldn't handle LBA48 devices either
17 * making it pretty useless.
18 *
19 * After a while, initio picked the driver up, renamed it to
20 * sata_initio162x, updated it to use IDMA for ATA DMA commands and
21 * posted it on their website. It only used ATA_PROT_DMA for IDMA and
22 * attaching both devices and issuing IDMA and !IDMA commands
23 * simultaneously broke it due to PIRQ masking interaction but it did
24 * show how to use the IDMA (ADMA + some initio specific twists)
25 * engine.
26 *
27 * Then, I picked up their changes again and here's the usable driver
28 * which uses IDMA for everything. Everything works now including
29 * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some
30 * issues tho. Result Tf is not resported properly, NCQ isn't
31 * supported yet and CD/DVD writing works with DMA assisted PIO
32 * protocol (which, for native SATA devices, shouldn't cause any
33 * noticeable difference).
34 *
35 * Anyways, so, here's finally a working driver for inic162x. Enjoy!
36 *
37 * initio: If you guys wanna improve the driver regarding result TF
38 * access and other stuff, please feel free to contact me. I'll be
39 * happy to assist.
40 */
41
42 #include <linux/gfp.h>
43 #include <linux/kernel.h>
44 #include <linux/module.h>
45 #include <linux/pci.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
48 #include <linux/blkdev.h>
49 #include <scsi/scsi_device.h>
50
51 #define DRV_NAME "sata_inic162x"
52 #define DRV_VERSION "0.4"
53
54 enum {
55 MMIO_BAR_PCI = 5,
56 MMIO_BAR_CARDBUS = 1,
57
58 NR_PORTS = 2,
59
60 IDMA_CPB_TBL_SIZE = 4 * 32,
61
62 INIC_DMA_BOUNDARY = 0xffffff,
63
64 HOST_ACTRL = 0x08,
65 HOST_CTL = 0x7c,
66 HOST_STAT = 0x7e,
67 HOST_IRQ_STAT = 0xbc,
68 HOST_IRQ_MASK = 0xbe,
69
70 PORT_SIZE = 0x40,
71
72 /* registers for ATA TF operation */
73 PORT_TF_DATA = 0x00,
74 PORT_TF_FEATURE = 0x01,
75 PORT_TF_NSECT = 0x02,
76 PORT_TF_LBAL = 0x03,
77 PORT_TF_LBAM = 0x04,
78 PORT_TF_LBAH = 0x05,
79 PORT_TF_DEVICE = 0x06,
80 PORT_TF_COMMAND = 0x07,
81 PORT_TF_ALT_STAT = 0x08,
82 PORT_IRQ_STAT = 0x09,
83 PORT_IRQ_MASK = 0x0a,
84 PORT_PRD_CTL = 0x0b,
85 PORT_PRD_ADDR = 0x0c,
86 PORT_PRD_XFERLEN = 0x10,
87 PORT_CPB_CPBLAR = 0x18,
88 PORT_CPB_PTQFIFO = 0x1c,
89
90 /* IDMA register */
91 PORT_IDMA_CTL = 0x14,
92 PORT_IDMA_STAT = 0x16,
93
94 PORT_RPQ_FIFO = 0x1e,
95 PORT_RPQ_CNT = 0x1f,
96
97 PORT_SCR = 0x20,
98
99 /* HOST_CTL bits */
100 HCTL_LEDEN = (1 << 3), /* enable LED operation */
101 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
102 HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
103 HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
104 HCTL_PWRDWN = (1 << 12), /* power down PHYs */
105 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
106 HCTL_RPGSEL = (1 << 15), /* register page select */
107
108 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
109 HCTL_RPGSEL,
110
111 /* HOST_IRQ_(STAT|MASK) bits */
112 HIRQ_PORT0 = (1 << 0),
113 HIRQ_PORT1 = (1 << 1),
114 HIRQ_SOFT = (1 << 14),
115 HIRQ_GLOBAL = (1 << 15), /* STAT only */
116
117 /* PORT_IRQ_(STAT|MASK) bits */
118 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
119 PIRQ_ONLINE = (1 << 1), /* device plugged */
120 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
121 PIRQ_FATAL = (1 << 3), /* fatal error */
122 PIRQ_ATA = (1 << 4), /* ATA interrupt */
123 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
124 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
125
126 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
127 PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
128 PIRQ_MASK_FREEZE = 0xff,
129
130 /* PORT_PRD_CTL bits */
131 PRD_CTL_START = (1 << 0),
132 PRD_CTL_WR = (1 << 3),
133 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
134
135 /* PORT_IDMA_CTL bits */
136 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
137 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
138 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
139 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
140
141 /* PORT_IDMA_STAT bits */
142 IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
143 IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
144 IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
145 IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
146 IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
147 IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
148 IDMA_STAT_DONE = (1 << 7), /* ADMA done */
149
150 IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
151
152 /* CPB Control Flags*/
153 CPB_CTL_VALID = (1 << 0), /* CPB valid */
154 CPB_CTL_QUEUED = (1 << 1), /* queued command */
155 CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
156 CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
157 CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
158
159 /* CPB Response Flags */
160 CPB_RESP_DONE = (1 << 0), /* ATA command complete */
161 CPB_RESP_REL = (1 << 1), /* ATA release */
162 CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
163 CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
164 CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
165 CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
166 CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
167 CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
168
169 /* PRD Control Flags */
170 PRD_DRAIN = (1 << 1), /* ignore data excess */
171 PRD_CDB = (1 << 2), /* atapi packet command pointer */
172 PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
173 PRD_DMA = (1 << 4), /* data transfer method */
174 PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
175 PRD_IOM = (1 << 6), /* io/memory transfer */
176 PRD_END = (1 << 7), /* APRD chain end */
177 };
178
179 /* Comman Parameter Block */
180 struct inic_cpb {
181 u8 resp_flags; /* Response Flags */
182 u8 error; /* ATA Error */
183 u8 status; /* ATA Status */
184 u8 ctl_flags; /* Control Flags */
185 __le32 len; /* Total Transfer Length */
186 __le32 prd; /* First PRD pointer */
187 u8 rsvd[4];
188 /* 16 bytes */
189 u8 feature; /* ATA Feature */
190 u8 hob_feature; /* ATA Ex. Feature */
191 u8 device; /* ATA Device/Head */
192 u8 mirctl; /* Mirror Control */
193 u8 nsect; /* ATA Sector Count */
194 u8 hob_nsect; /* ATA Ex. Sector Count */
195 u8 lbal; /* ATA Sector Number */
196 u8 hob_lbal; /* ATA Ex. Sector Number */
197 u8 lbam; /* ATA Cylinder Low */
198 u8 hob_lbam; /* ATA Ex. Cylinder Low */
199 u8 lbah; /* ATA Cylinder High */
200 u8 hob_lbah; /* ATA Ex. Cylinder High */
201 u8 command; /* ATA Command */
202 u8 ctl; /* ATA Control */
203 u8 slave_error; /* Slave ATA Error */
204 u8 slave_status; /* Slave ATA Status */
205 /* 32 bytes */
206 } __packed;
207
208 /* Physical Region Descriptor */
209 struct inic_prd {
210 __le32 mad; /* Physical Memory Address */
211 __le16 len; /* Transfer Length */
212 u8 rsvd;
213 u8 flags; /* Control Flags */
214 } __packed;
215
216 struct inic_pkt {
217 struct inic_cpb cpb;
218 struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
219 u8 cdb[ATAPI_CDB_LEN];
220 } __packed;
221
222 struct inic_host_priv {
223 void __iomem *mmio_base;
224 u16 cached_hctl;
225 };
226
227 struct inic_port_priv {
228 struct inic_pkt *pkt;
229 dma_addr_t pkt_dma;
230 u32 *cpb_tbl;
231 dma_addr_t cpb_tbl_dma;
232 };
233
234 static struct scsi_host_template inic_sht = {
235 ATA_BASE_SHT(DRV_NAME),
236 .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
237 .dma_boundary = INIC_DMA_BOUNDARY,
238 };
239
240 static const int scr_map[] = {
241 [SCR_STATUS] = 0,
242 [SCR_ERROR] = 1,
243 [SCR_CONTROL] = 2,
244 };
245
246 static void __iomem *inic_port_base(struct ata_port *ap)
247 {
248 struct inic_host_priv *hpriv = ap->host->private_data;
249
250 return hpriv->mmio_base + ap->port_no * PORT_SIZE;
251 }
252
253 static void inic_reset_port(void __iomem *port_base)
254 {
255 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
256
257 /* stop IDMA engine */
258 readw(idma_ctl); /* flush */
259 msleep(1);
260
261 /* mask IRQ and assert reset */
262 writew(IDMA_CTL_RST_IDMA, idma_ctl);
263 readw(idma_ctl); /* flush */
264 msleep(1);
265
266 /* release reset */
267 writew(0, idma_ctl);
268
269 /* clear irq */
270 writeb(0xff, port_base + PORT_IRQ_STAT);
271 }
272
273 static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
274 {
275 void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
276 void __iomem *addr;
277
278 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
279 return -EINVAL;
280
281 addr = scr_addr + scr_map[sc_reg] * 4;
282 *val = readl(scr_addr + scr_map[sc_reg] * 4);
283
284 /* this controller has stuck DIAG.N, ignore it */
285 if (sc_reg == SCR_ERROR)
286 *val &= ~SERR_PHYRDY_CHG;
287 return 0;
288 }
289
290 static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
291 {
292 void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
293
294 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
295 return -EINVAL;
296
297 writel(val, scr_addr + scr_map[sc_reg] * 4);
298 return 0;
299 }
300
301 static void inic_stop_idma(struct ata_port *ap)
302 {
303 void __iomem *port_base = inic_port_base(ap);
304
305 readb(port_base + PORT_RPQ_FIFO);
306 readb(port_base + PORT_RPQ_CNT);
307 writew(0, port_base + PORT_IDMA_CTL);
308 }
309
310 static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
311 {
312 struct ata_eh_info *ehi = &ap->link.eh_info;
313 struct inic_port_priv *pp = ap->private_data;
314 struct inic_cpb *cpb = &pp->pkt->cpb;
315 bool freeze = false;
316
317 ata_ehi_clear_desc(ehi);
318 ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
319 irq_stat, idma_stat);
320
321 inic_stop_idma(ap);
322
323 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
324 ata_ehi_push_desc(ehi, "hotplug");
325 ata_ehi_hotplugged(ehi);
326 freeze = true;
327 }
328
329 if (idma_stat & IDMA_STAT_PERR) {
330 ata_ehi_push_desc(ehi, "PCI error");
331 freeze = true;
332 }
333
334 if (idma_stat & IDMA_STAT_CPBERR) {
335 ata_ehi_push_desc(ehi, "CPB error");
336
337 if (cpb->resp_flags & CPB_RESP_IGNORED) {
338 __ata_ehi_push_desc(ehi, " ignored");
339 ehi->err_mask |= AC_ERR_INVALID;
340 freeze = true;
341 }
342
343 if (cpb->resp_flags & CPB_RESP_ATA_ERR)
344 ehi->err_mask |= AC_ERR_DEV;
345
346 if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
347 __ata_ehi_push_desc(ehi, " spurious-intr");
348 ehi->err_mask |= AC_ERR_HSM;
349 freeze = true;
350 }
351
352 if (cpb->resp_flags &
353 (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
354 __ata_ehi_push_desc(ehi, " data-over/underflow");
355 ehi->err_mask |= AC_ERR_HSM;
356 freeze = true;
357 }
358 }
359
360 if (freeze)
361 ata_port_freeze(ap);
362 else
363 ata_port_abort(ap);
364 }
365
366 static void inic_host_intr(struct ata_port *ap)
367 {
368 void __iomem *port_base = inic_port_base(ap);
369 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
370 u8 irq_stat;
371 u16 idma_stat;
372
373 /* read and clear IRQ status */
374 irq_stat = readb(port_base + PORT_IRQ_STAT);
375 writeb(irq_stat, port_base + PORT_IRQ_STAT);
376 idma_stat = readw(port_base + PORT_IDMA_STAT);
377
378 if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
379 inic_host_err_intr(ap, irq_stat, idma_stat);
380
381 if (unlikely(!qc))
382 goto spurious;
383
384 if (likely(idma_stat & IDMA_STAT_DONE)) {
385 inic_stop_idma(ap);
386
387 /* Depending on circumstances, device error
388 * isn't reported by IDMA, check it explicitly.
389 */
390 if (unlikely(readb(port_base + PORT_TF_COMMAND) &
391 (ATA_DF | ATA_ERR)))
392 qc->err_mask |= AC_ERR_DEV;
393
394 ata_qc_complete(qc);
395 return;
396 }
397
398 spurious:
399 ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
400 qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
401 }
402
403 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
404 {
405 struct ata_host *host = dev_instance;
406 struct inic_host_priv *hpriv = host->private_data;
407 u16 host_irq_stat;
408 int i, handled = 0;
409
410 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
411
412 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
413 goto out;
414
415 spin_lock(&host->lock);
416
417 for (i = 0; i < NR_PORTS; i++)
418 if (host_irq_stat & (HIRQ_PORT0 << i)) {
419 inic_host_intr(host->ports[i]);
420 handled++;
421 }
422
423 spin_unlock(&host->lock);
424
425 out:
426 return IRQ_RETVAL(handled);
427 }
428
429 static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
430 {
431 /* For some reason ATAPI_PROT_DMA doesn't work for some
432 * commands including writes and other misc ops. Use PIO
433 * protocol instead, which BTW is driven by the DMA engine
434 * anyway, so it shouldn't make much difference for native
435 * SATA devices.
436 */
437 if (atapi_cmd_type(qc->cdb[0]) == READ)
438 return 0;
439 return 1;
440 }
441
442 static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
443 {
444 struct scatterlist *sg;
445 unsigned int si;
446 u8 flags = 0;
447
448 if (qc->tf.flags & ATA_TFLAG_WRITE)
449 flags |= PRD_WRITE;
450
451 if (ata_is_dma(qc->tf.protocol))
452 flags |= PRD_DMA;
453
454 for_each_sg(qc->sg, sg, qc->n_elem, si) {
455 prd->mad = cpu_to_le32(sg_dma_address(sg));
456 prd->len = cpu_to_le16(sg_dma_len(sg));
457 prd->flags = flags;
458 prd++;
459 }
460
461 WARN_ON(!si);
462 prd[-1].flags |= PRD_END;
463 }
464
465 static void inic_qc_prep(struct ata_queued_cmd *qc)
466 {
467 struct inic_port_priv *pp = qc->ap->private_data;
468 struct inic_pkt *pkt = pp->pkt;
469 struct inic_cpb *cpb = &pkt->cpb;
470 struct inic_prd *prd = pkt->prd;
471 bool is_atapi = ata_is_atapi(qc->tf.protocol);
472 bool is_data = ata_is_data(qc->tf.protocol);
473 unsigned int cdb_len = 0;
474
475 VPRINTK("ENTER\n");
476
477 if (is_atapi)
478 cdb_len = qc->dev->cdb_len;
479
480 /* prepare packet, based on initio driver */
481 memset(pkt, 0, sizeof(struct inic_pkt));
482
483 cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
484 if (is_atapi || is_data)
485 cpb->ctl_flags |= CPB_CTL_DATA;
486
487 cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
488 cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
489
490 cpb->device = qc->tf.device;
491 cpb->feature = qc->tf.feature;
492 cpb->nsect = qc->tf.nsect;
493 cpb->lbal = qc->tf.lbal;
494 cpb->lbam = qc->tf.lbam;
495 cpb->lbah = qc->tf.lbah;
496
497 if (qc->tf.flags & ATA_TFLAG_LBA48) {
498 cpb->hob_feature = qc->tf.hob_feature;
499 cpb->hob_nsect = qc->tf.hob_nsect;
500 cpb->hob_lbal = qc->tf.hob_lbal;
501 cpb->hob_lbam = qc->tf.hob_lbam;
502 cpb->hob_lbah = qc->tf.hob_lbah;
503 }
504
505 cpb->command = qc->tf.command;
506 /* don't load ctl - dunno why. it's like that in the initio driver */
507
508 /* setup PRD for CDB */
509 if (is_atapi) {
510 memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
511 prd->mad = cpu_to_le32(pp->pkt_dma +
512 offsetof(struct inic_pkt, cdb));
513 prd->len = cpu_to_le16(cdb_len);
514 prd->flags = PRD_CDB | PRD_WRITE;
515 if (!is_data)
516 prd->flags |= PRD_END;
517 prd++;
518 }
519
520 /* setup sg table */
521 if (is_data)
522 inic_fill_sg(prd, qc);
523
524 pp->cpb_tbl[0] = pp->pkt_dma;
525 }
526
527 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
528 {
529 struct ata_port *ap = qc->ap;
530 void __iomem *port_base = inic_port_base(ap);
531
532 /* fire up the ADMA engine */
533 writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
534 writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
535 writeb(0, port_base + PORT_CPB_PTQFIFO);
536
537 return 0;
538 }
539
540 static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
541 {
542 void __iomem *port_base = inic_port_base(ap);
543
544 tf->feature = readb(port_base + PORT_TF_FEATURE);
545 tf->nsect = readb(port_base + PORT_TF_NSECT);
546 tf->lbal = readb(port_base + PORT_TF_LBAL);
547 tf->lbam = readb(port_base + PORT_TF_LBAM);
548 tf->lbah = readb(port_base + PORT_TF_LBAH);
549 tf->device = readb(port_base + PORT_TF_DEVICE);
550 tf->command = readb(port_base + PORT_TF_COMMAND);
551 }
552
553 static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
554 {
555 struct ata_taskfile *rtf = &qc->result_tf;
556 struct ata_taskfile tf;
557
558 /* FIXME: Except for status and error, result TF access
559 * doesn't work. I tried reading from BAR0/2, CPB and BAR5.
560 * None works regardless of which command interface is used.
561 * For now return true iff status indicates device error.
562 * This means that we're reporting bogus sector for RW
563 * failures. Eeekk....
564 */
565 inic_tf_read(qc->ap, &tf);
566
567 if (!(tf.command & ATA_ERR))
568 return false;
569
570 rtf->command = tf.command;
571 rtf->feature = tf.feature;
572 return true;
573 }
574
575 static void inic_freeze(struct ata_port *ap)
576 {
577 void __iomem *port_base = inic_port_base(ap);
578
579 writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
580 writeb(0xff, port_base + PORT_IRQ_STAT);
581 }
582
583 static void inic_thaw(struct ata_port *ap)
584 {
585 void __iomem *port_base = inic_port_base(ap);
586
587 writeb(0xff, port_base + PORT_IRQ_STAT);
588 writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
589 }
590
591 static int inic_check_ready(struct ata_link *link)
592 {
593 void __iomem *port_base = inic_port_base(link->ap);
594
595 return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
596 }
597
598 /*
599 * SRST and SControl hardreset don't give valid signature on this
600 * controller. Only controller specific hardreset mechanism works.
601 */
602 static int inic_hardreset(struct ata_link *link, unsigned int *class,
603 unsigned long deadline)
604 {
605 struct ata_port *ap = link->ap;
606 void __iomem *port_base = inic_port_base(ap);
607 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
608 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
609 int rc;
610
611 /* hammer it into sane state */
612 inic_reset_port(port_base);
613
614 writew(IDMA_CTL_RST_ATA, idma_ctl);
615 readw(idma_ctl); /* flush */
616 ata_msleep(ap, 1);
617 writew(0, idma_ctl);
618
619 rc = sata_link_resume(link, timing, deadline);
620 if (rc) {
621 ata_link_warn(link,
622 "failed to resume link after reset (errno=%d)\n",
623 rc);
624 return rc;
625 }
626
627 *class = ATA_DEV_NONE;
628 if (ata_link_online(link)) {
629 struct ata_taskfile tf;
630
631 /* wait for link to become ready */
632 rc = ata_wait_after_reset(link, deadline, inic_check_ready);
633 /* link occupied, -ENODEV too is an error */
634 if (rc) {
635 ata_link_warn(link,
636 "device not ready after hardreset (errno=%d)\n",
637 rc);
638 return rc;
639 }
640
641 inic_tf_read(ap, &tf);
642 *class = ata_dev_classify(&tf);
643 }
644
645 return 0;
646 }
647
648 static void inic_error_handler(struct ata_port *ap)
649 {
650 void __iomem *port_base = inic_port_base(ap);
651
652 inic_reset_port(port_base);
653 ata_std_error_handler(ap);
654 }
655
656 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
657 {
658 /* make DMA engine forget about the failed command */
659 if (qc->flags & ATA_QCFLAG_FAILED)
660 inic_reset_port(inic_port_base(qc->ap));
661 }
662
663 static void init_port(struct ata_port *ap)
664 {
665 void __iomem *port_base = inic_port_base(ap);
666 struct inic_port_priv *pp = ap->private_data;
667
668 /* clear packet and CPB table */
669 memset(pp->pkt, 0, sizeof(struct inic_pkt));
670 memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
671
672 /* setup CPB lookup table addresses */
673 writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
674 }
675
676 static int inic_port_resume(struct ata_port *ap)
677 {
678 init_port(ap);
679 return 0;
680 }
681
682 static int inic_port_start(struct ata_port *ap)
683 {
684 struct device *dev = ap->host->dev;
685 struct inic_port_priv *pp;
686
687 /* alloc and initialize private data */
688 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
689 if (!pp)
690 return -ENOMEM;
691 ap->private_data = pp;
692
693 /* Alloc resources */
694 pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
695 &pp->pkt_dma, GFP_KERNEL);
696 if (!pp->pkt)
697 return -ENOMEM;
698
699 pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
700 &pp->cpb_tbl_dma, GFP_KERNEL);
701 if (!pp->cpb_tbl)
702 return -ENOMEM;
703
704 init_port(ap);
705
706 return 0;
707 }
708
709 static struct ata_port_operations inic_port_ops = {
710 .inherits = &sata_port_ops,
711
712 .check_atapi_dma = inic_check_atapi_dma,
713 .qc_prep = inic_qc_prep,
714 .qc_issue = inic_qc_issue,
715 .qc_fill_rtf = inic_qc_fill_rtf,
716
717 .freeze = inic_freeze,
718 .thaw = inic_thaw,
719 .hardreset = inic_hardreset,
720 .error_handler = inic_error_handler,
721 .post_internal_cmd = inic_post_internal_cmd,
722
723 .scr_read = inic_scr_read,
724 .scr_write = inic_scr_write,
725
726 .port_resume = inic_port_resume,
727 .port_start = inic_port_start,
728 };
729
730 static struct ata_port_info inic_port_info = {
731 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
732 .pio_mask = ATA_PIO4,
733 .mwdma_mask = ATA_MWDMA2,
734 .udma_mask = ATA_UDMA6,
735 .port_ops = &inic_port_ops
736 };
737
738 static int init_controller(void __iomem *mmio_base, u16 hctl)
739 {
740 int i;
741 u16 val;
742
743 hctl &= ~HCTL_KNOWN_BITS;
744
745 /* Soft reset whole controller. Spec says reset duration is 3
746 * PCI clocks, be generous and give it 10ms.
747 */
748 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
749 readw(mmio_base + HOST_CTL); /* flush */
750
751 for (i = 0; i < 10; i++) {
752 msleep(1);
753 val = readw(mmio_base + HOST_CTL);
754 if (!(val & HCTL_SOFTRST))
755 break;
756 }
757
758 if (val & HCTL_SOFTRST)
759 return -EIO;
760
761 /* mask all interrupts and reset ports */
762 for (i = 0; i < NR_PORTS; i++) {
763 void __iomem *port_base = mmio_base + i * PORT_SIZE;
764
765 writeb(0xff, port_base + PORT_IRQ_MASK);
766 inic_reset_port(port_base);
767 }
768
769 /* port IRQ is masked now, unmask global IRQ */
770 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
771 val = readw(mmio_base + HOST_IRQ_MASK);
772 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
773 writew(val, mmio_base + HOST_IRQ_MASK);
774
775 return 0;
776 }
777
778 #ifdef CONFIG_PM
779 static int inic_pci_device_resume(struct pci_dev *pdev)
780 {
781 struct ata_host *host = dev_get_drvdata(&pdev->dev);
782 struct inic_host_priv *hpriv = host->private_data;
783 int rc;
784
785 rc = ata_pci_device_do_resume(pdev);
786 if (rc)
787 return rc;
788
789 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
790 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
791 if (rc)
792 return rc;
793 }
794
795 ata_host_resume(host);
796
797 return 0;
798 }
799 #endif
800
801 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
802 {
803 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
804 struct ata_host *host;
805 struct inic_host_priv *hpriv;
806 void __iomem * const *iomap;
807 int mmio_bar;
808 int i, rc;
809
810 ata_print_version_once(&pdev->dev, DRV_VERSION);
811
812 /* alloc host */
813 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
814 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
815 if (!host || !hpriv)
816 return -ENOMEM;
817
818 host->private_data = hpriv;
819
820 /* Acquire resources and fill host. Note that PCI and cardbus
821 * use different BARs.
822 */
823 rc = pcim_enable_device(pdev);
824 if (rc)
825 return rc;
826
827 if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
828 mmio_bar = MMIO_BAR_PCI;
829 else
830 mmio_bar = MMIO_BAR_CARDBUS;
831
832 rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
833 if (rc)
834 return rc;
835 host->iomap = iomap = pcim_iomap_table(pdev);
836 hpriv->mmio_base = iomap[mmio_bar];
837 hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
838
839 for (i = 0; i < NR_PORTS; i++) {
840 struct ata_port *ap = host->ports[i];
841
842 ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
843 ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
844 }
845
846 /* Set dma_mask. This devices doesn't support 64bit addressing. */
847 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
848 if (rc) {
849 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
850 return rc;
851 }
852
853 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
854 if (rc) {
855 dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
856 return rc;
857 }
858
859 /*
860 * This controller is braindamaged. dma_boundary is 0xffff
861 * like others but it will lock up the whole machine HARD if
862 * 65536 byte PRD entry is fed. Reduce maximum segment size.
863 */
864 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
865 if (rc) {
866 dev_err(&pdev->dev, "failed to set the maximum segment size\n");
867 return rc;
868 }
869
870 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
871 if (rc) {
872 dev_err(&pdev->dev, "failed to initialize controller\n");
873 return rc;
874 }
875
876 pci_set_master(pdev);
877 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
878 &inic_sht);
879 }
880
881 static const struct pci_device_id inic_pci_tbl[] = {
882 { PCI_VDEVICE(INIT, 0x1622), },
883 { },
884 };
885
886 static struct pci_driver inic_pci_driver = {
887 .name = DRV_NAME,
888 .id_table = inic_pci_tbl,
889 #ifdef CONFIG_PM
890 .suspend = ata_pci_device_suspend,
891 .resume = inic_pci_device_resume,
892 #endif
893 .probe = inic_init_one,
894 .remove = ata_pci_remove_one,
895 };
896
897 static int __init inic_init(void)
898 {
899 return pci_register_driver(&inic_pci_driver);
900 }
901
902 static void __exit inic_exit(void)
903 {
904 pci_unregister_driver(&inic_pci_driver);
905 }
906
907 MODULE_AUTHOR("Tejun Heo");
908 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
909 MODULE_LICENSE("GPL v2");
910 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
911 MODULE_VERSION(DRV_VERSION);
912
913 module_init(inic_init);
914 module_exit(inic_exit);
Linux Btrfs Development