2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
4 * Copyright (C) 2003-2007 Micronas
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
33 #include "dvb_frontend.h"
35 #include "drxd_firm.h"
37 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
38 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
42 #define DRX_I2C_RMW 0x10
43 #define DRX_I2C_BROADCAST 0x20
44 #define DRX_I2C_CLEARCRC 0x80
45 #define DRX_I2C_SINGLE_MASTER 0xC0
46 #define DRX_I2C_MODEFLAGS 0xC0
47 #define DRX_I2C_FLAGS 0xF0
50 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
53 #define DEFAULT_LOCK_TIMEOUT 1100
55 #define DRX_CHANNEL_AUTO 0
56 #define DRX_CHANNEL_HIGH 1
57 #define DRX_CHANNEL_LOW 2
59 #define DRX_LOCK_MPEG 1
60 #define DRX_LOCK_FEC 2
61 #define DRX_LOCK_DEMOD 4
63 /****************************************************************************/
72 DRXD_UNINITIALIZED
= 0,
85 OM_DVBT_Diversity_Front
,
90 enum AGC_CTRL_MODE ctrlMode
;
91 u16 outputLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
92 u16 settleLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
93 u16 minOutputLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
94 u16 maxOutputLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
95 u16 speed
; /* range [0, ... , 1023], 1/n of fullscale range */
117 IFFILTER_DISCRETE
= 1
121 struct dvb_frontend frontend
;
122 struct dvb_frontend_ops ops
;
123 struct dvb_frontend_parameters param
;
125 const struct firmware
*fw
;
128 struct i2c_adapter
*i2c
;
130 struct drxd_config config
;
137 u16 hi_cfg_timing_div
;
138 u16 hi_cfg_bridge_delay
;
139 u16 hi_cfg_wakeup_key
;
142 u16 intermediate_freq
;
145 enum CSCDState cscd_state
;
146 enum CDrxdState drxd_state
;
149 s16 osc_clock_deviation
;
150 u16 expected_sys_clock_freq
;
157 struct SCfgAgc if_agc_cfg
;
158 struct SCfgAgc rf_agc_cfg
;
160 struct SNoiseCal noise_cal
;
163 u32 org_fe_fs_add_incr
;
164 u16 current_fe_if_incr
;
167 u16 m_FeAgRegAgAgcSio
;
169 u16 m_EcOcRegOcModeLop
;
170 u16 m_EcOcRegSncSncLvl
;
171 u8
*m_InitAtomicRead
;
183 u8
*m_InitDiversityFront
;
184 u8
*m_InitDiversityEnd
;
185 u8
*m_DisableDiversity
;
186 u8
*m_StartDiversityFront
;
187 u8
*m_StartDiversityEnd
;
189 u8
*m_DiversityDelay8MHZ
;
190 u8
*m_DiversityDelay6MHZ
;
193 u32 microcode_length
;
200 enum app_env app_env_default
;
201 enum app_env app_env_diversity
;
205 /****************************************************************************/
206 /* I2C **********************************************************************/
207 /****************************************************************************/
209 static int i2c_write(struct i2c_adapter
*adap
, u8 adr
, u8
* data
, int len
)
211 struct i2c_msg msg
= {.addr
= adr
, .flags
= 0, .buf
= data
, .len
= len
};
213 if (i2c_transfer(adap
, &msg
, 1) != 1)
218 static int i2c_read(struct i2c_adapter
*adap
,
219 u8 adr
, u8
*msg
, int len
, u8
*answ
, int alen
)
221 struct i2c_msg msgs
[2] = {
223 .addr
= adr
, .flags
= 0,
224 .buf
= msg
, .len
= len
226 .addr
= adr
, .flags
= I2C_M_RD
,
227 .buf
= answ
, .len
= alen
230 if (i2c_transfer(adap
, msgs
, 2) != 2)
235 static inline u32
MulDiv32(u32 a
, u32 b
, u32 c
)
239 tmp64
= (u64
)a
* (u64
)b
;
245 static int Read16(struct drxd_state
*state
, u32 reg
, u16
*data
, u8 flags
)
247 u8 adr
= state
->config
.demod_address
;
248 u8 mm1
[4] = { reg
& 0xff, (reg
>> 16) & 0xff,
249 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff
252 if (i2c_read(state
->i2c
, adr
, mm1
, 4, mm2
, 2) < 0)
255 *data
= mm2
[0] | (mm2
[1] << 8);
256 return mm2
[0] | (mm2
[1] << 8);
259 static int Read32(struct drxd_state
*state
, u32 reg
, u32
*data
, u8 flags
)
261 u8 adr
= state
->config
.demod_address
;
262 u8 mm1
[4] = { reg
& 0xff, (reg
>> 16) & 0xff,
263 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff
267 if (i2c_read(state
->i2c
, adr
, mm1
, 4, mm2
, 4) < 0)
271 mm2
[0] | (mm2
[1] << 8) | (mm2
[2] << 16) | (mm2
[3] << 24);
275 static int Write16(struct drxd_state
*state
, u32 reg
, u16 data
, u8 flags
)
277 u8 adr
= state
->config
.demod_address
;
278 u8 mm
[6] = { reg
& 0xff, (reg
>> 16) & 0xff,
279 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff,
280 data
& 0xff, (data
>> 8) & 0xff
283 if (i2c_write(state
->i2c
, adr
, mm
, 6) < 0)
288 static int Write32(struct drxd_state
*state
, u32 reg
, u32 data
, u8 flags
)
290 u8 adr
= state
->config
.demod_address
;
291 u8 mm
[8] = { reg
& 0xff, (reg
>> 16) & 0xff,
292 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff,
293 data
& 0xff, (data
>> 8) & 0xff,
294 (data
>> 16) & 0xff, (data
>> 24) & 0xff
297 if (i2c_write(state
->i2c
, adr
, mm
, 8) < 0)
302 static int write_chunk(struct drxd_state
*state
,
303 u32 reg
, u8
*data
, u32 len
, u8 flags
)
305 u8 adr
= state
->config
.demod_address
;
306 u8 mm
[CHUNK_SIZE
+ 4] = { reg
& 0xff, (reg
>> 16) & 0xff,
307 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff
311 for (i
= 0; i
< len
; i
++)
313 if (i2c_write(state
->i2c
, adr
, mm
, 4 + len
) < 0) {
314 printk(KERN_ERR
"error in write_chunk\n");
320 static int WriteBlock(struct drxd_state
*state
,
321 u32 Address
, u16 BlockSize
, u8
*pBlock
, u8 Flags
)
323 while (BlockSize
> 0) {
324 u16 Chunk
= BlockSize
> CHUNK_SIZE
? CHUNK_SIZE
: BlockSize
;
326 if (write_chunk(state
, Address
, pBlock
, Chunk
, Flags
) < 0)
329 Address
+= (Chunk
>> 1);
335 static int WriteTable(struct drxd_state
*state
, u8
* pTable
)
344 u32 Address
= pTable
[0] | (pTable
[1] << 8) |
345 (pTable
[2] << 16) | (pTable
[3] << 24);
347 if (Address
== 0xFFFFFFFF)
349 pTable
+= sizeof(u32
);
351 Length
= pTable
[0] | (pTable
[1] << 8);
352 pTable
+= sizeof(u16
);
355 status
= WriteBlock(state
, Address
, Length
* 2, pTable
, 0);
356 pTable
+= (Length
* 2);
361 /****************************************************************************/
362 /****************************************************************************/
363 /****************************************************************************/
365 static int ResetCEFR(struct drxd_state
*state
)
367 return WriteTable(state
, state
->m_ResetCEFR
);
370 static int InitCP(struct drxd_state
*state
)
372 return WriteTable(state
, state
->m_InitCP
);
375 static int InitCE(struct drxd_state
*state
)
378 enum app_env AppEnv
= state
->app_env_default
;
381 status
= WriteTable(state
, state
->m_InitCE
);
385 if (state
->operation_mode
== OM_DVBT_Diversity_Front
||
386 state
->operation_mode
== OM_DVBT_Diversity_End
) {
387 AppEnv
= state
->app_env_diversity
;
389 if (AppEnv
== APPENV_STATIC
) {
390 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0000, 0);
393 } else if (AppEnv
== APPENV_PORTABLE
) {
394 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0001, 0);
397 } else if (AppEnv
== APPENV_MOBILE
&& state
->type_A
) {
398 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0002, 0);
401 } else if (AppEnv
== APPENV_MOBILE
&& !state
->type_A
) {
402 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0006, 0);
408 status
= Write16(state
, B_CE_REG_COMM_EXEC__A
, 0x0001, 0);
415 static int StopOC(struct drxd_state
*state
)
419 u16 ocModeLop
= state
->m_EcOcRegOcModeLop
;
424 /* Store output configuration */
425 status
= Read16(state
, EC_OC_REG_SNC_ISC_LVL__A
, &ocSyncLvl
, 0);
428 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
429 state
->m_EcOcRegSncSncLvl
= ocSyncLvl
;
430 /* m_EcOcRegOcModeLop = ocModeLop; */
432 /* Flush FIFO (byte-boundary) at fixed rate */
433 status
= Read16(state
, EC_OC_REG_RCN_MAP_LOP__A
, &dtoIncLop
, 0);
436 status
= Read16(state
, EC_OC_REG_RCN_MAP_HIP__A
, &dtoIncHip
, 0);
439 status
= Write16(state
, EC_OC_REG_DTO_INC_LOP__A
, dtoIncLop
, 0);
442 status
= Write16(state
, EC_OC_REG_DTO_INC_HIP__A
, dtoIncHip
, 0);
445 ocModeLop
&= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M
);
446 ocModeLop
|= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC
;
447 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, ocModeLop
, 0);
450 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_HOLD
, 0);
455 /* Output pins to '0' */
456 status
= Write16(state
, EC_OC_REG_OCR_MPG_UOS__A
, EC_OC_REG_OCR_MPG_UOS__M
, 0);
460 /* Force the OC out of sync */
461 ocSyncLvl
&= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M
);
462 status
= Write16(state
, EC_OC_REG_SNC_ISC_LVL__A
, ocSyncLvl
, 0);
465 ocModeLop
&= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M
);
466 ocModeLop
|= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE
;
467 ocModeLop
|= 0x2; /* Magically-out-of-sync */
468 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, ocModeLop
, 0);
471 status
= Write16(state
, EC_OC_REG_COMM_INT_STA__A
, 0x0, 0);
474 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_ACTIVE
, 0);
482 static int StartOC(struct drxd_state
*state
)
488 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_HOLD
, 0);
492 /* Restore output configuration */
493 status
= Write16(state
, EC_OC_REG_SNC_ISC_LVL__A
, state
->m_EcOcRegSncSncLvl
, 0);
496 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, state
->m_EcOcRegOcModeLop
, 0);
500 /* Output pins active again */
501 status
= Write16(state
, EC_OC_REG_OCR_MPG_UOS__A
, EC_OC_REG_OCR_MPG_UOS_INIT
, 0);
506 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_ACTIVE
, 0);
513 static int InitEQ(struct drxd_state
*state
)
515 return WriteTable(state
, state
->m_InitEQ
);
518 static int InitEC(struct drxd_state
*state
)
520 return WriteTable(state
, state
->m_InitEC
);
523 static int InitSC(struct drxd_state
*state
)
525 return WriteTable(state
, state
->m_InitSC
);
528 static int InitAtomicRead(struct drxd_state
*state
)
530 return WriteTable(state
, state
->m_InitAtomicRead
);
533 static int CorrectSysClockDeviation(struct drxd_state
*state
);
535 static int DRX_GetLockStatus(struct drxd_state
*state
, u32
* pLockStatus
)
538 const u16 mpeg_lock_mask
= (SC_RA_RAM_LOCK_MPEG__M
|
539 SC_RA_RAM_LOCK_FEC__M
|
540 SC_RA_RAM_LOCK_DEMOD__M
);
541 const u16 fec_lock_mask
= (SC_RA_RAM_LOCK_FEC__M
|
542 SC_RA_RAM_LOCK_DEMOD__M
);
543 const u16 demod_lock_mask
= SC_RA_RAM_LOCK_DEMOD__M
;
549 status
= Read16(state
, SC_RA_RAM_LOCK__A
, &ScRaRamLock
, 0x0000);
551 printk(KERN_ERR
"Can't read SC_RA_RAM_LOCK__A status = %08x\n", status
);
555 if (state
->drxd_state
!= DRXD_STARTED
)
558 if ((ScRaRamLock
& mpeg_lock_mask
) == mpeg_lock_mask
) {
559 *pLockStatus
|= DRX_LOCK_MPEG
;
560 CorrectSysClockDeviation(state
);
563 if ((ScRaRamLock
& fec_lock_mask
) == fec_lock_mask
)
564 *pLockStatus
|= DRX_LOCK_FEC
;
566 if ((ScRaRamLock
& demod_lock_mask
) == demod_lock_mask
)
567 *pLockStatus
|= DRX_LOCK_DEMOD
;
571 /****************************************************************************/
573 static int SetCfgIfAgc(struct drxd_state
*state
, struct SCfgAgc
*cfg
)
577 if (cfg
->outputLevel
> DRXD_FE_CTRL_MAX
)
580 if (cfg
->ctrlMode
== AGC_CTRL_USER
) {
582 u16 FeAgRegPm1AgcWri
;
583 u16 FeAgRegAgModeLop
;
585 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &FeAgRegAgModeLop
, 0);
588 FeAgRegAgModeLop
&= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M
);
589 FeAgRegAgModeLop
|= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC
;
590 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, FeAgRegAgModeLop
, 0);
594 FeAgRegPm1AgcWri
= (u16
) (cfg
->outputLevel
&
595 FE_AG_REG_PM1_AGC_WRI__M
);
596 status
= Write16(state
, FE_AG_REG_PM1_AGC_WRI__A
, FeAgRegPm1AgcWri
, 0);
600 } else if (cfg
->ctrlMode
== AGC_CTRL_AUTO
) {
601 if (((cfg
->maxOutputLevel
) < (cfg
->minOutputLevel
)) ||
602 ((cfg
->maxOutputLevel
) > DRXD_FE_CTRL_MAX
) ||
603 ((cfg
->speed
) > DRXD_FE_CTRL_MAX
) ||
604 ((cfg
->settleLevel
) > DRXD_FE_CTRL_MAX
)
608 u16 FeAgRegAgModeLop
;
609 u16 FeAgRegEgcSetLvl
;
614 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &FeAgRegAgModeLop
, 0);
617 FeAgRegAgModeLop
&= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M
);
619 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC
;
620 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, FeAgRegAgModeLop
, 0);
624 /* == Settle level == */
626 FeAgRegEgcSetLvl
= (u16
) ((cfg
->settleLevel
>> 1) &
627 FE_AG_REG_EGC_SET_LVL__M
);
628 status
= Write16(state
, FE_AG_REG_EGC_SET_LVL__A
, FeAgRegEgcSetLvl
, 0);
634 slope
= (u16
) ((cfg
->maxOutputLevel
-
635 cfg
->minOutputLevel
) / 2);
636 offset
= (u16
) ((cfg
->maxOutputLevel
+
637 cfg
->minOutputLevel
) / 2 - 511);
639 status
= Write16(state
, FE_AG_REG_GC1_AGC_RIC__A
, slope
, 0);
642 status
= Write16(state
, FE_AG_REG_GC1_AGC_OFF__A
, offset
, 0);
648 const u16 maxRur
= 8;
649 const u16 slowIncrDecLUT
[] = { 3, 4, 4, 5, 6 };
650 const u16 fastIncrDecLUT
[] = { 14, 15, 15, 16,
657 u16 fineSteps
= (DRXD_FE_CTRL_MAX
+ 1) /
659 u16 fineSpeed
= (u16
) (cfg
->speed
-
663 u16 invRurCount
= (u16
) (cfg
->speed
/
666 if (invRurCount
> maxRur
) {
668 fineSpeed
+= fineSteps
;
670 rurCount
= maxRur
- invRurCount
;
675 (2^(fineSpeed/fineSteps))
676 => range[default...2*default>
678 (2^(fineSpeed/fineSteps))
682 fastIncrDecLUT
[fineSpeed
/
686 slowIncrDecLUT
[fineSpeed
/
690 status
= Write16(state
, FE_AG_REG_EGC_RUR_CNT__A
, rurCount
, 0);
693 status
= Write16(state
, FE_AG_REG_EGC_FAS_INC__A
, fastIncrDec
, 0);
696 status
= Write16(state
, FE_AG_REG_EGC_FAS_DEC__A
, fastIncrDec
, 0);
699 status
= Write16(state
, FE_AG_REG_EGC_SLO_INC__A
, slowIncrDec
, 0);
702 status
= Write16(state
, FE_AG_REG_EGC_SLO_DEC__A
, slowIncrDec
, 0);
710 /* No OFF mode for IF control */
716 static int SetCfgRfAgc(struct drxd_state
*state
, struct SCfgAgc
*cfg
)
720 if (cfg
->outputLevel
> DRXD_FE_CTRL_MAX
)
723 if (cfg
->ctrlMode
== AGC_CTRL_USER
) {
726 u16 level
= (cfg
->outputLevel
);
728 if (level
== DRXD_FE_CTRL_MAX
)
731 status
= Write16(state
, FE_AG_REG_PM2_AGC_WRI__A
, level
, 0x0000);
737 /* Powerdown PD2, WRI source */
738 state
->m_FeAgRegAgPwd
&= ~(FE_AG_REG_AG_PWD_PWD_PD2__M
);
739 state
->m_FeAgRegAgPwd
|=
740 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE
;
741 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, state
->m_FeAgRegAgPwd
, 0x0000);
745 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
748 AgModeLop
&= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M
|
749 FE_AG_REG_AG_MODE_LOP_MODE_E__M
));
750 AgModeLop
|= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
|
751 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC
);
752 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
756 /* enable AGC2 pin */
758 u16 FeAgRegAgAgcSio
= 0;
759 status
= Read16(state
, FE_AG_REG_AG_AGC_SIO__A
, &FeAgRegAgAgcSio
, 0x0000);
763 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
);
765 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT
;
766 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, FeAgRegAgAgcSio
, 0x0000);
772 } else if (cfg
->ctrlMode
== AGC_CTRL_AUTO
) {
777 /* Automatic control */
778 /* Powerup PD2, AGC2 as output, TGC source */
779 (state
->m_FeAgRegAgPwd
) &=
780 ~(FE_AG_REG_AG_PWD_PWD_PD2__M
);
781 (state
->m_FeAgRegAgPwd
) |=
782 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE
;
783 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, (state
->m_FeAgRegAgPwd
), 0x0000);
787 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
790 AgModeLop
&= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M
|
791 FE_AG_REG_AG_MODE_LOP_MODE_E__M
));
792 AgModeLop
|= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
|
793 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC
);
794 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
798 level
= (((cfg
->settleLevel
) >> 4) &
799 FE_AG_REG_TGC_SET_LVL__M
);
800 status
= Write16(state
, FE_AG_REG_TGC_SET_LVL__A
, level
, 0x0000);
804 /* Min/max: don't care */
808 /* enable AGC2 pin */
810 u16 FeAgRegAgAgcSio
= 0;
811 status
= Read16(state
, FE_AG_REG_AG_AGC_SIO__A
, &FeAgRegAgAgcSio
, 0x0000);
815 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
);
817 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT
;
818 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, FeAgRegAgAgcSio
, 0x0000);
828 /* No RF AGC control */
829 /* Powerdown PD2, AGC2 as output, WRI source */
830 (state
->m_FeAgRegAgPwd
) &=
831 ~(FE_AG_REG_AG_PWD_PWD_PD2__M
);
832 (state
->m_FeAgRegAgPwd
) |=
833 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE
;
834 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, (state
->m_FeAgRegAgPwd
), 0x0000);
838 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
841 AgModeLop
&= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M
|
842 FE_AG_REG_AG_MODE_LOP_MODE_E__M
));
843 AgModeLop
|= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
|
844 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC
);
845 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
849 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
851 u16 FeAgRegAgAgcSio
= 0;
852 status
= Read16(state
, FE_AG_REG_AG_AGC_SIO__A
, &FeAgRegAgAgcSio
, 0x0000);
856 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
);
858 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT
;
859 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, FeAgRegAgAgcSio
, 0x0000);
868 static int ReadIFAgc(struct drxd_state
*state
, u32
* pValue
)
873 if (state
->if_agc_cfg
.ctrlMode
!= AGC_CTRL_OFF
) {
875 status
= Read16(state
, FE_AG_REG_GC1_AGC_DAT__A
, &Value
, 0);
876 Value
&= FE_AG_REG_GC1_AGC_DAT__M
;
888 u32 R1
= state
->if_agc_cfg
.R1
;
889 u32 R2
= state
->if_agc_cfg
.R2
;
890 u32 R3
= state
->if_agc_cfg
.R3
;
892 u32 Vmax
= (3300 * R2
) / (R1
+ R2
);
893 u32 Rpar
= (R2
* R3
) / (R3
+ R2
);
894 u32 Vmin
= (3300 * Rpar
) / (R1
+ Rpar
);
895 u32 Vout
= Vmin
+ ((Vmax
- Vmin
) * Value
) / 1024;
903 static int load_firmware(struct drxd_state
*state
, const char *fw_name
)
905 const struct firmware
*fw
;
907 if (request_firmware(&fw
, fw_name
, state
->dev
) < 0) {
908 printk(KERN_ERR
"drxd: firmware load failure [%s]\n", fw_name
);
912 state
->microcode
= kmalloc(fw
->size
, GFP_KERNEL
);
913 if (state
->microcode
== NULL
) {
914 release_firmware(fw
);
915 printk(KERN_ERR
"drxd: firmware load failure: no memory\n");
919 memcpy(state
->microcode
, fw
->data
, fw
->size
);
920 state
->microcode_length
= fw
->size
;
921 release_firmware(fw
);
925 static int DownloadMicrocode(struct drxd_state
*state
,
926 const u8
*pMCImage
, u32 Length
)
937 pSrc
= (u8
*) pMCImage
;
938 Flags
= (pSrc
[0] << 8) | pSrc
[1];
940 offset
+= sizeof(u16
);
941 nBlocks
= (pSrc
[0] << 8) | pSrc
[1];
943 offset
+= sizeof(u16
);
945 for (i
= 0; i
< nBlocks
; i
++) {
946 Address
= (pSrc
[0] << 24) | (pSrc
[1] << 16) |
947 (pSrc
[2] << 8) | pSrc
[3];
949 offset
+= sizeof(u32
);
951 BlockSize
= ((pSrc
[0] << 8) | pSrc
[1]) * sizeof(u16
);
953 offset
+= sizeof(u16
);
955 Flags
= (pSrc
[0] << 8) | pSrc
[1];
957 offset
+= sizeof(u16
);
959 BlockCRC
= (pSrc
[0] << 8) | pSrc
[1];
961 offset
+= sizeof(u16
);
963 status
= WriteBlock(state
, Address
, BlockSize
,
964 pSrc
, DRX_I2C_CLEARCRC
);
974 static int HI_Command(struct drxd_state
*state
, u16 cmd
, u16
* pResult
)
980 status
= Write16(state
, HI_RA_RAM_SRV_CMD__A
, cmd
, 0);
986 if (nrRetries
> DRXD_MAX_RETRIES
) {
990 status
= Read16(state
, HI_RA_RAM_SRV_CMD__A
, &waitCmd
, 0);
991 } while (waitCmd
!= 0);
994 status
= Read16(state
, HI_RA_RAM_SRV_RES__A
, pResult
, 0);
998 static int HI_CfgCommand(struct drxd_state
*state
)
1002 mutex_lock(&state
->mutex
);
1003 Write16(state
, HI_RA_RAM_SRV_CFG_KEY__A
, HI_RA_RAM_SRV_RST_KEY_ACT
, 0);
1004 Write16(state
, HI_RA_RAM_SRV_CFG_DIV__A
, state
->hi_cfg_timing_div
, 0);
1005 Write16(state
, HI_RA_RAM_SRV_CFG_BDL__A
, state
->hi_cfg_bridge_delay
, 0);
1006 Write16(state
, HI_RA_RAM_SRV_CFG_WUP__A
, state
->hi_cfg_wakeup_key
, 0);
1007 Write16(state
, HI_RA_RAM_SRV_CFG_ACT__A
, state
->hi_cfg_ctrl
, 0);
1009 Write16(state
, HI_RA_RAM_SRV_CFG_KEY__A
, HI_RA_RAM_SRV_RST_KEY_ACT
, 0);
1011 if ((state
->hi_cfg_ctrl
& HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
) ==
1012 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
)
1013 status
= Write16(state
, HI_RA_RAM_SRV_CMD__A
,
1014 HI_RA_RAM_SRV_CMD_CONFIG
, 0);
1016 status
= HI_Command(state
, HI_RA_RAM_SRV_CMD_CONFIG
, 0);
1017 mutex_unlock(&state
->mutex
);
1021 static int InitHI(struct drxd_state
*state
)
1023 state
->hi_cfg_wakeup_key
= (state
->chip_adr
);
1024 /* port/bridge/power down ctrl */
1025 state
->hi_cfg_ctrl
= HI_RA_RAM_SRV_CFG_ACT_SLV0_ON
;
1026 return HI_CfgCommand(state
);
1029 static int HI_ResetCommand(struct drxd_state
*state
)
1033 mutex_lock(&state
->mutex
);
1034 status
= Write16(state
, HI_RA_RAM_SRV_RST_KEY__A
,
1035 HI_RA_RAM_SRV_RST_KEY_ACT
, 0);
1037 status
= HI_Command(state
, HI_RA_RAM_SRV_CMD_RESET
, 0);
1038 mutex_unlock(&state
->mutex
);
1043 static int DRX_ConfigureI2CBridge(struct drxd_state
*state
, int bEnableBridge
)
1045 state
->hi_cfg_ctrl
&= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M
);
1047 state
->hi_cfg_ctrl
|= HI_RA_RAM_SRV_CFG_ACT_BRD_ON
;
1049 state
->hi_cfg_ctrl
|= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF
;
1051 return HI_CfgCommand(state
);
1054 #define HI_TR_WRITE 0x9
1055 #define HI_TR_READ 0xA
1056 #define HI_TR_READ_WRITE 0xB
1057 #define HI_TR_BROADCAST 0x4
1060 static int AtomicReadBlock(struct drxd_state
*state
,
1061 u32 Addr
, u16 DataSize
, u8
*pData
, u8 Flags
)
1066 /* Parameter check */
1067 if ((!pData
) || ((DataSize
& 1) != 0))
1070 mutex_lock(&state
->mutex
);
1073 /* Instruct HI to read n bytes */
1074 /* TODO use proper names forthese egisters */
1075 status
= Write16(state
, HI_RA_RAM_SRV_CFG_KEY__A
, (HI_TR_FUNC_ADDR
& 0xFFFF), 0);
1078 status
= Write16(state
, HI_RA_RAM_SRV_CFG_DIV__A
, (u16
) (Addr
>> 16), 0);
1081 status
= Write16(state
, HI_RA_RAM_SRV_CFG_BDL__A
, (u16
) (Addr
& 0xFFFF), 0);
1084 status
= Write16(state
, HI_RA_RAM_SRV_CFG_WUP__A
, (u16
) ((DataSize
/ 2) - 1), 0);
1087 status
= Write16(state
, HI_RA_RAM_SRV_CFG_ACT__A
, HI_TR_READ
, 0);
1091 status
= HI_Command(state
, HI_RA_RAM_SRV_CMD_EXECUTE
, 0);
1098 for (i
= 0; i
< (DataSize
/ 2); i
+= 1) {
1101 status
= Read16(state
, (HI_RA_RAM_USR_BEGIN__A
+ i
),
1105 pData
[2 * i
] = (u8
) (word
& 0xFF);
1106 pData
[(2 * i
) + 1] = (u8
) (word
>> 8);
1109 mutex_unlock(&state
->mutex
);
1113 static int AtomicReadReg32(struct drxd_state
*state
,
1114 u32 Addr
, u32
*pData
, u8 Flags
)
1116 u8 buf
[sizeof(u32
)];
1121 status
= AtomicReadBlock(state
, Addr
, sizeof(u32
), buf
, Flags
);
1122 *pData
= (((u32
) buf
[0]) << 0) +
1123 (((u32
) buf
[1]) << 8) +
1124 (((u32
) buf
[2]) << 16) + (((u32
) buf
[3]) << 24);
1129 static int StopAllProcessors(struct drxd_state
*state
)
1131 return Write16(state
, HI_COMM_EXEC__A
,
1132 SC_COMM_EXEC_CTL_STOP
, DRX_I2C_BROADCAST
);
1135 static int EnableAndResetMB(struct drxd_state
*state
)
1137 if (state
->type_A
) {
1138 /* disable? monitor bus observe @ EC_OC */
1139 Write16(state
, EC_OC_REG_OC_MON_SIO__A
, 0x0000, 0x0000);
1142 /* do inverse broadcast, followed by explicit write to HI */
1143 Write16(state
, HI_COMM_MB__A
, 0x0000, DRX_I2C_BROADCAST
);
1144 Write16(state
, HI_COMM_MB__A
, 0x0000, 0x0000);
1148 static int InitCC(struct drxd_state
*state
)
1150 if (state
->osc_clock_freq
== 0 ||
1151 state
->osc_clock_freq
> 20000 ||
1152 (state
->osc_clock_freq
% 4000) != 0) {
1153 printk(KERN_ERR
"invalid osc frequency %d\n", state
->osc_clock_freq
);
1157 Write16(state
, CC_REG_OSC_MODE__A
, CC_REG_OSC_MODE_M20
, 0);
1158 Write16(state
, CC_REG_PLL_MODE__A
, CC_REG_PLL_MODE_BYPASS_PLL
|
1159 CC_REG_PLL_MODE_PUMP_CUR_12
, 0);
1160 Write16(state
, CC_REG_REF_DIVIDE__A
, state
->osc_clock_freq
/ 4000, 0);
1161 Write16(state
, CC_REG_PWD_MODE__A
, CC_REG_PWD_MODE_DOWN_PLL
, 0);
1162 Write16(state
, CC_REG_UPDATE__A
, CC_REG_UPDATE_KEY
, 0);
1167 static int ResetECOD(struct drxd_state
*state
)
1172 status
= Write16(state
, EC_OD_REG_SYNC__A
, 0x0664, 0);
1174 status
= Write16(state
, B_EC_OD_REG_SYNC__A
, 0x0664, 0);
1177 status
= WriteTable(state
, state
->m_ResetECRAM
);
1179 status
= Write16(state
, EC_OD_REG_COMM_EXEC__A
, 0x0001, 0);
1183 /* Configure PGA switch */
1185 static int SetCfgPga(struct drxd_state
*state
, int pgaSwitch
)
1194 status
= Read16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
1197 AgModeLop
&= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M
));
1198 AgModeLop
|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC
;
1199 status
= Write16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
1204 status
= Read16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, &AgModeHip
, 0x0000);
1207 AgModeHip
&= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M
));
1208 AgModeHip
|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC
;
1209 status
= Write16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, AgModeHip
, 0x0000);
1213 /* enable fine and coarse gain, enable AAF,
1215 status
= Write16(state
, B_FE_AG_REG_AG_PGA_MODE__A
, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN
, 0x0000);
1219 /* PGA off, bypass */
1222 status
= Read16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
1225 AgModeLop
&= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M
));
1226 AgModeLop
|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC
;
1227 status
= Write16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
1232 status
= Read16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, &AgModeHip
, 0x0000);
1235 AgModeHip
&= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M
));
1236 AgModeHip
|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC
;
1237 status
= Write16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, AgModeHip
, 0x0000);
1241 /* disable fine and coarse gain, enable AAF,
1243 status
= Write16(state
, B_FE_AG_REG_AG_PGA_MODE__A
, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
, 0x0000);
1251 static int InitFE(struct drxd_state
*state
)
1256 status
= WriteTable(state
, state
->m_InitFE_1
);
1260 if (state
->type_A
) {
1261 status
= Write16(state
, FE_AG_REG_AG_PGA_MODE__A
,
1262 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
,
1266 status
= SetCfgPga(state
, 0);
1269 Write16(state
, B_FE_AG_REG_AG_PGA_MODE__A
,
1270 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
,
1276 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, state
->m_FeAgRegAgAgcSio
, 0x0000);
1279 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, state
->m_FeAgRegAgPwd
, 0x0000);
1283 status
= WriteTable(state
, state
->m_InitFE_2
);
1292 static int InitFT(struct drxd_state
*state
)
1295 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1298 return Write16(state
, FT_REG_COMM_EXEC__A
, 0x0001, 0x0000);
1301 static int SC_WaitForReady(struct drxd_state
*state
)
1306 for (i
= 0; i
< DRXD_MAX_RETRIES
; i
+= 1) {
1307 int status
= Read16(state
, SC_RA_RAM_CMD__A
, &curCmd
, 0);
1308 if (status
== 0 || curCmd
== 0)
1314 static int SC_SendCommand(struct drxd_state
*state
, u16 cmd
)
1319 Write16(state
, SC_RA_RAM_CMD__A
, cmd
, 0);
1320 SC_WaitForReady(state
);
1322 Read16(state
, SC_RA_RAM_CMD_ADDR__A
, &errCode
, 0);
1324 if (errCode
== 0xFFFF) {
1325 printk(KERN_ERR
"Command Error\n");
1332 static int SC_ProcStartCommand(struct drxd_state
*state
,
1333 u16 subCmd
, u16 param0
, u16 param1
)
1338 mutex_lock(&state
->mutex
);
1340 Read16(state
, SC_COMM_EXEC__A
, &scExec
, 0);
1345 SC_WaitForReady(state
);
1346 Write16(state
, SC_RA_RAM_CMD_ADDR__A
, subCmd
, 0);
1347 Write16(state
, SC_RA_RAM_PARAM1__A
, param1
, 0);
1348 Write16(state
, SC_RA_RAM_PARAM0__A
, param0
, 0);
1350 SC_SendCommand(state
, SC_RA_RAM_CMD_PROC_START
);
1352 mutex_unlock(&state
->mutex
);
1356 static int SC_SetPrefParamCommand(struct drxd_state
*state
,
1357 u16 subCmd
, u16 param0
, u16 param1
)
1361 mutex_lock(&state
->mutex
);
1363 status
= SC_WaitForReady(state
);
1366 status
= Write16(state
, SC_RA_RAM_CMD_ADDR__A
, subCmd
, 0);
1369 status
= Write16(state
, SC_RA_RAM_PARAM1__A
, param1
, 0);
1372 status
= Write16(state
, SC_RA_RAM_PARAM0__A
, param0
, 0);
1376 status
= SC_SendCommand(state
, SC_RA_RAM_CMD_SET_PREF_PARAM
);
1380 mutex_unlock(&state
->mutex
);
1385 static int SC_GetOpParamCommand(struct drxd_state
*state
, u16
* result
)
1389 mutex_lock(&state
->mutex
);
1391 status
= SC_WaitForReady(state
);
1394 status
= SC_SendCommand(state
, SC_RA_RAM_CMD_GET_OP_PARAM
);
1397 status
= Read16(state
, SC_RA_RAM_PARAM0__A
, result
, 0);
1401 mutex_unlock(&state
->mutex
);
1406 static int ConfigureMPEGOutput(struct drxd_state
*state
, int bEnableOutput
)
1411 u16 EcOcRegIprInvMpg
= 0;
1412 u16 EcOcRegOcModeLop
= 0;
1413 u16 EcOcRegOcModeHip
= 0;
1414 u16 EcOcRegOcMpgSio
= 0;
1416 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1418 if (state
->operation_mode
== OM_DVBT_Diversity_Front
) {
1419 if (bEnableOutput
) {
1421 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR
;
1423 EcOcRegOcMpgSio
|= EC_OC_REG_OC_MPG_SIO__M
;
1425 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE
;
1427 EcOcRegOcModeLop
= state
->m_EcOcRegOcModeLop
;
1430 EcOcRegOcMpgSio
&= (~(EC_OC_REG_OC_MPG_SIO__M
));
1432 EcOcRegOcMpgSio
|= EC_OC_REG_OC_MPG_SIO__M
;
1434 /* Don't Insert RS Byte */
1435 if (state
->insert_rs_byte
) {
1437 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M
));
1439 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M
);
1441 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE
;
1444 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE
;
1446 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M
);
1448 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE
;
1451 /* Mode = Parallel */
1452 if (state
->enable_parallel
)
1454 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M
));
1457 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL
;
1460 /* EcOcRegIprInvMpg |= 0x00FF; */
1461 EcOcRegIprInvMpg
&= (~(0x00FF));
1463 /* Invert Error ( we don't use the pin ) */
1464 /* EcOcRegIprInvMpg |= 0x0100; */
1465 EcOcRegIprInvMpg
&= (~(0x0100));
1467 /* Invert Start ( we don't use the pin ) */
1468 /* EcOcRegIprInvMpg |= 0x0200; */
1469 EcOcRegIprInvMpg
&= (~(0x0200));
1471 /* Invert Valid ( we don't use the pin ) */
1472 /* EcOcRegIprInvMpg |= 0x0400; */
1473 EcOcRegIprInvMpg
&= (~(0x0400));
1476 /* EcOcRegIprInvMpg |= 0x0800; */
1477 EcOcRegIprInvMpg
&= (~(0x0800));
1479 /* EcOcRegOcModeLop =0x05; */
1480 status
= Write16(state
, EC_OC_REG_IPR_INV_MPG__A
, EcOcRegIprInvMpg
, 0);
1483 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, EcOcRegOcModeLop
, 0);
1486 status
= Write16(state
, EC_OC_REG_OC_MODE_HIP__A
, EcOcRegOcModeHip
, 0x0000);
1489 status
= Write16(state
, EC_OC_REG_OC_MPG_SIO__A
, EcOcRegOcMpgSio
, 0);
1496 static int SetDeviceTypeId(struct drxd_state
*state
)
1502 status
= Read16(state
, CC_REG_JTAGID_L__A
, &deviceId
, 0);
1505 /* TODO: why twice? */
1506 status
= Read16(state
, CC_REG_JTAGID_L__A
, &deviceId
, 0);
1509 printk(KERN_INFO
"drxd: deviceId = %04x\n", deviceId
);
1513 state
->diversity
= 0;
1514 if (deviceId
== 0) { /* on A2 only 3975 available */
1516 printk(KERN_INFO
"DRX3975D-A2\n");
1519 printk(KERN_INFO
"DRX397%dD-B1\n", deviceId
);
1522 state
->diversity
= 1;
1528 state
->diversity
= 1;
1542 /* Init Table selection */
1543 state
->m_InitAtomicRead
= DRXD_InitAtomicRead
;
1544 state
->m_InitSC
= DRXD_InitSC
;
1545 state
->m_ResetECRAM
= DRXD_ResetECRAM
;
1546 if (state
->type_A
) {
1547 state
->m_ResetCEFR
= DRXD_ResetCEFR
;
1548 state
->m_InitFE_1
= DRXD_InitFEA2_1
;
1549 state
->m_InitFE_2
= DRXD_InitFEA2_2
;
1550 state
->m_InitCP
= DRXD_InitCPA2
;
1551 state
->m_InitCE
= DRXD_InitCEA2
;
1552 state
->m_InitEQ
= DRXD_InitEQA2
;
1553 state
->m_InitEC
= DRXD_InitECA2
;
1554 if (load_firmware(state
, DRX_FW_FILENAME_A2
))
1557 state
->m_ResetCEFR
= NULL
;
1558 state
->m_InitFE_1
= DRXD_InitFEB1_1
;
1559 state
->m_InitFE_2
= DRXD_InitFEB1_2
;
1560 state
->m_InitCP
= DRXD_InitCPB1
;
1561 state
->m_InitCE
= DRXD_InitCEB1
;
1562 state
->m_InitEQ
= DRXD_InitEQB1
;
1563 state
->m_InitEC
= DRXD_InitECB1
;
1564 if (load_firmware(state
, DRX_FW_FILENAME_B1
))
1567 if (state
->diversity
) {
1568 state
->m_InitDiversityFront
= DRXD_InitDiversityFront
;
1569 state
->m_InitDiversityEnd
= DRXD_InitDiversityEnd
;
1570 state
->m_DisableDiversity
= DRXD_DisableDiversity
;
1571 state
->m_StartDiversityFront
= DRXD_StartDiversityFront
;
1572 state
->m_StartDiversityEnd
= DRXD_StartDiversityEnd
;
1573 state
->m_DiversityDelay8MHZ
= DRXD_DiversityDelay8MHZ
;
1574 state
->m_DiversityDelay6MHZ
= DRXD_DiversityDelay6MHZ
;
1576 state
->m_InitDiversityFront
= NULL
;
1577 state
->m_InitDiversityEnd
= NULL
;
1578 state
->m_DisableDiversity
= NULL
;
1579 state
->m_StartDiversityFront
= NULL
;
1580 state
->m_StartDiversityEnd
= NULL
;
1581 state
->m_DiversityDelay8MHZ
= NULL
;
1582 state
->m_DiversityDelay6MHZ
= NULL
;
1588 static int CorrectSysClockDeviation(struct drxd_state
*state
)
1594 u32 sysClockInHz
= 0;
1595 u32 sysClockFreq
= 0; /* in kHz */
1596 s16 oscClockDeviation
;
1600 /* Retrieve bandwidth and incr, sanity check */
1602 /* These accesses should be AtomicReadReg32, but that
1603 causes trouble (at least for diversity */
1604 status
= Read32(state
, LC_RA_RAM_IFINCR_NOM_L__A
, ((u32
*) &nomincr
), 0);
1607 status
= Read32(state
, FE_IF_REG_INCR0__A
, (u32
*) &incr
, 0);
1611 if (state
->type_A
) {
1612 if ((nomincr
- incr
< -500) || (nomincr
- incr
> 500))
1615 if ((nomincr
- incr
< -2000) || (nomincr
- incr
> 2000))
1619 switch (state
->param
.u
.ofdm
.bandwidth
) {
1620 case BANDWIDTH_8_MHZ
:
1621 bandwidth
= DRXD_BANDWIDTH_8MHZ_IN_HZ
;
1623 case BANDWIDTH_7_MHZ
:
1624 bandwidth
= DRXD_BANDWIDTH_7MHZ_IN_HZ
;
1626 case BANDWIDTH_6_MHZ
:
1627 bandwidth
= DRXD_BANDWIDTH_6MHZ_IN_HZ
;
1634 /* Compute new sysclock value
1635 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1637 sysClockInHz
= MulDiv32(incr
, bandwidth
, 1 << 21);
1638 sysClockFreq
= (u32
) (sysClockInHz
/ 1000);
1640 if ((sysClockInHz
% 1000) > 500)
1643 /* Compute clock deviation in ppm */
1644 oscClockDeviation
= (u16
) ((((s32
) (sysClockFreq
) -
1646 (state
->expected_sys_clock_freq
)) *
1649 (state
->expected_sys_clock_freq
));
1651 Diff
= oscClockDeviation
- state
->osc_clock_deviation
;
1652 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1653 if (Diff
>= -200 && Diff
<= 200) {
1654 state
->sys_clock_freq
= (u16
) sysClockFreq
;
1655 if (oscClockDeviation
!= state
->osc_clock_deviation
) {
1656 if (state
->config
.osc_deviation
) {
1657 state
->config
.osc_deviation(state
->priv
,
1660 state
->osc_clock_deviation
=
1664 /* switch OFF SRMM scan in SC */
1665 status
= Write16(state
, SC_RA_RAM_SAMPLE_RATE_COUNT__A
, DRXD_OSCDEV_DONT_SCAN
, 0);
1668 /* overrule FE_IF internal value for
1669 proper re-locking */
1670 status
= Write16(state
, SC_RA_RAM_IF_SAVE__AX
, state
->current_fe_if_incr
, 0);
1673 state
->cscd_state
= CSCD_SAVED
;
1680 static int DRX_Stop(struct drxd_state
*state
)
1684 if (state
->drxd_state
!= DRXD_STARTED
)
1688 if (state
->cscd_state
!= CSCD_SAVED
) {
1690 status
= DRX_GetLockStatus(state
, &lock
);
1695 status
= StopOC(state
);
1699 state
->drxd_state
= DRXD_STOPPED
;
1701 status
= ConfigureMPEGOutput(state
, 0);
1705 if (state
->type_A
) {
1706 /* Stop relevant processors off the device */
1707 status
= Write16(state
, EC_OD_REG_COMM_EXEC__A
, 0x0000, 0x0000);
1711 status
= Write16(state
, SC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1714 status
= Write16(state
, LC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1718 /* Stop all processors except HI & CC & FE */
1719 status
= Write16(state
, B_SC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1722 status
= Write16(state
, B_LC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1725 status
= Write16(state
, B_FT_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1728 status
= Write16(state
, B_CP_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1731 status
= Write16(state
, B_CE_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1734 status
= Write16(state
, B_EQ_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1737 status
= Write16(state
, EC_OD_REG_COMM_EXEC__A
, 0x0000, 0);
1746 int SetOperationMode(struct drxd_state
*state
, int oMode
)
1751 if (state
->drxd_state
!= DRXD_STOPPED
) {
1756 if (oMode
== state
->operation_mode
) {
1761 if (oMode
!= OM_Default
&& !state
->diversity
) {
1767 case OM_DVBT_Diversity_Front
:
1768 status
= WriteTable(state
, state
->m_InitDiversityFront
);
1770 case OM_DVBT_Diversity_End
:
1771 status
= WriteTable(state
, state
->m_InitDiversityEnd
);
1774 /* We need to check how to
1775 get DRXD out of diversity */
1777 status
= WriteTable(state
, state
->m_DisableDiversity
);
1783 state
->operation_mode
= oMode
;
1787 static int StartDiversity(struct drxd_state
*state
)
1793 if (state
->operation_mode
== OM_DVBT_Diversity_Front
) {
1794 status
= WriteTable(state
, state
->m_StartDiversityFront
);
1797 } else if (state
->operation_mode
== OM_DVBT_Diversity_End
) {
1798 status
= WriteTable(state
, state
->m_StartDiversityEnd
);
1801 if (state
->param
.u
.ofdm
.bandwidth
== BANDWIDTH_8_MHZ
) {
1802 status
= WriteTable(state
, state
->m_DiversityDelay8MHZ
);
1806 status
= WriteTable(state
, state
->m_DiversityDelay6MHZ
);
1811 status
= Read16(state
, B_EQ_REG_RC_SEL_CAR__A
, &rcControl
, 0);
1814 rcControl
&= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M
);
1815 rcControl
|= B_EQ_REG_RC_SEL_CAR_DIV_ON
|
1816 /* combining enabled */
1817 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC
|
1818 B_EQ_REG_RC_SEL_CAR_PASS_A_CC
|
1819 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC
;
1820 status
= Write16(state
, B_EQ_REG_RC_SEL_CAR__A
, rcControl
, 0);
1828 static int SetFrequencyShift(struct drxd_state
*state
,
1829 u32 offsetFreq
, int channelMirrored
)
1831 int negativeShift
= (state
->tuner_mirrors
== channelMirrored
);
1833 /* Handle all mirroring
1835 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1836 * feFsRegAddInc to 28 bits below
1837 * (if the result before masking is more than 28 bits, this means
1838 * that the ADC is mirroring.
1839 * The masking is in fact the aliasing of the ADC)
1843 /* Compute register value, unsigned computation */
1844 state
->fe_fs_add_incr
= MulDiv32(state
->intermediate_freq
+
1846 1 << 28, state
->sys_clock_freq
);
1847 /* Remove integer part */
1848 state
->fe_fs_add_incr
&= 0x0FFFFFFFL
;
1850 state
->fe_fs_add_incr
= ((1 << 28) - state
->fe_fs_add_incr
);
1852 /* Save the frequency shift without tunerOffset compensation
1853 for CtrlGetChannel. */
1854 state
->org_fe_fs_add_incr
= MulDiv32(state
->intermediate_freq
,
1855 1 << 28, state
->sys_clock_freq
);
1856 /* Remove integer part */
1857 state
->org_fe_fs_add_incr
&= 0x0FFFFFFFL
;
1859 state
->org_fe_fs_add_incr
= ((1L << 28) -
1860 state
->org_fe_fs_add_incr
);
1862 return Write32(state
, FE_FS_REG_ADD_INC_LOP__A
,
1863 state
->fe_fs_add_incr
, 0);
1866 static int SetCfgNoiseCalibration(struct drxd_state
*state
,
1867 struct SNoiseCal
*noiseCal
)
1873 status
= Read16(state
, SC_RA_RAM_BE_OPT_ENA__A
, &beOptEna
, 0);
1876 if (noiseCal
->cpOpt
) {
1877 beOptEna
|= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT
);
1879 beOptEna
&= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT
);
1880 status
= Write16(state
, CP_REG_AC_NEXP_OFFS__A
, noiseCal
->cpNexpOfs
, 0);
1884 status
= Write16(state
, SC_RA_RAM_BE_OPT_ENA__A
, beOptEna
, 0);
1888 if (!state
->type_A
) {
1889 status
= Write16(state
, B_SC_RA_RAM_CO_TD_CAL_2K__A
, noiseCal
->tdCal2k
, 0);
1892 status
= Write16(state
, B_SC_RA_RAM_CO_TD_CAL_8K__A
, noiseCal
->tdCal8k
, 0);
1901 static int DRX_Start(struct drxd_state
*state
, s32 off
)
1903 struct dvb_ofdm_parameters
*p
= &state
->param
.u
.ofdm
;
1906 u16 transmissionParams
= 0;
1907 u16 operationMode
= 0;
1908 u16 qpskTdTpsPwr
= 0;
1909 u16 qam16TdTpsPwr
= 0;
1910 u16 qam64TdTpsPwr
= 0;
1913 int mirrorFreqSpect
;
1915 u16 qpskSnCeGain
= 0;
1916 u16 qam16SnCeGain
= 0;
1917 u16 qam64SnCeGain
= 0;
1918 u16 qpskIsGainMan
= 0;
1919 u16 qam16IsGainMan
= 0;
1920 u16 qam64IsGainMan
= 0;
1921 u16 qpskIsGainExp
= 0;
1922 u16 qam16IsGainExp
= 0;
1923 u16 qam64IsGainExp
= 0;
1924 u16 bandwidthParam
= 0;
1927 off
= (off
- 500) / 1000;
1929 off
= (off
+ 500) / 1000;
1932 if (state
->drxd_state
!= DRXD_STOPPED
)
1934 status
= ResetECOD(state
);
1937 if (state
->type_A
) {
1938 status
= InitSC(state
);
1942 status
= InitFT(state
);
1945 status
= InitCP(state
);
1948 status
= InitCE(state
);
1951 status
= InitEQ(state
);
1954 status
= InitSC(state
);
1959 /* Restore current IF & RF AGC settings */
1961 status
= SetCfgIfAgc(state
, &state
->if_agc_cfg
);
1964 status
= SetCfgRfAgc(state
, &state
->rf_agc_cfg
);
1968 mirrorFreqSpect
= (state
->param
.inversion
== INVERSION_ON
);
1970 switch (p
->transmission_mode
) {
1971 default: /* Not set, detect it automatically */
1972 operationMode
|= SC_RA_RAM_OP_AUTO_MODE__M
;
1973 /* fall through , try first guess DRX_FFTMODE_8K */
1974 case TRANSMISSION_MODE_8K
:
1975 transmissionParams
|= SC_RA_RAM_OP_PARAM_MODE_8K
;
1976 if (state
->type_A
) {
1977 status
= Write16(state
, EC_SB_REG_TR_MODE__A
, EC_SB_REG_TR_MODE_8K
, 0x0000);
1985 case TRANSMISSION_MODE_2K
:
1986 transmissionParams
|= SC_RA_RAM_OP_PARAM_MODE_2K
;
1987 if (state
->type_A
) {
1988 status
= Write16(state
, EC_SB_REG_TR_MODE__A
, EC_SB_REG_TR_MODE_2K
, 0x0000);
1998 switch (p
->guard_interval
) {
1999 case GUARD_INTERVAL_1_4
:
2000 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_4
;
2002 case GUARD_INTERVAL_1_8
:
2003 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_8
;
2005 case GUARD_INTERVAL_1_16
:
2006 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_16
;
2008 case GUARD_INTERVAL_1_32
:
2009 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_32
;
2011 default: /* Not set, detect it automatically */
2012 operationMode
|= SC_RA_RAM_OP_AUTO_GUARD__M
;
2013 /* try first guess 1/4 */
2014 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_4
;
2018 switch (p
->hierarchy_information
) {
2020 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_A1
;
2021 if (state
->type_A
) {
2022 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0001, 0x0000);
2025 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0001, 0x0000);
2029 qpskTdTpsPwr
= EQ_TD_TPS_PWR_UNKNOWN
;
2030 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHA1
;
2031 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHA1
;
2034 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
;
2036 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE
;
2038 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE
;
2041 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
;
2043 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE
;
2045 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE
;
2050 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_A2
;
2051 if (state
->type_A
) {
2052 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0002, 0x0000);
2055 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0002, 0x0000);
2059 qpskTdTpsPwr
= EQ_TD_TPS_PWR_UNKNOWN
;
2060 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHA2
;
2061 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHA2
;
2064 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
;
2066 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE
;
2068 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE
;
2071 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
;
2073 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE
;
2075 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE
;
2079 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_A4
;
2080 if (state
->type_A
) {
2081 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0003, 0x0000);
2084 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0003, 0x0000);
2088 qpskTdTpsPwr
= EQ_TD_TPS_PWR_UNKNOWN
;
2089 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHA4
;
2090 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHA4
;
2093 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
;
2095 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE
;
2097 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE
;
2100 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
;
2102 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE
;
2104 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE
;
2107 case HIERARCHY_AUTO
:
2109 /* Not set, detect it automatically, start with none */
2110 operationMode
|= SC_RA_RAM_OP_AUTO_HIER__M
;
2111 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_NO
;
2112 if (state
->type_A
) {
2113 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0000, 0x0000);
2116 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0000, 0x0000);
2120 qpskTdTpsPwr
= EQ_TD_TPS_PWR_QPSK
;
2121 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHAN
;
2122 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHAN
;
2125 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE
;
2127 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE
;
2129 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE
;
2132 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE
;
2134 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE
;
2136 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE
;
2144 switch (p
->constellation
) {
2146 operationMode
|= SC_RA_RAM_OP_AUTO_CONST__M
;
2147 /* fall through , try first guess
2148 DRX_CONSTELLATION_QAM64 */
2150 transmissionParams
|= SC_RA_RAM_OP_PARAM_CONST_QAM64
;
2151 if (state
->type_A
) {
2152 status
= Write16(state
, EQ_REG_OT_CONST__A
, 0x0002, 0x0000);
2155 status
= Write16(state
, EC_SB_REG_CONST__A
, EC_SB_REG_CONST_64QAM
, 0x0000);
2158 status
= Write16(state
, EC_SB_REG_SCALE_MSB__A
, 0x0020, 0x0000);
2161 status
= Write16(state
, EC_SB_REG_SCALE_BIT2__A
, 0x0008, 0x0000);
2164 status
= Write16(state
, EC_SB_REG_SCALE_LSB__A
, 0x0002, 0x0000);
2168 status
= Write16(state
, EQ_REG_TD_TPS_PWR_OFS__A
, qam64TdTpsPwr
, 0x0000);
2171 status
= Write16(state
, EQ_REG_SN_CEGAIN__A
, qam64SnCeGain
, 0x0000);
2174 status
= Write16(state
, EQ_REG_IS_GAIN_MAN__A
, qam64IsGainMan
, 0x0000);
2177 status
= Write16(state
, EQ_REG_IS_GAIN_EXP__A
, qam64IsGainExp
, 0x0000);
2183 transmissionParams
|= SC_RA_RAM_OP_PARAM_CONST_QPSK
;
2184 if (state
->type_A
) {
2185 status
= Write16(state
, EQ_REG_OT_CONST__A
, 0x0000, 0x0000);
2188 status
= Write16(state
, EC_SB_REG_CONST__A
, EC_SB_REG_CONST_QPSK
, 0x0000);
2191 status
= Write16(state
, EC_SB_REG_SCALE_MSB__A
, 0x0010, 0x0000);
2194 status
= Write16(state
, EC_SB_REG_SCALE_BIT2__A
, 0x0000, 0x0000);
2197 status
= Write16(state
, EC_SB_REG_SCALE_LSB__A
, 0x0000, 0x0000);
2201 status
= Write16(state
, EQ_REG_TD_TPS_PWR_OFS__A
, qpskTdTpsPwr
, 0x0000);
2204 status
= Write16(state
, EQ_REG_SN_CEGAIN__A
, qpskSnCeGain
, 0x0000);
2207 status
= Write16(state
, EQ_REG_IS_GAIN_MAN__A
, qpskIsGainMan
, 0x0000);
2210 status
= Write16(state
, EQ_REG_IS_GAIN_EXP__A
, qpskIsGainExp
, 0x0000);
2217 transmissionParams
|= SC_RA_RAM_OP_PARAM_CONST_QAM16
;
2218 if (state
->type_A
) {
2219 status
= Write16(state
, EQ_REG_OT_CONST__A
, 0x0001, 0x0000);
2222 status
= Write16(state
, EC_SB_REG_CONST__A
, EC_SB_REG_CONST_16QAM
, 0x0000);
2225 status
= Write16(state
, EC_SB_REG_SCALE_MSB__A
, 0x0010, 0x0000);
2228 status
= Write16(state
, EC_SB_REG_SCALE_BIT2__A
, 0x0004, 0x0000);
2231 status
= Write16(state
, EC_SB_REG_SCALE_LSB__A
, 0x0000, 0x0000);
2235 status
= Write16(state
, EQ_REG_TD_TPS_PWR_OFS__A
, qam16TdTpsPwr
, 0x0000);
2238 status
= Write16(state
, EQ_REG_SN_CEGAIN__A
, qam16SnCeGain
, 0x0000);
2241 status
= Write16(state
, EQ_REG_IS_GAIN_MAN__A
, qam16IsGainMan
, 0x0000);
2244 status
= Write16(state
, EQ_REG_IS_GAIN_EXP__A
, qam16IsGainExp
, 0x0000);
2255 switch (DRX_CHANNEL_HIGH
) {
2257 case DRX_CHANNEL_AUTO
:
2258 case DRX_CHANNEL_LOW
:
2259 transmissionParams
|= SC_RA_RAM_OP_PARAM_PRIO_LO
;
2260 status
= Write16(state
, EC_SB_REG_PRIOR__A
, EC_SB_REG_PRIOR_LO
, 0x0000);
2264 case DRX_CHANNEL_HIGH
:
2265 transmissionParams
|= SC_RA_RAM_OP_PARAM_PRIO_HI
;
2266 status
= Write16(state
, EC_SB_REG_PRIOR__A
, EC_SB_REG_PRIOR_HI
, 0x0000);
2273 switch (p
->code_rate_HP
) {
2275 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_1_2
;
2276 if (state
->type_A
) {
2277 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C1_2
, 0x0000);
2283 operationMode
|= SC_RA_RAM_OP_AUTO_RATE__M
;
2285 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_2_3
;
2286 if (state
->type_A
) {
2287 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C2_3
, 0x0000);
2293 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_3_4
;
2294 if (state
->type_A
) {
2295 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C3_4
, 0x0000);
2301 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_5_6
;
2302 if (state
->type_A
) {
2303 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C5_6
, 0x0000);
2309 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_7_8
;
2310 if (state
->type_A
) {
2311 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C7_8
, 0x0000);
2321 /* First determine real bandwidth (Hz) */
2322 /* Also set delay for impulse noise cruncher (only A2) */
2323 /* Also set parameters for EC_OC fix, note
2324 EC_OC_REG_TMD_HIL_MAR is changed
2325 by SC for fix for some 8K,1/8 guard but is restored by
2328 switch (p
->bandwidth
) {
2329 case BANDWIDTH_AUTO
:
2330 case BANDWIDTH_8_MHZ
:
2331 /* (64/7)*(8/8)*1000000 */
2332 bandwidth
= DRXD_BANDWIDTH_8MHZ_IN_HZ
;
2335 status
= Write16(state
,
2336 FE_AG_REG_IND_DEL__A
, 50, 0x0000);
2338 case BANDWIDTH_7_MHZ
:
2339 /* (64/7)*(7/8)*1000000 */
2340 bandwidth
= DRXD_BANDWIDTH_7MHZ_IN_HZ
;
2341 bandwidthParam
= 0x4807; /*binary:0100 1000 0000 0111 */
2342 status
= Write16(state
,
2343 FE_AG_REG_IND_DEL__A
, 59, 0x0000);
2345 case BANDWIDTH_6_MHZ
:
2346 /* (64/7)*(6/8)*1000000 */
2347 bandwidth
= DRXD_BANDWIDTH_6MHZ_IN_HZ
;
2348 bandwidthParam
= 0x0F07; /*binary: 0000 1111 0000 0111 */
2349 status
= Write16(state
,
2350 FE_AG_REG_IND_DEL__A
, 71, 0x0000);
2358 status
= Write16(state
, SC_RA_RAM_BAND__A
, bandwidthParam
, 0x0000);
2364 status
= Read16(state
, SC_RA_RAM_CONFIG__A
, &sc_config
, 0);
2368 /* enable SLAVE mode in 2k 1/32 to
2369 prevent timing change glitches */
2370 if ((p
->transmission_mode
== TRANSMISSION_MODE_2K
) &&
2371 (p
->guard_interval
== GUARD_INTERVAL_1_32
)) {
2373 sc_config
|= SC_RA_RAM_CONFIG_SLAVE__M
;
2376 sc_config
&= ~SC_RA_RAM_CONFIG_SLAVE__M
;
2378 status
= Write16(state
, SC_RA_RAM_CONFIG__A
, sc_config
, 0);
2383 status
= SetCfgNoiseCalibration(state
, &state
->noise_cal
);
2387 if (state
->cscd_state
== CSCD_INIT
) {
2388 /* switch on SRMM scan in SC */
2389 status
= Write16(state
, SC_RA_RAM_SAMPLE_RATE_COUNT__A
, DRXD_OSCDEV_DO_SCAN
, 0x0000);
2392 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2393 state
->cscd_state
= CSCD_SET
;
2396 /* Now compute FE_IF_REG_INCR */
2397 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2398 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2399 feIfIncr
= MulDiv32(state
->sys_clock_freq
* 1000,
2400 (1ULL << 21), bandwidth
) - (1 << 23);
2401 status
= Write16(state
, FE_IF_REG_INCR0__A
, (u16
) (feIfIncr
& FE_IF_REG_INCR0__M
), 0x0000);
2404 status
= Write16(state
, FE_IF_REG_INCR1__A
, (u16
) ((feIfIncr
>> FE_IF_REG_INCR0__W
) & FE_IF_REG_INCR1__M
), 0x0000);
2407 /* Bandwidth setting done */
2409 /* Mirror & frequency offset */
2410 SetFrequencyShift(state
, off
, mirrorFreqSpect
);
2412 /* Start SC, write channel settings to SC */
2414 /* Enable SC after setting all other parameters */
2415 status
= Write16(state
, SC_COMM_STATE__A
, 0, 0x0000);
2418 status
= Write16(state
, SC_COMM_EXEC__A
, 1, 0x0000);
2422 /* Write SC parameter registers, operation mode */
2424 operationMode
= (SC_RA_RAM_OP_AUTO_MODE__M
|
2425 SC_RA_RAM_OP_AUTO_GUARD__M
|
2426 SC_RA_RAM_OP_AUTO_CONST__M
|
2427 SC_RA_RAM_OP_AUTO_HIER__M
|
2428 SC_RA_RAM_OP_AUTO_RATE__M
);
2430 status
= SC_SetPrefParamCommand(state
, 0x0000, transmissionParams
, operationMode
);
2434 /* Start correct processes to get in lock */
2435 status
= SC_ProcStartCommand(state
, SC_RA_RAM_PROC_LOCKTRACK
, SC_RA_RAM_SW_EVENT_RUN_NMASK__M
, SC_RA_RAM_LOCKTRACK_MIN
);
2439 status
= StartOC(state
);
2443 if (state
->operation_mode
!= OM_Default
) {
2444 status
= StartDiversity(state
);
2449 state
->drxd_state
= DRXD_STARTED
;
2455 static int CDRXD(struct drxd_state
*state
, u32 IntermediateFrequency
)
2457 u32 ulRfAgcOutputLevel
= 0xffffffff;
2458 u32 ulRfAgcSettleLevel
= 528; /* Optimum value for MT2060 */
2459 u32 ulRfAgcMinLevel
= 0; /* Currently unused */
2460 u32 ulRfAgcMaxLevel
= DRXD_FE_CTRL_MAX
; /* Currently unused */
2461 u32 ulRfAgcSpeed
= 0; /* Currently unused */
2462 u32 ulRfAgcMode
= 0; /*2; Off */
2463 u32 ulRfAgcR1
= 820;
2464 u32 ulRfAgcR2
= 2200;
2465 u32 ulRfAgcR3
= 150;
2466 u32 ulIfAgcMode
= 0; /* Auto */
2467 u32 ulIfAgcOutputLevel
= 0xffffffff;
2468 u32 ulIfAgcSettleLevel
= 0xffffffff;
2469 u32 ulIfAgcMinLevel
= 0xffffffff;
2470 u32 ulIfAgcMaxLevel
= 0xffffffff;
2471 u32 ulIfAgcSpeed
= 0xffffffff;
2472 u32 ulIfAgcR1
= 820;
2473 u32 ulIfAgcR2
= 2200;
2474 u32 ulIfAgcR3
= 150;
2475 u32 ulClock
= state
->config
.clock
;
2476 u32 ulSerialMode
= 0;
2477 u32 ulEcOcRegOcModeLop
= 4; /* Dynamic DTO source */
2478 u32 ulHiI2cDelay
= HI_I2C_DELAY
;
2479 u32 ulHiI2cBridgeDelay
= HI_I2C_BRIDGE_DELAY
;
2480 u32 ulHiI2cPatch
= 0;
2481 u32 ulEnvironment
= APPENV_PORTABLE
;
2482 u32 ulEnvironmentDiversity
= APPENV_MOBILE
;
2483 u32 ulIFFilter
= IFFILTER_SAW
;
2485 state
->if_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2486 state
->if_agc_cfg
.outputLevel
= 0;
2487 state
->if_agc_cfg
.settleLevel
= 140;
2488 state
->if_agc_cfg
.minOutputLevel
= 0;
2489 state
->if_agc_cfg
.maxOutputLevel
= 1023;
2490 state
->if_agc_cfg
.speed
= 904;
2492 if (ulIfAgcMode
== 1 && ulIfAgcOutputLevel
<= DRXD_FE_CTRL_MAX
) {
2493 state
->if_agc_cfg
.ctrlMode
= AGC_CTRL_USER
;
2494 state
->if_agc_cfg
.outputLevel
= (u16
) (ulIfAgcOutputLevel
);
2497 if (ulIfAgcMode
== 0 &&
2498 ulIfAgcSettleLevel
<= DRXD_FE_CTRL_MAX
&&
2499 ulIfAgcMinLevel
<= DRXD_FE_CTRL_MAX
&&
2500 ulIfAgcMaxLevel
<= DRXD_FE_CTRL_MAX
&&
2501 ulIfAgcSpeed
<= DRXD_FE_CTRL_MAX
) {
2502 state
->if_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2503 state
->if_agc_cfg
.settleLevel
= (u16
) (ulIfAgcSettleLevel
);
2504 state
->if_agc_cfg
.minOutputLevel
= (u16
) (ulIfAgcMinLevel
);
2505 state
->if_agc_cfg
.maxOutputLevel
= (u16
) (ulIfAgcMaxLevel
);
2506 state
->if_agc_cfg
.speed
= (u16
) (ulIfAgcSpeed
);
2509 state
->if_agc_cfg
.R1
= (u16
) (ulIfAgcR1
);
2510 state
->if_agc_cfg
.R2
= (u16
) (ulIfAgcR2
);
2511 state
->if_agc_cfg
.R3
= (u16
) (ulIfAgcR3
);
2513 state
->rf_agc_cfg
.R1
= (u16
) (ulRfAgcR1
);
2514 state
->rf_agc_cfg
.R2
= (u16
) (ulRfAgcR2
);
2515 state
->rf_agc_cfg
.R3
= (u16
) (ulRfAgcR3
);
2517 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2518 /* rest of the RFAgcCfg structure currently unused */
2519 if (ulRfAgcMode
== 1 && ulRfAgcOutputLevel
<= DRXD_FE_CTRL_MAX
) {
2520 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_USER
;
2521 state
->rf_agc_cfg
.outputLevel
= (u16
) (ulRfAgcOutputLevel
);
2524 if (ulRfAgcMode
== 0 &&
2525 ulRfAgcSettleLevel
<= DRXD_FE_CTRL_MAX
&&
2526 ulRfAgcMinLevel
<= DRXD_FE_CTRL_MAX
&&
2527 ulRfAgcMaxLevel
<= DRXD_FE_CTRL_MAX
&&
2528 ulRfAgcSpeed
<= DRXD_FE_CTRL_MAX
) {
2529 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2530 state
->rf_agc_cfg
.settleLevel
= (u16
) (ulRfAgcSettleLevel
);
2531 state
->rf_agc_cfg
.minOutputLevel
= (u16
) (ulRfAgcMinLevel
);
2532 state
->rf_agc_cfg
.maxOutputLevel
= (u16
) (ulRfAgcMaxLevel
);
2533 state
->rf_agc_cfg
.speed
= (u16
) (ulRfAgcSpeed
);
2536 if (ulRfAgcMode
== 2)
2537 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_OFF
;
2539 if (ulEnvironment
<= 2)
2540 state
->app_env_default
= (enum app_env
)
2542 if (ulEnvironmentDiversity
<= 2)
2543 state
->app_env_diversity
= (enum app_env
)
2544 (ulEnvironmentDiversity
);
2546 if (ulIFFilter
== IFFILTER_DISCRETE
) {
2547 /* discrete filter */
2548 state
->noise_cal
.cpOpt
= 0;
2549 state
->noise_cal
.cpNexpOfs
= 40;
2550 state
->noise_cal
.tdCal2k
= -40;
2551 state
->noise_cal
.tdCal8k
= -24;
2554 state
->noise_cal
.cpOpt
= 1;
2555 state
->noise_cal
.cpNexpOfs
= 0;
2556 state
->noise_cal
.tdCal2k
= -21;
2557 state
->noise_cal
.tdCal8k
= -24;
2559 state
->m_EcOcRegOcModeLop
= (u16
) (ulEcOcRegOcModeLop
);
2561 state
->chip_adr
= (state
->config
.demod_address
<< 1) | 1;
2562 switch (ulHiI2cPatch
) {
2564 state
->m_HiI2cPatch
= DRXD_HiI2cPatch_1
;
2567 state
->m_HiI2cPatch
= DRXD_HiI2cPatch_3
;
2570 state
->m_HiI2cPatch
= NULL
;
2573 /* modify tuner and clock attributes */
2574 state
->intermediate_freq
= (u16
) (IntermediateFrequency
/ 1000);
2575 /* expected system clock frequency in kHz */
2576 state
->expected_sys_clock_freq
= 48000;
2577 /* real system clock frequency in kHz */
2578 state
->sys_clock_freq
= 48000;
2579 state
->osc_clock_freq
= (u16
) ulClock
;
2580 state
->osc_clock_deviation
= 0;
2581 state
->cscd_state
= CSCD_INIT
;
2582 state
->drxd_state
= DRXD_UNINITIALIZED
;
2586 state
->tuner_mirrors
= 0;
2588 /* modify MPEG output attributes */
2589 state
->insert_rs_byte
= state
->config
.insert_rs_byte
;
2590 state
->enable_parallel
= (ulSerialMode
!= 1);
2592 /* Timing div, 250ns/Psys */
2593 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2595 state
->hi_cfg_timing_div
= (u16
) ((state
->sys_clock_freq
/ 1000) *
2596 ulHiI2cDelay
) / 1000;
2597 /* Bridge delay, uses oscilator clock */
2598 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2599 state
->hi_cfg_bridge_delay
= (u16
) ((state
->osc_clock_freq
/ 1000) *
2600 ulHiI2cBridgeDelay
) / 1000;
2602 state
->m_FeAgRegAgPwd
= DRXD_DEF_AG_PWD_CONSUMER
;
2603 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2604 state
->m_FeAgRegAgAgcSio
= DRXD_DEF_AG_AGC_SIO
;
2608 int DRXD_init(struct drxd_state
*state
, const u8
* fw
, u32 fw_size
)
2613 if (state
->init_done
)
2616 CDRXD(state
, state
->config
.IF
? state
->config
.IF
: 36000000);
2619 state
->operation_mode
= OM_Default
;
2621 status
= SetDeviceTypeId(state
);
2625 /* Apply I2c address patch to B1 */
2626 if (!state
->type_A
&& state
->m_HiI2cPatch
!= NULL
)
2627 status
= WriteTable(state
, state
->m_HiI2cPatch
);
2631 if (state
->type_A
) {
2632 /* HI firmware patch for UIO readout,
2633 avoid clearing of result register */
2634 status
= Write16(state
, 0x43012D, 0x047f, 0);
2639 status
= HI_ResetCommand(state
);
2643 status
= StopAllProcessors(state
);
2646 status
= InitCC(state
);
2650 state
->osc_clock_deviation
= 0;
2652 if (state
->config
.osc_deviation
)
2653 state
->osc_clock_deviation
=
2654 state
->config
.osc_deviation(state
->priv
, 0, 0);
2656 /* Handle clock deviation */
2658 s32 devA
= (s32
) (state
->osc_clock_deviation
) *
2659 (s32
) (state
->expected_sys_clock_freq
);
2660 /* deviation in kHz */
2661 s32 deviation
= (devA
/ (1000000L));
2662 /* rounding, signed */
2667 if ((devB
* (devA
% 1000000L) > 1000000L)) {
2669 deviation
+= (devB
/ 2);
2672 state
->sys_clock_freq
=
2673 (u16
) ((state
->expected_sys_clock_freq
) +
2676 status
= InitHI(state
);
2679 status
= InitAtomicRead(state
);
2683 status
= EnableAndResetMB(state
);
2687 status
= ResetCEFR(state
);
2692 status
= DownloadMicrocode(state
, fw
, fw_size
);
2696 status
= DownloadMicrocode(state
, state
->microcode
, state
->microcode_length
);
2702 state
->m_FeAgRegAgPwd
= DRXD_DEF_AG_PWD_PRO
;
2703 SetCfgPga(state
, 0); /* PGA = 0 dB */
2705 state
->m_FeAgRegAgPwd
= DRXD_DEF_AG_PWD_CONSUMER
;
2708 state
->m_FeAgRegAgAgcSio
= DRXD_DEF_AG_AGC_SIO
;
2710 status
= InitFE(state
);
2713 status
= InitFT(state
);
2716 status
= InitCP(state
);
2719 status
= InitCE(state
);
2722 status
= InitEQ(state
);
2725 status
= InitEC(state
);
2728 status
= InitSC(state
);
2732 status
= SetCfgIfAgc(state
, &state
->if_agc_cfg
);
2735 status
= SetCfgRfAgc(state
, &state
->rf_agc_cfg
);
2739 state
->cscd_state
= CSCD_INIT
;
2740 status
= Write16(state
, SC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
2743 status
= Write16(state
, LC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
2747 driverVersion
= (((VERSION_MAJOR
/ 10) << 4) +
2748 (VERSION_MAJOR
% 10)) << 24;
2749 driverVersion
+= (((VERSION_MINOR
/ 10) << 4) +
2750 (VERSION_MINOR
% 10)) << 16;
2751 driverVersion
+= ((VERSION_PATCH
/ 1000) << 12) +
2752 ((VERSION_PATCH
/ 100) << 8) +
2753 ((VERSION_PATCH
/ 10) << 4) + (VERSION_PATCH
% 10);
2755 status
= Write32(state
, SC_RA_RAM_DRIVER_VERSION__AX
, driverVersion
, 0);
2759 status
= StopOC(state
);
2763 state
->drxd_state
= DRXD_STOPPED
;
2764 state
->init_done
= 1;
2770 int DRXD_status(struct drxd_state
*state
, u32
* pLockStatus
)
2772 DRX_GetLockStatus(state
, pLockStatus
);
2774 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2775 if (*pLockStatus
& DRX_LOCK_FEC
) {
2776 ConfigureMPEGOutput(state
, 1);
2777 /* Get status again, in case we have MPEG lock now */
2778 /*DRX_GetLockStatus(state, pLockStatus); */
2784 /****************************************************************************/
2785 /****************************************************************************/
2786 /****************************************************************************/
2788 static int drxd_read_signal_strength(struct dvb_frontend
*fe
, u16
* strength
)
2790 struct drxd_state
*state
= fe
->demodulator_priv
;
2794 res
= ReadIFAgc(state
, &value
);
2798 *strength
= 0xffff - (value
<< 4);
2802 static int drxd_read_status(struct dvb_frontend
*fe
, fe_status_t
* status
)
2804 struct drxd_state
*state
= fe
->demodulator_priv
;
2807 DRXD_status(state
, &lock
);
2809 /* No MPEG lock in V255 firmware, bug ? */
2811 if (lock
& DRX_LOCK_MPEG
)
2812 *status
|= FE_HAS_LOCK
;
2814 if (lock
& DRX_LOCK_FEC
)
2815 *status
|= FE_HAS_LOCK
;
2817 if (lock
& DRX_LOCK_FEC
)
2818 *status
|= FE_HAS_VITERBI
| FE_HAS_SYNC
;
2819 if (lock
& DRX_LOCK_DEMOD
)
2820 *status
|= FE_HAS_CARRIER
| FE_HAS_SIGNAL
;
2825 static int drxd_init(struct dvb_frontend
*fe
)
2827 struct drxd_state
*state
= fe
->demodulator_priv
;
2830 /* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2831 return DRXD_init(state
, 0, 0);
2833 err
= DRXD_init(state
, state
->fw
->data
, state
->fw
->size
);
2834 release_firmware(state
->fw
);
2838 int drxd_config_i2c(struct dvb_frontend
*fe
, int onoff
)
2840 struct drxd_state
*state
= fe
->demodulator_priv
;
2842 if (state
->config
.disable_i2c_gate_ctrl
== 1)
2845 return DRX_ConfigureI2CBridge(state
, onoff
);
2847 EXPORT_SYMBOL(drxd_config_i2c
);
2849 static int drxd_get_tune_settings(struct dvb_frontend
*fe
,
2850 struct dvb_frontend_tune_settings
*sets
)
2852 sets
->min_delay_ms
= 10000;
2853 sets
->max_drift
= 0;
2854 sets
->step_size
= 0;
2858 static int drxd_read_ber(struct dvb_frontend
*fe
, u32
* ber
)
2864 static int drxd_read_snr(struct dvb_frontend
*fe
, u16
* snr
)
2870 static int drxd_read_ucblocks(struct dvb_frontend
*fe
, u32
* ucblocks
)
2876 static int drxd_sleep(struct dvb_frontend
*fe
)
2878 struct drxd_state
*state
= fe
->demodulator_priv
;
2880 ConfigureMPEGOutput(state
, 0);
2884 static int drxd_get_frontend(struct dvb_frontend
*fe
,
2885 struct dvb_frontend_parameters
*param
)
2890 static int drxd_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
2892 return drxd_config_i2c(fe
, enable
);
2895 static int drxd_set_frontend(struct dvb_frontend
*fe
,
2896 struct dvb_frontend_parameters
*param
)
2898 struct drxd_state
*state
= fe
->demodulator_priv
;
2901 state
->param
= *param
;
2904 if (fe
->ops
.tuner_ops
.set_params
) {
2905 fe
->ops
.tuner_ops
.set_params(fe
, param
);
2906 if (fe
->ops
.i2c_gate_ctrl
)
2907 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2910 /* FIXME: move PLL drivers */
2911 if (state
->config
.pll_set
&&
2912 state
->config
.pll_set(state
->priv
, param
,
2913 state
->config
.pll_address
,
2914 state
->config
.demoda_address
, &off
) < 0) {
2915 printk(KERN_ERR
"Error in pll_set\n");
2921 return DRX_Start(state
, off
);
2924 static void drxd_release(struct dvb_frontend
*fe
)
2926 struct drxd_state
*state
= fe
->demodulator_priv
;
2931 static struct dvb_frontend_ops drxd_ops
= {
2934 .name
= "Micronas DRXD DVB-T",
2936 .frequency_min
= 47125000,
2937 .frequency_max
= 855250000,
2938 .frequency_stepsize
= 166667,
2939 .frequency_tolerance
= 0,
2940 .caps
= FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
|
2941 FE_CAN_FEC_3_4
| FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
|
2943 FE_CAN_QAM_16
| FE_CAN_QAM_64
|
2945 FE_CAN_TRANSMISSION_MODE_AUTO
|
2946 FE_CAN_GUARD_INTERVAL_AUTO
|
2947 FE_CAN_HIERARCHY_AUTO
| FE_CAN_RECOVER
| FE_CAN_MUTE_TS
},
2949 .release
= drxd_release
,
2951 .sleep
= drxd_sleep
,
2952 .i2c_gate_ctrl
= drxd_i2c_gate_ctrl
,
2954 .set_frontend
= drxd_set_frontend
,
2955 .get_frontend
= drxd_get_frontend
,
2956 .get_tune_settings
= drxd_get_tune_settings
,
2958 .read_status
= drxd_read_status
,
2959 .read_ber
= drxd_read_ber
,
2960 .read_signal_strength
= drxd_read_signal_strength
,
2961 .read_snr
= drxd_read_snr
,
2962 .read_ucblocks
= drxd_read_ucblocks
,
2965 struct dvb_frontend
*drxd_attach(const struct drxd_config
*config
,
2966 void *priv
, struct i2c_adapter
*i2c
,
2969 struct drxd_state
*state
= NULL
;
2971 state
= kmalloc(sizeof(struct drxd_state
), GFP_KERNEL
);
2974 memset(state
, 0, sizeof(*state
));
2976 memcpy(&state
->ops
, &drxd_ops
, sizeof(struct dvb_frontend_ops
));
2978 state
->config
= *config
;
2982 mutex_init(&state
->mutex
);
2984 if (Read16(state
, 0, 0, 0) < 0)
2987 memcpy(&state
->frontend
.ops
, &drxd_ops
,
2988 sizeof(struct dvb_frontend_ops
));
2989 state
->frontend
.demodulator_priv
= state
;
2990 ConfigureMPEGOutput(state
, 0);
2991 return &state
->frontend
;
2994 printk(KERN_ERR
"drxd: not found\n");
2998 EXPORT_SYMBOL(drxd_attach
);
3000 MODULE_DESCRIPTION("DRXD driver");
3001 MODULE_AUTHOR("Micronas");
3002 MODULE_LICENSE("GPL");