1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 #include <linux/backlight.h>
41 /* General customization:
44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46 #define DRIVER_NAME "i915"
47 #define DRIVER_DESC "Intel Graphics"
48 #define DRIVER_DATE "20080730"
56 #define pipe_name(p) ((p) + 'A')
63 #define plane_name(p) ((p) + 'A')
65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
79 #define DRIVER_MAJOR 1
80 #define DRIVER_MINOR 6
81 #define DRIVER_PATCHLEVEL 0
83 #define WATCH_COHERENCY 0
86 #define I915_GEM_PHYS_CURSOR_0 1
87 #define I915_GEM_PHYS_CURSOR_1 2
88 #define I915_GEM_PHYS_OVERLAY_REGS 3
89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91 struct drm_i915_gem_phys_object
{
93 struct page
**page_list
;
94 drm_dma_handle_t
*handle
;
95 struct drm_i915_gem_object
*cur_obj
;
99 struct mem_block
*next
;
100 struct mem_block
*prev
;
103 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header
;
107 struct opregion_acpi
;
108 struct opregion_swsci
;
109 struct opregion_asle
;
111 struct intel_opregion
{
112 struct opregion_header
*header
;
113 struct opregion_acpi
*acpi
;
114 struct opregion_swsci
*swsci
;
115 struct opregion_asle
*asle
;
117 u32 __iomem
*lid_state
;
119 #define OPREGION_SIZE (8*1024)
121 struct intel_overlay
;
122 struct intel_overlay_error_state
;
124 struct drm_i915_master_private
{
125 drm_local_map_t
*sarea
;
126 struct _drm_i915_sarea
*sarea_priv
;
128 #define I915_FENCE_REG_NONE -1
130 struct drm_i915_fence_reg
{
131 struct list_head lru_list
;
132 struct drm_i915_gem_object
*obj
;
133 uint32_t setup_seqno
;
136 struct sdvo_device_mapping
{
146 struct intel_display_error_state
;
148 struct drm_i915_error_state
{
151 u32 pipestat
[I915_MAX_PIPES
];
156 u32 error
; /* gen6+ */
157 u32 bcs_acthd
; /* gen6+ blt engine */
162 u32 vcs_acthd
; /* gen6+ bsd engine */
174 struct drm_i915_error_object
{
178 } *ringbuffer
[I915_NUM_RINGS
], *batchbuffer
[I915_NUM_RINGS
];
179 struct drm_i915_error_buffer
{
193 } *active_bo
, *pinned_bo
;
194 u32 active_bo_count
, pinned_bo_count
;
195 struct intel_overlay_error_state
*overlay
;
196 struct intel_display_error_state
*display
;
199 struct drm_i915_display_funcs
{
200 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
201 bool (*fbc_enabled
)(struct drm_device
*dev
);
202 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
203 void (*disable_fbc
)(struct drm_device
*dev
);
204 int (*get_display_clock_speed
)(struct drm_device
*dev
);
205 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
206 void (*update_wm
)(struct drm_device
*dev
);
207 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
208 struct drm_display_mode
*mode
,
209 struct drm_display_mode
*adjusted_mode
,
211 struct drm_framebuffer
*old_fb
);
212 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
213 void (*init_clock_gating
)(struct drm_device
*dev
);
214 void (*init_pch_clock_gating
)(struct drm_device
*dev
);
215 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
216 struct drm_framebuffer
*fb
,
217 struct drm_i915_gem_object
*obj
);
218 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
220 /* clock updates for mode set */
222 /* render clock increase/decrease */
223 /* display clock increase/decrease */
224 /* pll clock increase/decrease */
227 struct intel_device_info
{
237 u8 is_broadwater
: 1;
241 u8 has_pipe_cxsr
: 1;
243 u8 cursor_needs_physical
: 1;
245 u8 overlay_needs_physical
: 1;
252 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
253 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
254 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
255 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
256 FBC_BAD_PLANE
, /* fbc not supported on plane */
257 FBC_NOT_TILED
, /* buffer not tiled */
258 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
263 PCH_IBX
, /* Ibexpeak PCH */
264 PCH_CPT
, /* Cougarpoint PCH */
267 #define QUIRK_PIPEA_FORCE (1<<0)
268 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
271 struct intel_fbc_work
;
273 typedef struct drm_i915_private
{
274 struct drm_device
*dev
;
276 const struct intel_device_info
*info
;
279 int relative_constants_mode
;
285 struct i2c_adapter adapter
;
286 struct i2c_adapter
*force_bit
;
290 struct pci_dev
*bridge_dev
;
291 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
294 drm_dma_handle_t
*status_page_dmah
;
296 drm_local_map_t hws_map
;
297 struct drm_i915_gem_object
*pwrctx
;
298 struct drm_i915_gem_object
*renderctx
;
300 struct resource mch_res
;
308 atomic_t irq_received
;
310 /* protects the irq masks */
312 /** Cached value of IMR to avoid reads in updating the bitfield */
318 u32 hotplug_supported_mask
;
319 struct work_struct hotplug_work
;
321 int tex_lru_log_granularity
;
322 int allow_batchbuffer
;
323 struct mem_block
*agp_heap
;
324 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
328 /* For hangcheck timer */
329 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
330 struct timer_list hangcheck_timer
;
333 uint32_t last_instdone
;
334 uint32_t last_instdone1
;
336 unsigned long cfb_size
;
338 enum plane cfb_plane
;
340 struct intel_fbc_work
*fbc_work
;
342 struct intel_opregion opregion
;
345 struct intel_overlay
*overlay
;
348 int backlight_level
; /* restore backlight to this value */
349 bool backlight_enabled
;
350 struct drm_display_mode
*panel_fixed_mode
;
351 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
352 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
354 /* Feature bits from the VBIOS */
355 unsigned int int_tv_support
:1;
356 unsigned int lvds_dither
:1;
357 unsigned int lvds_vbt
:1;
358 unsigned int int_crt_support
:1;
359 unsigned int lvds_use_ssc
:1;
370 struct edp_power_seq pps
;
372 bool no_aux_handshake
;
374 struct notifier_block lid_notifier
;
377 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
378 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
379 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
381 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
383 spinlock_t error_lock
;
384 struct drm_i915_error_state
*first_error
;
385 struct work_struct error_work
;
386 struct completion error_completion
;
387 struct workqueue_struct
*wq
;
389 /* Display functions */
390 struct drm_i915_display_funcs display
;
392 /* PCH chipset type */
393 enum intel_pch pch_type
;
395 unsigned long quirks
;
420 u32 saveTRANS_HTOTAL_A
;
421 u32 saveTRANS_HBLANK_A
;
422 u32 saveTRANS_HSYNC_A
;
423 u32 saveTRANS_VTOTAL_A
;
424 u32 saveTRANS_VBLANK_A
;
425 u32 saveTRANS_VSYNC_A
;
433 u32 savePFIT_PGM_RATIOS
;
434 u32 saveBLC_HIST_CTL
;
436 u32 saveBLC_PWM_CTL2
;
437 u32 saveBLC_CPU_PWM_CTL
;
438 u32 saveBLC_CPU_PWM_CTL2
;
451 u32 saveTRANS_HTOTAL_B
;
452 u32 saveTRANS_HBLANK_B
;
453 u32 saveTRANS_HSYNC_B
;
454 u32 saveTRANS_VTOTAL_B
;
455 u32 saveTRANS_VBLANK_B
;
456 u32 saveTRANS_VSYNC_B
;
470 u32 savePP_ON_DELAYS
;
471 u32 savePP_OFF_DELAYS
;
479 u32 savePFIT_CONTROL
;
480 u32 save_palette_a
[256];
481 u32 save_palette_b
[256];
482 u32 saveDPFC_CB_BASE
;
483 u32 saveFBC_CFB_BASE
;
486 u32 saveFBC_CONTROL2
;
496 u32 saveCACHE_MODE_0
;
497 u32 saveMI_ARB_STATE
;
508 uint64_t saveFENCE
[16];
519 u32 savePIPEA_GMCH_DATA_M
;
520 u32 savePIPEB_GMCH_DATA_M
;
521 u32 savePIPEA_GMCH_DATA_N
;
522 u32 savePIPEB_GMCH_DATA_N
;
523 u32 savePIPEA_DP_LINK_M
;
524 u32 savePIPEB_DP_LINK_M
;
525 u32 savePIPEA_DP_LINK_N
;
526 u32 savePIPEB_DP_LINK_N
;
537 u32 savePCH_DREF_CONTROL
;
538 u32 saveDISP_ARB_CTL
;
539 u32 savePIPEA_DATA_M1
;
540 u32 savePIPEA_DATA_N1
;
541 u32 savePIPEA_LINK_M1
;
542 u32 savePIPEA_LINK_N1
;
543 u32 savePIPEB_DATA_M1
;
544 u32 savePIPEB_DATA_N1
;
545 u32 savePIPEB_LINK_M1
;
546 u32 savePIPEB_LINK_N1
;
547 u32 saveMCHBAR_RENDER_STANDBY
;
548 u32 savePCH_PORT_HOTPLUG
;
551 /** Bridge to intel-gtt-ko */
552 const struct intel_gtt
*gtt
;
553 /** Memory allocator for GTT stolen memory */
554 struct drm_mm stolen
;
555 /** Memory allocator for GTT */
556 struct drm_mm gtt_space
;
557 /** List of all objects in gtt_space. Used to restore gtt
558 * mappings on resume */
559 struct list_head gtt_list
;
561 /** Usable portion of the GTT for GEM */
562 unsigned long gtt_start
;
563 unsigned long gtt_mappable_end
;
564 unsigned long gtt_end
;
566 struct io_mapping
*gtt_mapping
;
569 struct shrinker inactive_shrinker
;
572 * List of objects currently involved in rendering.
574 * Includes buffers having the contents of their GPU caches
575 * flushed, not necessarily primitives. last_rendering_seqno
576 * represents when the rendering involved will be completed.
578 * A reference is held on the buffer while on this list.
580 struct list_head active_list
;
583 * List of objects which are not in the ringbuffer but which
584 * still have a write_domain which needs to be flushed before
587 * last_rendering_seqno is 0 while an object is in this list.
589 * A reference is held on the buffer while on this list.
591 struct list_head flushing_list
;
594 * LRU list of objects which are not in the ringbuffer and
595 * are ready to unbind, but are still in the GTT.
597 * last_rendering_seqno is 0 while an object is in this list.
599 * A reference is not held on the buffer while on this list,
600 * as merely being GTT-bound shouldn't prevent its being
601 * freed, and we'll pull it off the list in the free path.
603 struct list_head inactive_list
;
606 * LRU list of objects which are not in the ringbuffer but
607 * are still pinned in the GTT.
609 struct list_head pinned_list
;
611 /** LRU list of objects with fence regs on them. */
612 struct list_head fence_list
;
615 * List of objects currently pending being freed.
617 * These objects are no longer in use, but due to a signal
618 * we were prevented from freeing them at the appointed time.
620 struct list_head deferred_free_list
;
623 * We leave the user IRQ off as much as possible,
624 * but this means that requests will finish and never
625 * be retired once the system goes idle. Set a timer to
626 * fire periodically while the ring is running. When it
627 * fires, go retire requests.
629 struct delayed_work retire_work
;
632 * Are we in a non-interruptible section of code like
638 * Flag if the X Server, and thus DRM, is not currently in
639 * control of the device.
641 * This is set between LeaveVT and EnterVT. It needs to be
642 * replaced with a semaphore. It also needs to be
643 * transitioned away from for kernel modesetting.
648 * Flag if the hardware appears to be wedged.
650 * This is set when attempts to idle the device timeout.
651 * It prevents command submission from occurring and makes
652 * every pending request fail
656 /** Bit 6 swizzling required for X tiling */
657 uint32_t bit_6_swizzle_x
;
658 /** Bit 6 swizzling required for Y tiling */
659 uint32_t bit_6_swizzle_y
;
661 /* storage for physical objects */
662 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
664 /* accounting, useful for userland debugging */
666 size_t mappable_gtt_total
;
667 size_t object_memory
;
670 struct sdvo_device_mapping sdvo_mappings
[2];
671 /* indicate whether the LVDS_BORDER should be enabled or not */
672 unsigned int lvds_border_bits
;
673 /* Panel fitter placement and size for Ironlake+ */
674 u32 pch_pf_pos
, pch_pf_size
;
675 int panel_t3
, panel_t12
;
677 struct drm_crtc
*plane_to_crtc_mapping
[2];
678 struct drm_crtc
*pipe_to_crtc_mapping
[2];
679 wait_queue_head_t pending_flip_queue
;
680 bool flip_pending_is_done
;
682 /* Reclocking support */
683 bool render_reclock_avail
;
684 bool lvds_downclock_avail
;
685 /* indicates the reduced downclock for LVDS*/
687 struct work_struct idle_work
;
688 struct timer_list idle_timer
;
692 struct child_device_config
*child_dev
;
693 struct drm_connector
*int_lvds_connector
;
694 struct drm_connector
*int_edp_connector
;
696 bool mchbar_need_disable
;
698 struct work_struct rps_work
;
709 unsigned long last_time1
;
711 struct timespec last_time2
;
712 unsigned long gfx_power
;
716 spinlock_t
*mchdev_lock
;
718 enum no_fbc_reason no_fbc_reason
;
720 struct drm_mm_node
*compressed_fb
;
721 struct drm_mm_node
*compressed_llb
;
723 unsigned long last_gpu_reset
;
725 /* list of fbdev register on this device */
726 struct intel_fbdev
*fbdev
;
728 struct backlight_device
*backlight
;
730 struct drm_property
*broadcast_rgb_property
;
731 struct drm_property
*force_audio_property
;
733 atomic_t forcewake_count
;
734 } drm_i915_private_t
;
736 enum i915_cache_level
{
739 I915_CACHE_LLC_MLC
, /* gen6+ */
742 struct drm_i915_gem_object
{
743 struct drm_gem_object base
;
745 /** Current space allocated to this object in the GTT, if any. */
746 struct drm_mm_node
*gtt_space
;
747 struct list_head gtt_list
;
749 /** This object's place on the active/flushing/inactive lists */
750 struct list_head ring_list
;
751 struct list_head mm_list
;
752 /** This object's place on GPU write list */
753 struct list_head gpu_write_list
;
754 /** This object's place in the batchbuffer or on the eviction list */
755 struct list_head exec_list
;
758 * This is set if the object is on the active or flushing lists
759 * (has pending rendering), and is not set if it's on inactive (ready
762 unsigned int active
: 1;
765 * This is set if the object has been written to since last bound
768 unsigned int dirty
: 1;
771 * This is set if the object has been written to since the last
774 unsigned int pending_gpu_write
: 1;
777 * Fence register bits (if any) for this object. Will be set
778 * as needed when mapped into the GTT.
779 * Protected by dev->struct_mutex.
781 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
783 signed int fence_reg
: 5;
786 * Advice: are the backing pages purgeable?
788 unsigned int madv
: 2;
791 * Current tiling mode for the object.
793 unsigned int tiling_mode
: 2;
794 unsigned int tiling_changed
: 1;
796 /** How many users have pinned this object in GTT space. The following
797 * users can each hold at most one reference: pwrite/pread, pin_ioctl
798 * (via user_pin_count), execbuffer (objects are not allowed multiple
799 * times for the same batchbuffer), and the framebuffer code. When
800 * switching/pageflipping, the framebuffer code has at most two buffers
803 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
804 * bits with absolutely no headroom. So use 4 bits. */
805 unsigned int pin_count
: 4;
806 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
809 * Is the object at the current location in the gtt mappable and
810 * fenceable? Used to avoid costly recalculations.
812 unsigned int map_and_fenceable
: 1;
815 * Whether the current gtt mapping needs to be mappable (and isn't just
816 * mappable by accident). Track pin and fault separate for a more
817 * accurate mappable working set.
819 unsigned int fault_mappable
: 1;
820 unsigned int pin_mappable
: 1;
823 * Is the GPU currently using a fence to access this buffer,
825 unsigned int pending_fenced_gpu_access
:1;
826 unsigned int fenced_gpu_access
:1;
828 unsigned int cache_level
:2;
835 struct scatterlist
*sg_list
;
839 * Used for performing relocations during execbuffer insertion.
841 struct hlist_node exec_node
;
842 unsigned long exec_handle
;
843 struct drm_i915_gem_exec_object2
*exec_entry
;
846 * Current offset of the object in GTT space.
848 * This is the same as gtt_space->start
852 /** Breadcrumb of last rendering to the buffer. */
853 uint32_t last_rendering_seqno
;
854 struct intel_ring_buffer
*ring
;
856 /** Breadcrumb of last fenced GPU access to the buffer. */
857 uint32_t last_fenced_seqno
;
858 struct intel_ring_buffer
*last_fenced_ring
;
860 /** Current tiling stride for the object, if it's tiled. */
863 /** Record of address bit 17 of each page at last unbind. */
864 unsigned long *bit_17
;
868 * If present, while GEM_DOMAIN_CPU is in the read domain this array
869 * flags which individual pages are valid.
871 uint8_t *page_cpu_valid
;
873 /** User space pin count and filp owning the pin */
874 uint32_t user_pin_count
;
875 struct drm_file
*pin_filp
;
877 /** for phy allocated objects */
878 struct drm_i915_gem_phys_object
*phys_obj
;
881 * Number of crtcs where this object is currently the fb, but
882 * will be page flipped away on the next vblank. When it
883 * reaches 0, dev_priv->pending_flip_queue will be woken up.
885 atomic_t pending_flip
;
888 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
891 * Request queue structure.
893 * The request queue allows us to note sequence numbers that have been emitted
894 * and may be associated with active buffers to be retired.
896 * By keeping this list, we can avoid having to do questionable
897 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
898 * an emission time with seqnos for tracking how far ahead of the GPU we are.
900 struct drm_i915_gem_request
{
901 /** On Which ring this request was generated */
902 struct intel_ring_buffer
*ring
;
904 /** GEM sequence number associated with this request. */
907 /** Time at which this request was emitted, in jiffies. */
908 unsigned long emitted_jiffies
;
910 /** global list entry for this request */
911 struct list_head list
;
913 struct drm_i915_file_private
*file_priv
;
914 /** file_priv list entry for this request */
915 struct list_head client_list
;
918 struct drm_i915_file_private
{
920 struct spinlock lock
;
921 struct list_head request_list
;
925 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
927 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
928 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
929 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
930 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
931 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
932 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
933 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
934 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
935 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
936 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
937 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
938 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
939 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
940 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
941 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
942 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
943 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
944 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
945 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
946 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
949 * The genX designation typically refers to the render engine, so render
950 * capability related checks should use IS_GEN, while display and other checks
951 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
954 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
955 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
956 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
957 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
958 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
959 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
961 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
962 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
963 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
965 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
966 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
968 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
969 * rows, which changed the alignment requirements and fence programming.
971 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
973 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
974 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
975 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
976 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
977 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
978 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
979 /* dsparb controlled by hw only */
980 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
982 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
983 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
984 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
986 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
987 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
989 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
990 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
991 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
993 #include "i915_trace.h"
995 extern struct drm_ioctl_desc i915_ioctls
[];
996 extern int i915_max_ioctl
;
997 extern unsigned int i915_fbpercrtc __always_unused
;
998 extern int i915_panel_ignore_lid __read_mostly
;
999 extern unsigned int i915_powersave __read_mostly
;
1000 extern unsigned int i915_semaphores __read_mostly
;
1001 extern unsigned int i915_lvds_downclock __read_mostly
;
1002 extern unsigned int i915_panel_use_ssc __read_mostly
;
1003 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1004 extern unsigned int i915_enable_rc6 __read_mostly
;
1005 extern unsigned int i915_enable_fbc __read_mostly
;
1006 extern bool i915_enable_hangcheck __read_mostly
;
1008 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1009 extern int i915_resume(struct drm_device
*dev
);
1010 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1011 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1014 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1015 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1016 extern int i915_driver_unload(struct drm_device
*);
1017 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1018 extern void i915_driver_lastclose(struct drm_device
* dev
);
1019 extern void i915_driver_preclose(struct drm_device
*dev
,
1020 struct drm_file
*file_priv
);
1021 extern void i915_driver_postclose(struct drm_device
*dev
,
1022 struct drm_file
*file_priv
);
1023 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1024 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1026 extern int i915_emit_box(struct drm_device
*dev
,
1027 struct drm_clip_rect
*box
,
1029 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
1030 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1031 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1032 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1033 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1037 void i915_hangcheck_elapsed(unsigned long data
);
1038 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1039 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
1040 struct drm_file
*file_priv
);
1041 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
1042 struct drm_file
*file_priv
);
1044 extern void intel_irq_init(struct drm_device
*dev
);
1046 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1047 struct drm_file
*file_priv
);
1048 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1049 struct drm_file
*file_priv
);
1050 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1051 struct drm_file
*file_priv
);
1054 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1057 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1059 void intel_enable_asle (struct drm_device
*dev
);
1061 #ifdef CONFIG_DEBUG_FS
1062 extern void i915_destroy_error_state(struct drm_device
*dev
);
1064 #define i915_destroy_error_state(x)
1069 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
1070 struct drm_file
*file_priv
);
1071 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
1072 struct drm_file
*file_priv
);
1073 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
1074 struct drm_file
*file_priv
);
1075 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
1076 struct drm_file
*file_priv
);
1077 extern void i915_mem_takedown(struct mem_block
**heap
);
1078 extern void i915_mem_release(struct drm_device
* dev
,
1079 struct drm_file
*file_priv
, struct mem_block
*heap
);
1081 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1082 struct drm_file
*file_priv
);
1083 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1084 struct drm_file
*file_priv
);
1085 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1086 struct drm_file
*file_priv
);
1087 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1088 struct drm_file
*file_priv
);
1089 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1090 struct drm_file
*file_priv
);
1091 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1092 struct drm_file
*file_priv
);
1093 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1094 struct drm_file
*file_priv
);
1095 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1096 struct drm_file
*file_priv
);
1097 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1098 struct drm_file
*file_priv
);
1099 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1100 struct drm_file
*file_priv
);
1101 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1102 struct drm_file
*file_priv
);
1103 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1104 struct drm_file
*file_priv
);
1105 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1106 struct drm_file
*file_priv
);
1107 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1108 struct drm_file
*file_priv
);
1109 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1110 struct drm_file
*file_priv
);
1111 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1112 struct drm_file
*file_priv
);
1113 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1114 struct drm_file
*file_priv
);
1115 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1116 struct drm_file
*file_priv
);
1117 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1118 struct drm_file
*file_priv
);
1119 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1120 struct drm_file
*file_priv
);
1121 void i915_gem_load(struct drm_device
*dev
);
1122 int i915_gem_init_object(struct drm_gem_object
*obj
);
1123 int __must_check
i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
1124 uint32_t invalidate_domains
,
1125 uint32_t flush_domains
);
1126 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1128 void i915_gem_free_object(struct drm_gem_object
*obj
);
1129 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1131 bool map_and_fenceable
);
1132 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1133 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1134 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1135 void i915_gem_lastclose(struct drm_device
*dev
);
1137 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1138 int __must_check
i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
);
1139 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1140 struct intel_ring_buffer
*ring
,
1143 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1144 struct drm_device
*dev
,
1145 struct drm_mode_create_dumb
*args
);
1146 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1147 uint32_t handle
, uint64_t *offset
);
1148 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1151 * Returns true if seq1 is later than seq2.
1154 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1156 return (int32_t)(seq1
- seq2
) >= 0;
1160 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1162 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1163 return ring
->outstanding_lazy_request
= dev_priv
->next_seqno
;
1166 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
1167 struct intel_ring_buffer
*pipelined
);
1168 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1170 void i915_gem_retire_requests(struct drm_device
*dev
);
1171 void i915_gem_reset(struct drm_device
*dev
);
1172 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1173 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1174 uint32_t read_domains
,
1175 uint32_t write_domain
);
1176 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1177 int __must_check
i915_gem_init_ringbuffer(struct drm_device
*dev
);
1178 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1179 void i915_gem_do_init(struct drm_device
*dev
,
1180 unsigned long start
,
1181 unsigned long mappable_end
,
1183 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1184 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1185 int __must_check
i915_add_request(struct intel_ring_buffer
*ring
,
1186 struct drm_file
*file
,
1187 struct drm_i915_gem_request
*request
);
1188 int __must_check
i915_wait_request(struct intel_ring_buffer
*ring
,
1190 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1192 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1195 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1197 struct intel_ring_buffer
*pipelined
);
1198 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1199 struct drm_i915_gem_object
*obj
,
1202 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1203 struct drm_i915_gem_object
*obj
);
1204 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1205 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1208 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1212 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1213 enum i915_cache_level cache_level
);
1215 /* i915_gem_gtt.c */
1216 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1217 int __must_check
i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
);
1218 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object
*obj
,
1219 enum i915_cache_level cache_level
);
1220 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1222 /* i915_gem_evict.c */
1223 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1224 unsigned alignment
, bool mappable
);
1225 int __must_check
i915_gem_evict_everything(struct drm_device
*dev
,
1226 bool purgeable_only
);
1227 int __must_check
i915_gem_evict_inactive(struct drm_device
*dev
,
1228 bool purgeable_only
);
1230 /* i915_gem_tiling.c */
1231 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1232 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1233 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1235 /* i915_gem_debug.c */
1236 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1237 const char *where
, uint32_t mark
);
1239 int i915_verify_lists(struct drm_device
*dev
);
1241 #define i915_verify_lists(dev) 0
1243 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1245 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1246 const char *where
, uint32_t mark
);
1248 /* i915_debugfs.c */
1249 int i915_debugfs_init(struct drm_minor
*minor
);
1250 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1252 /* i915_suspend.c */
1253 extern int i915_save_state(struct drm_device
*dev
);
1254 extern int i915_restore_state(struct drm_device
*dev
);
1256 /* i915_suspend.c */
1257 extern int i915_save_state(struct drm_device
*dev
);
1258 extern int i915_restore_state(struct drm_device
*dev
);
1261 extern int intel_setup_gmbus(struct drm_device
*dev
);
1262 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1263 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1264 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1265 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1267 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1269 extern void intel_i2c_reset(struct drm_device
*dev
);
1271 /* intel_opregion.c */
1272 extern int intel_opregion_setup(struct drm_device
*dev
);
1274 extern void intel_opregion_init(struct drm_device
*dev
);
1275 extern void intel_opregion_fini(struct drm_device
*dev
);
1276 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1277 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1278 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1280 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1281 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1282 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1283 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1284 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1289 extern void intel_register_dsm_handler(void);
1290 extern void intel_unregister_dsm_handler(void);
1292 static inline void intel_register_dsm_handler(void) { return; }
1293 static inline void intel_unregister_dsm_handler(void) { return; }
1294 #endif /* CONFIG_ACPI */
1297 extern void intel_modeset_init(struct drm_device
*dev
);
1298 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1299 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1300 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1301 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1302 extern void intel_disable_fbc(struct drm_device
*dev
);
1303 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1304 extern void ironlake_enable_rc6(struct drm_device
*dev
);
1305 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1306 extern void intel_detect_pch (struct drm_device
*dev
);
1307 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1310 #ifdef CONFIG_DEBUG_FS
1311 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1312 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1314 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1315 extern void intel_display_print_error_state(struct seq_file
*m
,
1316 struct drm_device
*dev
,
1317 struct intel_display_error_state
*error
);
1320 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1322 #define BEGIN_LP_RING(n) \
1323 intel_ring_begin(LP_RING(dev_priv), (n))
1325 #define OUT_RING(x) \
1326 intel_ring_emit(LP_RING(dev_priv), x)
1328 #define ADVANCE_LP_RING() \
1329 intel_ring_advance(LP_RING(dev_priv))
1332 * Lock test for when it's just for synchronization of ring access.
1334 * In that case, we don't need to do it when GEM is initialized as nobody else
1335 * has access to the ring.
1337 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1338 if (LP_RING(dev->dev_private)->obj == NULL) \
1339 LOCK_TEST_WITH_RETURN(dev, file); \
1342 /* On SNB platform, before reading ring registers forcewake bit
1343 * must be set to prevent GT core from power down and stale values being
1346 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1347 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1348 void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1350 /* We give fast paths for the really cool registers */
1351 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1352 (((dev_priv)->info->gen >= 6) && \
1353 ((reg) < 0x40000) && \
1354 ((reg) != FORCEWAKE))
1356 #define __i915_read(x, y) \
1357 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1359 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1360 gen6_gt_force_wake_get(dev_priv); \
1361 val = read##y(dev_priv->regs + reg); \
1362 gen6_gt_force_wake_put(dev_priv); \
1364 val = read##y(dev_priv->regs + reg); \
1366 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1376 #define __i915_write(x, y) \
1377 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1378 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1379 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1380 __gen6_gt_wait_for_fifo(dev_priv); \
1382 write##y(val, dev_priv->regs + reg); \
1390 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1391 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1393 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1394 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1395 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1396 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1398 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1399 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1400 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1401 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1403 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1404 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1406 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1407 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)