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x86/PCI: use host bridge _CRS info on ASUS M2V-MX SE
[linux-btrfs-devel.git] / drivers / gpu / drm / nouveau / nouveau_state.c
blob10656e430b44106f26497beb648e19dca9226994
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
41
42 static void nouveau_stub_takedown(struct drm_device *dev) {}
43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
44
45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
46 {
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
49
50 switch (dev_priv->chipset & 0xf0) {
51 case 0x00:
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
56 engine->instmem.get = nv04_instmem_get;
57 engine->instmem.put = nv04_instmem_put;
58 engine->instmem.map = nv04_instmem_map;
59 engine->instmem.unmap = nv04_instmem_unmap;
60 engine->instmem.flush = nv04_instmem_flush;
61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
68 engine->fifo.channels = 16;
69 engine->fifo.init = nv04_fifo_init;
70 engine->fifo.takedown = nv04_fifo_fini;
71 engine->fifo.disable = nv04_fifo_disable;
72 engine->fifo.enable = nv04_fifo_enable;
73 engine->fifo.reassign = nv04_fifo_reassign;
74 engine->fifo.cache_pull = nv04_fifo_cache_pull;
75 engine->fifo.channel_id = nv04_fifo_channel_id;
76 engine->fifo.create_context = nv04_fifo_create_context;
77 engine->fifo.destroy_context = nv04_fifo_destroy_context;
78 engine->fifo.load_context = nv04_fifo_load_context;
79 engine->fifo.unload_context = nv04_fifo_unload_context;
80 engine->display.early_init = nv04_display_early_init;
81 engine->display.late_takedown = nv04_display_late_takedown;
82 engine->display.create = nv04_display_create;
83 engine->display.init = nv04_display_init;
84 engine->display.destroy = nv04_display_destroy;
85 engine->gpio.init = nouveau_stub_init;
86 engine->gpio.takedown = nouveau_stub_takedown;
87 engine->gpio.get = NULL;
88 engine->gpio.set = NULL;
89 engine->gpio.irq_enable = NULL;
90 engine->pm.clock_get = nv04_pm_clock_get;
91 engine->pm.clock_pre = nv04_pm_clock_pre;
92 engine->pm.clock_set = nv04_pm_clock_set;
93 engine->vram.init = nouveau_mem_detect;
94 engine->vram.takedown = nouveau_stub_takedown;
95 engine->vram.flags_valid = nouveau_mem_flags_valid;
96 break;
97 case 0x10:
98 engine->instmem.init = nv04_instmem_init;
99 engine->instmem.takedown = nv04_instmem_takedown;
100 engine->instmem.suspend = nv04_instmem_suspend;
101 engine->instmem.resume = nv04_instmem_resume;
102 engine->instmem.get = nv04_instmem_get;
103 engine->instmem.put = nv04_instmem_put;
104 engine->instmem.map = nv04_instmem_map;
105 engine->instmem.unmap = nv04_instmem_unmap;
106 engine->instmem.flush = nv04_instmem_flush;
107 engine->mc.init = nv04_mc_init;
108 engine->mc.takedown = nv04_mc_takedown;
109 engine->timer.init = nv04_timer_init;
110 engine->timer.read = nv04_timer_read;
111 engine->timer.takedown = nv04_timer_takedown;
112 engine->fb.init = nv10_fb_init;
113 engine->fb.takedown = nv10_fb_takedown;
114 engine->fb.init_tile_region = nv10_fb_init_tile_region;
115 engine->fb.set_tile_region = nv10_fb_set_tile_region;
116 engine->fb.free_tile_region = nv10_fb_free_tile_region;
117 engine->fifo.channels = 32;
118 engine->fifo.init = nv10_fifo_init;
119 engine->fifo.takedown = nv04_fifo_fini;
120 engine->fifo.disable = nv04_fifo_disable;
121 engine->fifo.enable = nv04_fifo_enable;
122 engine->fifo.reassign = nv04_fifo_reassign;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
124 engine->fifo.channel_id = nv10_fifo_channel_id;
125 engine->fifo.create_context = nv10_fifo_create_context;
126 engine->fifo.destroy_context = nv04_fifo_destroy_context;
127 engine->fifo.load_context = nv10_fifo_load_context;
128 engine->fifo.unload_context = nv10_fifo_unload_context;
129 engine->display.early_init = nv04_display_early_init;
130 engine->display.late_takedown = nv04_display_late_takedown;
131 engine->display.create = nv04_display_create;
132 engine->display.init = nv04_display_init;
133 engine->display.destroy = nv04_display_destroy;
134 engine->gpio.init = nouveau_stub_init;
135 engine->gpio.takedown = nouveau_stub_takedown;
136 engine->gpio.get = nv10_gpio_get;
137 engine->gpio.set = nv10_gpio_set;
138 engine->gpio.irq_enable = NULL;
139 engine->pm.clock_get = nv04_pm_clock_get;
140 engine->pm.clock_pre = nv04_pm_clock_pre;
141 engine->pm.clock_set = nv04_pm_clock_set;
142 engine->vram.init = nouveau_mem_detect;
143 engine->vram.takedown = nouveau_stub_takedown;
144 engine->vram.flags_valid = nouveau_mem_flags_valid;
145 break;
146 case 0x20:
147 engine->instmem.init = nv04_instmem_init;
148 engine->instmem.takedown = nv04_instmem_takedown;
149 engine->instmem.suspend = nv04_instmem_suspend;
150 engine->instmem.resume = nv04_instmem_resume;
151 engine->instmem.get = nv04_instmem_get;
152 engine->instmem.put = nv04_instmem_put;
153 engine->instmem.map = nv04_instmem_map;
154 engine->instmem.unmap = nv04_instmem_unmap;
155 engine->instmem.flush = nv04_instmem_flush;
156 engine->mc.init = nv04_mc_init;
157 engine->mc.takedown = nv04_mc_takedown;
158 engine->timer.init = nv04_timer_init;
159 engine->timer.read = nv04_timer_read;
160 engine->timer.takedown = nv04_timer_takedown;
161 engine->fb.init = nv10_fb_init;
162 engine->fb.takedown = nv10_fb_takedown;
163 engine->fb.init_tile_region = nv10_fb_init_tile_region;
164 engine->fb.set_tile_region = nv10_fb_set_tile_region;
165 engine->fb.free_tile_region = nv10_fb_free_tile_region;
166 engine->fifo.channels = 32;
167 engine->fifo.init = nv10_fifo_init;
168 engine->fifo.takedown = nv04_fifo_fini;
169 engine->fifo.disable = nv04_fifo_disable;
170 engine->fifo.enable = nv04_fifo_enable;
171 engine->fifo.reassign = nv04_fifo_reassign;
172 engine->fifo.cache_pull = nv04_fifo_cache_pull;
173 engine->fifo.channel_id = nv10_fifo_channel_id;
174 engine->fifo.create_context = nv10_fifo_create_context;
175 engine->fifo.destroy_context = nv04_fifo_destroy_context;
176 engine->fifo.load_context = nv10_fifo_load_context;
177 engine->fifo.unload_context = nv10_fifo_unload_context;
178 engine->display.early_init = nv04_display_early_init;
179 engine->display.late_takedown = nv04_display_late_takedown;
180 engine->display.create = nv04_display_create;
181 engine->display.init = nv04_display_init;
182 engine->display.destroy = nv04_display_destroy;
183 engine->gpio.init = nouveau_stub_init;
184 engine->gpio.takedown = nouveau_stub_takedown;
185 engine->gpio.get = nv10_gpio_get;
186 engine->gpio.set = nv10_gpio_set;
187 engine->gpio.irq_enable = NULL;
188 engine->pm.clock_get = nv04_pm_clock_get;
189 engine->pm.clock_pre = nv04_pm_clock_pre;
190 engine->pm.clock_set = nv04_pm_clock_set;
191 engine->vram.init = nouveau_mem_detect;
192 engine->vram.takedown = nouveau_stub_takedown;
193 engine->vram.flags_valid = nouveau_mem_flags_valid;
194 break;
195 case 0x30:
196 engine->instmem.init = nv04_instmem_init;
197 engine->instmem.takedown = nv04_instmem_takedown;
198 engine->instmem.suspend = nv04_instmem_suspend;
199 engine->instmem.resume = nv04_instmem_resume;
200 engine->instmem.get = nv04_instmem_get;
201 engine->instmem.put = nv04_instmem_put;
202 engine->instmem.map = nv04_instmem_map;
203 engine->instmem.unmap = nv04_instmem_unmap;
204 engine->instmem.flush = nv04_instmem_flush;
205 engine->mc.init = nv04_mc_init;
206 engine->mc.takedown = nv04_mc_takedown;
207 engine->timer.init = nv04_timer_init;
208 engine->timer.read = nv04_timer_read;
209 engine->timer.takedown = nv04_timer_takedown;
210 engine->fb.init = nv30_fb_init;
211 engine->fb.takedown = nv30_fb_takedown;
212 engine->fb.init_tile_region = nv30_fb_init_tile_region;
213 engine->fb.set_tile_region = nv10_fb_set_tile_region;
214 engine->fb.free_tile_region = nv30_fb_free_tile_region;
215 engine->fifo.channels = 32;
216 engine->fifo.init = nv10_fifo_init;
217 engine->fifo.takedown = nv04_fifo_fini;
218 engine->fifo.disable = nv04_fifo_disable;
219 engine->fifo.enable = nv04_fifo_enable;
220 engine->fifo.reassign = nv04_fifo_reassign;
221 engine->fifo.cache_pull = nv04_fifo_cache_pull;
222 engine->fifo.channel_id = nv10_fifo_channel_id;
223 engine->fifo.create_context = nv10_fifo_create_context;
224 engine->fifo.destroy_context = nv04_fifo_destroy_context;
225 engine->fifo.load_context = nv10_fifo_load_context;
226 engine->fifo.unload_context = nv10_fifo_unload_context;
227 engine->display.early_init = nv04_display_early_init;
228 engine->display.late_takedown = nv04_display_late_takedown;
229 engine->display.create = nv04_display_create;
230 engine->display.init = nv04_display_init;
231 engine->display.destroy = nv04_display_destroy;
232 engine->gpio.init = nouveau_stub_init;
233 engine->gpio.takedown = nouveau_stub_takedown;
234 engine->gpio.get = nv10_gpio_get;
235 engine->gpio.set = nv10_gpio_set;
236 engine->gpio.irq_enable = NULL;
237 engine->pm.clock_get = nv04_pm_clock_get;
238 engine->pm.clock_pre = nv04_pm_clock_pre;
239 engine->pm.clock_set = nv04_pm_clock_set;
240 engine->pm.voltage_get = nouveau_voltage_gpio_get;
241 engine->pm.voltage_set = nouveau_voltage_gpio_set;
242 engine->vram.init = nouveau_mem_detect;
243 engine->vram.takedown = nouveau_stub_takedown;
244 engine->vram.flags_valid = nouveau_mem_flags_valid;
245 break;
246 case 0x40:
247 case 0x60:
248 engine->instmem.init = nv04_instmem_init;
249 engine->instmem.takedown = nv04_instmem_takedown;
250 engine->instmem.suspend = nv04_instmem_suspend;
251 engine->instmem.resume = nv04_instmem_resume;
252 engine->instmem.get = nv04_instmem_get;
253 engine->instmem.put = nv04_instmem_put;
254 engine->instmem.map = nv04_instmem_map;
255 engine->instmem.unmap = nv04_instmem_unmap;
256 engine->instmem.flush = nv04_instmem_flush;
257 engine->mc.init = nv40_mc_init;
258 engine->mc.takedown = nv40_mc_takedown;
259 engine->timer.init = nv04_timer_init;
260 engine->timer.read = nv04_timer_read;
261 engine->timer.takedown = nv04_timer_takedown;
262 engine->fb.init = nv40_fb_init;
263 engine->fb.takedown = nv40_fb_takedown;
264 engine->fb.init_tile_region = nv30_fb_init_tile_region;
265 engine->fb.set_tile_region = nv40_fb_set_tile_region;
266 engine->fb.free_tile_region = nv30_fb_free_tile_region;
267 engine->fifo.channels = 32;
268 engine->fifo.init = nv40_fifo_init;
269 engine->fifo.takedown = nv04_fifo_fini;
270 engine->fifo.disable = nv04_fifo_disable;
271 engine->fifo.enable = nv04_fifo_enable;
272 engine->fifo.reassign = nv04_fifo_reassign;
273 engine->fifo.cache_pull = nv04_fifo_cache_pull;
274 engine->fifo.channel_id = nv10_fifo_channel_id;
275 engine->fifo.create_context = nv40_fifo_create_context;
276 engine->fifo.destroy_context = nv04_fifo_destroy_context;
277 engine->fifo.load_context = nv40_fifo_load_context;
278 engine->fifo.unload_context = nv40_fifo_unload_context;
279 engine->display.early_init = nv04_display_early_init;
280 engine->display.late_takedown = nv04_display_late_takedown;
281 engine->display.create = nv04_display_create;
282 engine->display.init = nv04_display_init;
283 engine->display.destroy = nv04_display_destroy;
284 engine->gpio.init = nouveau_stub_init;
285 engine->gpio.takedown = nouveau_stub_takedown;
286 engine->gpio.get = nv10_gpio_get;
287 engine->gpio.set = nv10_gpio_set;
288 engine->gpio.irq_enable = NULL;
289 engine->pm.clock_get = nv04_pm_clock_get;
290 engine->pm.clock_pre = nv04_pm_clock_pre;
291 engine->pm.clock_set = nv04_pm_clock_set;
292 engine->pm.voltage_get = nouveau_voltage_gpio_get;
293 engine->pm.voltage_set = nouveau_voltage_gpio_set;
294 engine->pm.temp_get = nv40_temp_get;
295 engine->vram.init = nouveau_mem_detect;
296 engine->vram.takedown = nouveau_stub_takedown;
297 engine->vram.flags_valid = nouveau_mem_flags_valid;
298 break;
299 case 0x50:
300 case 0x80: /* gotta love NVIDIA's consistency.. */
301 case 0x90:
302 case 0xA0:
303 engine->instmem.init = nv50_instmem_init;
304 engine->instmem.takedown = nv50_instmem_takedown;
305 engine->instmem.suspend = nv50_instmem_suspend;
306 engine->instmem.resume = nv50_instmem_resume;
307 engine->instmem.get = nv50_instmem_get;
308 engine->instmem.put = nv50_instmem_put;
309 engine->instmem.map = nv50_instmem_map;
310 engine->instmem.unmap = nv50_instmem_unmap;
311 if (dev_priv->chipset == 0x50)
312 engine->instmem.flush = nv50_instmem_flush;
313 else
314 engine->instmem.flush = nv84_instmem_flush;
315 engine->mc.init = nv50_mc_init;
316 engine->mc.takedown = nv50_mc_takedown;
317 engine->timer.init = nv04_timer_init;
318 engine->timer.read = nv04_timer_read;
319 engine->timer.takedown = nv04_timer_takedown;
320 engine->fb.init = nv50_fb_init;
321 engine->fb.takedown = nv50_fb_takedown;
322 engine->fifo.channels = 128;
323 engine->fifo.init = nv50_fifo_init;
324 engine->fifo.takedown = nv50_fifo_takedown;
325 engine->fifo.disable = nv04_fifo_disable;
326 engine->fifo.enable = nv04_fifo_enable;
327 engine->fifo.reassign = nv04_fifo_reassign;
328 engine->fifo.channel_id = nv50_fifo_channel_id;
329 engine->fifo.create_context = nv50_fifo_create_context;
330 engine->fifo.destroy_context = nv50_fifo_destroy_context;
331 engine->fifo.load_context = nv50_fifo_load_context;
332 engine->fifo.unload_context = nv50_fifo_unload_context;
333 engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
334 engine->display.early_init = nv50_display_early_init;
335 engine->display.late_takedown = nv50_display_late_takedown;
336 engine->display.create = nv50_display_create;
337 engine->display.init = nv50_display_init;
338 engine->display.destroy = nv50_display_destroy;
339 engine->gpio.init = nv50_gpio_init;
340 engine->gpio.takedown = nv50_gpio_fini;
341 engine->gpio.get = nv50_gpio_get;
342 engine->gpio.set = nv50_gpio_set;
343 engine->gpio.irq_register = nv50_gpio_irq_register;
344 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
345 engine->gpio.irq_enable = nv50_gpio_irq_enable;
346 switch (dev_priv->chipset) {
347 case 0x84:
348 case 0x86:
349 case 0x92:
350 case 0x94:
351 case 0x96:
352 case 0x98:
353 case 0xa0:
354 case 0xaa:
355 case 0xac:
356 case 0x50:
357 engine->pm.clock_get = nv50_pm_clock_get;
358 engine->pm.clock_pre = nv50_pm_clock_pre;
359 engine->pm.clock_set = nv50_pm_clock_set;
360 break;
361 default:
362 engine->pm.clock_get = nva3_pm_clock_get;
363 engine->pm.clock_pre = nva3_pm_clock_pre;
364 engine->pm.clock_set = nva3_pm_clock_set;
365 break;
366 }
367 engine->pm.voltage_get = nouveau_voltage_gpio_get;
368 engine->pm.voltage_set = nouveau_voltage_gpio_set;
369 if (dev_priv->chipset >= 0x84)
370 engine->pm.temp_get = nv84_temp_get;
371 else
372 engine->pm.temp_get = nv40_temp_get;
373 engine->vram.init = nv50_vram_init;
374 engine->vram.takedown = nv50_vram_fini;
375 engine->vram.get = nv50_vram_new;
376 engine->vram.put = nv50_vram_del;
377 engine->vram.flags_valid = nv50_vram_flags_valid;
378 break;
379 case 0xC0:
380 engine->instmem.init = nvc0_instmem_init;
381 engine->instmem.takedown = nvc0_instmem_takedown;
382 engine->instmem.suspend = nvc0_instmem_suspend;
383 engine->instmem.resume = nvc0_instmem_resume;
384 engine->instmem.get = nv50_instmem_get;
385 engine->instmem.put = nv50_instmem_put;
386 engine->instmem.map = nv50_instmem_map;
387 engine->instmem.unmap = nv50_instmem_unmap;
388 engine->instmem.flush = nv84_instmem_flush;
389 engine->mc.init = nv50_mc_init;
390 engine->mc.takedown = nv50_mc_takedown;
391 engine->timer.init = nv04_timer_init;
392 engine->timer.read = nv04_timer_read;
393 engine->timer.takedown = nv04_timer_takedown;
394 engine->fb.init = nvc0_fb_init;
395 engine->fb.takedown = nvc0_fb_takedown;
396 engine->fifo.channels = 128;
397 engine->fifo.init = nvc0_fifo_init;
398 engine->fifo.takedown = nvc0_fifo_takedown;
399 engine->fifo.disable = nvc0_fifo_disable;
400 engine->fifo.enable = nvc0_fifo_enable;
401 engine->fifo.reassign = nvc0_fifo_reassign;
402 engine->fifo.channel_id = nvc0_fifo_channel_id;
403 engine->fifo.create_context = nvc0_fifo_create_context;
404 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
405 engine->fifo.load_context = nvc0_fifo_load_context;
406 engine->fifo.unload_context = nvc0_fifo_unload_context;
407 engine->display.early_init = nv50_display_early_init;
408 engine->display.late_takedown = nv50_display_late_takedown;
409 engine->display.create = nv50_display_create;
410 engine->display.init = nv50_display_init;
411 engine->display.destroy = nv50_display_destroy;
412 engine->gpio.init = nv50_gpio_init;
413 engine->gpio.takedown = nouveau_stub_takedown;
414 engine->gpio.get = nv50_gpio_get;
415 engine->gpio.set = nv50_gpio_set;
416 engine->gpio.irq_register = nv50_gpio_irq_register;
417 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
418 engine->gpio.irq_enable = nv50_gpio_irq_enable;
419 engine->vram.init = nvc0_vram_init;
420 engine->vram.takedown = nv50_vram_fini;
421 engine->vram.get = nvc0_vram_new;
422 engine->vram.put = nv50_vram_del;
423 engine->vram.flags_valid = nvc0_vram_flags_valid;
424 engine->pm.temp_get = nv84_temp_get;
425 break;
426 default:
427 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
428 return 1;
429 }
430
431 return 0;
432 }
433
434 static unsigned int
435 nouveau_vga_set_decode(void *priv, bool state)
436 {
437 struct drm_device *dev = priv;
438 struct drm_nouveau_private *dev_priv = dev->dev_private;
439
440 if (dev_priv->chipset >= 0x40)
441 nv_wr32(dev, 0x88054, state);
442 else
443 nv_wr32(dev, 0x1854, state);
444
445 if (state)
446 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
447 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
448 else
449 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
450 }
451
452 static int
453 nouveau_card_init_channel(struct drm_device *dev)
454 {
455 struct drm_nouveau_private *dev_priv = dev->dev_private;
456 int ret;
457
458 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
459 NvDmaFB, NvDmaTT);
460 if (ret)
461 return ret;
462
463 mutex_unlock(&dev_priv->channel->mutex);
464 return 0;
465 }
466
467 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
468 enum vga_switcheroo_state state)
469 {
470 struct drm_device *dev = pci_get_drvdata(pdev);
471 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
472 if (state == VGA_SWITCHEROO_ON) {
473 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
474 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
475 nouveau_pci_resume(pdev);
476 drm_kms_helper_poll_enable(dev);
477 dev->switch_power_state = DRM_SWITCH_POWER_ON;
478 } else {
479 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
480 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
481 drm_kms_helper_poll_disable(dev);
482 nouveau_pci_suspend(pdev, pmm);
483 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
484 }
485 }
486
487 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
488 {
489 struct drm_device *dev = pci_get_drvdata(pdev);
490 nouveau_fbcon_output_poll_changed(dev);
491 }
492
493 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
494 {
495 struct drm_device *dev = pci_get_drvdata(pdev);
496 bool can_switch;
497
498 spin_lock(&dev->count_lock);
499 can_switch = (dev->open_count == 0);
500 spin_unlock(&dev->count_lock);
501 return can_switch;
502 }
503
504 int
505 nouveau_card_init(struct drm_device *dev)
506 {
507 struct drm_nouveau_private *dev_priv = dev->dev_private;
508 struct nouveau_engine *engine;
509 int ret, e = 0;
510
511 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
512 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
513 nouveau_switcheroo_reprobe,
514 nouveau_switcheroo_can_switch);
515
516 /* Initialise internal driver API hooks */
517 ret = nouveau_init_engine_ptrs(dev);
518 if (ret)
519 goto out;
520 engine = &dev_priv->engine;
521 spin_lock_init(&dev_priv->channels.lock);
522 spin_lock_init(&dev_priv->tile.lock);
523 spin_lock_init(&dev_priv->context_switch_lock);
524 spin_lock_init(&dev_priv->vm_lock);
525
526 /* Make the CRTCs and I2C buses accessible */
527 ret = engine->display.early_init(dev);
528 if (ret)
529 goto out;
530
531 /* Parse BIOS tables / Run init tables if card not POSTed */
532 ret = nouveau_bios_init(dev);
533 if (ret)
534 goto out_display_early;
535
536 nouveau_pm_init(dev);
537
538 ret = engine->vram.init(dev);
539 if (ret)
540 goto out_bios;
541
542 ret = nouveau_gpuobj_init(dev);
543 if (ret)
544 goto out_vram;
545
546 ret = engine->instmem.init(dev);
547 if (ret)
548 goto out_gpuobj;
549
550 ret = nouveau_mem_vram_init(dev);
551 if (ret)
552 goto out_instmem;
553
554 ret = nouveau_mem_gart_init(dev);
555 if (ret)
556 goto out_ttmvram;
557
558 /* PMC */
559 ret = engine->mc.init(dev);
560 if (ret)
561 goto out_gart;
562
563 /* PGPIO */
564 ret = engine->gpio.init(dev);
565 if (ret)
566 goto out_mc;
567
568 /* PTIMER */
569 ret = engine->timer.init(dev);
570 if (ret)
571 goto out_gpio;
572
573 /* PFB */
574 ret = engine->fb.init(dev);
575 if (ret)
576 goto out_timer;
577
578 if (!dev_priv->noaccel) {
579 switch (dev_priv->card_type) {
580 case NV_04:
581 nv04_graph_create(dev);
582 break;
583 case NV_10:
584 nv10_graph_create(dev);
585 break;
586 case NV_20:
587 case NV_30:
588 nv20_graph_create(dev);
589 break;
590 case NV_40:
591 nv40_graph_create(dev);
592 break;
593 case NV_50:
594 nv50_graph_create(dev);
595 break;
596 case NV_C0:
597 nvc0_graph_create(dev);
598 break;
599 default:
600 break;
601 }
602
603 switch (dev_priv->chipset) {
604 case 0x84:
605 case 0x86:
606 case 0x92:
607 case 0x94:
608 case 0x96:
609 case 0xa0:
610 nv84_crypt_create(dev);
611 break;
612 }
613
614 switch (dev_priv->card_type) {
615 case NV_50:
616 switch (dev_priv->chipset) {
617 case 0xa3:
618 case 0xa5:
619 case 0xa8:
620 case 0xaf:
621 nva3_copy_create(dev);
622 break;
623 }
624 break;
625 case NV_C0:
626 nvc0_copy_create(dev, 0);
627 nvc0_copy_create(dev, 1);
628 break;
629 default:
630 break;
631 }
632
633 if (dev_priv->card_type == NV_40)
634 nv40_mpeg_create(dev);
635 else
636 if (dev_priv->card_type == NV_50 &&
637 (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
638 nv50_mpeg_create(dev);
639
640 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
641 if (dev_priv->eng[e]) {
642 ret = dev_priv->eng[e]->init(dev, e);
643 if (ret)
644 goto out_engine;
645 }
646 }
647
648 /* PFIFO */
649 ret = engine->fifo.init(dev);
650 if (ret)
651 goto out_engine;
652 }
653
654 ret = engine->display.create(dev);
655 if (ret)
656 goto out_fifo;
657
658 ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
659 if (ret)
660 goto out_vblank;
661
662 ret = nouveau_irq_init(dev);
663 if (ret)
664 goto out_vblank;
665
666 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
667
668 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
669 ret = nouveau_fence_init(dev);
670 if (ret)
671 goto out_irq;
672
673 ret = nouveau_card_init_channel(dev);
674 if (ret)
675 goto out_fence;
676 }
677
678 nouveau_fbcon_init(dev);
679 drm_kms_helper_poll_init(dev);
680 return 0;
681
682 out_fence:
683 nouveau_fence_fini(dev);
684 out_irq:
685 nouveau_irq_fini(dev);
686 out_vblank:
687 drm_vblank_cleanup(dev);
688 engine->display.destroy(dev);
689 out_fifo:
690 if (!dev_priv->noaccel)
691 engine->fifo.takedown(dev);
692 out_engine:
693 if (!dev_priv->noaccel) {
694 for (e = e - 1; e >= 0; e--) {
695 if (!dev_priv->eng[e])
696 continue;
697 dev_priv->eng[e]->fini(dev, e, false);
698 dev_priv->eng[e]->destroy(dev,e );
699 }
700 }
701
702 engine->fb.takedown(dev);
703 out_timer:
704 engine->timer.takedown(dev);
705 out_gpio:
706 engine->gpio.takedown(dev);
707 out_mc:
708 engine->mc.takedown(dev);
709 out_gart:
710 nouveau_mem_gart_fini(dev);
711 out_ttmvram:
712 nouveau_mem_vram_fini(dev);
713 out_instmem:
714 engine->instmem.takedown(dev);
715 out_gpuobj:
716 nouveau_gpuobj_takedown(dev);
717 out_vram:
718 engine->vram.takedown(dev);
719 out_bios:
720 nouveau_pm_fini(dev);
721 nouveau_bios_takedown(dev);
722 out_display_early:
723 engine->display.late_takedown(dev);
724 out:
725 vga_client_register(dev->pdev, NULL, NULL, NULL);
726 return ret;
727 }
728
729 static void nouveau_card_takedown(struct drm_device *dev)
730 {
731 struct drm_nouveau_private *dev_priv = dev->dev_private;
732 struct nouveau_engine *engine = &dev_priv->engine;
733 int e;
734
735 drm_kms_helper_poll_fini(dev);
736 nouveau_fbcon_fini(dev);
737
738 if (dev_priv->channel) {
739 nouveau_channel_put_unlocked(&dev_priv->channel);
740 nouveau_fence_fini(dev);
741 }
742
743 engine->display.destroy(dev);
744
745 if (!dev_priv->noaccel) {
746 engine->fifo.takedown(dev);
747 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
748 if (dev_priv->eng[e]) {
749 dev_priv->eng[e]->fini(dev, e, false);
750 dev_priv->eng[e]->destroy(dev,e );
751 }
752 }
753 }
754 engine->fb.takedown(dev);
755 engine->timer.takedown(dev);
756 engine->gpio.takedown(dev);
757 engine->mc.takedown(dev);
758 engine->display.late_takedown(dev);
759
760 if (dev_priv->vga_ram) {
761 nouveau_bo_unpin(dev_priv->vga_ram);
762 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
763 }
764
765 mutex_lock(&dev->struct_mutex);
766 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
767 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
768 mutex_unlock(&dev->struct_mutex);
769 nouveau_mem_gart_fini(dev);
770 nouveau_mem_vram_fini(dev);
771
772 engine->instmem.takedown(dev);
773 nouveau_gpuobj_takedown(dev);
774 engine->vram.takedown(dev);
775
776 nouveau_irq_fini(dev);
777 drm_vblank_cleanup(dev);
778
779 nouveau_pm_fini(dev);
780 nouveau_bios_takedown(dev);
781
782 vga_client_register(dev->pdev, NULL, NULL, NULL);
783 }
784
785 int
786 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
787 {
788 struct drm_nouveau_private *dev_priv = dev->dev_private;
789 struct nouveau_fpriv *fpriv;
790 int ret;
791
792 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
793 if (unlikely(!fpriv))
794 return -ENOMEM;
795
796 spin_lock_init(&fpriv->lock);
797 INIT_LIST_HEAD(&fpriv->channels);
798
799 if (dev_priv->card_type == NV_50) {
800 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
801 &fpriv->vm);
802 if (ret) {
803 kfree(fpriv);
804 return ret;
805 }
806 } else
807 if (dev_priv->card_type >= NV_C0) {
808 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
809 &fpriv->vm);
810 if (ret) {
811 kfree(fpriv);
812 return ret;
813 }
814 }
815
816 file_priv->driver_priv = fpriv;
817 return 0;
818 }
819
820 /* here a client dies, release the stuff that was allocated for its
821 * file_priv */
822 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
823 {
824 nouveau_channel_cleanup(dev, file_priv);
825 }
826
827 void
828 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
829 {
830 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
831 nouveau_vm_ref(NULL, &fpriv->vm, NULL);
832 kfree(fpriv);
833 }
834
835 /* first module load, setup the mmio/fb mapping */
836 /* KMS: we need mmio at load time, not when the first drm client opens. */
837 int nouveau_firstopen(struct drm_device *dev)
838 {
839 return 0;
840 }
841
842 /* if we have an OF card, copy vbios to RAMIN */
843 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
844 {
845 #if defined(__powerpc__)
846 int size, i;
847 const uint32_t *bios;
848 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
849 if (!dn) {
850 NV_INFO(dev, "Unable to get the OF node\n");
851 return;
852 }
853
854 bios = of_get_property(dn, "NVDA,BMP", &size);
855 if (bios) {
856 for (i = 0; i < size; i += 4)
857 nv_wi32(dev, i, bios[i/4]);
858 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
859 } else {
860 NV_INFO(dev, "Unable to get the OF bios\n");
861 }
862 #endif
863 }
864
865 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
866 {
867 struct pci_dev *pdev = dev->pdev;
868 struct apertures_struct *aper = alloc_apertures(3);
869 if (!aper)
870 return NULL;
871
872 aper->ranges[0].base = pci_resource_start(pdev, 1);
873 aper->ranges[0].size = pci_resource_len(pdev, 1);
874 aper->count = 1;
875
876 if (pci_resource_len(pdev, 2)) {
877 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
878 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
879 aper->count++;
880 }
881
882 if (pci_resource_len(pdev, 3)) {
883 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
884 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
885 aper->count++;
886 }
887
888 return aper;
889 }
890
891 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
892 {
893 struct drm_nouveau_private *dev_priv = dev->dev_private;
894 bool primary = false;
895 dev_priv->apertures = nouveau_get_apertures(dev);
896 if (!dev_priv->apertures)
897 return -ENOMEM;
898
899 #ifdef CONFIG_X86
900 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
901 #endif
902
903 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
904 return 0;
905 }
906
907 int nouveau_load(struct drm_device *dev, unsigned long flags)
908 {
909 struct drm_nouveau_private *dev_priv;
910 uint32_t reg0;
911 resource_size_t mmio_start_offs;
912 int ret;
913
914 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
915 if (!dev_priv) {
916 ret = -ENOMEM;
917 goto err_out;
918 }
919 dev->dev_private = dev_priv;
920 dev_priv->dev = dev;
921
922 dev_priv->flags = flags & NOUVEAU_FLAGS;
923
924 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
925 dev->pci_vendor, dev->pci_device, dev->pdev->class);
926
927 /* resource 0 is mmio regs */
928 /* resource 1 is linear FB */
929 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
930 /* resource 6 is bios */
931
932 /* map the mmio regs */
933 mmio_start_offs = pci_resource_start(dev->pdev, 0);
934 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
935 if (!dev_priv->mmio) {
936 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
937 "Please report your setup to " DRIVER_EMAIL "\n");
938 ret = -EINVAL;
939 goto err_priv;
940 }
941 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
942 (unsigned long long)mmio_start_offs);
943
944 #ifdef __BIG_ENDIAN
945 /* Put the card in BE mode if it's not */
946 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
947 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
948
949 DRM_MEMORYBARRIER();
950 #endif
951
952 /* Time to determine the card architecture */
953 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
954 dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
955
956 /* We're dealing with >=NV10 */
957 if ((reg0 & 0x0f000000) > 0) {
958 /* Bit 27-20 contain the architecture in hex */
959 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
960 dev_priv->stepping = (reg0 & 0xff);
961 /* NV04 or NV05 */
962 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
963 if (reg0 & 0x00f00000)
964 dev_priv->chipset = 0x05;
965 else
966 dev_priv->chipset = 0x04;
967 } else
968 dev_priv->chipset = 0xff;
969
970 switch (dev_priv->chipset & 0xf0) {
971 case 0x00:
972 case 0x10:
973 case 0x20:
974 case 0x30:
975 dev_priv->card_type = dev_priv->chipset & 0xf0;
976 break;
977 case 0x40:
978 case 0x60:
979 dev_priv->card_type = NV_40;
980 break;
981 case 0x50:
982 case 0x80:
983 case 0x90:
984 case 0xa0:
985 dev_priv->card_type = NV_50;
986 break;
987 case 0xc0:
988 dev_priv->card_type = NV_C0;
989 break;
990 default:
991 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
992 ret = -EINVAL;
993 goto err_mmio;
994 }
995
996 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
997 dev_priv->card_type, reg0);
998
999 /* Determine whether we'll attempt acceleration or not, some
1000 * cards are disabled by default here due to them being known
1001 * non-functional, or never been tested due to lack of hw.
1002 */
1003 dev_priv->noaccel = !!nouveau_noaccel;
1004 if (nouveau_noaccel == -1) {
1005 switch (dev_priv->chipset) {
1006 case 0xc1: /* known broken */
1007 case 0xc8: /* never tested */
1008 NV_INFO(dev, "acceleration disabled by default, pass "
1009 "noaccel=0 to force enable\n");
1010 dev_priv->noaccel = true;
1011 break;
1012 default:
1013 dev_priv->noaccel = false;
1014 break;
1015 }
1016 }
1017
1018 ret = nouveau_remove_conflicting_drivers(dev);
1019 if (ret)
1020 goto err_mmio;
1021
1022 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1023 if (dev_priv->card_type >= NV_40) {
1024 int ramin_bar = 2;
1025 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1026 ramin_bar = 3;
1027
1028 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1029 dev_priv->ramin =
1030 ioremap(pci_resource_start(dev->pdev, ramin_bar),
1031 dev_priv->ramin_size);
1032 if (!dev_priv->ramin) {
1033 NV_ERROR(dev, "Failed to PRAMIN BAR");
1034 ret = -ENOMEM;
1035 goto err_mmio;
1036 }
1037 } else {
1038 dev_priv->ramin_size = 1 * 1024 * 1024;
1039 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1040 dev_priv->ramin_size);
1041 if (!dev_priv->ramin) {
1042 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1043 ret = -ENOMEM;
1044 goto err_mmio;
1045 }
1046 }
1047
1048 nouveau_OF_copy_vbios_to_ramin(dev);
1049
1050 /* Special flags */
1051 if (dev->pci_device == 0x01a0)
1052 dev_priv->flags |= NV_NFORCE;
1053 else if (dev->pci_device == 0x01f0)
1054 dev_priv->flags |= NV_NFORCE2;
1055
1056 /* For kernel modesetting, init card now and bring up fbcon */
1057 ret = nouveau_card_init(dev);
1058 if (ret)
1059 goto err_ramin;
1060
1061 return 0;
1062
1063 err_ramin:
1064 iounmap(dev_priv->ramin);
1065 err_mmio:
1066 iounmap(dev_priv->mmio);
1067 err_priv:
1068 kfree(dev_priv);
1069 dev->dev_private = NULL;
1070 err_out:
1071 return ret;
1072 }
1073
1074 void nouveau_lastclose(struct drm_device *dev)
1075 {
1076 vga_switcheroo_process_delayed_switch();
1077 }
1078
1079 int nouveau_unload(struct drm_device *dev)
1080 {
1081 struct drm_nouveau_private *dev_priv = dev->dev_private;
1082
1083 nouveau_card_takedown(dev);
1084
1085 iounmap(dev_priv->mmio);
1086 iounmap(dev_priv->ramin);
1087
1088 kfree(dev_priv);
1089 dev->dev_private = NULL;
1090 return 0;
1091 }
1092
1093 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv)
1095 {
1096 struct drm_nouveau_private *dev_priv = dev->dev_private;
1097 struct drm_nouveau_getparam *getparam = data;
1098
1099 switch (getparam->param) {
1100 case NOUVEAU_GETPARAM_CHIPSET_ID:
1101 getparam->value = dev_priv->chipset;
1102 break;
1103 case NOUVEAU_GETPARAM_PCI_VENDOR:
1104 getparam->value = dev->pci_vendor;
1105 break;
1106 case NOUVEAU_GETPARAM_PCI_DEVICE:
1107 getparam->value = dev->pci_device;
1108 break;
1109 case NOUVEAU_GETPARAM_BUS_TYPE:
1110 if (drm_pci_device_is_agp(dev))
1111 getparam->value = NV_AGP;
1112 else if (pci_is_pcie(dev->pdev))
1113 getparam->value = NV_PCIE;
1114 else
1115 getparam->value = NV_PCI;
1116 break;
1117 case NOUVEAU_GETPARAM_FB_SIZE:
1118 getparam->value = dev_priv->fb_available_size;
1119 break;
1120 case NOUVEAU_GETPARAM_AGP_SIZE:
1121 getparam->value = dev_priv->gart_info.aper_size;
1122 break;
1123 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1124 getparam->value = 0; /* deprecated */
1125 break;
1126 case NOUVEAU_GETPARAM_PTIMER_TIME:
1127 getparam->value = dev_priv->engine.timer.read(dev);
1128 break;
1129 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1130 getparam->value = 1;
1131 break;
1132 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1133 getparam->value = 1;
1134 break;
1135 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1136 /* NV40 and NV50 versions are quite different, but register
1137 * address is the same. User is supposed to know the card
1138 * family anyway... */
1139 if (dev_priv->chipset >= 0x40) {
1140 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1141 break;
1142 }
1143 /* FALLTHRU */
1144 default:
1145 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1146 return -EINVAL;
1147 }
1148
1149 return 0;
1150 }
1151
1152 int
1153 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1154 struct drm_file *file_priv)
1155 {
1156 struct drm_nouveau_setparam *setparam = data;
1157
1158 switch (setparam->param) {
1159 default:
1160 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1161 return -EINVAL;
1162 }
1163
1164 return 0;
1165 }
1166
1167 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1168 bool
1169 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1170 uint32_t reg, uint32_t mask, uint32_t val)
1171 {
1172 struct drm_nouveau_private *dev_priv = dev->dev_private;
1173 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1174 uint64_t start = ptimer->read(dev);
1175
1176 do {
1177 if ((nv_rd32(dev, reg) & mask) == val)
1178 return true;
1179 } while (ptimer->read(dev) - start < timeout);
1180
1181 return false;
1182 }
1183
1184 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1185 bool
1186 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1187 uint32_t reg, uint32_t mask, uint32_t val)
1188 {
1189 struct drm_nouveau_private *dev_priv = dev->dev_private;
1190 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1191 uint64_t start = ptimer->read(dev);
1192
1193 do {
1194 if ((nv_rd32(dev, reg) & mask) != val)
1195 return true;
1196 } while (ptimer->read(dev) - start < timeout);
1197
1198 return false;
1199 }
1200
1201 /* Waits for PGRAPH to go completely idle */
1202 bool nouveau_wait_for_idle(struct drm_device *dev)
1203 {
1204 struct drm_nouveau_private *dev_priv = dev->dev_private;
1205 uint32_t mask = ~0;
1206
1207 if (dev_priv->card_type == NV_40)
1208 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1209
1210 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1211 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1212 nv_rd32(dev, NV04_PGRAPH_STATUS));
1213 return false;
1214 }
1215
1216 return true;
1217 }
1218
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