x86/PCI: use host bridge _CRS info on ASUS M2V-MX SE
[linux-btrfs-devel.git] / drivers / staging / cxt1e1 / pmcc4_defs.h
bloba39505f45c29a10180713aba317b497477d728c5
1 /*
2 * $Id: pmcc4_defs.h,v 1.0 2005/09/28 00:10:09 rickd PMCC4_3_1B $
3 */
5 #ifndef _INC_PMCC4_DEFS_H_
6 #define _INC_PMCC4_DEFS_H_
8 /*-----------------------------------------------------------------------------
9 * c4_defs.h -
11 * Implementation elements of the wanPMC-C4T1E1 device driver
13 * Copyright (C) 2005 SBE, Inc.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * For further information, contact via email: support@sbei.com
26 * SBE, Inc. San Ramon, California U.S.A.
27 *-----------------------------------------------------------------------------
28 * RCS info:
29 * RCS revision: $Revision: 1.0 $
30 * Last changed on $Date: 2005/09/28 00:10:09 $
31 * Changed by $Author: rickd $
32 *-----------------------------------------------------------------------------
33 * $Log: pmcc4_defs.h,v $
34 * Revision 1.0 2005/09/28 00:10:09 rickd
35 * Initial revision
37 *-----------------------------------------------------------------------------
41 #define MAX_BOARDS 8
42 #define MAX_CHANS_USED 128
44 #ifdef SBE_PMCC4_ENABLE
45 #define MUSYCC_NPORTS 4 /* CN8474 */
46 #endif
47 #ifdef SBE_WAN256T3_ENABLE
48 #define MUSYCC_NPORTS 8 /* CN8478 */
49 #endif
50 #define MUSYCC_NCHANS 32 /* actually, chans per port */
52 #define MUSYCC_NIQD 0x1000 /* power of 2 */
53 #define MUSYCC_MRU 2048 /* default */
54 #define MUSYCC_MTU 2048 /* default */
55 #define MUSYCC_TXDESC_MIN 10 /* HDLC mode default */
56 #define MUSYCC_RXDESC_MIN 18 /* HDLC mode default */
57 #define MUSYCC_TXDESC_TRANS 4 /* Transparent mode minimum # of TX descriptors */
58 #define MUSYCC_RXDESC_TRANS 12 /* Transparent mode minimum # of RX descriptors */
60 #define MAX_DEFAULT_IFQLEN 32 /* network qlen */
63 #define SBE_IFACETMPL "pmcc4-%d"
64 #ifdef IFNAMSIZ
65 #define SBE_IFACETMPL_SIZE IFNAMSIZ
66 #else
67 #define SBE_IFACETMPL_SIZE 16
68 #endif
70 /* we want the PMCC4 watchdog to fire off every 250ms */
71 #define WATCHDOG_TIMEOUT 250000
73 /* if we restart the watchdog every 250ms, then we'll time out
74 * an additional 300ms later */
75 #define WATCHDOG_UTIMEOUT (WATCHDOG_TIMEOUT+300000)
77 #if !defined(SBE_ISR_TASKLET) && !defined(SBE_ISR_IMMEDIATE) && !defined(SBE_ISR_INLINE)
78 #define SBE_ISR_TASKLET
79 #endif
81 #endif /*** _INC_PMCC4_DEFS_H_ ***/