drivers/staging/gma500/cdv_device.c

   1 /**************************************************************************
   2  * Copyright (c) 2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #include <linux/backlight.h>
  21 #include <drm/drmP.h>
  22 #include <drm/drm.h>
  23 #include "psb_drm.h"
  24 #include "psb_drv.h"
  25 #include "psb_reg.h"
  26 #include "psb_intel_reg.h"
  27 #include "intel_bios.h"
  28 #include "cdv_device.h"
  29
  30 #define VGA_SR_INDEX            0x3c4
  31 #define VGA_SR_DATA             0x3c5
  32
  33 /* FIXME: should check if we are the active VGA device ?? */
  34 static void cdv_disable_vga(struct drm_device *dev)
  35 {
  36         u8 sr1;
  37         u32 vga_reg;
  38
  39         vga_reg = VGACNTRL;
  40
  41         outb(1, VGA_SR_INDEX);
  42         sr1 = inb(VGA_SR_DATA);
  43         outb(sr1 | 1<<5, VGA_SR_DATA);
  44         udelay(300);
  45
  46         REG_WRITE(vga_reg, VGA_DISP_DISABLE);
  47         REG_READ(vga_reg);
  48 }
  49
  50 static int cdv_output_init(struct drm_device *dev)
  51 {
  52         struct drm_psb_private *dev_priv = dev->dev_private;
  53         cdv_disable_vga(dev);
  54
  55         cdv_intel_crt_init(dev, &dev_priv->mode_dev);
  56         cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
  57
  58         /* These bits indicate HDMI not SDVO on CDV, but we don't yet support
  59            the HDMI interface */
  60         if (REG_READ(SDVOB) & SDVO_DETECTED)
  61                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
  62         if (REG_READ(SDVOC) & SDVO_DETECTED)
  63                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
  64         return 0;
  65 }
  66
  67 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  68
  69 /*
  70  *      Poulsbo Backlight Interfaces
  71  */
  72
  73 #define BLC_PWM_PRECISION_FACTOR 100    /* 10000000 */
  74 #define BLC_PWM_FREQ_CALC_CONSTANT 32
  75 #define MHz 1000000
  76
  77 #define PSB_BLC_PWM_PRECISION_FACTOR    10
  78 #define PSB_BLC_MAX_PWM_REG_FREQ        0xFFFE
  79 #define PSB_BLC_MIN_PWM_REG_FREQ        0x2
  80
  81 #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
  82 #define PSB_BACKLIGHT_PWM_CTL_SHIFT     (16)
  83
  84 static int cdv_brightness;
  85 static struct backlight_device *cdv_backlight_device;
  86
  87 static int cdv_get_brightness(struct backlight_device *bd)
  88 {
  89         /* return locally cached var instead of HW read (due to DPST etc.) */
  90         /* FIXME: ideally return actual value in case firmware fiddled with
  91            it */
  92         return cdv_brightness;
  93 }
  94
  95
  96 static int cdv_backlight_setup(struct drm_device *dev)
  97 {
  98         struct drm_psb_private *dev_priv = dev->dev_private;
  99         unsigned long core_clock;
 100         /* u32 bl_max_freq; */
 101         /* unsigned long value; */
 102         u16 bl_max_freq;
 103         uint32_t value;
 104         uint32_t blc_pwm_precision_factor;
 105
 106         /* get bl_max_freq and pol from dev_priv*/
 107         if (!dev_priv->lvds_bl) {
 108                 dev_err(dev->dev, "Has no valid LVDS backlight info\n");
 109                 return -ENOENT;
 110         }
 111         bl_max_freq = dev_priv->lvds_bl->freq;
 112         blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
 113
 114         core_clock = dev_priv->core_freq;
 115
 116         value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
 117         value *= blc_pwm_precision_factor;
 118         value /= bl_max_freq;
 119         value /= blc_pwm_precision_factor;
 120
 121         if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
 122                  value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
 123                                 return -ERANGE;
 124         else {
 125                 /* FIXME */
 126         }
 127         return 0;
 128 }
 129
 130 static int cdv_set_brightness(struct backlight_device *bd)
 131 {
 132         int level = bd->props.brightness;
 133
 134         /* Percentage 1-100% being valid */
 135         if (level < 1)
 136                 level = 1;
 137
 138         /*cdv_intel_lvds_set_brightness(dev, level); FIXME */
 139         cdv_brightness = level;
 140         return 0;
 141 }
 142
 143 static const struct backlight_ops cdv_ops = {
 144         .get_brightness = cdv_get_brightness,
 145         .update_status  = cdv_set_brightness,
 146 };
 147
 148 static int cdv_backlight_init(struct drm_device *dev)
 149 {
 150         struct drm_psb_private *dev_priv = dev->dev_private;
 151         int ret;
 152         struct backlight_properties props;
 153
 154         memset(&props, 0, sizeof(struct backlight_properties));
 155         props.max_brightness = 100;
 156         props.type = BACKLIGHT_PLATFORM;
 157
 158         cdv_backlight_device = backlight_device_register("psb-bl",
 159                                         NULL, (void *)dev, &cdv_ops, &props);
 160         if (IS_ERR(cdv_backlight_device))
 161                 return PTR_ERR(cdv_backlight_device);
 162
 163         ret = cdv_backlight_setup(dev);
 164         if (ret < 0) {
 165                 backlight_device_unregister(cdv_backlight_device);
 166                 cdv_backlight_device = NULL;
 167                 return ret;
 168         }
 169         cdv_backlight_device->props.brightness = 100;
 170         cdv_backlight_device->props.max_brightness = 100;
 171         backlight_update_status(cdv_backlight_device);
 172         dev_priv->backlight_device = cdv_backlight_device;
 173         return 0;
 174 }
 175
 176 #endif
 177
 178 /*
 179  *      Provide the Cedarview specific chip logic and low level methods
 180  *      for power management
 181  *
 182  *      FIXME: we need to implement the apm/ospm base management bits
 183  *      for this and the MID devices.
 184  */
 185
 186 static inline u32 CDV_MSG_READ32(uint port, uint offset)
 187 {
 188         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 189         uint32_t ret_val = 0;
 190         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 191         pci_write_config_dword(pci_root, 0xD0, mcr);
 192         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 193         pci_dev_put(pci_root);
 194         return ret_val;
 195 }
 196
 197 static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
 198 {
 199         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 200         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 201         pci_write_config_dword(pci_root, 0xD4, value);
 202         pci_write_config_dword(pci_root, 0xD0, mcr);
 203         pci_dev_put(pci_root);
 204 }
 205
 206 #define PSB_APM_CMD                     0x0
 207 #define PSB_APM_STS                     0x04
 208 #define PSB_PM_SSC                      0x20
 209 #define PSB_PM_SSS                      0x30
 210 #define PSB_PWRGT_GFX_MASK              0x3
 211 #define CDV_PWRGT_DISPLAY_CNTR          0x000fc00c
 212 #define CDV_PWRGT_DISPLAY_STS           0x000fc00c
 213
 214 static void cdv_init_pm(struct drm_device *dev)
 215 {
 216         struct drm_psb_private *dev_priv = dev->dev_private;
 217         u32 pwr_cnt;
 218         int i;
 219
 220         dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
 221                                                         PSB_APMBA) & 0xFFFF;
 222         dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
 223                                                         PSB_OSPMBA) & 0xFFFF;
 224
 225         /* Force power on for now */
 226         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 227         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 228
 229         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 230         for (i = 0; i < 5; i++) {
 231                 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 232                 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
 233                         break;
 234                 udelay(10);
 235         }
 236         pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
 237         pwr_cnt &= ~CDV_PWRGT_DISPLAY_CNTR;
 238         outl(pwr_cnt, dev_priv->ospm_base + PSB_PM_SSC);
 239         for (i = 0; i < 5; i++) {
 240                 u32 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
 241                 if ((pwr_sts & CDV_PWRGT_DISPLAY_STS) == 0)
 242                         break;
 243                 udelay(10);
 244         }
 245 }
 246
 247 /**
 248  *      cdv_save_display_registers      -       save registers lost on suspend
 249  *      @dev: our DRM device
 250  *
 251  *      Save the state we need in order to be able to restore the interface
 252  *      upon resume from suspend
 253  *
 254  *      FIXME: review
 255  */
 256 static int cdv_save_display_registers(struct drm_device *dev)
 257 {
 258         return 0;
 259 }
 260
 261 /**
 262  *      cdv_restore_display_registers   -       restore lost register state
 263  *      @dev: our DRM device
 264  *
 265  *      Restore register state that was lost during suspend and resume.
 266  *
 267  *      FIXME: review
 268  */
 269 static int cdv_restore_display_registers(struct drm_device *dev)
 270 {
 271         return 0;
 272 }
 273
 274 static int cdv_power_down(struct drm_device *dev)
 275 {
 276         return 0;
 277 }
 278
 279 static int cdv_power_up(struct drm_device *dev)
 280 {
 281         return 0;
 282 }
 283
 284 /* FIXME ? - shared with Poulsbo */
 285 static void cdv_get_core_freq(struct drm_device *dev)
 286 {
 287         uint32_t clock;
 288         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 289         struct drm_psb_private *dev_priv = dev->dev_private;
 290
 291         pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
 292         pci_read_config_dword(pci_root, 0xD4, &clock);
 293         pci_dev_put(pci_root);
 294
 295         switch (clock & 0x07) {
 296         case 0:
 297                 dev_priv->core_freq = 100;
 298                 break;
 299         case 1:
 300                 dev_priv->core_freq = 133;
 301                 break;
 302         case 2:
 303                 dev_priv->core_freq = 150;
 304                 break;
 305         case 3:
 306                 dev_priv->core_freq = 178;
 307                 break;
 308         case 4:
 309                 dev_priv->core_freq = 200;
 310                 break;
 311         case 5:
 312         case 6:
 313         case 7:
 314                 dev_priv->core_freq = 266;
 315         default:
 316                 dev_priv->core_freq = 0;
 317         }
 318 }
 319
 320 static int cdv_chip_setup(struct drm_device *dev)
 321 {
 322         cdv_get_core_freq(dev);
 323         gma_intel_opregion_init(dev);
 324         psb_intel_init_bios(dev);
 325         return 0;
 326 }
 327
 328 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
 329
 330 const struct psb_ops cdv_chip_ops = {
 331         .name = "Cedartrail",
 332         .accel_2d = 0,
 333         .pipes = 2,
 334         .sgx_offset = MRST_SGX_OFFSET,
 335         .chip_setup = cdv_chip_setup,
 336
 337         .crtc_helper = &cdv_intel_helper_funcs,
 338         .crtc_funcs = &cdv_intel_crtc_funcs,
 339
 340         .output_init = cdv_output_init,
 341
 342 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 343         .backlight_init = cdv_backlight_init,
 344 #endif
 345
 346         .init_pm = cdv_init_pm,
 347         .save_regs = cdv_save_display_registers,
 348         .restore_regs = cdv_restore_display_registers,
 349         .power_down = cdv_power_down,
 350         .power_up = cdv_power_up,
 351 };