drivers/staging/gma500/psb_irq.c

   1 /**************************************************************************
   2  * Copyright (c) 2007, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
  19  * develop this driver.
  20  *
  21  **************************************************************************/
  22 /*
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "psb_drv.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "power.h"
  30 #include "mdfld_output.h"
  31
  32 /*
  33  * inline functions
  34  */
  35
  36 static inline u32
  37 psb_pipestat(int pipe)
  38 {
  39         if (pipe == 0)
  40                 return PIPEASTAT;
  41         if (pipe == 1)
  42                 return PIPEBSTAT;
  43         if (pipe == 2)
  44                 return PIPECSTAT;
  45         BUG();
  46 }
  47
  48 static inline u32
  49 mid_pipe_event(int pipe)
  50 {
  51         if (pipe == 0)
  52                 return _PSB_PIPEA_EVENT_FLAG;
  53         if (pipe == 1)
  54                 return _MDFLD_PIPEB_EVENT_FLAG;
  55         if (pipe == 2)
  56                 return _MDFLD_PIPEC_EVENT_FLAG;
  57         BUG();
  58 }
  59
  60 static inline u32
  61 mid_pipe_vsync(int pipe)
  62 {
  63         if (pipe == 0)
  64                 return _PSB_VSYNC_PIPEA_FLAG;
  65         if (pipe == 1)
  66                 return _PSB_VSYNC_PIPEB_FLAG;
  67         if (pipe == 2)
  68                 return _MDFLD_PIPEC_VBLANK_FLAG;
  69         BUG();
  70 }
  71
  72 static inline u32
  73 mid_pipeconf(int pipe)
  74 {
  75         if (pipe == 0)
  76                 return PIPEACONF;
  77         if (pipe == 1)
  78                 return PIPEBCONF;
  79         if (pipe == 2)
  80                 return PIPECCONF;
  81         BUG();
  82 }
  83
  84 void
  85 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  86 {
  87         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  88                 u32 reg = psb_pipestat(pipe);
  89                 dev_priv->pipestat[pipe] |= mask;
  90                 /* Enable the interrupt, clear any pending status */
  91                 if (gma_power_begin(dev_priv->dev, false)) {
  92                         u32 writeVal = PSB_RVDC32(reg);
  93                         writeVal |= (mask | (mask >> 16));
  94                         PSB_WVDC32(writeVal, reg);
  95                         (void) PSB_RVDC32(reg);
  96                         gma_power_end(dev_priv->dev);
  97                 }
  98         }
  99 }
 100
 101 void
 102 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = psb_pipestat(pipe);
 106                 dev_priv->pipestat[pipe] &= ~mask;
 107                 if (gma_power_begin(dev_priv->dev, false)) {
 108                         u32 writeVal = PSB_RVDC32(reg);
 109                         writeVal &= ~mask;
 110                         PSB_WVDC32(writeVal, reg);
 111                         (void) PSB_RVDC32(reg);
 112                         gma_power_end(dev_priv->dev);
 113                 }
 114         }
 115 }
 116
 117 void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 118 {
 119         if (gma_power_begin(dev_priv->dev, false)) {
 120                 u32 pipe_event = mid_pipe_event(pipe);
 121                 dev_priv->vdc_irq_mask |= pipe_event;
 122                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 123                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 124                 gma_power_end(dev_priv->dev);
 125         }
 126 }
 127
 128 void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 129 {
 130         if (dev_priv->pipestat[pipe] == 0) {
 131                 if (gma_power_begin(dev_priv->dev, false)) {
 132                         u32 pipe_event = mid_pipe_event(pipe);
 133                         dev_priv->vdc_irq_mask &= ~pipe_event;
 134                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 135                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 136                         gma_power_end(dev_priv->dev);
 137                 }
 138         }
 139 }
 140
 141 /**
 142  * Display controller interrupt handler for vsync/vblank.
 143  *
 144  */
 145 static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe)
 146 {
 147         drm_handle_vblank(dev, pipe);
 148 }
 149
 150
 151 /**
 152  * Display controller interrupt handler for pipe event.
 153  *
 154  */
 155 #define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
 156 static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
 157 {
 158         struct drm_psb_private *dev_priv =
 159             (struct drm_psb_private *) dev->dev_private;
 160
 161         uint32_t pipe_stat_val = 0;
 162         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 163         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 164         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 165         uint32_t i = 0;
 166
 167         spin_lock(&dev_priv->irqmask_lock);
 168
 169         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 170         pipe_stat_val &= pipe_enable | pipe_status;
 171         pipe_stat_val &= pipe_stat_val >> 16;
 172
 173         spin_unlock(&dev_priv->irqmask_lock);
 174
 175         /* clear the 2nd level interrupt status bits */
 176         /**
 177         * FIXME: shouldn't use while loop here. However, the interrupt
 178         * status 'sticky' bits cannot be cleared by setting '1' to that
 179         * bit once...
 180         */
 181         for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) {
 182                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 183                 (void) PSB_RVDC32(pipe_stat_reg);
 184
 185                 if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0)
 186                         break;
 187         }
 188
 189         if (i == WAIT_STATUS_CLEAR_LOOP_COUNT)
 190                 dev_err(dev->dev,
 191         "%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
 192                         __func__, PSB_RVDC32(pipe_stat_reg));
 193
 194         if (pipe_stat_val & PIPE_VBLANK_STATUS)
 195                 mid_vblank_handler(dev, pipe);
 196
 197         if (pipe_stat_val & PIPE_TE_STATUS)
 198                 drm_handle_vblank(dev, pipe);
 199 }
 200
 201 /*
 202  * Display controller interrupt handler.
 203  */
 204 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 205 {
 206         if (vdc_stat & _PSB_PIPEA_EVENT_FLAG)
 207                 mid_pipe_event_handler(dev, 0);
 208 }
 209
 210 irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
 211 {
 212         struct drm_device *dev = (struct drm_device *) arg;
 213         struct drm_psb_private *dev_priv =
 214             (struct drm_psb_private *) dev->dev_private;
 215
 216         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
 217         int handled = 0;
 218
 219         spin_lock(&dev_priv->irqmask_lock);
 220
 221         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 222
 223         if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
 224                 dsp_int = 1;
 225
 226         if (vdc_stat & _PSB_IRQ_SGX_FLAG)
 227                 sgx_int = 1;
 228
 229         vdc_stat &= dev_priv->vdc_irq_mask;
 230         spin_unlock(&dev_priv->irqmask_lock);
 231
 232         if (dsp_int && gma_power_is_on(dev)) {
 233                 psb_vdc_interrupt(dev, vdc_stat);
 234                 handled = 1;
 235         }
 236
 237         if (sgx_int) {
 238                 /* Not expected - we have it masked, shut it up */
 239                 u32 s, s2;
 240                 s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 241                 s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 242                 PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
 243                 PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
 244                 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
 245                    we may as well poll even if we add that ! */
 246                 handled = 1;
 247         }
 248
 249         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 250         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 251         DRM_READMEMORYBARRIER();
 252
 253         if (!handled)
 254                 return IRQ_NONE;
 255
 256         return IRQ_HANDLED;
 257 }
 258
 259 void psb_irq_preinstall(struct drm_device *dev)
 260 {
 261         struct drm_psb_private *dev_priv =
 262             (struct drm_psb_private *) dev->dev_private;
 263         unsigned long irqflags;
 264
 265         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 266
 267         if (gma_power_is_on(dev))
 268                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 269         if (dev->vblank_enabled[0])
 270                 dev_priv->vdc_irq_mask |= _PSB_PIPEA_EVENT_FLAG;
 271         if (dev->vblank_enabled[1])
 272                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
 273         if (dev->vblank_enabled[2])
 274                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
 275
 276         /*This register is safe even if display island is off*/
 277         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 278         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 279 }
 280
 281 int psb_irq_postinstall(struct drm_device *dev)
 282 {
 283         struct drm_psb_private *dev_priv =
 284             (struct drm_psb_private *) dev->dev_private;
 285         unsigned long irqflags;
 286
 287         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 288
 289         /* This register is safe even if display island is off */
 290         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 291         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 292
 293         if (dev->vblank_enabled[0])
 294                 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 295         else
 296                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 297
 298         if (dev->vblank_enabled[1])
 299                 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 300         else
 301                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 302
 303         if (dev->vblank_enabled[2])
 304                 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 305         else
 306                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 307
 308         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 309         return 0;
 310 }
 311
 312 void psb_irq_uninstall(struct drm_device *dev)
 313 {
 314         struct drm_psb_private *dev_priv =
 315             (struct drm_psb_private *) dev->dev_private;
 316         unsigned long irqflags;
 317
 318         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 319
 320         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 321
 322         if (dev->vblank_enabled[0])
 323                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 324
 325         if (dev->vblank_enabled[1])
 326                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 327
 328         if (dev->vblank_enabled[2])
 329                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 330
 331         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 332                                   _PSB_IRQ_MSVDX_FLAG |
 333                                   _LNC_IRQ_TOPAZ_FLAG;
 334
 335         /* These two registers are safe even if display island is off */
 336         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 337         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 338
 339         wmb();
 340
 341         /* This register is safe even if display island is off */
 342         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 343         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 344 }
 345
 346 void psb_irq_turn_on_dpst(struct drm_device *dev)
 347 {
 348         struct drm_psb_private *dev_priv =
 349                 (struct drm_psb_private *) dev->dev_private;
 350         u32 hist_reg;
 351         u32 pwm_reg;
 352
 353         if (gma_power_begin(dev, false)) {
 354                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 355                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 356                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 357                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 358
 359                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 360                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 361                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 362                                                 | PWM_PHASEIN_INT_ENABLE,
 363                                                            PWM_CONTROL_LOGIC);
 364                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 365
 366                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 367
 368                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 369                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 370                                                         HISTOGRAM_INT_CONTROL);
 371                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 372                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 373                                                         PWM_CONTROL_LOGIC);
 374
 375                 gma_power_end(dev);
 376         }
 377 }
 378
 379 int psb_irq_enable_dpst(struct drm_device *dev)
 380 {
 381         struct drm_psb_private *dev_priv =
 382                 (struct drm_psb_private *) dev->dev_private;
 383         unsigned long irqflags;
 384
 385         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 386
 387         /* enable DPST */
 388         mid_enable_pipe_event(dev_priv, 0);
 389         psb_irq_turn_on_dpst(dev);
 390
 391         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 392         return 0;
 393 }
 394
 395 void psb_irq_turn_off_dpst(struct drm_device *dev)
 396 {
 397         struct drm_psb_private *dev_priv =
 398             (struct drm_psb_private *) dev->dev_private;
 399         u32 hist_reg;
 400         u32 pwm_reg;
 401
 402         if (gma_power_begin(dev, false)) {
 403                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 404                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 405
 406                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 407
 408                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 409                 PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
 410                                                         PWM_CONTROL_LOGIC);
 411                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 412
 413                 gma_power_end(dev);
 414         }
 415 }
 416
 417 int psb_irq_disable_dpst(struct drm_device *dev)
 418 {
 419         struct drm_psb_private *dev_priv =
 420             (struct drm_psb_private *) dev->dev_private;
 421         unsigned long irqflags;
 422
 423         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 424
 425         mid_disable_pipe_event(dev_priv, 0);
 426         psb_irq_turn_off_dpst(dev);
 427
 428         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 429
 430         return 0;
 431 }
 432
 433 #ifdef PSB_FIXME
 434 static int psb_vblank_do_wait(struct drm_device *dev,
 435                               unsigned int *sequence, atomic_t *counter)
 436 {
 437         unsigned int cur_vblank;
 438         int ret = 0;
 439         DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
 440                     (((cur_vblank = atomic_read(counter))
 441                       - *sequence) <= (1 << 23)));
 442         *sequence = cur_vblank;
 443
 444         return ret;
 445 }
 446 #endif
 447
 448 /*
 449  * It is used to enable VBLANK interrupt
 450  */
 451 int psb_enable_vblank(struct drm_device *dev, int pipe)
 452 {
 453         struct drm_psb_private *dev_priv = dev->dev_private;
 454         unsigned long irqflags;
 455         uint32_t reg_val = 0;
 456         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 457
 458 #if defined(CONFIG_DRM_PSB_MFLD)
 459         /* Medfield is different - we should perhaps extract out vblank
 460            and blacklight etc ops */
 461         if (IS_MFLD(dev) && !mdfld_panel_dpi(dev))
 462                 return mdfld_enable_te(dev, pipe);
 463 #endif
 464         if (gma_power_begin(dev, false)) {
 465                 reg_val = REG_READ(pipeconf_reg);
 466                 gma_power_end(dev);
 467         }
 468
 469         if (!(reg_val & PIPEACONF_ENABLE))
 470                 return -EINVAL;
 471
 472         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 473
 474         mid_enable_pipe_event(dev_priv, pipe);
 475         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 476
 477         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 478
 479         return 0;
 480 }
 481
 482 /*
 483  * It is used to disable VBLANK interrupt
 484  */
 485 void psb_disable_vblank(struct drm_device *dev, int pipe)
 486 {
 487         struct drm_psb_private *dev_priv = dev->dev_private;
 488         unsigned long irqflags;
 489
 490 #if defined(CONFIG_DRM_PSB_MFLD)
 491         if (IS_MFLD(dev) && !mdfld_panel_dpi(dev))
 492                 mdfld_disable_te(dev, pipe);
 493 #endif
 494         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 495
 496         mid_disable_pipe_event(dev_priv, pipe);
 497         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 498
 499         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 500 }
 501
 502 /**
 503  *      mdfld_enable_te         -       enable TE events
 504  *      @dev: our DRM device
 505  *      @pipe: which pipe to work on
 506  *
 507  *      Enable TE events on a Medfield display pipe. Medfield specific.
 508  */
 509 int mdfld_enable_te(struct drm_device *dev, int pipe)
 510 {
 511         struct drm_psb_private *dev_priv = dev->dev_private;
 512         unsigned long flags;
 513         uint32_t reg_val = 0;
 514         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 515
 516         if (gma_power_begin(dev, false)) {
 517                 reg_val = REG_READ(pipeconf_reg);
 518                 gma_power_end(dev);
 519         }
 520
 521         if (!(reg_val & PIPEACONF_ENABLE))
 522                 return -EINVAL;
 523
 524         spin_lock_irqsave(&dev_priv->irqmask_lock, flags);
 525
 526         mid_enable_pipe_event(dev_priv, pipe);
 527         psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 528
 529         spin_unlock_irqrestore(&dev_priv->irqmask_lock, flags);
 530
 531         return 0;
 532 }
 533
 534 /**
 535  *      mdfld_disable_te                -       disable TE events
 536  *      @dev: our DRM device
 537  *      @pipe: which pipe to work on
 538  *
 539  *      Disable TE events on a Medfield display pipe. Medfield specific.
 540  */
 541 void mdfld_disable_te(struct drm_device *dev, int pipe)
 542 {
 543         struct drm_psb_private *dev_priv = dev->dev_private;
 544         unsigned long flags;
 545
 546         spin_lock_irqsave(&dev_priv->irqmask_lock, flags);
 547
 548         mid_disable_pipe_event(dev_priv, pipe);
 549         psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 550
 551         spin_unlock_irqrestore(&dev_priv->irqmask_lock, flags);
 552 }
 553
 554 /* Called from drm generic code, passed a 'crtc', which
 555  * we use as a pipe index
 556  */
 557 u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
 558 {
 559         uint32_t high_frame = PIPEAFRAMEHIGH;
 560         uint32_t low_frame = PIPEAFRAMEPIXEL;
 561         uint32_t pipeconf_reg = PIPEACONF;
 562         uint32_t reg_val = 0;
 563         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 564
 565         switch (pipe) {
 566         case 0:
 567                 break;
 568         case 1:
 569                 high_frame = PIPEBFRAMEHIGH;
 570                 low_frame = PIPEBFRAMEPIXEL;
 571                 pipeconf_reg = PIPEBCONF;
 572                 break;
 573         case 2:
 574                 high_frame = PIPECFRAMEHIGH;
 575                 low_frame = PIPECFRAMEPIXEL;
 576                 pipeconf_reg = PIPECCONF;
 577                 break;
 578         default:
 579                 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
 580                 return 0;
 581         }
 582
 583         if (!gma_power_begin(dev, false))
 584                 return 0;
 585
 586         reg_val = REG_READ(pipeconf_reg);
 587
 588         if (!(reg_val & PIPEACONF_ENABLE)) {
 589                 dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
 590                                                                 pipe);
 591                 goto psb_get_vblank_counter_exit;
 592         }
 593
 594         /*
 595          * High & low register fields aren't synchronized, so make sure
 596          * we get a low value that's stable across two reads of the high
 597          * register.
 598          */
 599         do {
 600                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 601                          PIPE_FRAME_HIGH_SHIFT);
 602                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 603                         PIPE_FRAME_LOW_SHIFT);
 604                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 605                          PIPE_FRAME_HIGH_SHIFT);
 606         } while (high1 != high2);
 607
 608         count = (high1 << 8) | low;
 609
 610 psb_get_vblank_counter_exit:
 611
 612         gma_power_end(dev);
 613
 614         return count;
 615 }
 616