1 #ifndef _R819XU_PHYREG_H
2 #define _R819XU_PHYREG_H
5 #define RF_DATA 0x1d4 // FW will write RF data in the register.
7 //Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
9 #define rPMAC_Reset 0x100
10 #define rPMAC_TxStart 0x104
11 #define rPMAC_TxLegacySIG 0x108
12 #define rPMAC_TxHTSIG1 0x10c
13 #define rPMAC_TxHTSIG2 0x110
14 #define rPMAC_PHYDebug 0x114
15 #define rPMAC_TxPacketNum 0x118
16 #define rPMAC_TxIdle 0x11c
17 #define rPMAC_TxMACHeader0 0x120
18 #define rPMAC_TxMACHeader1 0x124
19 #define rPMAC_TxMACHeader2 0x128
20 #define rPMAC_TxMACHeader3 0x12c
21 #define rPMAC_TxMACHeader4 0x130
22 #define rPMAC_TxMACHeader5 0x134
23 #define rPMAC_TxDataType 0x138
24 #define rPMAC_TxRandomSeed 0x13c
25 #define rPMAC_CCKPLCPPreamble 0x140
26 #define rPMAC_CCKPLCPHeader 0x144
27 #define rPMAC_CCKCRC16 0x148
28 #define rPMAC_OFDMRxCRC32OK 0x170
29 #define rPMAC_OFDMRxCRC32Er 0x174
30 #define rPMAC_OFDMRxParityEr 0x178
31 #define rPMAC_OFDMRxCRC8Er 0x17c
32 #define rPMAC_CCKCRxRC16Er 0x180
33 #define rPMAC_CCKCRxRC32Er 0x184
34 #define rPMAC_CCKCRxRC32OK 0x188
35 #define rPMAC_TxStatus 0x18c
38 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC
39 #define rFPGA0_TxInfo 0x804
40 #define rFPGA0_PSDFunction 0x808
41 #define rFPGA0_TxGainStage 0x80c
42 #define rFPGA0_RFTiming1 0x810
43 #define rFPGA0_RFTiming2 0x814
44 //#define rFPGA0_XC_RFTiming 0x818
45 //#define rFPGA0_XD_RFTiming 0x81c
46 #define rFPGA0_XA_HSSIParameter1 0x820
47 #define rFPGA0_XA_HSSIParameter2 0x824
48 #define rFPGA0_XB_HSSIParameter1 0x828
49 #define rFPGA0_XB_HSSIParameter2 0x82c
50 #define rFPGA0_XC_HSSIParameter1 0x830
51 #define rFPGA0_XC_HSSIParameter2 0x834
52 #define rFPGA0_XD_HSSIParameter1 0x838
53 #define rFPGA0_XD_HSSIParameter2 0x83c
54 #define rFPGA0_XA_LSSIParameter 0x840
55 #define rFPGA0_XB_LSSIParameter 0x844
56 #define rFPGA0_XC_LSSIParameter 0x848
57 #define rFPGA0_XD_LSSIParameter 0x84c
58 #define rFPGA0_RFWakeUpParameter 0x850
59 #define rFPGA0_RFSleepUpParameter 0x854
60 #define rFPGA0_XAB_SwitchControl 0x858
61 #define rFPGA0_XCD_SwitchControl 0x85c
62 #define rFPGA0_XA_RFInterfaceOE 0x860
63 #define rFPGA0_XB_RFInterfaceOE 0x864
64 #define rFPGA0_XC_RFInterfaceOE 0x868
65 #define rFPGA0_XD_RFInterfaceOE 0x86c
66 #define rFPGA0_XAB_RFInterfaceSW 0x870
67 #define rFPGA0_XCD_RFInterfaceSW 0x874
68 #define rFPGA0_XAB_RFParameter 0x878
69 #define rFPGA0_XCD_RFParameter 0x87c
70 #define rFPGA0_AnalogParameter1 0x880
71 #define rFPGA0_AnalogParameter2 0x884
72 #define rFPGA0_AnalogParameter3 0x888
73 #define rFPGA0_AnalogParameter4 0x88c
74 #define rFPGA0_XA_LSSIReadBack 0x8a0
75 #define rFPGA0_XB_LSSIReadBack 0x8a4
76 #define rFPGA0_XC_LSSIReadBack 0x8a8
77 #define rFPGA0_XD_LSSIReadBack 0x8ac
78 #define rFPGA0_PSDReport 0x8b4
79 #define rFPGA0_XAB_RFInterfaceRB 0x8e0
80 #define rFPGA0_XCD_RFInterfaceRB 0x8e4
83 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC
84 #define rFPGA1_TxBlock 0x904
85 #define rFPGA1_DebugSelect 0x908
86 #define rFPGA1_TxInfo 0x90c
89 #define rCCK0_System 0xa00
90 #define rCCK0_AFESetting 0xa04
91 #define rCCK0_CCA 0xa08
92 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level
93 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC
94 #define rCCK0_RxHP 0xa14
95 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
96 #define rCCK0_DSPParameter2 0xa1c //SQ threshold
97 #define rCCK0_TxFilter1 0xa20
98 #define rCCK0_TxFilter2 0xa24
99 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
100 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d
101 #define rCCK0_TRSSIReport 0xa50
102 #define rCCK0_RxReport 0xa54 //0xa57
103 #define rCCK0_FACounterLower 0xa5c //0xa5b
104 #define rCCK0_FACounterUpper 0xa58 //0xa5c
107 #define rOFDM0_LSTF 0xc00
108 #define rOFDM0_TRxPathEnable 0xc04
109 #define rOFDM0_TRMuxPar 0xc08
110 #define rOFDM0_TRSWIsolation 0xc0c
111 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
112 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
113 #define rOFDM0_XBRxAFE 0xc18
114 #define rOFDM0_XBRxIQImbalance 0xc1c
115 #define rOFDM0_XCRxAFE 0xc20
116 #define rOFDM0_XCRxIQImbalance 0xc24
117 #define rOFDM0_XDRxAFE 0xc28
118 #define rOFDM0_XDRxIQImbalance 0xc2c
119 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD
120 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
121 #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
122 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
123 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
124 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
125 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
126 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
127 #define rOFDM0_XAAGCCore1 0xc50
128 #define rOFDM0_XAAGCCore2 0xc54
129 #define rOFDM0_XBAGCCore1 0xc58
130 #define rOFDM0_XBAGCCore2 0xc5c
131 #define rOFDM0_XCAGCCore1 0xc60
132 #define rOFDM0_XCAGCCore2 0xc64
133 #define rOFDM0_XDAGCCore1 0xc68
134 #define rOFDM0_XDAGCCore2 0xc6c
135 #define rOFDM0_AGCParameter1 0xc70
136 #define rOFDM0_AGCParameter2 0xc74
137 #define rOFDM0_AGCRSSITable 0xc78
138 #define rOFDM0_HTSTFAGC 0xc7c
139 #define rOFDM0_XATxIQImbalance 0xc80
140 #define rOFDM0_XATxAFE 0xc84
141 #define rOFDM0_XBTxIQImbalance 0xc88
142 #define rOFDM0_XBTxAFE 0xc8c
143 #define rOFDM0_XCTxIQImbalance 0xc90
144 #define rOFDM0_XCTxAFE 0xc94
145 #define rOFDM0_XDTxIQImbalance 0xc98
146 #define rOFDM0_XDTxAFE 0xc9c
147 #define rOFDM0_RxHPParameter 0xce0
148 #define rOFDM0_TxPseudoNoiseWgt 0xce4
149 #define rOFDM0_FrameSync 0xcf0
150 #define rOFDM0_DFSReport 0xcf4
151 #define rOFDM0_TxCoeff1 0xca4
152 #define rOFDM0_TxCoeff2 0xca8
153 #define rOFDM0_TxCoeff3 0xcac
154 #define rOFDM0_TxCoeff4 0xcb0
155 #define rOFDM0_TxCoeff5 0xcb4
156 #define rOFDM0_TxCoeff6 0xcb8
160 #define rOFDM1_LSTF 0xd00
161 #define rOFDM1_TRxPathEnable 0xd04
162 #define rOFDM1_CFO 0xd08
163 #define rOFDM1_CSI1 0xd10
164 #define rOFDM1_SBD 0xd14
165 #define rOFDM1_CSI2 0xd18
166 #define rOFDM1_CFOTracking 0xd2c
167 #define rOFDM1_TRxMesaure1 0xd34
168 #define rOFDM1_IntfDet 0xd3c
169 #define rOFDM1_PseudoNoiseStateAB 0xd50
170 #define rOFDM1_PseudoNoiseStateCD 0xd54
171 #define rOFDM1_RxPseudoNoiseWgt 0xd58
172 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail
173 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
174 #define rOFDM_PHYCounter3 0xda8 //MCS not support
175 #define rOFDM_ShortCFOAB 0xdac
176 #define rOFDM_ShortCFOCD 0xdb0
177 #define rOFDM_LongCFOAB 0xdb4
178 #define rOFDM_LongCFOCD 0xdb8
179 #define rOFDM_TailCFOAB 0xdbc
180 #define rOFDM_TailCFOCD 0xdc0
181 #define rOFDM_PWMeasure1 0xdc4
182 #define rOFDM_PWMeasure2 0xdc8
183 #define rOFDM_BWReport 0xdcc
184 #define rOFDM_AGCReport 0xdd0
185 #define rOFDM_RxSNR 0xdd4
186 #define rOFDM_RxEVMCSI 0xdd8
187 #define rOFDM_SIGReport 0xddc
190 #define rTxAGC_Rate18_06 0xe00
191 #define rTxAGC_Rate54_24 0xe04
192 #define rTxAGC_CCK_Mcs32 0xe08
193 #define rTxAGC_Mcs03_Mcs00 0xe10
194 #define rTxAGC_Mcs07_Mcs04 0xe14
195 #define rTxAGC_Mcs11_Mcs08 0xe18
196 #define rTxAGC_Mcs15_Mcs12 0xe1c
201 #define rZebra1_HSSIEnable 0x0
202 #define rZebra1_TRxEnable1 0x1
203 #define rZebra1_TRxEnable2 0x2
204 #define rZebra1_AGC 0x4
205 #define rZebra1_ChargePump 0x5
206 #define rZebra1_Channel 0x7
207 #define rZebra1_TxGain 0x8
208 #define rZebra1_TxLPF 0x9
209 #define rZebra1_RxLPF 0xb
210 #define rZebra1_RxHPFCorner 0xc
213 #define rGlobalCtrl 0
214 #define rRTL8256_TxLPF 19
215 #define rRTL8256_RxLPF 11
218 #define rRTL8258_TxLPF 0x11
219 #define rRTL8258_RxLPF 0x13
220 #define rRTL8258_RSSILPF 0xa
224 #define bBBResetB 0x100
225 #define bGlobalResetB 0x200
226 #define bOFDMTxStart 0x4
227 #define bCCKTxStart 0x8
228 #define bCRC32Debug 0x100
229 #define bPMACLoopback 0x10
230 #define bTxLSIG 0xffffff
231 #define bOFDMTxRate 0xf
232 #define bOFDMTxReserved 0x10
233 #define bOFDMTxLength 0x1ffe0
234 #define bOFDMTxParity 0x20000
235 #define bTxHTSIG1 0xffffff
236 #define bTxHTMCSRate 0x7f
238 #define bTxHTLength 0xffff00
239 #define bTxHTSIG2 0xffffff
240 #define bTxHTSmoothing 0x1
241 #define bTxHTSounding 0x2
242 #define bTxHTReserved 0x4
243 #define bTxHTAggreation 0x8
244 #define bTxHTSTBC 0x30
245 #define bTxHTAdvanceCoding 0x40
246 #define bTxHTShortGI 0x80
247 #define bTxHTNumberHT_LTF 0x300
248 #define bTxHTCRC8 0x3fc00
249 #define bCounterReset 0x10000
250 #define bNumOfOFDMTx 0xffff
251 #define bNumOfCCKTx 0xffff0000
252 #define bTxIdleInterval 0xffff
253 #define bOFDMService 0xffff0000
254 #define bTxMACHeader 0xffffffff
255 #define bTxDataInit 0xff
256 #define bTxHTMode 0x100
257 #define bTxDataType 0x30000
258 #define bTxRandomSeed 0xffffffff
259 #define bCCKTxPreamble 0x1
260 #define bCCKTxSFD 0xffff0000
261 #define bCCKTxSIG 0xff
262 #define bCCKTxService 0xff00
263 #define bCCKLengthExt 0x8000
264 #define bCCKTxLength 0xffff0000
265 #define bCCKTxCRC16 0xffff
266 #define bCCKTxStatus 0x1
267 #define bOFDMTxStatus 0x2
271 #define bJapanMode 0x2
272 #define bCCKTxSC 0x30
273 #define bCCKEn 0x1000000
274 #define bOFDMEn 0x2000000
275 #define bOFDMRxADCPhase 0x10000
276 #define bOFDMTxDACPhase 0x40000
277 #define bXATxAGC 0x3f
278 #define bXBTxAGC 0xf00
279 #define bXCTxAGC 0xf000
280 #define bXDTxAGC 0xf0000
281 #define bPAStart 0xf0000000
282 #define bTRStart 0x00f00000
283 #define bRFStart 0x0000f000
284 #define bBBStart 0x000000f0
285 #define bBBCCKStart 0x0000000f
286 #define bPAEnd 0xf //Reg0x814
287 #define bTREnd 0x0f000000
288 #define bRFEnd 0x000f0000
289 #define bCCAMask 0x000000f0 //T2R
290 #define bR2RCCAMask 0x00000f00
291 #define bHSSI_R2TDelay 0xf8000000
292 #define bHSSI_T2RDelay 0xf80000
293 #define bContTxHSSI 0x400 //chane gain at continue Tx
294 #define bIGFromCCK 0x200
295 #define bAGCAddress 0x3f
296 #define bRxHPTx 0x7000
297 #define bRxHPT2R 0x38000
298 #define bRxHPCCKIni 0xc0000
299 #define bAGCTxCode 0xc00000
300 #define bAGCRxCode 0x300000
301 #define b3WireDataLength 0x800
302 #define b3WireAddressLength 0x400
303 #define b3WireRFPowerDown 0x1
304 //#define bHWSISelect 0x8
305 #define b5GPAPEPolarity 0x40000000
306 #define b2GPAPEPolarity 0x80000000
307 #define bRFSW_TxDefaultAnt 0x3
308 #define bRFSW_TxOptionAnt 0x30
309 #define bRFSW_RxDefaultAnt 0x300
310 #define bRFSW_RxOptionAnt 0x3000
311 #define bRFSI_3WireData 0x1
312 #define bRFSI_3WireClock 0x2
313 #define bRFSI_3WireLoad 0x4
314 #define bRFSI_3WireRW 0x8
315 #define bRFSI_3Wire 0xf //3-wire total control
316 #define bRFSI_RFENV 0x10
317 #define bRFSI_TRSW 0x20
318 #define bRFSI_TRSWB 0x40
319 #define bRFSI_ANTSW 0x100
320 #define bRFSI_ANTSWB 0x200
321 #define bRFSI_PAPE 0x400
322 #define bRFSI_PAPE5G 0x800
323 #define bBandSelect 0x1
324 #define bHTSIG2_GI 0x80
325 #define bHTSIG2_Smoothing 0x01
326 #define bHTSIG2_Sounding 0x02
327 #define bHTSIG2_Aggreaton 0x08
328 #define bHTSIG2_STBC 0x30
329 #define bHTSIG2_AdvCoding 0x40
330 #define bHTSIG2_NumOfHTLTF 0x300
331 #define bHTSIG2_CRC8 0x3fc
332 #define bHTSIG1_MCS 0x7f
333 #define bHTSIG1_BandWidth 0x80
334 #define bHTSIG1_HTLength 0xffff
335 #define bLSIG_Rate 0xf
336 #define bLSIG_Reserved 0x10
337 #define bLSIG_Length 0x1fffe
338 #define bLSIG_Parity 0x20
339 #define bCCKRxPhase 0x4
340 #define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address
341 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
342 #define bLSSIReadBackData 0xfff
343 #define bLSSIReadOKFlag 0x1000
344 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
346 #define bRegulator0Standby 0x1
347 #define bRegulatorPLLStandby 0x2
348 #define bRegulator1Standby 0x4
349 #define bPLLPowerUp 0x8
350 #define bDPLLPowerUp 0x10
351 #define bDA10PowerUp 0x20
352 #define bAD7PowerUp 0x200
353 #define bDA6PowerUp 0x2000
354 #define bXtalPowerUp 0x4000
355 #define b40MDClkPowerUP 0x8000
356 #define bDA6DebugMode 0x20000
357 #define bDA6Swing 0x380000
358 #define bADClkPhase 0x4000000
359 #define b80MClkDelay 0x18000000
360 #define bAFEWatchDogEnable 0x20000000
361 #define bXtalCap 0x0f000000
362 #define bIntDifClkEnable 0x400
363 #define bExtSigClkEnable 0x800
364 #define bBandgapMbiasPowerUp 0x10000
365 #define bAD11SHGain 0xc0000
366 #define bAD11InputRange 0x700000
367 #define bAD11OPCurrent 0x3800000
368 #define bIPathLoopback 0x4000000
369 #define bQPathLoopback 0x8000000
370 #define bAFELoopback 0x10000000
371 #define bDA10Swing 0x7e0
372 #define bDA10Reverse 0x800
373 #define bDAClkSource 0x1000
374 #define bAD7InputRange 0x6000
375 #define bAD7Gain 0x38000
376 #define bAD7OutputCMMode 0x40000
377 #define bAD7InputCMMode 0x380000
378 #define bAD7Current 0xc00000
379 #define bRegulatorAdjust 0x7000000
380 #define bAD11PowerUpAtTx 0x1
381 #define bDA10PSAtTx 0x10
382 #define bAD11PowerUpAtRx 0x100
383 #define bDA10PSAtRx 0x1000
385 #define bCCKRxAGCFormat 0x200
387 #define bPSDFFTSamplepPoint 0xc000
388 #define bPSDAverageNum 0x3000
389 #define bIQPathControl 0xc00
390 #define bPSDFreq 0x3ff
391 #define bPSDAntennaPath 0x30
392 #define bPSDIQSwitch 0x40
393 #define bPSDRxTrigger 0x400000
394 #define bPSDTxTrigger 0x80000000
395 #define bPSDSineToneScale 0x7f000000
396 #define bPSDReport 0xffff
399 #define bOFDMTxSC 0x30000000
401 #define bOFDMTxOn 0x2
402 #define bDebugPage 0xfff //reset debug page and also HWord, LWord
403 #define bDebugItem 0xff //reset debug page and LWord
405 #define bAntNonHT 0x100
406 #define bAntHT1 0x1000
407 #define bAntHT2 0x10000
408 #define bAntHT1S1 0x100000
409 #define bAntNonHTS1 0x1000000
412 #define bCCKBBMode 0x3
413 #define bCCKTxPowerSaving 0x80
414 #define bCCKRxPowerSaving 0x40
415 #define bCCKSideBand 0x10
416 #define bCCKScramble 0x8
417 #define bCCKAntDiversity 0x8000
418 #define bCCKCarrierRecovery 0x4000
419 #define bCCKTxRate 0x3000
420 #define bCCKDCCancel 0x0800
421 #define bCCKISICancel 0x0400
422 #define bCCKMatchFilter 0x0200
423 #define bCCKEqualizer 0x0100
424 #define bCCKPreambleDetect 0x800000
425 #define bCCKFastFalseCCA 0x400000
426 #define bCCKChEstStart 0x300000
427 #define bCCKCCACount 0x080000
428 #define bCCKcs_lim 0x070000
429 #define bCCKBistMode 0x80000000
430 #define bCCKCCAMask 0x40000000
431 #define bCCKTxDACPhase 0x4
432 #define bCCKRxADCPhase 0x20000000 //r_rx_clk
433 #define bCCKr_cp_mode0 0x0100
434 #define bCCKTxDCOffset 0xf0
435 #define bCCKRxDCOffset 0xf
436 #define bCCKCCAMode 0xc000
437 #define bCCKFalseCS_lim 0x3f00
438 #define bCCKCS_ratio 0xc00000
439 #define bCCKCorgBit_sel 0x300000
440 #define bCCKPD_lim 0x0f0000
441 #define bCCKNewCCA 0x80000000
442 #define bCCKRxHPofIG 0x8000
443 #define bCCKRxIG 0x7f00
444 #define bCCKLNAPolarity 0x800000
445 #define bCCKRx1stGain 0x7f0000
446 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
447 #define bCCKRxAGCSatLevel 0x1f000000
448 #define bCCKRxAGCSatCount 0xe0
449 #define bCCKRxRFSettle 0x1f //AGCsamp_dly
450 #define bCCKFixedRxAGC 0x8000
451 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
452 #define bCCKAntennaPolarity 0x2000
453 #define bCCKTxFilterType 0x0c00
454 #define bCCKRxAGCReportType 0x0300
455 #define bCCKRxDAGCEn 0x80000000
456 #define bCCKRxDAGCPeriod 0x20000000
457 #define bCCKRxDAGCSatLevel 0x1f000000
458 #define bCCKTimingRecovery 0x800000
459 #define bCCKTxC0 0x3f0000
460 #define bCCKTxC1 0x3f000000
461 #define bCCKTxC2 0x3f
462 #define bCCKTxC3 0x3f00
463 #define bCCKTxC4 0x3f0000
464 #define bCCKTxC5 0x3f000000
465 #define bCCKTxC6 0x3f
466 #define bCCKTxC7 0x3f00
467 #define bCCKDebugPort 0xff0000
468 #define bCCKDACDebug 0x0f000000
469 #define bCCKFalseAlarmEnable 0x8000
470 #define bCCKFalseAlarmRead 0x4000
471 #define bCCKTRSSI 0x7f
472 #define bCCKRxAGCReport 0xfe
473 #define bCCKRxReport_AntSel 0x80000000
474 #define bCCKRxReport_MFOff 0x40000000
475 #define bCCKRxRxReport_SQLoss 0x20000000
476 #define bCCKRxReport_Pktloss 0x10000000
477 #define bCCKRxReport_Lockedbit 0x08000000
478 #define bCCKRxReport_RateError 0x04000000
479 #define bCCKRxReport_RxRate 0x03000000
480 #define bCCKRxFACounterLower 0xff
481 #define bCCKRxFACounterUpper 0xff000000
482 #define bCCKRxHPAGCStart 0xe000
483 #define bCCKRxHPAGCFinal 0x1c00
485 #define bCCKRxFalseAlarmEnable 0x8000
486 #define bCCKFACounterFreeze 0x4000
488 #define bCCKTxPathSel 0x10000000
489 #define bCCKDefaultRxPath 0xc000000
490 #define bCCKOptionRxPath 0x3000000
493 #define bNumOfSTF 0x3
494 #define bShift_L 0xc0
504 #define bTRSSIFreq 0x200
505 #define bADCBackoff 0x3000
506 #define bDFIRBackoff 0xc000
507 #define bTRSSILatchPhase 0x10000
508 #define bRxIDCOffset 0xff
509 #define bRxQDCOffset 0xff00
510 #define bRxDFIRMode 0x1800000
511 #define bRxDCNFType 0xe000000
512 #define bRXIQImb_A 0x3ff
513 #define bRXIQImb_B 0xfc00
514 #define bRXIQImb_C 0x3f0000
515 #define bRXIQImb_D 0xffc00000
516 #define bDC_dc_Notch 0x60000
517 #define bRxNBINotch 0x1f000000
519 #define bPD_TH_Opt2 0xc000
520 #define bPWED_TH 0x700
521 #define bIfMF_Win_L 0x800
522 #define bPD_Option 0x1000
523 #define bMF_Win_L 0xe000
524 #define bBW_Search_L 0x30000
525 #define bwin_enh_L 0xc0000
526 #define bBW_TH 0x700000
527 #define bED_TH2 0x3800000
528 #define bBW_option 0x4000000
529 #define bRatio_TH 0x18000000
530 #define bWindow_L 0xe0000000
531 #define bSBD_Option 0x1
532 #define bFrame_TH 0x1c
533 #define bFS_Option 0x60
534 #define bDC_Slope_check 0x80
535 #define bFGuard_Counter_DC_L 0xe00
536 #define bFrame_Weight_Short 0x7000
537 #define bSub_Tune 0xe00000
538 #define bFrame_DC_Length 0xe000000
539 #define bSBD_start_offset 0x30000000
540 #define bFrame_TH_2 0x7
541 #define bFrame_GI2_TH 0x38
542 #define bGI2_Sync_en 0x40
543 #define bSarch_Short_Early 0x300
544 #define bSarch_Short_Late 0xc00
545 #define bSarch_GI2_Late 0x70000
546 #define bCFOAntSum 0x1
548 #define bCFOStartOffset 0xc
549 #define bCFOLookBack 0x70
550 #define bCFOSumWeight 0x80
551 #define bDAGCEnable 0x10000
552 #define bTXIQImb_A 0x3ff
553 #define bTXIQImb_B 0xfc00
554 #define bTXIQImb_C 0x3f0000
555 #define bTXIQImb_D 0xffc00000
556 #define bTxIDCOffset 0xff
557 #define bTxQDCOffset 0xff00
558 #define bTxDFIRMode 0x10000
559 #define bTxPesudoNoiseOn 0x4000000
560 #define bTxPesudoNoise_A 0xff
561 #define bTxPesudoNoise_B 0xff00
562 #define bTxPesudoNoise_C 0xff0000
563 #define bTxPesudoNoise_D 0xff000000
564 #define bCCADropOption 0x20000
565 #define bCCADropThres 0xfff00000
567 #define bEDCCA_L 0xf0
568 #define bLambda_ED 0x300
569 #define bRxInitialGain 0x7f
570 #define bRxAntDivEn 0x80
571 #define bRxAGCAddressForLNA 0x7f00
572 #define bRxHighPowerFlow 0x8000
573 #define bRxAGCFreezeThres 0xc0000
574 #define bRxFreezeStep_AGC1 0x300000
575 #define bRxFreezeStep_AGC2 0xc00000
576 #define bRxFreezeStep_AGC3 0x3000000
577 #define bRxFreezeStep_AGC0 0xc000000
578 #define bRxRssi_Cmp_En 0x10000000
579 #define bRxQuickAGCEn 0x20000000
580 #define bRxAGCFreezeThresMode 0x40000000
581 #define bRxOverFlowCheckType 0x80000000
582 #define bRxAGCShift 0x7f
583 #define bTRSW_Tri_Only 0x80
584 #define bPowerThres 0x300
586 #define bRxAGCTogetherEn 0x2
587 #define bRxAGCMin 0x4
588 #define bRxHP_Ini 0x7
589 #define bRxHP_TRLNA 0x70
590 #define bRxHP_RSSI 0x700
591 #define bRxHP_BBP1 0x7000
592 #define bRxHP_BBP2 0x70000
593 #define bRxHP_BBP3 0x700000
594 #define bRSSI_H 0x7f0000 //the threshold for high power
595 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
596 #define bRxSettle_TRSW 0x7
597 #define bRxSettle_LNA 0x38
598 #define bRxSettle_RSSI 0x1c0
599 #define bRxSettle_BBP 0xe00
600 #define bRxSettle_RxHP 0x7000
601 #define bRxSettle_AntSW_RSSI 0x38000
602 #define bRxSettle_AntSW 0xc0000
603 #define bRxProcessTime_DAGC 0x300000
604 #define bRxSettle_HSSI 0x400000
605 #define bRxProcessTime_BBPPW 0x800000
606 #define bRxAntennaPowerShift 0x3000000
607 #define bRSSITableSelect 0xc000000
608 #define bRxHP_Final 0x7000000
609 #define bRxHTSettle_BBP 0x7
610 #define bRxHTSettle_HSSI 0x8
611 #define bRxHTSettle_RxHP 0x70
612 #define bRxHTSettle_BBPPW 0x80
613 #define bRxHTSettle_Idle 0x300
614 #define bRxHTSettle_Reserved 0x1c00
615 #define bRxHTRxHPEn 0x8000
616 #define bRxHTAGCFreezeThres 0x30000
617 #define bRxHTAGCTogetherEn 0x40000
618 #define bRxHTAGCMin 0x80000
619 #define bRxHTAGCEn 0x100000
620 #define bRxHTDAGCEn 0x200000
621 #define bRxHTRxHP_BBP 0x1c00000
622 #define bRxHTRxHP_Final 0xe0000000
623 #define bRxPWRatioTH 0x3
624 #define bRxPWRatioEn 0x4
625 #define bRxMFHold 0x3800
626 #define bRxPD_Delay_TH1 0x38
627 #define bRxPD_Delay_TH2 0x1c0
628 #define bRxPD_DC_COUNT_MAX 0x600
629 //#define bRxMF_Hold 0x3800
630 #define bRxPD_Delay_TH 0x8000
631 #define bRxProcess_Delay 0xf0000
632 #define bRxSearchrange_GI2_Early 0x700000
633 #define bRxFrame_Guard_Counter_L 0x3800000
634 #define bRxSGI_Guard_L 0xc000000
635 #define bRxSGI_Search_L 0x30000000
636 #define bRxSGI_TH 0xc0000000
637 #define bDFSCnt0 0xff
638 #define bDFSCnt1 0xff00
639 #define bDFSFlag 0xf0000
641 #define bMFWeightSum 0x300000
642 #define bMinIdxTH 0x7f000000
644 #define bDAFormat 0x40000
646 #define bTxChEmuEnable 0x01000000
648 #define bTRSWIsolation_A 0x7f
649 #define bTRSWIsolation_B 0x7f00
650 #define bTRSWIsolation_C 0x7f0000
651 #define bTRSWIsolation_D 0x7f000000
653 #define bExtLNAGain 0x7c00
657 #define bAntennaMapping 0x10
659 #define bCFOAntSumD 0x200
660 #define bPHYCounterReset 0x8000000
661 #define bCFOReportGet 0x4000000
662 #define bOFDMContinueTx 0x10000000
663 #define bOFDMSingleCarrier 0x20000000
664 #define bOFDMSingleTone 0x40000000
665 //#define bRxPath1 0x01
666 //#define bRxPath2 0x02
667 //#define bRxPath3 0x04
668 //#define bRxPath4 0x08
669 //#define bTxPath1 0x10
670 //#define bTxPath2 0x20
671 #define bHTDetect 0x100
672 #define bCFOEn 0x10000
673 #define bCFOValue 0xfff00000
674 #define bSigTone_Re 0x3f
675 #define bSigTone_Im 0x7f00
676 #define bCounter_CCA 0xffff
677 #define bCounter_ParityFail 0xffff0000
678 #define bCounter_RateIllegal 0xffff
679 #define bCounter_CRC8Fail 0xffff0000
680 #define bCounter_MCSNoSupport 0xffff
681 #define bCounter_FastSync 0xffff
682 #define bShortCFO 0xfff
683 #define bShortCFOTLength 12 //total
684 #define bShortCFOFLength 11 //fraction
685 #define bLongCFO 0x7ff
686 #define bLongCFOTLength 11
687 #define bLongCFOFLength 11
688 #define bTailCFO 0x1fff
689 #define bTailCFOTLength 13
690 #define bTailCFOFLength 12
692 #define bmax_en_pwdB 0xffff
693 #define bCC_power_dB 0xffff0000
694 #define bnoise_pwdB 0xffff
695 #define bPowerMeasTLength 10
696 #define bPowerMeasFLength 3
697 #define bRx_HT_BW 0x1
701 #define bNB_intf_det_on 0x1
702 #define bIntf_win_len_cfg 0x30
703 #define bNB_Intf_TH_cfg 0x1c0
706 #define bTableSel 0x40
709 #define bRxSNR_A 0xff
710 #define bRxSNR_B 0xff00
711 #define bRxSNR_C 0xff0000
712 #define bRxSNR_D 0xff000000
713 #define bSNREVMTLength 8
714 #define bSNREVMFLength 1
717 #define bCSI2nd 0xff00
718 #define bRxEVM1st 0xff0000
719 #define bRxEVM2nd 0xff000000
723 #define bSGIEN 0x10000
725 #define bSFactorQAM1 0xf
726 #define bSFactorQAM2 0xf0
727 #define bSFactorQAM3 0xf00
728 #define bSFactorQAM4 0xf000
729 #define bSFactorQAM5 0xf0000
730 #define bSFactorQAM6 0xf0000
731 #define bSFactorQAM7 0xf00000
732 #define bSFactorQAM8 0xf000000
733 #define bSFactorQAM9 0xf0000000
734 #define bCSIScheme 0x100000
736 #define bNoiseLvlTopSet 0x3
737 #define bChSmooth 0x4
738 #define bChSmoothCfg1 0x38
739 #define bChSmoothCfg2 0x1c0
740 #define bChSmoothCfg3 0xe00
741 #define bChSmoothCfg4 0x7000
742 #define bMRCMode 0x800000
743 #define bTHEVMCfg 0x7000000
745 #define bLoopFitType 0x1
747 #define bUpdCFOOffData 0x80
748 #define bAdvUpdCFO 0x100
749 #define bAdvTimeCtrl 0x800
750 #define bUpdClko 0x1000
752 #define bTrackingMode 0x8000
753 #define bPhCmpEnable 0x10000
754 #define bUpdClkoLTF 0x20000
755 #define bComChCFO 0x40000
756 #define bCSIEstiMode 0x80000
757 #define bAdvUpdEqz 0x100000
758 #define bUChCfg 0x7000000
759 #define bUpdEqz 0x8000000
762 #define bTxAGCRate18_06 0x7f7f7f7f
763 #define bTxAGCRate54_24 0x7f7f7f7f
764 #define bTxAGCRateMCS32 0x7f
765 #define bTxAGCRateCCK 0x7f00
766 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
767 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
768 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
769 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
773 #define bRxPesudoNoiseOn 0x20000000
774 #define bRxPesudoNoise_A 0xff
775 #define bRxPesudoNoise_B 0xff00
776 #define bRxPesudoNoise_C 0xff0000
777 #define bRxPesudoNoise_D 0xff000000
778 #define bPesudoNoiseState_A 0xffff
779 #define bPesudoNoiseState_B 0xffff0000
780 #define bPesudoNoiseState_C 0xffff
781 #define bPesudoNoiseState_D 0xffff0000
785 #define bZebra1_HSSIEnable 0x8
786 #define bZebra1_TRxControl 0xc00
787 #define bZebra1_TRxGainSetting 0x07f
788 #define bZebra1_RxCorner 0xc00
789 #define bZebra1_TxChargePump 0x38
790 #define bZebra1_RxChargePump 0x7
791 #define bZebra1_ChannelNum 0xf80
792 #define bZebra1_TxLPFBW 0x400
793 #define bZebra1_RxLPFBW 0x600
796 #define bRTL8256RegModeCtrl1 0x100
797 #define bRTL8256RegModeCtrl0 0x40
798 #define bRTL8256_TxLPFBW 0x18
799 #define bRTL8256_RxLPFBW 0x600
802 #define bRTL8258_TxLPFBW 0xc
803 #define bRTL8258_RxLPFBW 0xc00
804 #define bRTL8258_RSSILPFBW 0xc0
806 //byte endable for sb_write
815 //for PutRegsetting & GetRegSetting BitMask
816 #define bMaskByte0 0xff
817 #define bMaskByte1 0xff00
818 #define bMaskByte2 0xff0000
819 #define bMaskByte3 0xff000000
820 #define bMaskHWord 0xffff0000
821 #define bMaskLWord 0x0000ffff
822 #define bMaskDWord 0xffffffff
824 //for PutRFRegsetting & GetRFRegSetting BitMask
825 #define bMask12Bits 0xfff
830 #define LeftAntenna 0x0
831 #define RightAntenna 0x1
833 #define tCheckTxStatus 500 //500ms
834 #define tUpdateRxCounter 100 //100ms
840 //define Register-End
841 #define bPMAC_End 0x1ff
842 #define bFPGAPHY0_End 0x8ff
843 #define bFPGAPHY1_End 0x9ff
844 #define bCCKPHY0_End 0xaff
845 #define bOFDMPHY0_End 0xcff
846 #define bOFDMPHY1_End 0xdff
848 //define max debug item in each debug page
849 //#define bMaxItem_FPGA_PHY0 0x9
850 //#define bMaxItem_FPGA_PHY1 0x3
851 //#define bMaxItem_PHY_11B 0x16
852 //#define bMaxItem_OFDM_PHY0 0x29
853 //#define bMaxItem_OFDM_PHY1 0x0
855 #define bPMACControl 0x0
856 #define bWMACControl 0x1
857 #define bWNICControl 0x2
864 #define rRTL8256RxMixerPole 0xb
865 #define bZebraRxMixerPole 0x6
866 #define rRTL8256TxBBOPBias 0x9
867 #define bRTL8256TxBBOPBias 0x400
868 #define rRTL8256TxBBBW 19
869 #define bRTL8256TxBBBW 0x18
871 #endif //__INC_HAL8190PCIPHYREG_H