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x86/PCI: use host bridge _CRS info on ASUS M2V-MX SE
[linux-btrfs-devel.git] / drivers / usb / gadget / m66592-udc.h
blob7b93d579af372e713e945652393f749c7320f18e
1 /*
2 * M66592 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23 #ifndef __M66592_UDC_H__
24 #define __M66592_UDC_H__
25
26 #ifdef CONFIG_HAVE_CLK
27 #include <linux/clk.h>
28 #endif
29
30 #include <linux/usb/m66592.h>
31
32 #define M66592_SYSCFG 0x00
33 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
34 #define M66592_XTAL48 0x8000 /* 48MHz */
35 #define M66592_XTAL24 0x4000 /* 24MHz */
36 #define M66592_XTAL12 0x0000 /* 12MHz */
37 #define M66592_XCKE 0x2000 /* b13: External clock enable */
38 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
39 #define M66592_PLLC 0x0800 /* b11: PLL control */
40 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
41 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
42 #define M66592_HSE 0x0080 /* b7: Hi-speed enable */
43 #define M66592_DCFM 0x0040 /* b6: Controller function select */
44 #define M66592_DMRPD 0x0020 /* b5: D- pull down control */
45 #define M66592_DPRPU 0x0010 /* b4: D+ pull up control */
46 #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
47 #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */
48 #define M66592_USBE 0x0001 /* b0: USB module operation enable */
49
50 #define M66592_SYSSTS 0x02
51 #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */
52 #define M66592_SE1 0x0003 /* SE1 */
53 #define M66592_KSTS 0x0002 /* K State */
54 #define M66592_JSTS 0x0001 /* J State */
55 #define M66592_SE0 0x0000 /* SE0 */
56
57 #define M66592_DVSTCTR 0x04
58 #define M66592_WKUP 0x0100 /* b8: Remote wakeup */
59 #define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */
60 #define M66592_USBRST 0x0040 /* b6: USB reset enable */
61 #define M66592_RESUME 0x0020 /* b5: Resume enable */
62 #define M66592_UACT 0x0010 /* b4: USB bus enable */
63 #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */
64 #define M66592_HSMODE 0x0003 /* Hi-Speed mode */
65 #define M66592_FSMODE 0x0002 /* Full-Speed mode */
66 #define M66592_HSPROC 0x0001 /* HS handshake is processing */
67
68 #define M66592_TESTMODE 0x06
69 #define M66592_UTST 0x000F /* b4-0: Test select */
70 #define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */
71 #define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
72 #define M66592_H_TST_K 0x000A /* HOST TEST K */
73 #define M66592_H_TST_J 0x0009 /* HOST TEST J */
74 #define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */
75 #define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */
76 #define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
77 #define M66592_P_TST_K 0x0002 /* PERI TEST K */
78 #define M66592_P_TST_J 0x0001 /* PERI TEST J */
79 #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
80
81 /* built-in registers */
82 #define M66592_CFBCFG 0x0A
83 #define M66592_D0FBCFG 0x0C
84 #define M66592_LITTLE 0x0100 /* b8: Little endian mode */
85 /* external chip case */
86 #define M66592_PINCFG 0x0A
87 #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
88 #define M66592_BIGEND 0x0100 /* b8: Big endian mode */
89
90 #define M66592_DMA0CFG 0x0C
91 #define M66592_DMA1CFG 0x0E
92 #define M66592_DREQA 0x4000 /* b14: Dreq active select */
93 #define M66592_BURST 0x2000 /* b13: Burst mode */
94 #define M66592_DACKA 0x0400 /* b10: Dack active select */
95 #define M66592_DFORM 0x0380 /* b9-7: DMA mode select */
96 #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
97 #define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
98 #define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
99 #define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
100 #define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */
101 #define M66592_DENDA 0x0040 /* b6: Dend active select */
102 #define M66592_PKTM 0x0020 /* b5: Packet mode */
103 #define M66592_DENDE 0x0010 /* b4: Dend enable */
104 #define M66592_OBUS 0x0004 /* b2: OUTbus mode */
105
106 /* common case */
107 #define M66592_CFIFO 0x10
108 #define M66592_D0FIFO 0x14
109 #define M66592_D1FIFO 0x18
110
111 #define M66592_CFIFOSEL 0x1E
112 #define M66592_D0FIFOSEL 0x24
113 #define M66592_D1FIFOSEL 0x2A
114 #define M66592_RCNT 0x8000 /* b15: Read count mode */
115 #define M66592_REW 0x4000 /* b14: Buffer rewind */
116 #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
117 #define M66592_DREQE 0x1000 /* b12: DREQ output enable */
118 #define M66592_MBW_8 0x0000 /* 8bit */
119 #define M66592_MBW_16 0x0400 /* 16bit */
120 #define M66592_MBW_32 0x0800 /* 32bit */
121 #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
122 #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
123 #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
124 #define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */
125 #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */
126
127 #define M66592_CFIFOCTR 0x20
128 #define M66592_D0FIFOCTR 0x26
129 #define M66592_D1FIFOCTR 0x2c
130 #define M66592_BVAL 0x8000 /* b15: Buffer valid flag */
131 #define M66592_BCLR 0x4000 /* b14: Buffer clear */
132 #define M66592_FRDY 0x2000 /* b13: FIFO ready */
133 #define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */
134
135 #define M66592_CFIFOSIE 0x22
136 #define M66592_TGL 0x8000 /* b15: Buffer toggle */
137 #define M66592_SCLR 0x4000 /* b14: Buffer clear */
138 #define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */
139
140 #define M66592_D0FIFOTRN 0x28
141 #define M66592_D1FIFOTRN 0x2E
142 #define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */
143
144 #define M66592_INTENB0 0x30
145 #define M66592_VBSE 0x8000 /* b15: VBUS interrupt */
146 #define M66592_RSME 0x4000 /* b14: Resume interrupt */
147 #define M66592_SOFE 0x2000 /* b13: Frame update interrupt */
148 #define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */
149 #define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */
150 #define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */
151 #define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */
152 #define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */
153 #define M66592_URST 0x0080 /* b7: USB reset detected interrupt */
154 #define M66592_SADR 0x0040 /* b6: Set address executed interrupt */
155 #define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */
156 #define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */
157 #define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */
158 #define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */
159 #define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */
160 #define M66592_SERR 0x0001 /* b0: Sequence error interrupt */
161
162 #define M66592_INTENB1 0x32
163 #define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */
164 #define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */
165 #define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
166 #define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */
167 #define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */
168 #define M66592_INTL 0x0002 /* b1: Interrupt sense select */
169 #define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */
170
171 #define M66592_BRDYENB 0x36
172 #define M66592_BRDYSTS 0x46
173 #define M66592_BRDY7 0x0080 /* b7: PIPE7 */
174 #define M66592_BRDY6 0x0040 /* b6: PIPE6 */
175 #define M66592_BRDY5 0x0020 /* b5: PIPE5 */
176 #define M66592_BRDY4 0x0010 /* b4: PIPE4 */
177 #define M66592_BRDY3 0x0008 /* b3: PIPE3 */
178 #define M66592_BRDY2 0x0004 /* b2: PIPE2 */
179 #define M66592_BRDY1 0x0002 /* b1: PIPE1 */
180 #define M66592_BRDY0 0x0001 /* b1: PIPE0 */
181
182 #define M66592_NRDYENB 0x38
183 #define M66592_NRDYSTS 0x48
184 #define M66592_NRDY7 0x0080 /* b7: PIPE7 */
185 #define M66592_NRDY6 0x0040 /* b6: PIPE6 */
186 #define M66592_NRDY5 0x0020 /* b5: PIPE5 */
187 #define M66592_NRDY4 0x0010 /* b4: PIPE4 */
188 #define M66592_NRDY3 0x0008 /* b3: PIPE3 */
189 #define M66592_NRDY2 0x0004 /* b2: PIPE2 */
190 #define M66592_NRDY1 0x0002 /* b1: PIPE1 */
191 #define M66592_NRDY0 0x0001 /* b1: PIPE0 */
192
193 #define M66592_BEMPENB 0x3A
194 #define M66592_BEMPSTS 0x4A
195 #define M66592_BEMP7 0x0080 /* b7: PIPE7 */
196 #define M66592_BEMP6 0x0040 /* b6: PIPE6 */
197 #define M66592_BEMP5 0x0020 /* b5: PIPE5 */
198 #define M66592_BEMP4 0x0010 /* b4: PIPE4 */
199 #define M66592_BEMP3 0x0008 /* b3: PIPE3 */
200 #define M66592_BEMP2 0x0004 /* b2: PIPE2 */
201 #define M66592_BEMP1 0x0002 /* b1: PIPE1 */
202 #define M66592_BEMP0 0x0001 /* b0: PIPE0 */
203
204 #define M66592_SOFCFG 0x3C
205 #define M66592_SOFM 0x000C /* b3-2: SOF palse mode */
206 #define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */
207 #define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
208 #define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */
209
210 #define M66592_INTSTS0 0x40
211 #define M66592_VBINT 0x8000 /* b15: VBUS interrupt */
212 #define M66592_RESM 0x4000 /* b14: Resume interrupt */
213 #define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */
214 #define M66592_DVST 0x1000 /* b12: Device state transition */
215 #define M66592_CTRT 0x0800 /* b11: Control stage transition */
216 #define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */
217 #define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */
218 #define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */
219 #define M66592_VBSTS 0x0080 /* b7: VBUS input port */
220 #define M66592_DVSQ 0x0070 /* b6-4: Device state */
221 #define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */
222 #define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */
223 #define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */
224 #define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */
225 #define M66592_DS_SUSP 0x0040 /* Suspend */
226 #define M66592_DS_CNFG 0x0030 /* Configured */
227 #define M66592_DS_ADDS 0x0020 /* Address */
228 #define M66592_DS_DFLT 0x0010 /* Default */
229 #define M66592_DS_POWR 0x0000 /* Powered */
230 #define M66592_DVSQS 0x0030 /* b5-4: Device state */
231 #define M66592_VALID 0x0008 /* b3: Setup packet detected flag */
232 #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */
233 #define M66592_CS_SQER 0x0006 /* Sequence error */
234 #define M66592_CS_WRND 0x0005 /* Control write nodata status */
235 #define M66592_CS_WRSS 0x0004 /* Control write status stage */
236 #define M66592_CS_WRDS 0x0003 /* Control write data stage */
237 #define M66592_CS_RDSS 0x0002 /* Control read status stage */
238 #define M66592_CS_RDDS 0x0001 /* Control read data stage */
239 #define M66592_CS_IDST 0x0000 /* Idle or setup stage */
240
241 #define M66592_INTSTS1 0x42
242 #define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */
243 #define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */
244 #define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */
245 #define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */
246
247 #define M66592_FRMNUM 0x4C
248 #define M66592_OVRN 0x8000 /* b15: Overrun error */
249 #define M66592_CRCE 0x4000 /* b14: Received data error */
250 #define M66592_SOFRM 0x0800 /* b11: SOF output mode */
251 #define M66592_FRNM 0x07FF /* b10-0: Frame number */
252
253 #define M66592_UFRMNUM 0x4E
254 #define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */
255
256 #define M66592_RECOVER 0x50
257 #define M66592_STSRECOV 0x0700 /* Status recovery */
258 #define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */
259 #define M66592_STSR_DEFAULT 0x0100 /* Default state */
260 #define M66592_STSR_ADDRESS 0x0200 /* Address state */
261 #define M66592_STSR_CONFIG 0x0300 /* Configured state */
262 #define M66592_USBADDR 0x007F /* b6-0: USB address */
263
264 #define M66592_USBREQ 0x54
265 #define M66592_bRequest 0xFF00 /* b15-8: bRequest */
266 #define M66592_GET_STATUS 0x0000
267 #define M66592_CLEAR_FEATURE 0x0100
268 #define M66592_ReqRESERVED 0x0200
269 #define M66592_SET_FEATURE 0x0300
270 #define M66592_ReqRESERVED1 0x0400
271 #define M66592_SET_ADDRESS 0x0500
272 #define M66592_GET_DESCRIPTOR 0x0600
273 #define M66592_SET_DESCRIPTOR 0x0700
274 #define M66592_GET_CONFIGURATION 0x0800
275 #define M66592_SET_CONFIGURATION 0x0900
276 #define M66592_GET_INTERFACE 0x0A00
277 #define M66592_SET_INTERFACE 0x0B00
278 #define M66592_SYNCH_FRAME 0x0C00
279 #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */
280 #define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */
281 #define M66592_HOST_TO_DEVICE 0x0000
282 #define M66592_DEVICE_TO_HOST 0x0080
283 #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */
284 #define M66592_STANDARD 0x0000
285 #define M66592_CLASS 0x0020
286 #define M66592_VENDOR 0x0040
287 #define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */
288 #define M66592_DEVICE 0x0000
289 #define M66592_INTERFACE 0x0001
290 #define M66592_ENDPOINT 0x0002
291
292 #define M66592_USBVAL 0x56
293 #define M66592_wValue 0xFFFF /* b15-0: wValue */
294 /* Standard Feature Selector */
295 #define M66592_ENDPOINT_HALT 0x0000
296 #define M66592_DEVICE_REMOTE_WAKEUP 0x0001
297 #define M66592_TEST_MODE 0x0002
298 /* Descriptor Types */
299 #define M66592_DT_TYPE 0xFF00
300 #define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8)
301 #define M66592_DT_DEVICE 0x01
302 #define M66592_DT_CONFIGURATION 0x02
303 #define M66592_DT_STRING 0x03
304 #define M66592_DT_INTERFACE 0x04
305 #define M66592_DT_ENDPOINT 0x05
306 #define M66592_DT_DEVICE_QUALIFIER 0x06
307 #define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07
308 #define M66592_DT_INTERFACE_POWER 0x08
309 #define M66592_DT_INDEX 0x00FF
310 #define M66592_CONF_NUM 0x00FF
311 #define M66592_ALT_SET 0x00FF
312
313 #define M66592_USBINDEX 0x58
314 #define M66592_wIndex 0xFFFF /* b15-0: wIndex */
315 #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */
316 #define M66592_TEST_J 0x0100 /* Test_J */
317 #define M66592_TEST_K 0x0200 /* Test_K */
318 #define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */
319 #define M66592_TEST_PACKET 0x0400 /* Test_Packet */
320 #define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */
321 #define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */
322 #define M66592_TEST_Reserved 0x4000 /* Reserved */
323 #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */
324 #define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */
325 #define M66592_EP_DIR_IN 0x0080
326 #define M66592_EP_DIR_OUT 0x0000
327
328 #define M66592_USBLENG 0x5A
329 #define M66592_wLength 0xFFFF /* b15-0: wLength */
330
331 #define M66592_DCPCFG 0x5C
332 #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
333 #define M66592_DIR 0x0010 /* b4: Control transfer DIR select */
334
335 #define M66592_DCPMAXP 0x5E
336 #define M66592_DEVSEL 0xC000 /* b15-14: Device address select */
337 #define M66592_DEVICE_0 0x0000 /* Device address 0 */
338 #define M66592_DEVICE_1 0x4000 /* Device address 1 */
339 #define M66592_DEVICE_2 0x8000 /* Device address 2 */
340 #define M66592_DEVICE_3 0xC000 /* Device address 3 */
341 #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */
342
343 #define M66592_DCPCTR 0x60
344 #define M66592_BSTS 0x8000 /* b15: Buffer status */
345 #define M66592_SUREQ 0x4000 /* b14: Send USB request */
346 #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
347 #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
348 #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
349 #define M66592_CCPL 0x0004 /* b2: control transfer complete */
350 #define M66592_PID 0x0003 /* b1-0: Response PID */
351 #define M66592_PID_STALL 0x0002 /* STALL */
352 #define M66592_PID_BUF 0x0001 /* BUF */
353 #define M66592_PID_NAK 0x0000 /* NAK */
354
355 #define M66592_PIPESEL 0x64
356 #define M66592_PIPENM 0x0007 /* b2-0: Pipe select */
357 #define M66592_PIPE0 0x0000 /* PIPE 0 */
358 #define M66592_PIPE1 0x0001 /* PIPE 1 */
359 #define M66592_PIPE2 0x0002 /* PIPE 2 */
360 #define M66592_PIPE3 0x0003 /* PIPE 3 */
361 #define M66592_PIPE4 0x0004 /* PIPE 4 */
362 #define M66592_PIPE5 0x0005 /* PIPE 5 */
363 #define M66592_PIPE6 0x0006 /* PIPE 6 */
364 #define M66592_PIPE7 0x0007 /* PIPE 7 */
365
366 #define M66592_PIPECFG 0x66
367 #define M66592_TYP 0xC000 /* b15-14: Transfer type */
368 #define M66592_ISO 0xC000 /* Isochronous */
369 #define M66592_INT 0x8000 /* Interrupt */
370 #define M66592_BULK 0x4000 /* Bulk */
371 #define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */
372 #define M66592_DBLB 0x0200 /* b9: Double buffer mode select */
373 #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
374 #define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */
375 #define M66592_DIR 0x0010 /* b4: Transfer direction select */
376 #define M66592_DIR_H_OUT 0x0010 /* HOST OUT */
377 #define M66592_DIR_P_IN 0x0010 /* PERI IN */
378 #define M66592_DIR_H_IN 0x0000 /* HOST IN */
379 #define M66592_DIR_P_OUT 0x0000 /* PERI OUT */
380 #define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */
381 #define M66592_EP1 0x0001
382 #define M66592_EP2 0x0002
383 #define M66592_EP3 0x0003
384 #define M66592_EP4 0x0004
385 #define M66592_EP5 0x0005
386 #define M66592_EP6 0x0006
387 #define M66592_EP7 0x0007
388 #define M66592_EP8 0x0008
389 #define M66592_EP9 0x0009
390 #define M66592_EP10 0x000A
391 #define M66592_EP11 0x000B
392 #define M66592_EP12 0x000C
393 #define M66592_EP13 0x000D
394 #define M66592_EP14 0x000E
395 #define M66592_EP15 0x000F
396
397 #define M66592_PIPEBUF 0x68
398 #define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
399 #define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10)
400 #define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */
401
402 #define M66592_PIPEMAXP 0x6A
403 #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */
404
405 #define M66592_PIPEPERI 0x6C
406 #define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */
407 #define M66592_IITV 0x0007 /* b2-0: ISO interval */
408
409 #define M66592_PIPE1CTR 0x70
410 #define M66592_PIPE2CTR 0x72
411 #define M66592_PIPE3CTR 0x74
412 #define M66592_PIPE4CTR 0x76
413 #define M66592_PIPE5CTR 0x78
414 #define M66592_PIPE6CTR 0x7A
415 #define M66592_PIPE7CTR 0x7C
416 #define M66592_BSTS 0x8000 /* b15: Buffer status */
417 #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */
418 #define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */
419 #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
420 #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
421 #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
422 #define M66592_PID 0x0003 /* b1-0: Response PID */
423
424 #define M66592_INVALID_REG 0x7E
425
426
427 #define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
428
429 #define M66592_MAX_SAMPLING 10
430
431 #define M66592_MAX_NUM_PIPE 8
432 #define M66592_MAX_NUM_BULK 3
433 #define M66592_MAX_NUM_ISOC 2
434 #define M66592_MAX_NUM_INT 2
435
436 #define M66592_BASE_PIPENUM_BULK 3
437 #define M66592_BASE_PIPENUM_ISOC 1
438 #define M66592_BASE_PIPENUM_INT 6
439
440 #define M66592_BASE_BUFNUM 6
441 #define M66592_MAX_BUFNUM 0x4F
442
443 struct m66592_pipe_info {
444 u16 pipe;
445 u16 epnum;
446 u16 maxpacket;
447 u16 type;
448 u16 interval;
449 u16 dir_in;
450 };
451
452 struct m66592_request {
453 struct usb_request req;
454 struct list_head queue;
455 };
456
457 struct m66592_ep {
458 struct usb_ep ep;
459 struct m66592 *m66592;
460
461 struct list_head queue;
462 unsigned busy:1;
463 unsigned internal_ccpl:1; /* use only control */
464
465 /* this member can able to after m66592_enable */
466 unsigned use_dma:1;
467 u16 pipenum;
468 u16 type;
469 const struct usb_endpoint_descriptor *desc;
470 /* register address */
471 unsigned long fifoaddr;
472 unsigned long fifosel;
473 unsigned long fifoctr;
474 unsigned long fifotrn;
475 unsigned long pipectr;
476 };
477
478 struct m66592 {
479 spinlock_t lock;
480 void __iomem *reg;
481 #ifdef CONFIG_HAVE_CLK
482 struct clk *clk;
483 #endif
484 struct m66592_platdata *pdata;
485 unsigned long irq_trigger;
486
487 struct usb_gadget gadget;
488 struct usb_gadget_driver *driver;
489
490 struct m66592_ep ep[M66592_MAX_NUM_PIPE];
491 struct m66592_ep *pipenum2ep[M66592_MAX_NUM_PIPE];
492 struct m66592_ep *epaddr2ep[16];
493
494 struct usb_request *ep0_req; /* for internal request */
495 __le16 ep0_data; /* for internal request */
496 u16 old_vbus;
497
498 struct timer_list timer;
499
500 int scount;
501
502 int old_dvsq;
503
504 /* pipe config */
505 int bulk;
506 int interrupt;
507 int isochronous;
508 int num_dma;
509 };
510
511 #define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
512 #define m66592_to_gadget(m66592) (&m66592->gadget)
513
514 #define is_bulk_pipe(pipenum) \
515 ((pipenum >= M66592_BASE_PIPENUM_BULK) && \
516 (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK)))
517 #define is_interrupt_pipe(pipenum) \
518 ((pipenum >= M66592_BASE_PIPENUM_INT) && \
519 (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT)))
520 #define is_isoc_pipe(pipenum) \
521 ((pipenum >= M66592_BASE_PIPENUM_ISOC) && \
522 (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC)))
523
524 #define enable_irq_ready(m66592, pipenum) \
525 enable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
526 #define disable_irq_ready(m66592, pipenum) \
527 disable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
528 #define enable_irq_empty(m66592, pipenum) \
529 enable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
530 #define disable_irq_empty(m66592, pipenum) \
531 disable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
532 #define enable_irq_nrdy(m66592, pipenum) \
533 enable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
534 #define disable_irq_nrdy(m66592, pipenum) \
535 disable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
536
537 /*-------------------------------------------------------------------------*/
538 static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
539 {
540 return ioread16(m66592->reg + offset);
541 }
542
543 static inline void m66592_read_fifo(struct m66592 *m66592,
544 unsigned long offset,
545 void *buf, unsigned long len)
546 {
547 void __iomem *fifoaddr = m66592->reg + offset;
548
549 if (m66592->pdata->on_chip) {
550 len = (len + 3) / 4;
551 ioread32_rep(fifoaddr, buf, len);
552 } else {
553 len = (len + 1) / 2;
554 ioread16_rep(fifoaddr, buf, len);
555 }
556 }
557
558 static inline void m66592_write(struct m66592 *m66592, u16 val,
559 unsigned long offset)
560 {
561 iowrite16(val, m66592->reg + offset);
562 }
563
564 static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
565 unsigned long offset)
566 {
567 u16 tmp;
568 tmp = m66592_read(m66592, offset);
569 tmp = tmp & (~pat);
570 tmp = tmp | val;
571 m66592_write(m66592, tmp, offset);
572 }
573
574 #define m66592_bclr(m66592, val, offset) \
575 m66592_mdfy(m66592, 0, val, offset)
576 #define m66592_bset(m66592, val, offset) \
577 m66592_mdfy(m66592, val, 0, offset)
578
579 static inline void m66592_write_fifo(struct m66592 *m66592,
580 struct m66592_ep *ep,
581 void *buf, unsigned long len)
582 {
583 void __iomem *fifoaddr = m66592->reg + ep->fifoaddr;
584
585 if (m66592->pdata->on_chip) {
586 unsigned long count;
587 unsigned char *pb;
588 int i;
589
590 count = len / 4;
591 iowrite32_rep(fifoaddr, buf, count);
592
593 if (len & 0x00000003) {
594 pb = buf + count * 4;
595 for (i = 0; i < (len & 0x00000003); i++) {
596 if (m66592_read(m66592, M66592_CFBCFG)) /* le */
597 iowrite8(pb[i], fifoaddr + (3 - i));
598 else
599 iowrite8(pb[i], fifoaddr + i);
600 }
601 }
602 } else {
603 unsigned long odd = len & 0x0001;
604
605 len = len / 2;
606 iowrite16_rep(fifoaddr, buf, len);
607 if (odd) {
608 unsigned char *p = buf + len*2;
609 if (m66592->pdata->wr0_shorted_to_wr1)
610 m66592_bclr(m66592, M66592_MBW_16, ep->fifosel);
611 iowrite8(*p, fifoaddr);
612 if (m66592->pdata->wr0_shorted_to_wr1)
613 m66592_bset(m66592, M66592_MBW_16, ep->fifosel);
614 }
615 }
616 }
617
618 #endif /* ifndef __M66592_UDC_H__ */
619
620
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