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x86/PCI: use host bridge _CRS info on ASUS M2V-MX SE
[linux-btrfs-devel.git] / drivers / usb / gadget / pxa25x_udc.c
blobe4e59b4de25db5ff776748fa25b91bf86f0a40a2
1 /*
2 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
3 *
4 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
5 * Copyright (C) 2003 Robert Schwebel, Pengutronix
6 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
7 * Copyright (C) 2003 David Brownell
8 * Copyright (C) 2003 Joshua Wise
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26 /* #define VERBOSE_DEBUG */
27
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/ioport.h>
32 #include <linux/types.h>
33 #include <linux/errno.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/init.h>
37 #include <linux/timer.h>
38 #include <linux/list.h>
39 #include <linux/interrupt.h>
40 #include <linux/mm.h>
41 #include <linux/platform_device.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/irq.h>
44 #include <linux/clk.h>
45 #include <linux/err.h>
46 #include <linux/seq_file.h>
47 #include <linux/debugfs.h>
48 #include <linux/io.h>
49 #include <linux/prefetch.h>
50
51 #include <asm/byteorder.h>
52 #include <asm/dma.h>
53 #include <asm/gpio.h>
54 #include <asm/system.h>
55 #include <asm/mach-types.h>
56 #include <asm/unaligned.h>
57
58 #include <linux/usb/ch9.h>
59 #include <linux/usb/gadget.h>
60 #include <linux/usb/otg.h>
61
62 /*
63 * This driver is PXA25x only. Grab the right register definitions.
64 */
65 #ifdef CONFIG_ARCH_PXA
66 #include <mach/pxa25x-udc.h>
67 #endif
68
69 #ifdef CONFIG_ARCH_LUBBOCK
70 #include <mach/lubbock.h>
71 #endif
72
73 #include <asm/mach/udc_pxa2xx.h>
74
75
76 /*
77 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
78 * series processors. The UDC for the IXP 4xx series is very similar.
79 * There are fifteen endpoints, in addition to ep0.
80 *
81 * Such controller drivers work with a gadget driver. The gadget driver
82 * returns descriptors, implements configuration and data protocols used
83 * by the host to interact with this device, and allocates endpoints to
84 * the different protocol interfaces. The controller driver virtualizes
85 * usb hardware so that the gadget drivers will be more portable.
86 *
87 * This UDC hardware wants to implement a bit too much USB protocol, so
88 * it constrains the sorts of USB configuration change events that work.
89 * The errata for these chips are misleading; some "fixed" bugs from
90 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
91 *
92 * Note that the UDC hardware supports DMA (except on IXP) but that's
93 * not used here. IN-DMA (to host) is simple enough, when the data is
94 * suitably aligned (16 bytes) ... the network stack doesn't do that,
95 * other software can. OUT-DMA is buggy in most chip versions, as well
96 * as poorly designed (data toggle not automatic). So this driver won't
97 * bother using DMA. (Mostly-working IN-DMA support was available in
98 * kernels before 2.6.23, but was never enabled or well tested.)
99 */
100
101 #define DRIVER_VERSION "30-June-2007"
102 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
103
104
105 static const char driver_name [] = "pxa25x_udc";
106
107 static const char ep0name [] = "ep0";
108
109
110 #ifdef CONFIG_ARCH_IXP4XX
111
112 /* cpu-specific register addresses are compiled in to this code */
113 #ifdef CONFIG_ARCH_PXA
114 #error "Can't configure both IXP and PXA"
115 #endif
116
117 /* IXP doesn't yet support <linux/clk.h> */
118 #define clk_get(dev,name) NULL
119 #define clk_enable(clk) do { } while (0)
120 #define clk_disable(clk) do { } while (0)
121 #define clk_put(clk) do { } while (0)
122
123 #endif
124
125 #include "pxa25x_udc.h"
126
127
128 #ifdef CONFIG_USB_PXA25X_SMALL
129 #define SIZE_STR " (small)"
130 #else
131 #define SIZE_STR ""
132 #endif
133
134 /* ---------------------------------------------------------------------------
135 * endpoint related parts of the api to the usb controller hardware,
136 * used by gadget driver; and the inner talker-to-hardware core.
137 * ---------------------------------------------------------------------------
138 */
139
140 static void pxa25x_ep_fifo_flush (struct usb_ep *ep);
141 static void nuke (struct pxa25x_ep *, int status);
142
143 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
144 static void pullup_off(void)
145 {
146 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
147 int off_level = mach->gpio_pullup_inverted;
148
149 if (gpio_is_valid(mach->gpio_pullup))
150 gpio_set_value(mach->gpio_pullup, off_level);
151 else if (mach->udc_command)
152 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
153 }
154
155 static void pullup_on(void)
156 {
157 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
158 int on_level = !mach->gpio_pullup_inverted;
159
160 if (gpio_is_valid(mach->gpio_pullup))
161 gpio_set_value(mach->gpio_pullup, on_level);
162 else if (mach->udc_command)
163 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
164 }
165
166 static void pio_irq_enable(int bEndpointAddress)
167 {
168 bEndpointAddress &= 0xf;
169 if (bEndpointAddress < 8)
170 UICR0 &= ~(1 << bEndpointAddress);
171 else {
172 bEndpointAddress -= 8;
173 UICR1 &= ~(1 << bEndpointAddress);
174 }
175 }
176
177 static void pio_irq_disable(int bEndpointAddress)
178 {
179 bEndpointAddress &= 0xf;
180 if (bEndpointAddress < 8)
181 UICR0 |= 1 << bEndpointAddress;
182 else {
183 bEndpointAddress -= 8;
184 UICR1 |= 1 << bEndpointAddress;
185 }
186 }
187
188 /* The UDCCR reg contains mask and interrupt status bits,
189 * so using '|=' isn't safe as it may ack an interrupt.
190 */
191 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
192
193 static inline void udc_set_mask_UDCCR(int mask)
194 {
195 UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
196 }
197
198 static inline void udc_clear_mask_UDCCR(int mask)
199 {
200 UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
201 }
202
203 static inline void udc_ack_int_UDCCR(int mask)
204 {
205 /* udccr contains the bits we dont want to change */
206 __u32 udccr = UDCCR & UDCCR_MASK_BITS;
207
208 UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
209 }
210
211 /*
212 * endpoint enable/disable
213 *
214 * we need to verify the descriptors used to enable endpoints. since pxa25x
215 * endpoint configurations are fixed, and are pretty much always enabled,
216 * there's not a lot to manage here.
217 *
218 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
219 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
220 * for a single interface (with only the default altsetting) and for gadget
221 * drivers that don't halt endpoints (not reset by set_interface). that also
222 * means that if you use ISO, you must violate the USB spec rule that all
223 * iso endpoints must be in non-default altsettings.
224 */
225 static int pxa25x_ep_enable (struct usb_ep *_ep,
226 const struct usb_endpoint_descriptor *desc)
227 {
228 struct pxa25x_ep *ep;
229 struct pxa25x_udc *dev;
230
231 ep = container_of (_ep, struct pxa25x_ep, ep);
232 if (!_ep || !desc || ep->desc || _ep->name == ep0name
233 || desc->bDescriptorType != USB_DT_ENDPOINT
234 || ep->bEndpointAddress != desc->bEndpointAddress
235 || ep->fifo_size < le16_to_cpu
236 (desc->wMaxPacketSize)) {
237 DMSG("%s, bad ep or descriptor\n", __func__);
238 return -EINVAL;
239 }
240
241 /* xfer types must match, except that interrupt ~= bulk */
242 if (ep->bmAttributes != desc->bmAttributes
243 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
244 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
245 DMSG("%s, %s type mismatch\n", __func__, _ep->name);
246 return -EINVAL;
247 }
248
249 /* hardware _could_ do smaller, but driver doesn't */
250 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
251 && le16_to_cpu (desc->wMaxPacketSize)
252 != BULK_FIFO_SIZE)
253 || !desc->wMaxPacketSize) {
254 DMSG("%s, bad %s maxpacket\n", __func__, _ep->name);
255 return -ERANGE;
256 }
257
258 dev = ep->dev;
259 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
260 DMSG("%s, bogus device state\n", __func__);
261 return -ESHUTDOWN;
262 }
263
264 ep->desc = desc;
265 ep->stopped = 0;
266 ep->pio_irqs = 0;
267 ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
268
269 /* flush fifo (mostly for OUT buffers) */
270 pxa25x_ep_fifo_flush (_ep);
271
272 /* ... reset halt state too, if we could ... */
273
274 DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
275 return 0;
276 }
277
278 static int pxa25x_ep_disable (struct usb_ep *_ep)
279 {
280 struct pxa25x_ep *ep;
281 unsigned long flags;
282
283 ep = container_of (_ep, struct pxa25x_ep, ep);
284 if (!_ep || !ep->desc) {
285 DMSG("%s, %s not enabled\n", __func__,
286 _ep ? ep->ep.name : NULL);
287 return -EINVAL;
288 }
289 local_irq_save(flags);
290
291 nuke (ep, -ESHUTDOWN);
292
293 /* flush fifo (mostly for IN buffers) */
294 pxa25x_ep_fifo_flush (_ep);
295
296 ep->desc = NULL;
297 ep->stopped = 1;
298
299 local_irq_restore(flags);
300 DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
301 return 0;
302 }
303
304 /*-------------------------------------------------------------------------*/
305
306 /* for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers
307 * must still pass correctly initialized endpoints, since other controller
308 * drivers may care about how it's currently set up (dma issues etc).
309 */
310
311 /*
312 * pxa25x_ep_alloc_request - allocate a request data structure
313 */
314 static struct usb_request *
315 pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
316 {
317 struct pxa25x_request *req;
318
319 req = kzalloc(sizeof(*req), gfp_flags);
320 if (!req)
321 return NULL;
322
323 INIT_LIST_HEAD (&req->queue);
324 return &req->req;
325 }
326
327
328 /*
329 * pxa25x_ep_free_request - deallocate a request data structure
330 */
331 static void
332 pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
333 {
334 struct pxa25x_request *req;
335
336 req = container_of (_req, struct pxa25x_request, req);
337 WARN_ON(!list_empty (&req->queue));
338 kfree(req);
339 }
340
341 /*-------------------------------------------------------------------------*/
342
343 /*
344 * done - retire a request; caller blocked irqs
345 */
346 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
347 {
348 unsigned stopped = ep->stopped;
349
350 list_del_init(&req->queue);
351
352 if (likely (req->req.status == -EINPROGRESS))
353 req->req.status = status;
354 else
355 status = req->req.status;
356
357 if (status && status != -ESHUTDOWN)
358 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
359 ep->ep.name, &req->req, status,
360 req->req.actual, req->req.length);
361
362 /* don't modify queue heads during completion callback */
363 ep->stopped = 1;
364 req->req.complete(&ep->ep, &req->req);
365 ep->stopped = stopped;
366 }
367
368
369 static inline void ep0_idle (struct pxa25x_udc *dev)
370 {
371 dev->ep0state = EP0_IDLE;
372 }
373
374 static int
375 write_packet(volatile u32 *uddr, struct pxa25x_request *req, unsigned max)
376 {
377 u8 *buf;
378 unsigned length, count;
379
380 buf = req->req.buf + req->req.actual;
381 prefetch(buf);
382
383 /* how big will this packet be? */
384 length = min(req->req.length - req->req.actual, max);
385 req->req.actual += length;
386
387 count = length;
388 while (likely(count--))
389 *uddr = *buf++;
390
391 return length;
392 }
393
394 /*
395 * write to an IN endpoint fifo, as many packets as possible.
396 * irqs will use this to write the rest later.
397 * caller guarantees at least one packet buffer is ready (or a zlp).
398 */
399 static int
400 write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
401 {
402 unsigned max;
403
404 max = le16_to_cpu(ep->desc->wMaxPacketSize);
405 do {
406 unsigned count;
407 int is_last, is_short;
408
409 count = write_packet(ep->reg_uddr, req, max);
410
411 /* last packet is usually short (or a zlp) */
412 if (unlikely (count != max))
413 is_last = is_short = 1;
414 else {
415 if (likely(req->req.length != req->req.actual)
416 || req->req.zero)
417 is_last = 0;
418 else
419 is_last = 1;
420 /* interrupt/iso maxpacket may not fill the fifo */
421 is_short = unlikely (max < ep->fifo_size);
422 }
423
424 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
425 ep->ep.name, count,
426 is_last ? "/L" : "", is_short ? "/S" : "",
427 req->req.length - req->req.actual, req);
428
429 /* let loose that packet. maybe try writing another one,
430 * double buffering might work. TSP, TPC, and TFS
431 * bit values are the same for all normal IN endpoints.
432 */
433 *ep->reg_udccs = UDCCS_BI_TPC;
434 if (is_short)
435 *ep->reg_udccs = UDCCS_BI_TSP;
436
437 /* requests complete when all IN data is in the FIFO */
438 if (is_last) {
439 done (ep, req, 0);
440 if (list_empty(&ep->queue))
441 pio_irq_disable (ep->bEndpointAddress);
442 return 1;
443 }
444
445 // TODO experiment: how robust can fifo mode tweaking be?
446 // double buffering is off in the default fifo mode, which
447 // prevents TFS from being set here.
448
449 } while (*ep->reg_udccs & UDCCS_BI_TFS);
450 return 0;
451 }
452
453 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
454 * ep0 data stage. these chips want very simple state transitions.
455 */
456 static inline
457 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
458 {
459 UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
460 USIR0 = USIR0_IR0;
461 dev->req_pending = 0;
462 DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
463 __func__, tag, UDCCS0, flags);
464 }
465
466 static int
467 write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
468 {
469 unsigned count;
470 int is_short;
471
472 count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
473 ep->dev->stats.write.bytes += count;
474
475 /* last packet "must be" short (or a zlp) */
476 is_short = (count != EP0_FIFO_SIZE);
477
478 DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
479 req->req.length - req->req.actual, req);
480
481 if (unlikely (is_short)) {
482 if (ep->dev->req_pending)
483 ep0start(ep->dev, UDCCS0_IPR, "short IN");
484 else
485 UDCCS0 = UDCCS0_IPR;
486
487 count = req->req.length;
488 done (ep, req, 0);
489 ep0_idle(ep->dev);
490 #ifndef CONFIG_ARCH_IXP4XX
491 #if 1
492 /* This seems to get rid of lost status irqs in some cases:
493 * host responds quickly, or next request involves config
494 * change automagic, or should have been hidden, or ...
495 *
496 * FIXME get rid of all udelays possible...
497 */
498 if (count >= EP0_FIFO_SIZE) {
499 count = 100;
500 do {
501 if ((UDCCS0 & UDCCS0_OPR) != 0) {
502 /* clear OPR, generate ack */
503 UDCCS0 = UDCCS0_OPR;
504 break;
505 }
506 count--;
507 udelay(1);
508 } while (count);
509 }
510 #endif
511 #endif
512 } else if (ep->dev->req_pending)
513 ep0start(ep->dev, 0, "IN");
514 return is_short;
515 }
516
517
518 /*
519 * read_fifo - unload packet(s) from the fifo we use for usb OUT
520 * transfers and put them into the request. caller should have made
521 * sure there's at least one packet ready.
522 *
523 * returns true if the request completed because of short packet or the
524 * request buffer having filled (and maybe overran till end-of-packet).
525 */
526 static int
527 read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
528 {
529 for (;;) {
530 u32 udccs;
531 u8 *buf;
532 unsigned bufferspace, count, is_short;
533
534 /* make sure there's a packet in the FIFO.
535 * UDCCS_{BO,IO}_RPC are all the same bit value.
536 * UDCCS_{BO,IO}_RNE are all the same bit value.
537 */
538 udccs = *ep->reg_udccs;
539 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
540 break;
541 buf = req->req.buf + req->req.actual;
542 prefetchw(buf);
543 bufferspace = req->req.length - req->req.actual;
544
545 /* read all bytes from this packet */
546 if (likely (udccs & UDCCS_BO_RNE)) {
547 count = 1 + (0x0ff & *ep->reg_ubcr);
548 req->req.actual += min (count, bufferspace);
549 } else /* zlp */
550 count = 0;
551 is_short = (count < ep->ep.maxpacket);
552 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
553 ep->ep.name, udccs, count,
554 is_short ? "/S" : "",
555 req, req->req.actual, req->req.length);
556 while (likely (count-- != 0)) {
557 u8 byte = (u8) *ep->reg_uddr;
558
559 if (unlikely (bufferspace == 0)) {
560 /* this happens when the driver's buffer
561 * is smaller than what the host sent.
562 * discard the extra data.
563 */
564 if (req->req.status != -EOVERFLOW)
565 DMSG("%s overflow %d\n",
566 ep->ep.name, count);
567 req->req.status = -EOVERFLOW;
568 } else {
569 *buf++ = byte;
570 bufferspace--;
571 }
572 }
573 *ep->reg_udccs = UDCCS_BO_RPC;
574 /* RPC/RSP/RNE could now reflect the other packet buffer */
575
576 /* iso is one request per packet */
577 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
578 if (udccs & UDCCS_IO_ROF)
579 req->req.status = -EHOSTUNREACH;
580 /* more like "is_done" */
581 is_short = 1;
582 }
583
584 /* completion */
585 if (is_short || req->req.actual == req->req.length) {
586 done (ep, req, 0);
587 if (list_empty(&ep->queue))
588 pio_irq_disable (ep->bEndpointAddress);
589 return 1;
590 }
591
592 /* finished that packet. the next one may be waiting... */
593 }
594 return 0;
595 }
596
597 /*
598 * special ep0 version of the above. no UBCR0 or double buffering; status
599 * handshaking is magic. most device protocols don't need control-OUT.
600 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
601 * protocols do use them.
602 */
603 static int
604 read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
605 {
606 u8 *buf, byte;
607 unsigned bufferspace;
608
609 buf = req->req.buf + req->req.actual;
610 bufferspace = req->req.length - req->req.actual;
611
612 while (UDCCS0 & UDCCS0_RNE) {
613 byte = (u8) UDDR0;
614
615 if (unlikely (bufferspace == 0)) {
616 /* this happens when the driver's buffer
617 * is smaller than what the host sent.
618 * discard the extra data.
619 */
620 if (req->req.status != -EOVERFLOW)
621 DMSG("%s overflow\n", ep->ep.name);
622 req->req.status = -EOVERFLOW;
623 } else {
624 *buf++ = byte;
625 req->req.actual++;
626 bufferspace--;
627 }
628 }
629
630 UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
631
632 /* completion */
633 if (req->req.actual >= req->req.length)
634 return 1;
635
636 /* finished that packet. the next one may be waiting... */
637 return 0;
638 }
639
640 /*-------------------------------------------------------------------------*/
641
642 static int
643 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
644 {
645 struct pxa25x_request *req;
646 struct pxa25x_ep *ep;
647 struct pxa25x_udc *dev;
648 unsigned long flags;
649
650 req = container_of(_req, struct pxa25x_request, req);
651 if (unlikely (!_req || !_req->complete || !_req->buf
652 || !list_empty(&req->queue))) {
653 DMSG("%s, bad params\n", __func__);
654 return -EINVAL;
655 }
656
657 ep = container_of(_ep, struct pxa25x_ep, ep);
658 if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
659 DMSG("%s, bad ep\n", __func__);
660 return -EINVAL;
661 }
662
663 dev = ep->dev;
664 if (unlikely (!dev->driver
665 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
666 DMSG("%s, bogus device state\n", __func__);
667 return -ESHUTDOWN;
668 }
669
670 /* iso is always one packet per request, that's the only way
671 * we can report per-packet status. that also helps with dma.
672 */
673 if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
674 && req->req.length > le16_to_cpu
675 (ep->desc->wMaxPacketSize)))
676 return -EMSGSIZE;
677
678 DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
679 _ep->name, _req, _req->length, _req->buf);
680
681 local_irq_save(flags);
682
683 _req->status = -EINPROGRESS;
684 _req->actual = 0;
685
686 /* kickstart this i/o queue? */
687 if (list_empty(&ep->queue) && !ep->stopped) {
688 if (ep->desc == NULL/* ep0 */) {
689 unsigned length = _req->length;
690
691 switch (dev->ep0state) {
692 case EP0_IN_DATA_PHASE:
693 dev->stats.write.ops++;
694 if (write_ep0_fifo(ep, req))
695 req = NULL;
696 break;
697
698 case EP0_OUT_DATA_PHASE:
699 dev->stats.read.ops++;
700 /* messy ... */
701 if (dev->req_config) {
702 DBG(DBG_VERBOSE, "ep0 config ack%s\n",
703 dev->has_cfr ? "" : " raced");
704 if (dev->has_cfr)
705 UDCCFR = UDCCFR_AREN|UDCCFR_ACM
706 |UDCCFR_MB1;
707 done(ep, req, 0);
708 dev->ep0state = EP0_END_XFER;
709 local_irq_restore (flags);
710 return 0;
711 }
712 if (dev->req_pending)
713 ep0start(dev, UDCCS0_IPR, "OUT");
714 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
715 && read_ep0_fifo(ep, req))) {
716 ep0_idle(dev);
717 done(ep, req, 0);
718 req = NULL;
719 }
720 break;
721
722 default:
723 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
724 local_irq_restore (flags);
725 return -EL2HLT;
726 }
727 /* can the FIFO can satisfy the request immediately? */
728 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
729 if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0
730 && write_fifo(ep, req))
731 req = NULL;
732 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
733 && read_fifo(ep, req)) {
734 req = NULL;
735 }
736
737 if (likely (req && ep->desc))
738 pio_irq_enable(ep->bEndpointAddress);
739 }
740
741 /* pio or dma irq handler advances the queue. */
742 if (likely(req != NULL))
743 list_add_tail(&req->queue, &ep->queue);
744 local_irq_restore(flags);
745
746 return 0;
747 }
748
749
750 /*
751 * nuke - dequeue ALL requests
752 */
753 static void nuke(struct pxa25x_ep *ep, int status)
754 {
755 struct pxa25x_request *req;
756
757 /* called with irqs blocked */
758 while (!list_empty(&ep->queue)) {
759 req = list_entry(ep->queue.next,
760 struct pxa25x_request,
761 queue);
762 done(ep, req, status);
763 }
764 if (ep->desc)
765 pio_irq_disable (ep->bEndpointAddress);
766 }
767
768
769 /* dequeue JUST ONE request */
770 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
771 {
772 struct pxa25x_ep *ep;
773 struct pxa25x_request *req;
774 unsigned long flags;
775
776 ep = container_of(_ep, struct pxa25x_ep, ep);
777 if (!_ep || ep->ep.name == ep0name)
778 return -EINVAL;
779
780 local_irq_save(flags);
781
782 /* make sure it's actually queued on this endpoint */
783 list_for_each_entry (req, &ep->queue, queue) {
784 if (&req->req == _req)
785 break;
786 }
787 if (&req->req != _req) {
788 local_irq_restore(flags);
789 return -EINVAL;
790 }
791
792 done(ep, req, -ECONNRESET);
793
794 local_irq_restore(flags);
795 return 0;
796 }
797
798 /*-------------------------------------------------------------------------*/
799
800 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
801 {
802 struct pxa25x_ep *ep;
803 unsigned long flags;
804
805 ep = container_of(_ep, struct pxa25x_ep, ep);
806 if (unlikely (!_ep
807 || (!ep->desc && ep->ep.name != ep0name))
808 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
809 DMSG("%s, bad ep\n", __func__);
810 return -EINVAL;
811 }
812 if (value == 0) {
813 /* this path (reset toggle+halt) is needed to implement
814 * SET_INTERFACE on normal hardware. but it can't be
815 * done from software on the PXA UDC, and the hardware
816 * forgets to do it as part of SET_INTERFACE automagic.
817 */
818 DMSG("only host can clear %s halt\n", _ep->name);
819 return -EROFS;
820 }
821
822 local_irq_save(flags);
823
824 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
825 && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
826 || !list_empty(&ep->queue))) {
827 local_irq_restore(flags);
828 return -EAGAIN;
829 }
830
831 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
832 *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
833
834 /* ep0 needs special care */
835 if (!ep->desc) {
836 start_watchdog(ep->dev);
837 ep->dev->req_pending = 0;
838 ep->dev->ep0state = EP0_STALL;
839
840 /* and bulk/intr endpoints like dropping stalls too */
841 } else {
842 unsigned i;
843 for (i = 0; i < 1000; i += 20) {
844 if (*ep->reg_udccs & UDCCS_BI_SST)
845 break;
846 udelay(20);
847 }
848 }
849 local_irq_restore(flags);
850
851 DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
852 return 0;
853 }
854
855 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
856 {
857 struct pxa25x_ep *ep;
858
859 ep = container_of(_ep, struct pxa25x_ep, ep);
860 if (!_ep) {
861 DMSG("%s, bad ep\n", __func__);
862 return -ENODEV;
863 }
864 /* pxa can't report unclaimed bytes from IN fifos */
865 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
866 return -EOPNOTSUPP;
867 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
868 || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
869 return 0;
870 else
871 return (*ep->reg_ubcr & 0xfff) + 1;
872 }
873
874 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
875 {
876 struct pxa25x_ep *ep;
877
878 ep = container_of(_ep, struct pxa25x_ep, ep);
879 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
880 DMSG("%s, bad ep\n", __func__);
881 return;
882 }
883
884 /* toggle and halt bits stay unchanged */
885
886 /* for OUT, just read and discard the FIFO contents. */
887 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
888 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
889 (void) *ep->reg_uddr;
890 return;
891 }
892
893 /* most IN status is the same, but ISO can't stall */
894 *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
895 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
896 ? 0 : UDCCS_BI_SST);
897 }
898
899
900 static struct usb_ep_ops pxa25x_ep_ops = {
901 .enable = pxa25x_ep_enable,
902 .disable = pxa25x_ep_disable,
903
904 .alloc_request = pxa25x_ep_alloc_request,
905 .free_request = pxa25x_ep_free_request,
906
907 .queue = pxa25x_ep_queue,
908 .dequeue = pxa25x_ep_dequeue,
909
910 .set_halt = pxa25x_ep_set_halt,
911 .fifo_status = pxa25x_ep_fifo_status,
912 .fifo_flush = pxa25x_ep_fifo_flush,
913 };
914
915
916 /* ---------------------------------------------------------------------------
917 * device-scoped parts of the api to the usb controller hardware
918 * ---------------------------------------------------------------------------
919 */
920
921 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
922 {
923 return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
924 }
925
926 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
927 {
928 /* host may not have enabled remote wakeup */
929 if ((UDCCS0 & UDCCS0_DRWF) == 0)
930 return -EHOSTUNREACH;
931 udc_set_mask_UDCCR(UDCCR_RSM);
932 return 0;
933 }
934
935 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
936 static void udc_enable (struct pxa25x_udc *);
937 static void udc_disable(struct pxa25x_udc *);
938
939 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
940 * in active use.
941 */
942 static int pullup(struct pxa25x_udc *udc)
943 {
944 int is_active = udc->vbus && udc->pullup && !udc->suspended;
945 DMSG("%s\n", is_active ? "active" : "inactive");
946 if (is_active) {
947 if (!udc->active) {
948 udc->active = 1;
949 /* Enable clock for USB device */
950 clk_enable(udc->clk);
951 udc_enable(udc);
952 }
953 } else {
954 if (udc->active) {
955 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
956 DMSG("disconnect %s\n", udc->driver
957 ? udc->driver->driver.name
958 : "(no driver)");
959 stop_activity(udc, udc->driver);
960 }
961 udc_disable(udc);
962 /* Disable clock for USB device */
963 clk_disable(udc->clk);
964 udc->active = 0;
965 }
966
967 }
968 return 0;
969 }
970
971 /* VBUS reporting logically comes from a transceiver */
972 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
973 {
974 struct pxa25x_udc *udc;
975
976 udc = container_of(_gadget, struct pxa25x_udc, gadget);
977 udc->vbus = is_active;
978 DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
979 pullup(udc);
980 return 0;
981 }
982
983 /* drivers may have software control over D+ pullup */
984 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
985 {
986 struct pxa25x_udc *udc;
987
988 udc = container_of(_gadget, struct pxa25x_udc, gadget);
989
990 /* not all boards support pullup control */
991 if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
992 return -EOPNOTSUPP;
993
994 udc->pullup = (is_active != 0);
995 pullup(udc);
996 return 0;
997 }
998
999 /* boards may consume current from VBUS, up to 100-500mA based on config.
1000 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1001 * violate USB specs.
1002 */
1003 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1004 {
1005 struct pxa25x_udc *udc;
1006
1007 udc = container_of(_gadget, struct pxa25x_udc, gadget);
1008
1009 if (udc->transceiver)
1010 return otg_set_power(udc->transceiver, mA);
1011 return -EOPNOTSUPP;
1012 }
1013
1014 static int pxa25x_start(struct usb_gadget_driver *driver,
1015 int (*bind)(struct usb_gadget *));
1016 static int pxa25x_stop(struct usb_gadget_driver *driver);
1017
1018 static const struct usb_gadget_ops pxa25x_udc_ops = {
1019 .get_frame = pxa25x_udc_get_frame,
1020 .wakeup = pxa25x_udc_wakeup,
1021 .vbus_session = pxa25x_udc_vbus_session,
1022 .pullup = pxa25x_udc_pullup,
1023 .vbus_draw = pxa25x_udc_vbus_draw,
1024 .start = pxa25x_start,
1025 .stop = pxa25x_stop,
1026 };
1027
1028 /*-------------------------------------------------------------------------*/
1029
1030 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1031
1032 static int
1033 udc_seq_show(struct seq_file *m, void *_d)
1034 {
1035 struct pxa25x_udc *dev = m->private;
1036 unsigned long flags;
1037 int i;
1038 u32 tmp;
1039
1040 local_irq_save(flags);
1041
1042 /* basic device status */
1043 seq_printf(m, DRIVER_DESC "\n"
1044 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1045 driver_name, DRIVER_VERSION SIZE_STR "(pio)",
1046 dev->driver ? dev->driver->driver.name : "(none)",
1047 dev->gadget.speed == USB_SPEED_FULL ? "full speed" : "disconnected");
1048
1049 /* registers for device and ep0 */
1050 seq_printf(m,
1051 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1052 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1053
1054 tmp = UDCCR;
1055 seq_printf(m,
1056 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1057 (tmp & UDCCR_REM) ? " rem" : "",
1058 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1059 (tmp & UDCCR_SRM) ? " srm" : "",
1060 (tmp & UDCCR_SUSIR) ? " susir" : "",
1061 (tmp & UDCCR_RESIR) ? " resir" : "",
1062 (tmp & UDCCR_RSM) ? " rsm" : "",
1063 (tmp & UDCCR_UDA) ? " uda" : "",
1064 (tmp & UDCCR_UDE) ? " ude" : "");
1065
1066 tmp = UDCCS0;
1067 seq_printf(m,
1068 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1069 (tmp & UDCCS0_SA) ? " sa" : "",
1070 (tmp & UDCCS0_RNE) ? " rne" : "",
1071 (tmp & UDCCS0_FST) ? " fst" : "",
1072 (tmp & UDCCS0_SST) ? " sst" : "",
1073 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1074 (tmp & UDCCS0_FTF) ? " ftf" : "",
1075 (tmp & UDCCS0_IPR) ? " ipr" : "",
1076 (tmp & UDCCS0_OPR) ? " opr" : "");
1077
1078 if (dev->has_cfr) {
1079 tmp = UDCCFR;
1080 seq_printf(m,
1081 "udccfr %02X =%s%s\n", tmp,
1082 (tmp & UDCCFR_AREN) ? " aren" : "",
1083 (tmp & UDCCFR_ACM) ? " acm" : "");
1084 }
1085
1086 if (dev->gadget.speed != USB_SPEED_FULL || !dev->driver)
1087 goto done;
1088
1089 seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1090 dev->stats.write.bytes, dev->stats.write.ops,
1091 dev->stats.read.bytes, dev->stats.read.ops,
1092 dev->stats.irqs);
1093
1094 /* dump endpoint queues */
1095 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1096 struct pxa25x_ep *ep = &dev->ep [i];
1097 struct pxa25x_request *req;
1098
1099 if (i != 0) {
1100 const struct usb_endpoint_descriptor *desc;
1101
1102 desc = ep->desc;
1103 if (!desc)
1104 continue;
1105 tmp = *dev->ep [i].reg_udccs;
1106 seq_printf(m,
1107 "%s max %d %s udccs %02x irqs %lu\n",
1108 ep->ep.name, le16_to_cpu(desc->wMaxPacketSize),
1109 "pio", tmp, ep->pio_irqs);
1110 /* TODO translate all five groups of udccs bits! */
1111
1112 } else /* ep0 should only have one transfer queued */
1113 seq_printf(m, "ep0 max 16 pio irqs %lu\n",
1114 ep->pio_irqs);
1115
1116 if (list_empty(&ep->queue)) {
1117 seq_printf(m, "\t(nothing queued)\n");
1118 continue;
1119 }
1120 list_for_each_entry(req, &ep->queue, queue) {
1121 seq_printf(m,
1122 "\treq %p len %d/%d buf %p\n",
1123 &req->req, req->req.actual,
1124 req->req.length, req->req.buf);
1125 }
1126 }
1127
1128 done:
1129 local_irq_restore(flags);
1130 return 0;
1131 }
1132
1133 static int
1134 udc_debugfs_open(struct inode *inode, struct file *file)
1135 {
1136 return single_open(file, udc_seq_show, inode->i_private);
1137 }
1138
1139 static const struct file_operations debug_fops = {
1140 .open = udc_debugfs_open,
1141 .read = seq_read,
1142 .llseek = seq_lseek,
1143 .release = single_release,
1144 .owner = THIS_MODULE,
1145 };
1146
1147 #define create_debug_files(dev) \
1148 do { \
1149 dev->debugfs_udc = debugfs_create_file(dev->gadget.name, \
1150 S_IRUGO, NULL, dev, &debug_fops); \
1151 } while (0)
1152 #define remove_debug_files(dev) \
1153 do { \
1154 if (dev->debugfs_udc) \
1155 debugfs_remove(dev->debugfs_udc); \
1156 } while (0)
1157
1158 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
1159
1160 #define create_debug_files(dev) do {} while (0)
1161 #define remove_debug_files(dev) do {} while (0)
1162
1163 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
1164
1165 /*-------------------------------------------------------------------------*/
1166
1167 /*
1168 * udc_disable - disable USB device controller
1169 */
1170 static void udc_disable(struct pxa25x_udc *dev)
1171 {
1172 /* block all irqs */
1173 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1174 UICR0 = UICR1 = 0xff;
1175 UFNRH = UFNRH_SIM;
1176
1177 /* if hardware supports it, disconnect from usb */
1178 pullup_off();
1179
1180 udc_clear_mask_UDCCR(UDCCR_UDE);
1181
1182 ep0_idle (dev);
1183 dev->gadget.speed = USB_SPEED_UNKNOWN;
1184 }
1185
1186
1187 /*
1188 * udc_reinit - initialize software state
1189 */
1190 static void udc_reinit(struct pxa25x_udc *dev)
1191 {
1192 u32 i;
1193
1194 /* device/ep0 records init */
1195 INIT_LIST_HEAD (&dev->gadget.ep_list);
1196 INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1197 dev->ep0state = EP0_IDLE;
1198
1199 /* basic endpoint records init */
1200 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1201 struct pxa25x_ep *ep = &dev->ep[i];
1202
1203 if (i != 0)
1204 list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1205
1206 ep->desc = NULL;
1207 ep->stopped = 0;
1208 INIT_LIST_HEAD (&ep->queue);
1209 ep->pio_irqs = 0;
1210 }
1211
1212 /* the rest was statically initialized, and is read-only */
1213 }
1214
1215 /* until it's enabled, this UDC should be completely invisible
1216 * to any USB host.
1217 */
1218 static void udc_enable (struct pxa25x_udc *dev)
1219 {
1220 udc_clear_mask_UDCCR(UDCCR_UDE);
1221
1222 /* try to clear these bits before we enable the udc */
1223 udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1224
1225 ep0_idle(dev);
1226 dev->gadget.speed = USB_SPEED_UNKNOWN;
1227 dev->stats.irqs = 0;
1228
1229 /*
1230 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1231 * - enable UDC
1232 * - if RESET is already in progress, ack interrupt
1233 * - unmask reset interrupt
1234 */
1235 udc_set_mask_UDCCR(UDCCR_UDE);
1236 if (!(UDCCR & UDCCR_UDA))
1237 udc_ack_int_UDCCR(UDCCR_RSTIR);
1238
1239 if (dev->has_cfr /* UDC_RES2 is defined */) {
1240 /* pxa255 (a0+) can avoid a set_config race that could
1241 * prevent gadget drivers from configuring correctly
1242 */
1243 UDCCFR = UDCCFR_ACM | UDCCFR_MB1;
1244 } else {
1245 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1246 * which could result in missing packets and interrupts.
1247 * supposedly one bit per endpoint, controlling whether it
1248 * double buffers or not; ACM/AREN bits fit into the holes.
1249 * zero bits (like USIR0_IRx) disable double buffering.
1250 */
1251 UDC_RES1 = 0x00;
1252 UDC_RES2 = 0x00;
1253 }
1254
1255 /* enable suspend/resume and reset irqs */
1256 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1257
1258 /* enable ep0 irqs */
1259 UICR0 &= ~UICR0_IM0;
1260
1261 /* if hardware supports it, pullup D+ and wait for reset */
1262 pullup_on();
1263 }
1264
1265
1266 /* when a driver is successfully registered, it will receive
1267 * control requests including set_configuration(), which enables
1268 * non-control requests. then usb traffic follows until a
1269 * disconnect is reported. then a host may connect again, or
1270 * the driver might get unbound.
1271 */
1272 static int pxa25x_start(struct usb_gadget_driver *driver,
1273 int (*bind)(struct usb_gadget *))
1274 {
1275 struct pxa25x_udc *dev = the_controller;
1276 int retval;
1277
1278 if (!driver
1279 || driver->speed < USB_SPEED_FULL
1280 || !bind
1281 || !driver->disconnect
1282 || !driver->setup)
1283 return -EINVAL;
1284 if (!dev)
1285 return -ENODEV;
1286 if (dev->driver)
1287 return -EBUSY;
1288
1289 /* first hook up the driver ... */
1290 dev->driver = driver;
1291 dev->gadget.dev.driver = &driver->driver;
1292 dev->pullup = 1;
1293
1294 retval = device_add (&dev->gadget.dev);
1295 if (retval) {
1296 fail:
1297 dev->driver = NULL;
1298 dev->gadget.dev.driver = NULL;
1299 return retval;
1300 }
1301 retval = bind(&dev->gadget);
1302 if (retval) {
1303 DMSG("bind to driver %s --> error %d\n",
1304 driver->driver.name, retval);
1305 device_del (&dev->gadget.dev);
1306 goto fail;
1307 }
1308
1309 /* ... then enable host detection and ep0; and we're ready
1310 * for set_configuration as well as eventual disconnect.
1311 */
1312 DMSG("registered gadget driver '%s'\n", driver->driver.name);
1313
1314 /* connect to bus through transceiver */
1315 if (dev->transceiver) {
1316 retval = otg_set_peripheral(dev->transceiver, &dev->gadget);
1317 if (retval) {
1318 DMSG("can't bind to transceiver\n");
1319 if (driver->unbind)
1320 driver->unbind(&dev->gadget);
1321 goto bind_fail;
1322 }
1323 }
1324
1325 pullup(dev);
1326 dump_state(dev);
1327 return 0;
1328 bind_fail:
1329 return retval;
1330 }
1331
1332 static void
1333 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1334 {
1335 int i;
1336
1337 /* don't disconnect drivers more than once */
1338 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1339 driver = NULL;
1340 dev->gadget.speed = USB_SPEED_UNKNOWN;
1341
1342 /* prevent new request submissions, kill any outstanding requests */
1343 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1344 struct pxa25x_ep *ep = &dev->ep[i];
1345
1346 ep->stopped = 1;
1347 nuke(ep, -ESHUTDOWN);
1348 }
1349 del_timer_sync(&dev->timer);
1350
1351 /* report disconnect; the driver is already quiesced */
1352 if (driver)
1353 driver->disconnect(&dev->gadget);
1354
1355 /* re-init driver-visible data structures */
1356 udc_reinit(dev);
1357 }
1358
1359 static int pxa25x_stop(struct usb_gadget_driver *driver)
1360 {
1361 struct pxa25x_udc *dev = the_controller;
1362
1363 if (!dev)
1364 return -ENODEV;
1365 if (!driver || driver != dev->driver || !driver->unbind)
1366 return -EINVAL;
1367
1368 local_irq_disable();
1369 dev->pullup = 0;
1370 pullup(dev);
1371 stop_activity(dev, driver);
1372 local_irq_enable();
1373
1374 if (dev->transceiver)
1375 (void) otg_set_peripheral(dev->transceiver, NULL);
1376
1377 driver->unbind(&dev->gadget);
1378 dev->gadget.dev.driver = NULL;
1379 dev->driver = NULL;
1380
1381 device_del (&dev->gadget.dev);
1382
1383 DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1384 dump_state(dev);
1385 return 0;
1386 }
1387
1388 /*-------------------------------------------------------------------------*/
1389
1390 #ifdef CONFIG_ARCH_LUBBOCK
1391
1392 /* Lubbock has separate connect and disconnect irqs. More typical designs
1393 * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1394 */
1395
1396 static irqreturn_t
1397 lubbock_vbus_irq(int irq, void *_dev)
1398 {
1399 struct pxa25x_udc *dev = _dev;
1400 int vbus;
1401
1402 dev->stats.irqs++;
1403 switch (irq) {
1404 case LUBBOCK_USB_IRQ:
1405 vbus = 1;
1406 disable_irq(LUBBOCK_USB_IRQ);
1407 enable_irq(LUBBOCK_USB_DISC_IRQ);
1408 break;
1409 case LUBBOCK_USB_DISC_IRQ:
1410 vbus = 0;
1411 disable_irq(LUBBOCK_USB_DISC_IRQ);
1412 enable_irq(LUBBOCK_USB_IRQ);
1413 break;
1414 default:
1415 return IRQ_NONE;
1416 }
1417
1418 pxa25x_udc_vbus_session(&dev->gadget, vbus);
1419 return IRQ_HANDLED;
1420 }
1421
1422 #endif
1423
1424
1425 /*-------------------------------------------------------------------------*/
1426
1427 static inline void clear_ep_state (struct pxa25x_udc *dev)
1428 {
1429 unsigned i;
1430
1431 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1432 * fifos, and pending transactions mustn't be continued in any case.
1433 */
1434 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1435 nuke(&dev->ep[i], -ECONNABORTED);
1436 }
1437
1438 static void udc_watchdog(unsigned long _dev)
1439 {
1440 struct pxa25x_udc *dev = (void *)_dev;
1441
1442 local_irq_disable();
1443 if (dev->ep0state == EP0_STALL
1444 && (UDCCS0 & UDCCS0_FST) == 0
1445 && (UDCCS0 & UDCCS0_SST) == 0) {
1446 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1447 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1448 start_watchdog(dev);
1449 }
1450 local_irq_enable();
1451 }
1452
1453 static void handle_ep0 (struct pxa25x_udc *dev)
1454 {
1455 u32 udccs0 = UDCCS0;
1456 struct pxa25x_ep *ep = &dev->ep [0];
1457 struct pxa25x_request *req;
1458 union {
1459 struct usb_ctrlrequest r;
1460 u8 raw [8];
1461 u32 word [2];
1462 } u;
1463
1464 if (list_empty(&ep->queue))
1465 req = NULL;
1466 else
1467 req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1468
1469 /* clear stall status */
1470 if (udccs0 & UDCCS0_SST) {
1471 nuke(ep, -EPIPE);
1472 UDCCS0 = UDCCS0_SST;
1473 del_timer(&dev->timer);
1474 ep0_idle(dev);
1475 }
1476
1477 /* previous request unfinished? non-error iff back-to-back ... */
1478 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1479 nuke(ep, 0);
1480 del_timer(&dev->timer);
1481 ep0_idle(dev);
1482 }
1483
1484 switch (dev->ep0state) {
1485 case EP0_IDLE:
1486 /* late-breaking status? */
1487 udccs0 = UDCCS0;
1488
1489 /* start control request? */
1490 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1491 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1492 int i;
1493
1494 nuke (ep, -EPROTO);
1495
1496 /* read SETUP packet */
1497 for (i = 0; i < 8; i++) {
1498 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1499 bad_setup:
1500 DMSG("SETUP %d!\n", i);
1501 goto stall;
1502 }
1503 u.raw [i] = (u8) UDDR0;
1504 }
1505 if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1506 goto bad_setup;
1507
1508 got_setup:
1509 DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1510 u.r.bRequestType, u.r.bRequest,
1511 le16_to_cpu(u.r.wValue),
1512 le16_to_cpu(u.r.wIndex),
1513 le16_to_cpu(u.r.wLength));
1514
1515 /* cope with automagic for some standard requests. */
1516 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1517 == USB_TYPE_STANDARD;
1518 dev->req_config = 0;
1519 dev->req_pending = 1;
1520 switch (u.r.bRequest) {
1521 /* hardware restricts gadget drivers here! */
1522 case USB_REQ_SET_CONFIGURATION:
1523 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1524 /* reflect hardware's automagic
1525 * up to the gadget driver.
1526 */
1527 config_change:
1528 dev->req_config = 1;
1529 clear_ep_state(dev);
1530 /* if !has_cfr, there's no synch
1531 * else use AREN (later) not SA|OPR
1532 * USIR0_IR0 acts edge sensitive
1533 */
1534 }
1535 break;
1536 /* ... and here, even more ... */
1537 case USB_REQ_SET_INTERFACE:
1538 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1539 /* udc hardware is broken by design:
1540 * - altsetting may only be zero;
1541 * - hw resets all interfaces' eps;
1542 * - ep reset doesn't include halt(?).
1543 */
1544 DMSG("broken set_interface (%d/%d)\n",
1545 le16_to_cpu(u.r.wIndex),
1546 le16_to_cpu(u.r.wValue));
1547 goto config_change;
1548 }
1549 break;
1550 /* hardware was supposed to hide this */
1551 case USB_REQ_SET_ADDRESS:
1552 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1553 ep0start(dev, 0, "address");
1554 return;
1555 }
1556 break;
1557 }
1558
1559 if (u.r.bRequestType & USB_DIR_IN)
1560 dev->ep0state = EP0_IN_DATA_PHASE;
1561 else
1562 dev->ep0state = EP0_OUT_DATA_PHASE;
1563
1564 i = dev->driver->setup(&dev->gadget, &u.r);
1565 if (i < 0) {
1566 /* hardware automagic preventing STALL... */
1567 if (dev->req_config) {
1568 /* hardware sometimes neglects to tell
1569 * tell us about config change events,
1570 * so later ones may fail...
1571 */
1572 WARNING("config change %02x fail %d?\n",
1573 u.r.bRequest, i);
1574 return;
1575 /* TODO experiment: if has_cfr,
1576 * hardware didn't ACK; maybe we
1577 * could actually STALL!
1578 */
1579 }
1580 DBG(DBG_VERBOSE, "protocol STALL, "
1581 "%02x err %d\n", UDCCS0, i);
1582 stall:
1583 /* the watchdog timer helps deal with cases
1584 * where udc seems to clear FST wrongly, and
1585 * then NAKs instead of STALLing.
1586 */
1587 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1588 start_watchdog(dev);
1589 dev->ep0state = EP0_STALL;
1590
1591 /* deferred i/o == no response yet */
1592 } else if (dev->req_pending) {
1593 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1594 || dev->req_std || u.r.wLength))
1595 ep0start(dev, 0, "defer");
1596 else
1597 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1598 }
1599
1600 /* expect at least one data or status stage irq */
1601 return;
1602
1603 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1604 == (UDCCS0_OPR|UDCCS0_SA))) {
1605 unsigned i;
1606
1607 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1608 * still observed on a pxa255 a0.
1609 */
1610 DBG(DBG_VERBOSE, "e131\n");
1611 nuke(ep, -EPROTO);
1612
1613 /* read SETUP data, but don't trust it too much */
1614 for (i = 0; i < 8; i++)
1615 u.raw [i] = (u8) UDDR0;
1616 if ((u.r.bRequestType & USB_RECIP_MASK)
1617 > USB_RECIP_OTHER)
1618 goto stall;
1619 if (u.word [0] == 0 && u.word [1] == 0)
1620 goto stall;
1621 goto got_setup;
1622 } else {
1623 /* some random early IRQ:
1624 * - we acked FST
1625 * - IPR cleared
1626 * - OPR got set, without SA (likely status stage)
1627 */
1628 UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1629 }
1630 break;
1631 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1632 if (udccs0 & UDCCS0_OPR) {
1633 UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1634 DBG(DBG_VERBOSE, "ep0in premature status\n");
1635 if (req)
1636 done(ep, req, 0);
1637 ep0_idle(dev);
1638 } else /* irq was IPR clearing */ {
1639 if (req) {
1640 /* this IN packet might finish the request */
1641 (void) write_ep0_fifo(ep, req);
1642 } /* else IN token before response was written */
1643 }
1644 break;
1645 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1646 if (udccs0 & UDCCS0_OPR) {
1647 if (req) {
1648 /* this OUT packet might finish the request */
1649 if (read_ep0_fifo(ep, req))
1650 done(ep, req, 0);
1651 /* else more OUT packets expected */
1652 } /* else OUT token before read was issued */
1653 } else /* irq was IPR clearing */ {
1654 DBG(DBG_VERBOSE, "ep0out premature status\n");
1655 if (req)
1656 done(ep, req, 0);
1657 ep0_idle(dev);
1658 }
1659 break;
1660 case EP0_END_XFER:
1661 if (req)
1662 done(ep, req, 0);
1663 /* ack control-IN status (maybe in-zlp was skipped)
1664 * also appears after some config change events.
1665 */
1666 if (udccs0 & UDCCS0_OPR)
1667 UDCCS0 = UDCCS0_OPR;
1668 ep0_idle(dev);
1669 break;
1670 case EP0_STALL:
1671 UDCCS0 = UDCCS0_FST;
1672 break;
1673 }
1674 USIR0 = USIR0_IR0;
1675 }
1676
1677 static void handle_ep(struct pxa25x_ep *ep)
1678 {
1679 struct pxa25x_request *req;
1680 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1681 int completed;
1682 u32 udccs, tmp;
1683
1684 do {
1685 completed = 0;
1686 if (likely (!list_empty(&ep->queue)))
1687 req = list_entry(ep->queue.next,
1688 struct pxa25x_request, queue);
1689 else
1690 req = NULL;
1691
1692 // TODO check FST handling
1693
1694 udccs = *ep->reg_udccs;
1695 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1696 tmp = UDCCS_BI_TUR;
1697 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1698 tmp |= UDCCS_BI_SST;
1699 tmp &= udccs;
1700 if (likely (tmp))
1701 *ep->reg_udccs = tmp;
1702 if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1703 completed = write_fifo(ep, req);
1704
1705 } else { /* irq from RPC (or for ISO, ROF) */
1706 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1707 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1708 else
1709 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1710 tmp &= udccs;
1711 if (likely(tmp))
1712 *ep->reg_udccs = tmp;
1713
1714 /* fifos can hold packets, ready for reading... */
1715 if (likely(req)) {
1716 completed = read_fifo(ep, req);
1717 } else
1718 pio_irq_disable (ep->bEndpointAddress);
1719 }
1720 ep->pio_irqs++;
1721 } while (completed);
1722 }
1723
1724 /*
1725 * pxa25x_udc_irq - interrupt handler
1726 *
1727 * avoid delays in ep0 processing. the control handshaking isn't always
1728 * under software control (pxa250c0 and the pxa255 are better), and delays
1729 * could cause usb protocol errors.
1730 */
1731 static irqreturn_t
1732 pxa25x_udc_irq(int irq, void *_dev)
1733 {
1734 struct pxa25x_udc *dev = _dev;
1735 int handled;
1736
1737 dev->stats.irqs++;
1738 do {
1739 u32 udccr = UDCCR;
1740
1741 handled = 0;
1742
1743 /* SUSpend Interrupt Request */
1744 if (unlikely(udccr & UDCCR_SUSIR)) {
1745 udc_ack_int_UDCCR(UDCCR_SUSIR);
1746 handled = 1;
1747 DBG(DBG_VERBOSE, "USB suspend\n");
1748
1749 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1750 && dev->driver
1751 && dev->driver->suspend)
1752 dev->driver->suspend(&dev->gadget);
1753 ep0_idle (dev);
1754 }
1755
1756 /* RESume Interrupt Request */
1757 if (unlikely(udccr & UDCCR_RESIR)) {
1758 udc_ack_int_UDCCR(UDCCR_RESIR);
1759 handled = 1;
1760 DBG(DBG_VERBOSE, "USB resume\n");
1761
1762 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1763 && dev->driver
1764 && dev->driver->resume)
1765 dev->driver->resume(&dev->gadget);
1766 }
1767
1768 /* ReSeT Interrupt Request - USB reset */
1769 if (unlikely(udccr & UDCCR_RSTIR)) {
1770 udc_ack_int_UDCCR(UDCCR_RSTIR);
1771 handled = 1;
1772
1773 if ((UDCCR & UDCCR_UDA) == 0) {
1774 DBG(DBG_VERBOSE, "USB reset start\n");
1775
1776 /* reset driver and endpoints,
1777 * in case that's not yet done
1778 */
1779 stop_activity (dev, dev->driver);
1780
1781 } else {
1782 DBG(DBG_VERBOSE, "USB reset end\n");
1783 dev->gadget.speed = USB_SPEED_FULL;
1784 memset(&dev->stats, 0, sizeof dev->stats);
1785 /* driver and endpoints are still reset */
1786 }
1787
1788 } else {
1789 u32 usir0 = USIR0 & ~UICR0;
1790 u32 usir1 = USIR1 & ~UICR1;
1791 int i;
1792
1793 if (unlikely (!usir0 && !usir1))
1794 continue;
1795
1796 DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
1797
1798 /* control traffic */
1799 if (usir0 & USIR0_IR0) {
1800 dev->ep[0].pio_irqs++;
1801 handle_ep0(dev);
1802 handled = 1;
1803 }
1804
1805 /* endpoint data transfers */
1806 for (i = 0; i < 8; i++) {
1807 u32 tmp = 1 << i;
1808
1809 if (i && (usir0 & tmp)) {
1810 handle_ep(&dev->ep[i]);
1811 USIR0 |= tmp;
1812 handled = 1;
1813 }
1814 #ifndef CONFIG_USB_PXA25X_SMALL
1815 if (usir1 & tmp) {
1816 handle_ep(&dev->ep[i+8]);
1817 USIR1 |= tmp;
1818 handled = 1;
1819 }
1820 #endif
1821 }
1822 }
1823
1824 /* we could also ask for 1 msec SOF (SIR) interrupts */
1825
1826 } while (handled);
1827 return IRQ_HANDLED;
1828 }
1829
1830 /*-------------------------------------------------------------------------*/
1831
1832 static void nop_release (struct device *dev)
1833 {
1834 DMSG("%s %s\n", __func__, dev_name(dev));
1835 }
1836
1837 /* this uses load-time allocation and initialization (instead of
1838 * doing it at run-time) to save code, eliminate fault paths, and
1839 * be more obviously correct.
1840 */
1841 static struct pxa25x_udc memory = {
1842 .gadget = {
1843 .ops = &pxa25x_udc_ops,
1844 .ep0 = &memory.ep[0].ep,
1845 .name = driver_name,
1846 .dev = {
1847 .init_name = "gadget",
1848 .release = nop_release,
1849 },
1850 },
1851
1852 /* control endpoint */
1853 .ep[0] = {
1854 .ep = {
1855 .name = ep0name,
1856 .ops = &pxa25x_ep_ops,
1857 .maxpacket = EP0_FIFO_SIZE,
1858 },
1859 .dev = &memory,
1860 .reg_udccs = &UDCCS0,
1861 .reg_uddr = &UDDR0,
1862 },
1863
1864 /* first group of endpoints */
1865 .ep[1] = {
1866 .ep = {
1867 .name = "ep1in-bulk",
1868 .ops = &pxa25x_ep_ops,
1869 .maxpacket = BULK_FIFO_SIZE,
1870 },
1871 .dev = &memory,
1872 .fifo_size = BULK_FIFO_SIZE,
1873 .bEndpointAddress = USB_DIR_IN | 1,
1874 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1875 .reg_udccs = &UDCCS1,
1876 .reg_uddr = &UDDR1,
1877 },
1878 .ep[2] = {
1879 .ep = {
1880 .name = "ep2out-bulk",
1881 .ops = &pxa25x_ep_ops,
1882 .maxpacket = BULK_FIFO_SIZE,
1883 },
1884 .dev = &memory,
1885 .fifo_size = BULK_FIFO_SIZE,
1886 .bEndpointAddress = 2,
1887 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1888 .reg_udccs = &UDCCS2,
1889 .reg_ubcr = &UBCR2,
1890 .reg_uddr = &UDDR2,
1891 },
1892 #ifndef CONFIG_USB_PXA25X_SMALL
1893 .ep[3] = {
1894 .ep = {
1895 .name = "ep3in-iso",
1896 .ops = &pxa25x_ep_ops,
1897 .maxpacket = ISO_FIFO_SIZE,
1898 },
1899 .dev = &memory,
1900 .fifo_size = ISO_FIFO_SIZE,
1901 .bEndpointAddress = USB_DIR_IN | 3,
1902 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1903 .reg_udccs = &UDCCS3,
1904 .reg_uddr = &UDDR3,
1905 },
1906 .ep[4] = {
1907 .ep = {
1908 .name = "ep4out-iso",
1909 .ops = &pxa25x_ep_ops,
1910 .maxpacket = ISO_FIFO_SIZE,
1911 },
1912 .dev = &memory,
1913 .fifo_size = ISO_FIFO_SIZE,
1914 .bEndpointAddress = 4,
1915 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1916 .reg_udccs = &UDCCS4,
1917 .reg_ubcr = &UBCR4,
1918 .reg_uddr = &UDDR4,
1919 },
1920 .ep[5] = {
1921 .ep = {
1922 .name = "ep5in-int",
1923 .ops = &pxa25x_ep_ops,
1924 .maxpacket = INT_FIFO_SIZE,
1925 },
1926 .dev = &memory,
1927 .fifo_size = INT_FIFO_SIZE,
1928 .bEndpointAddress = USB_DIR_IN | 5,
1929 .bmAttributes = USB_ENDPOINT_XFER_INT,
1930 .reg_udccs = &UDCCS5,
1931 .reg_uddr = &UDDR5,
1932 },
1933
1934 /* second group of endpoints */
1935 .ep[6] = {
1936 .ep = {
1937 .name = "ep6in-bulk",
1938 .ops = &pxa25x_ep_ops,
1939 .maxpacket = BULK_FIFO_SIZE,
1940 },
1941 .dev = &memory,
1942 .fifo_size = BULK_FIFO_SIZE,
1943 .bEndpointAddress = USB_DIR_IN | 6,
1944 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1945 .reg_udccs = &UDCCS6,
1946 .reg_uddr = &UDDR6,
1947 },
1948 .ep[7] = {
1949 .ep = {
1950 .name = "ep7out-bulk",
1951 .ops = &pxa25x_ep_ops,
1952 .maxpacket = BULK_FIFO_SIZE,
1953 },
1954 .dev = &memory,
1955 .fifo_size = BULK_FIFO_SIZE,
1956 .bEndpointAddress = 7,
1957 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1958 .reg_udccs = &UDCCS7,
1959 .reg_ubcr = &UBCR7,
1960 .reg_uddr = &UDDR7,
1961 },
1962 .ep[8] = {
1963 .ep = {
1964 .name = "ep8in-iso",
1965 .ops = &pxa25x_ep_ops,
1966 .maxpacket = ISO_FIFO_SIZE,
1967 },
1968 .dev = &memory,
1969 .fifo_size = ISO_FIFO_SIZE,
1970 .bEndpointAddress = USB_DIR_IN | 8,
1971 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1972 .reg_udccs = &UDCCS8,
1973 .reg_uddr = &UDDR8,
1974 },
1975 .ep[9] = {
1976 .ep = {
1977 .name = "ep9out-iso",
1978 .ops = &pxa25x_ep_ops,
1979 .maxpacket = ISO_FIFO_SIZE,
1980 },
1981 .dev = &memory,
1982 .fifo_size = ISO_FIFO_SIZE,
1983 .bEndpointAddress = 9,
1984 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1985 .reg_udccs = &UDCCS9,
1986 .reg_ubcr = &UBCR9,
1987 .reg_uddr = &UDDR9,
1988 },
1989 .ep[10] = {
1990 .ep = {
1991 .name = "ep10in-int",
1992 .ops = &pxa25x_ep_ops,
1993 .maxpacket = INT_FIFO_SIZE,
1994 },
1995 .dev = &memory,
1996 .fifo_size = INT_FIFO_SIZE,
1997 .bEndpointAddress = USB_DIR_IN | 10,
1998 .bmAttributes = USB_ENDPOINT_XFER_INT,
1999 .reg_udccs = &UDCCS10,
2000 .reg_uddr = &UDDR10,
2001 },
2002
2003 /* third group of endpoints */
2004 .ep[11] = {
2005 .ep = {
2006 .name = "ep11in-bulk",
2007 .ops = &pxa25x_ep_ops,
2008 .maxpacket = BULK_FIFO_SIZE,
2009 },
2010 .dev = &memory,
2011 .fifo_size = BULK_FIFO_SIZE,
2012 .bEndpointAddress = USB_DIR_IN | 11,
2013 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2014 .reg_udccs = &UDCCS11,
2015 .reg_uddr = &UDDR11,
2016 },
2017 .ep[12] = {
2018 .ep = {
2019 .name = "ep12out-bulk",
2020 .ops = &pxa25x_ep_ops,
2021 .maxpacket = BULK_FIFO_SIZE,
2022 },
2023 .dev = &memory,
2024 .fifo_size = BULK_FIFO_SIZE,
2025 .bEndpointAddress = 12,
2026 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2027 .reg_udccs = &UDCCS12,
2028 .reg_ubcr = &UBCR12,
2029 .reg_uddr = &UDDR12,
2030 },
2031 .ep[13] = {
2032 .ep = {
2033 .name = "ep13in-iso",
2034 .ops = &pxa25x_ep_ops,
2035 .maxpacket = ISO_FIFO_SIZE,
2036 },
2037 .dev = &memory,
2038 .fifo_size = ISO_FIFO_SIZE,
2039 .bEndpointAddress = USB_DIR_IN | 13,
2040 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2041 .reg_udccs = &UDCCS13,
2042 .reg_uddr = &UDDR13,
2043 },
2044 .ep[14] = {
2045 .ep = {
2046 .name = "ep14out-iso",
2047 .ops = &pxa25x_ep_ops,
2048 .maxpacket = ISO_FIFO_SIZE,
2049 },
2050 .dev = &memory,
2051 .fifo_size = ISO_FIFO_SIZE,
2052 .bEndpointAddress = 14,
2053 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
2054 .reg_udccs = &UDCCS14,
2055 .reg_ubcr = &UBCR14,
2056 .reg_uddr = &UDDR14,
2057 },
2058 .ep[15] = {
2059 .ep = {
2060 .name = "ep15in-int",
2061 .ops = &pxa25x_ep_ops,
2062 .maxpacket = INT_FIFO_SIZE,
2063 },
2064 .dev = &memory,
2065 .fifo_size = INT_FIFO_SIZE,
2066 .bEndpointAddress = USB_DIR_IN | 15,
2067 .bmAttributes = USB_ENDPOINT_XFER_INT,
2068 .reg_udccs = &UDCCS15,
2069 .reg_uddr = &UDDR15,
2070 },
2071 #endif /* !CONFIG_USB_PXA25X_SMALL */
2072 };
2073
2074 #define CP15R0_VENDOR_MASK 0xffffe000
2075
2076 #if defined(CONFIG_ARCH_PXA)
2077 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2078
2079 #elif defined(CONFIG_ARCH_IXP4XX)
2080 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2081
2082 #endif
2083
2084 #define CP15R0_PROD_MASK 0x000003f0
2085 #define PXA25x 0x00000100 /* and PXA26x */
2086 #define PXA210 0x00000120
2087
2088 #define CP15R0_REV_MASK 0x0000000f
2089
2090 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2091
2092 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2093 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2094 #define PXA250_B2 0x00000104
2095 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2096 #define PXA250_B0 0x00000102
2097 #define PXA250_A1 0x00000101
2098 #define PXA250_A0 0x00000100
2099
2100 #define PXA210_C0 0x00000125
2101 #define PXA210_B2 0x00000124
2102 #define PXA210_B1 0x00000123
2103 #define PXA210_B0 0x00000122
2104 #define IXP425_A0 0x000001c1
2105 #define IXP425_B0 0x000001f1
2106 #define IXP465_AD 0x00000200
2107
2108 /*
2109 * probe - binds to the platform device
2110 */
2111 static int __init pxa25x_udc_probe(struct platform_device *pdev)
2112 {
2113 struct pxa25x_udc *dev = &memory;
2114 int retval, irq;
2115 u32 chiprev;
2116
2117 /* insist on Intel/ARM/XScale */
2118 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2119 if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2120 pr_err("%s: not XScale!\n", driver_name);
2121 return -ENODEV;
2122 }
2123
2124 /* trigger chiprev-specific logic */
2125 switch (chiprev & CP15R0_PRODREV_MASK) {
2126 #if defined(CONFIG_ARCH_PXA)
2127 case PXA255_A0:
2128 dev->has_cfr = 1;
2129 break;
2130 case PXA250_A0:
2131 case PXA250_A1:
2132 /* A0/A1 "not released"; ep 13, 15 unusable */
2133 /* fall through */
2134 case PXA250_B2: case PXA210_B2:
2135 case PXA250_B1: case PXA210_B1:
2136 case PXA250_B0: case PXA210_B0:
2137 /* OUT-DMA is broken ... */
2138 /* fall through */
2139 case PXA250_C0: case PXA210_C0:
2140 break;
2141 #elif defined(CONFIG_ARCH_IXP4XX)
2142 case IXP425_A0:
2143 case IXP425_B0:
2144 case IXP465_AD:
2145 dev->has_cfr = 1;
2146 break;
2147 #endif
2148 default:
2149 pr_err("%s: unrecognized processor: %08x\n",
2150 driver_name, chiprev);
2151 /* iop3xx, ixp4xx, ... */
2152 return -ENODEV;
2153 }
2154
2155 irq = platform_get_irq(pdev, 0);
2156 if (irq < 0)
2157 return -ENODEV;
2158
2159 dev->clk = clk_get(&pdev->dev, NULL);
2160 if (IS_ERR(dev->clk)) {
2161 retval = PTR_ERR(dev->clk);
2162 goto err_clk;
2163 }
2164
2165 pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
2166 dev->has_cfr ? "" : " (!cfr)",
2167 SIZE_STR "(pio)"
2168 );
2169
2170 /* other non-static parts of init */
2171 dev->dev = &pdev->dev;
2172 dev->mach = pdev->dev.platform_data;
2173
2174 dev->transceiver = otg_get_transceiver();
2175
2176 if (gpio_is_valid(dev->mach->gpio_pullup)) {
2177 if ((retval = gpio_request(dev->mach->gpio_pullup,
2178 "pca25x_udc GPIO PULLUP"))) {
2179 dev_dbg(&pdev->dev,
2180 "can't get pullup gpio %d, err: %d\n",
2181 dev->mach->gpio_pullup, retval);
2182 goto err_gpio_pullup;
2183 }
2184 gpio_direction_output(dev->mach->gpio_pullup, 0);
2185 }
2186
2187 init_timer(&dev->timer);
2188 dev->timer.function = udc_watchdog;
2189 dev->timer.data = (unsigned long) dev;
2190
2191 device_initialize(&dev->gadget.dev);
2192 dev->gadget.dev.parent = &pdev->dev;
2193 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2194
2195 the_controller = dev;
2196 platform_set_drvdata(pdev, dev);
2197
2198 udc_disable(dev);
2199 udc_reinit(dev);
2200
2201 dev->vbus = 0;
2202
2203 /* irq setup after old hardware state is cleaned up */
2204 retval = request_irq(irq, pxa25x_udc_irq,
2205 IRQF_DISABLED, driver_name, dev);
2206 if (retval != 0) {
2207 pr_err("%s: can't get irq %d, err %d\n",
2208 driver_name, irq, retval);
2209 goto err_irq1;
2210 }
2211 dev->got_irq = 1;
2212
2213 #ifdef CONFIG_ARCH_LUBBOCK
2214 if (machine_is_lubbock()) {
2215 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2216 lubbock_vbus_irq,
2217 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2218 driver_name, dev);
2219 if (retval != 0) {
2220 pr_err("%s: can't get irq %i, err %d\n",
2221 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2222 goto err_irq_lub;
2223 }
2224 retval = request_irq(LUBBOCK_USB_IRQ,
2225 lubbock_vbus_irq,
2226 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
2227 driver_name, dev);
2228 if (retval != 0) {
2229 pr_err("%s: can't get irq %i, err %d\n",
2230 driver_name, LUBBOCK_USB_IRQ, retval);
2231 goto lubbock_fail0;
2232 }
2233 } else
2234 #endif
2235 create_debug_files(dev);
2236
2237 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
2238 if (!retval)
2239 return retval;
2240
2241 remove_debug_files(dev);
2242 #ifdef CONFIG_ARCH_LUBBOCK
2243 lubbock_fail0:
2244 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2245 err_irq_lub:
2246 free_irq(irq, dev);
2247 #endif
2248 err_irq1:
2249 if (gpio_is_valid(dev->mach->gpio_pullup))
2250 gpio_free(dev->mach->gpio_pullup);
2251 err_gpio_pullup:
2252 if (dev->transceiver) {
2253 otg_put_transceiver(dev->transceiver);
2254 dev->transceiver = NULL;
2255 }
2256 clk_put(dev->clk);
2257 err_clk:
2258 return retval;
2259 }
2260
2261 static void pxa25x_udc_shutdown(struct platform_device *_dev)
2262 {
2263 pullup_off();
2264 }
2265
2266 static int __exit pxa25x_udc_remove(struct platform_device *pdev)
2267 {
2268 struct pxa25x_udc *dev = platform_get_drvdata(pdev);
2269
2270 usb_del_gadget_udc(&dev->gadget);
2271 if (dev->driver)
2272 return -EBUSY;
2273
2274 dev->pullup = 0;
2275 pullup(dev);
2276
2277 remove_debug_files(dev);
2278
2279 if (dev->got_irq) {
2280 free_irq(platform_get_irq(pdev, 0), dev);
2281 dev->got_irq = 0;
2282 }
2283 #ifdef CONFIG_ARCH_LUBBOCK
2284 if (machine_is_lubbock()) {
2285 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2286 free_irq(LUBBOCK_USB_IRQ, dev);
2287 }
2288 #endif
2289 if (gpio_is_valid(dev->mach->gpio_pullup))
2290 gpio_free(dev->mach->gpio_pullup);
2291
2292 clk_put(dev->clk);
2293
2294 if (dev->transceiver) {
2295 otg_put_transceiver(dev->transceiver);
2296 dev->transceiver = NULL;
2297 }
2298
2299 platform_set_drvdata(pdev, NULL);
2300 the_controller = NULL;
2301 return 0;
2302 }
2303
2304 /*-------------------------------------------------------------------------*/
2305
2306 #ifdef CONFIG_PM
2307
2308 /* USB suspend (controlled by the host) and system suspend (controlled
2309 * by the PXA) don't necessarily work well together. If USB is active,
2310 * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2311 * mode, or any deeper PM saving state.
2312 *
2313 * For now, we punt and forcibly disconnect from the USB host when PXA
2314 * enters any suspend state. While we're disconnected, we always disable
2315 * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2316 * Boards without software pullup control shouldn't use those states.
2317 * VBUS IRQs should probably be ignored so that the PXA device just acts
2318 * "dead" to USB hosts until system resume.
2319 */
2320 static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state)
2321 {
2322 struct pxa25x_udc *udc = platform_get_drvdata(dev);
2323 unsigned long flags;
2324
2325 if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
2326 WARNING("USB host won't detect disconnect!\n");
2327 udc->suspended = 1;
2328
2329 local_irq_save(flags);
2330 pullup(udc);
2331 local_irq_restore(flags);
2332
2333 return 0;
2334 }
2335
2336 static int pxa25x_udc_resume(struct platform_device *dev)
2337 {
2338 struct pxa25x_udc *udc = platform_get_drvdata(dev);
2339 unsigned long flags;
2340
2341 udc->suspended = 0;
2342 local_irq_save(flags);
2343 pullup(udc);
2344 local_irq_restore(flags);
2345
2346 return 0;
2347 }
2348
2349 #else
2350 #define pxa25x_udc_suspend NULL
2351 #define pxa25x_udc_resume NULL
2352 #endif
2353
2354 /*-------------------------------------------------------------------------*/
2355
2356 static struct platform_driver udc_driver = {
2357 .shutdown = pxa25x_udc_shutdown,
2358 .remove = __exit_p(pxa25x_udc_remove),
2359 .suspend = pxa25x_udc_suspend,
2360 .resume = pxa25x_udc_resume,
2361 .driver = {
2362 .owner = THIS_MODULE,
2363 .name = "pxa25x-udc",
2364 },
2365 };
2366
2367 static int __init udc_init(void)
2368 {
2369 pr_info("%s: version %s\n", driver_name, DRIVER_VERSION);
2370 return platform_driver_probe(&udc_driver, pxa25x_udc_probe);
2371 }
2372 module_init(udc_init);
2373
2374 static void __exit udc_exit(void)
2375 {
2376 platform_driver_unregister(&udc_driver);
2377 }
2378 module_exit(udc_exit);
2379
2380 MODULE_DESCRIPTION(DRIVER_DESC);
2381 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2382 MODULE_LICENSE("GPL");
2383 MODULE_ALIAS("platform:pxa25x-udc");
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