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x86/PCI: use host bridge _CRS info on ASUS M2V-MX SE
[linux-btrfs-devel.git] / drivers / usb / host / isp1760-hcd.c
blob840beda66dd94aa378c506918ffad093e1ba4052
1 /*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
12 *
13 */
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
17 #include <linux/list.h>
18 #include <linux/usb.h>
19 #include <linux/usb/hcd.h>
20 #include <linux/debugfs.h>
21 #include <linux/uaccess.h>
22 #include <linux/io.h>
23 #include <linux/mm.h>
24 #include <asm/unaligned.h>
25 #include <asm/cacheflush.h>
26
27 #include "isp1760-hcd.h"
28
29 static struct kmem_cache *qtd_cachep;
30 static struct kmem_cache *qh_cachep;
31 static struct kmem_cache *urb_listitem_cachep;
32
33 struct isp1760_hcd {
34 u32 hcs_params;
35 spinlock_t lock;
36 struct slotinfo atl_slots[32];
37 int atl_done_map;
38 struct slotinfo int_slots[32];
39 int int_done_map;
40 struct memory_chunk memory_pool[BLOCKS];
41 struct list_head controlqhs, bulkqhs, interruptqhs;
42 int active_ptds;
43
44 /* periodic schedule support */
45 #define DEFAULT_I_TDPS 1024
46 unsigned periodic_size;
47 unsigned i_thresh;
48 unsigned long reset_done;
49 unsigned long next_statechange;
50 unsigned int devflags;
51 };
52
53 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
54 {
55 return (struct isp1760_hcd *) (hcd->hcd_priv);
56 }
57
58 /* Section 2.2 Host Controller Capability Registers */
59 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
60 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
61 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
62 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
63 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
64 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
65 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
66
67 /* Section 2.3 Host Controller Operational Registers */
68 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
69 #define CMD_RESET (1<<1) /* reset HC not bus */
70 #define CMD_RUN (1<<0) /* start/stop HC */
71 #define STS_PCD (1<<2) /* port change detect */
72 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
73
74 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
75 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
76 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
77 #define PORT_RESET (1<<8) /* reset port */
78 #define PORT_SUSPEND (1<<7) /* suspend port */
79 #define PORT_RESUME (1<<6) /* resume it */
80 #define PORT_PE (1<<2) /* port enable */
81 #define PORT_CSC (1<<1) /* connect status change */
82 #define PORT_CONNECT (1<<0) /* device connected */
83 #define PORT_RWC_BITS (PORT_CSC)
84
85 struct isp1760_qtd {
86 u8 packet_type;
87 void *data_buffer;
88 u32 payload_addr;
89
90 /* the rest is HCD-private */
91 struct list_head qtd_list;
92 struct urb *urb;
93 size_t length;
94 size_t actual_length;
95
96 /* QTD_ENQUEUED: waiting for transfer (inactive) */
97 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
98 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
99 interrupt handler may touch this qtd! */
100 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
101 /* QTD_RETIRE: transfer error/abort qtd */
102 #define QTD_ENQUEUED 0
103 #define QTD_PAYLOAD_ALLOC 1
104 #define QTD_XFER_STARTED 2
105 #define QTD_XFER_COMPLETE 3
106 #define QTD_RETIRE 4
107 u32 status;
108 };
109
110 /* Queue head, one for each active endpoint */
111 struct isp1760_qh {
112 struct list_head qh_list;
113 struct list_head qtd_list;
114 u32 toggle;
115 u32 ping;
116 int slot;
117 };
118
119 struct urb_listitem {
120 struct list_head urb_list;
121 struct urb *urb;
122 };
123
124 /*
125 * Access functions for isp176x registers (addresses 0..0x03FF).
126 */
127 static u32 reg_read32(void __iomem *base, u32 reg)
128 {
129 return readl(base + reg);
130 }
131
132 static void reg_write32(void __iomem *base, u32 reg, u32 val)
133 {
134 writel(val, base + reg);
135 }
136
137 /*
138 * Access functions for isp176x memory (offset >= 0x0400).
139 *
140 * bank_reads8() reads memory locations prefetched by an earlier write to
141 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
142 * bank optimizations, you should use the more generic mem_reads8() below.
143 *
144 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
145 * below.
146 *
147 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
148 * doesn't quite work because some people have to enforce 32-bit access
149 */
150 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
151 __u32 *dst, u32 bytes)
152 {
153 __u32 __iomem *src;
154 u32 val;
155 __u8 *src_byteptr;
156 __u8 *dst_byteptr;
157
158 src = src_base + (bank_addr | src_offset);
159
160 if (src_offset < PAYLOAD_OFFSET) {
161 while (bytes >= 4) {
162 *dst = le32_to_cpu(__raw_readl(src));
163 bytes -= 4;
164 src++;
165 dst++;
166 }
167 } else {
168 while (bytes >= 4) {
169 *dst = __raw_readl(src);
170 bytes -= 4;
171 src++;
172 dst++;
173 }
174 }
175
176 if (!bytes)
177 return;
178
179 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
180 * allocated.
181 */
182 if (src_offset < PAYLOAD_OFFSET)
183 val = le32_to_cpu(__raw_readl(src));
184 else
185 val = __raw_readl(src);
186
187 dst_byteptr = (void *) dst;
188 src_byteptr = (void *) &val;
189 while (bytes > 0) {
190 *dst_byteptr = *src_byteptr;
191 dst_byteptr++;
192 src_byteptr++;
193 bytes--;
194 }
195 }
196
197 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
198 u32 bytes)
199 {
200 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
201 ndelay(90);
202 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
203 }
204
205 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
206 __u32 const *src, u32 bytes)
207 {
208 __u32 __iomem *dst;
209
210 dst = dst_base + dst_offset;
211
212 if (dst_offset < PAYLOAD_OFFSET) {
213 while (bytes >= 4) {
214 __raw_writel(cpu_to_le32(*src), dst);
215 bytes -= 4;
216 src++;
217 dst++;
218 }
219 } else {
220 while (bytes >= 4) {
221 __raw_writel(*src, dst);
222 bytes -= 4;
223 src++;
224 dst++;
225 }
226 }
227
228 if (!bytes)
229 return;
230 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
231 * extra bytes should not be read by the HW.
232 */
233
234 if (dst_offset < PAYLOAD_OFFSET)
235 __raw_writel(cpu_to_le32(*src), dst);
236 else
237 __raw_writel(*src, dst);
238 }
239
240 /*
241 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
242 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
243 */
244 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
245 struct ptd *ptd)
246 {
247 reg_write32(base, HC_MEMORY_REG,
248 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
249 ndelay(90);
250 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
251 (void *) ptd, sizeof(*ptd));
252 }
253
254 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
255 struct ptd *ptd)
256 {
257 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
258 &ptd->dw1, 7*sizeof(ptd->dw1));
259 /* Make sure dw0 gets written last (after other dw's and after payload)
260 since it contains the enable bit */
261 wmb();
262 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
263 sizeof(ptd->dw0));
264 }
265
266
267 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
268 static void init_memory(struct isp1760_hcd *priv)
269 {
270 int i, curr;
271 u32 payload_addr;
272
273 payload_addr = PAYLOAD_OFFSET;
274 for (i = 0; i < BLOCK_1_NUM; i++) {
275 priv->memory_pool[i].start = payload_addr;
276 priv->memory_pool[i].size = BLOCK_1_SIZE;
277 priv->memory_pool[i].free = 1;
278 payload_addr += priv->memory_pool[i].size;
279 }
280
281 curr = i;
282 for (i = 0; i < BLOCK_2_NUM; i++) {
283 priv->memory_pool[curr + i].start = payload_addr;
284 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
285 priv->memory_pool[curr + i].free = 1;
286 payload_addr += priv->memory_pool[curr + i].size;
287 }
288
289 curr = i;
290 for (i = 0; i < BLOCK_3_NUM; i++) {
291 priv->memory_pool[curr + i].start = payload_addr;
292 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
293 priv->memory_pool[curr + i].free = 1;
294 payload_addr += priv->memory_pool[curr + i].size;
295 }
296
297 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
298 }
299
300 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
301 {
302 struct isp1760_hcd *priv = hcd_to_priv(hcd);
303 int i;
304
305 WARN_ON(qtd->payload_addr);
306
307 if (!qtd->length)
308 return;
309
310 for (i = 0; i < BLOCKS; i++) {
311 if (priv->memory_pool[i].size >= qtd->length &&
312 priv->memory_pool[i].free) {
313 priv->memory_pool[i].free = 0;
314 qtd->payload_addr = priv->memory_pool[i].start;
315 return;
316 }
317 }
318 }
319
320 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
321 {
322 struct isp1760_hcd *priv = hcd_to_priv(hcd);
323 int i;
324
325 if (!qtd->payload_addr)
326 return;
327
328 for (i = 0; i < BLOCKS; i++) {
329 if (priv->memory_pool[i].start == qtd->payload_addr) {
330 WARN_ON(priv->memory_pool[i].free);
331 priv->memory_pool[i].free = 1;
332 qtd->payload_addr = 0;
333 return;
334 }
335 }
336
337 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
338 __func__, qtd->payload_addr);
339 WARN_ON(1);
340 qtd->payload_addr = 0;
341 }
342
343 static int handshake(struct usb_hcd *hcd, u32 reg,
344 u32 mask, u32 done, int usec)
345 {
346 u32 result;
347
348 do {
349 result = reg_read32(hcd->regs, reg);
350 if (result == ~0)
351 return -ENODEV;
352 result &= mask;
353 if (result == done)
354 return 0;
355 udelay(1);
356 usec--;
357 } while (usec > 0);
358 return -ETIMEDOUT;
359 }
360
361 /* reset a non-running (STS_HALT == 1) controller */
362 static int ehci_reset(struct usb_hcd *hcd)
363 {
364 int retval;
365 struct isp1760_hcd *priv = hcd_to_priv(hcd);
366
367 u32 command = reg_read32(hcd->regs, HC_USBCMD);
368
369 command |= CMD_RESET;
370 reg_write32(hcd->regs, HC_USBCMD, command);
371 hcd->state = HC_STATE_HALT;
372 priv->next_statechange = jiffies;
373 retval = handshake(hcd, HC_USBCMD,
374 CMD_RESET, 0, 250 * 1000);
375 return retval;
376 }
377
378 static struct isp1760_qh *qh_alloc(gfp_t flags)
379 {
380 struct isp1760_qh *qh;
381
382 qh = kmem_cache_zalloc(qh_cachep, flags);
383 if (!qh)
384 return NULL;
385
386 INIT_LIST_HEAD(&qh->qh_list);
387 INIT_LIST_HEAD(&qh->qtd_list);
388 qh->slot = -1;
389
390 return qh;
391 }
392
393 static void qh_free(struct isp1760_qh *qh)
394 {
395 WARN_ON(!list_empty(&qh->qtd_list));
396 WARN_ON(qh->slot > -1);
397 kmem_cache_free(qh_cachep, qh);
398 }
399
400 /* one-time init, only for memory state */
401 static int priv_init(struct usb_hcd *hcd)
402 {
403 struct isp1760_hcd *priv = hcd_to_priv(hcd);
404 u32 hcc_params;
405
406 spin_lock_init(&priv->lock);
407
408 INIT_LIST_HEAD(&priv->interruptqhs);
409 INIT_LIST_HEAD(&priv->controlqhs);
410 INIT_LIST_HEAD(&priv->bulkqhs);
411
412 /*
413 * hw default: 1K periodic list heads, one per frame.
414 * periodic_size can shrink by USBCMD update if hcc_params allows.
415 */
416 priv->periodic_size = DEFAULT_I_TDPS;
417
418 /* controllers may cache some of the periodic schedule ... */
419 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
420 /* full frame cache */
421 if (HCC_ISOC_CACHE(hcc_params))
422 priv->i_thresh = 8;
423 else /* N microframes cached */
424 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
425
426 return 0;
427 }
428
429 static int isp1760_hc_setup(struct usb_hcd *hcd)
430 {
431 struct isp1760_hcd *priv = hcd_to_priv(hcd);
432 int result;
433 u32 scratch, hwmode;
434
435 /* Setup HW Mode Control: This assumes a level active-low interrupt */
436 hwmode = HW_DATA_BUS_32BIT;
437
438 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
439 hwmode &= ~HW_DATA_BUS_32BIT;
440 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
441 hwmode |= HW_ANA_DIGI_OC;
442 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
443 hwmode |= HW_DACK_POL_HIGH;
444 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
445 hwmode |= HW_DREQ_POL_HIGH;
446 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
447 hwmode |= HW_INTR_HIGH_ACT;
448 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
449 hwmode |= HW_INTR_EDGE_TRIG;
450
451 /*
452 * We have to set this first in case we're in 16-bit mode.
453 * Write it twice to ensure correct upper bits if switching
454 * to 16-bit mode.
455 */
456 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
457 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
458
459 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
460 /* Change bus pattern */
461 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
462 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
463 if (scratch != 0xdeadbabe) {
464 dev_err(hcd->self.controller, "Scratch test failed.\n");
465 return -ENODEV;
466 }
467
468 /* pre reset */
469 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
470 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
471 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
472 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
473
474 /* reset */
475 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
476 mdelay(100);
477
478 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
479 mdelay(100);
480
481 result = ehci_reset(hcd);
482 if (result)
483 return result;
484
485 /* Step 11 passed */
486
487 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
488 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
489 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
490 "analog" : "digital");
491
492 /* This is weird: at the first plug-in of a device there seems to be
493 one packet queued that never gets returned? */
494 priv->active_ptds = -1;
495
496 /* ATL reset */
497 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
498 mdelay(10);
499 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
500
501 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
502
503 /*
504 * PORT 1 Control register of the ISP1760 is the OTG control
505 * register on ISP1761. Since there is no OTG or device controller
506 * support in this driver, we use port 1 as a "normal" USB host port on
507 * both chips.
508 */
509 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
510 mdelay(10);
511
512 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
513
514 return priv_init(hcd);
515 }
516
517 static void isp1760_init_maps(struct usb_hcd *hcd)
518 {
519 /*set last maps, for iso its only 1, else 32 tds bitmap*/
520 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
521 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
522 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
523
524 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
525 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
526 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
527
528 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
529 ATL_BUF_FILL | INT_BUF_FILL);
530 }
531
532 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
533 {
534 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
535 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
536 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
537 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
538 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
539 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
540 /* step 23 passed */
541 }
542
543 static int isp1760_run(struct usb_hcd *hcd)
544 {
545 int retval;
546 u32 temp;
547 u32 command;
548 u32 chipid;
549
550 hcd->uses_new_polling = 1;
551
552 hcd->state = HC_STATE_RUNNING;
553 isp1760_enable_interrupts(hcd);
554 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
555 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
556
557 command = reg_read32(hcd->regs, HC_USBCMD);
558 command &= ~(CMD_LRESET|CMD_RESET);
559 command |= CMD_RUN;
560 reg_write32(hcd->regs, HC_USBCMD, command);
561
562 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
563 if (retval)
564 return retval;
565
566 /*
567 * XXX
568 * Spec says to write FLAG_CF as last config action, priv code grabs
569 * the semaphore while doing so.
570 */
571 down_write(&ehci_cf_port_reset_rwsem);
572 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
573
574 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
575 up_write(&ehci_cf_port_reset_rwsem);
576 if (retval)
577 return retval;
578
579 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
580 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
581 chipid & 0xffff, chipid >> 16);
582
583 /* PTD Register Init Part 2, Step 28 */
584 /* enable INTs */
585 isp1760_init_maps(hcd);
586
587 /* GRR this is run-once init(), being done every time the HC starts.
588 * So long as they're part of class devices, we can't do it init()
589 * since the class device isn't created that early.
590 */
591 return 0;
592 }
593
594 static u32 base_to_chip(u32 base)
595 {
596 return ((base - 0x400) >> 3);
597 }
598
599 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
600 {
601 struct urb *urb;
602
603 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
604 return 1;
605
606 urb = qtd->urb;
607 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
608 return (qtd->urb != urb);
609 }
610
611 /* magic numbers that can affect system performance */
612 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
613 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
614 #define EHCI_TUNE_RL_TT 0
615 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
616 #define EHCI_TUNE_MULT_TT 1
617 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
618
619 static void create_ptd_atl(struct isp1760_qh *qh,
620 struct isp1760_qtd *qtd, struct ptd *ptd)
621 {
622 u32 maxpacket;
623 u32 multi;
624 u32 rl = RL_COUNTER;
625 u32 nak = NAK_COUNTER;
626
627 memset(ptd, 0, sizeof(*ptd));
628
629 /* according to 3.6.2, max packet len can not be > 0x400 */
630 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
631 usb_pipeout(qtd->urb->pipe));
632 multi = 1 + ((maxpacket >> 11) & 0x3);
633 maxpacket &= 0x7ff;
634
635 /* DW0 */
636 ptd->dw0 = DW0_VALID_BIT;
637 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
638 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
639 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
640
641 /* DW1 */
642 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
643 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
644 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
645
646 if (usb_pipebulk(qtd->urb->pipe))
647 ptd->dw1 |= DW1_TRANS_BULK;
648 else if (usb_pipeint(qtd->urb->pipe))
649 ptd->dw1 |= DW1_TRANS_INT;
650
651 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
652 /* split transaction */
653
654 ptd->dw1 |= DW1_TRANS_SPLIT;
655 if (qtd->urb->dev->speed == USB_SPEED_LOW)
656 ptd->dw1 |= DW1_SE_USB_LOSPEED;
657
658 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
659 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
660
661 /* SE bit for Split INT transfers */
662 if (usb_pipeint(qtd->urb->pipe) &&
663 (qtd->urb->dev->speed == USB_SPEED_LOW))
664 ptd->dw1 |= 2 << 16;
665
666 rl = 0;
667 nak = 0;
668 } else {
669 ptd->dw0 |= TO_DW0_MULTI(multi);
670 if (usb_pipecontrol(qtd->urb->pipe) ||
671 usb_pipebulk(qtd->urb->pipe))
672 ptd->dw3 |= TO_DW3_PING(qh->ping);
673 }
674 /* DW2 */
675 ptd->dw2 = 0;
676 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
677 ptd->dw2 |= TO_DW2_RL(rl);
678
679 /* DW3 */
680 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
681 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
682 if (usb_pipecontrol(qtd->urb->pipe)) {
683 if (qtd->data_buffer == qtd->urb->setup_packet)
684 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
685 else if (last_qtd_of_urb(qtd, qh))
686 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
687 }
688
689 ptd->dw3 |= DW3_ACTIVE_BIT;
690 /* Cerr */
691 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
692 }
693
694 static void transform_add_int(struct isp1760_qh *qh,
695 struct isp1760_qtd *qtd, struct ptd *ptd)
696 {
697 u32 usof;
698 u32 period;
699
700 /*
701 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
702 * the algorithm from the original Philips driver code, which was
703 * pretty much used in this driver before as well, is quite horrendous
704 * and, i believe, incorrect. The code below follows the datasheet and
705 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
706 * more reliable this way (fingers crossed...).
707 */
708
709 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
710 /* urb->interval is in units of microframes (1/8 ms) */
711 period = qtd->urb->interval >> 3;
712
713 if (qtd->urb->interval > 4)
714 usof = 0x01; /* One bit set =>
715 interval 1 ms * uFrame-match */
716 else if (qtd->urb->interval > 2)
717 usof = 0x22; /* Two bits set => interval 1/2 ms */
718 else if (qtd->urb->interval > 1)
719 usof = 0x55; /* Four bits set => interval 1/4 ms */
720 else
721 usof = 0xff; /* All bits set => interval 1/8 ms */
722 } else {
723 /* urb->interval is in units of frames (1 ms) */
724 period = qtd->urb->interval;
725 usof = 0x0f; /* Execute Start Split on any of the
726 four first uFrames */
727
728 /*
729 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
730 * complete split needs to be sent. Valid only for IN." Also,
731 * "All bits can be set to one for every transfer." (p 82,
732 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
733 * that number come from? 0xff seems to work fine...
734 */
735 /* ptd->dw5 = 0x1c; */
736 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
737 }
738
739 period = period >> 1;/* Ensure equal or shorter period than requested */
740 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
741
742 ptd->dw2 |= period;
743 ptd->dw4 = usof;
744 }
745
746 static void create_ptd_int(struct isp1760_qh *qh,
747 struct isp1760_qtd *qtd, struct ptd *ptd)
748 {
749 create_ptd_atl(qh, qtd, ptd);
750 transform_add_int(qh, qtd, ptd);
751 }
752
753 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
754 __releases(priv->lock)
755 __acquires(priv->lock)
756 {
757 struct isp1760_hcd *priv = hcd_to_priv(hcd);
758
759 if (!urb->unlinked) {
760 if (urb->status == -EINPROGRESS)
761 urb->status = 0;
762 }
763
764 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
765 void *ptr;
766 for (ptr = urb->transfer_buffer;
767 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
768 ptr += PAGE_SIZE)
769 flush_dcache_page(virt_to_page(ptr));
770 }
771
772 /* complete() can reenter this HCD */
773 usb_hcd_unlink_urb_from_ep(hcd, urb);
774 spin_unlock(&priv->lock);
775 usb_hcd_giveback_urb(hcd, urb, urb->status);
776 spin_lock(&priv->lock);
777 }
778
779 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
780 u8 packet_type)
781 {
782 struct isp1760_qtd *qtd;
783
784 qtd = kmem_cache_zalloc(qtd_cachep, flags);
785 if (!qtd)
786 return NULL;
787
788 INIT_LIST_HEAD(&qtd->qtd_list);
789 qtd->urb = urb;
790 qtd->packet_type = packet_type;
791 qtd->status = QTD_ENQUEUED;
792 qtd->actual_length = 0;
793
794 return qtd;
795 }
796
797 static void qtd_free(struct isp1760_qtd *qtd)
798 {
799 WARN_ON(qtd->payload_addr);
800 kmem_cache_free(qtd_cachep, qtd);
801 }
802
803 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
804 struct slotinfo *slots, struct isp1760_qtd *qtd,
805 struct isp1760_qh *qh, struct ptd *ptd)
806 {
807 struct isp1760_hcd *priv = hcd_to_priv(hcd);
808 int skip_map;
809
810 WARN_ON((slot < 0) || (slot > 31));
811 WARN_ON(qtd->length && !qtd->payload_addr);
812 WARN_ON(slots[slot].qtd);
813 WARN_ON(slots[slot].qh);
814 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
815
816 slots[slot].qtd = qtd;
817 slots[slot].qh = qh;
818 qh->slot = slot;
819 qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since
820 interrupt routine may preempt and expects this value. */
821 ptd_write(hcd->regs, ptd_offset, slot, ptd);
822 priv->active_ptds++;
823
824 /* Make sure done map has not triggered from some unlinked transfer */
825 if (ptd_offset == ATL_PTD_OFFSET) {
826 priv->atl_done_map |= reg_read32(hcd->regs,
827 HC_ATL_PTD_DONEMAP_REG);
828 priv->atl_done_map &= ~(1 << qh->slot);
829
830 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
831 skip_map &= ~(1 << qh->slot);
832 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
833 } else {
834 priv->int_done_map |= reg_read32(hcd->regs,
835 HC_INT_PTD_DONEMAP_REG);
836 priv->int_done_map &= ~(1 << qh->slot);
837
838 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
839 skip_map &= ~(1 << qh->slot);
840 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
841 }
842 }
843
844 static int is_short_bulk(struct isp1760_qtd *qtd)
845 {
846 return (usb_pipebulk(qtd->urb->pipe) &&
847 (qtd->actual_length < qtd->length));
848 }
849
850 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
851 struct list_head *urb_list)
852 {
853 int last_qtd;
854 struct isp1760_qtd *qtd, *qtd_next;
855 struct urb_listitem *urb_listitem;
856
857 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
858 if (qtd->status < QTD_XFER_COMPLETE)
859 break;
860
861 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
862 last_qtd = 1;
863 else
864 last_qtd = qtd->urb != qtd_next->urb;
865
866 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
867 qtd_next->status = QTD_RETIRE;
868
869 if (qtd->status == QTD_XFER_COMPLETE) {
870 if (qtd->actual_length) {
871 switch (qtd->packet_type) {
872 case IN_PID:
873 mem_reads8(hcd->regs, qtd->payload_addr,
874 qtd->data_buffer,
875 qtd->actual_length);
876 /* Fall through (?) */
877 case OUT_PID:
878 qtd->urb->actual_length +=
879 qtd->actual_length;
880 /* Fall through ... */
881 case SETUP_PID:
882 break;
883 }
884 }
885
886 if (is_short_bulk(qtd)) {
887 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
888 qtd->urb->status = -EREMOTEIO;
889 if (!last_qtd)
890 qtd_next->status = QTD_RETIRE;
891 }
892 }
893
894 if (qtd->payload_addr)
895 free_mem(hcd, qtd);
896
897 if (last_qtd) {
898 if ((qtd->status == QTD_RETIRE) &&
899 (qtd->urb->status == -EINPROGRESS))
900 qtd->urb->status = -EPIPE;
901 /* Defer calling of urb_done() since it releases lock */
902 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
903 GFP_ATOMIC);
904 if (unlikely(!urb_listitem))
905 break;
906 urb_listitem->urb = qtd->urb;
907 list_add_tail(&urb_listitem->urb_list, urb_list);
908 }
909
910 list_del(&qtd->qtd_list);
911 qtd_free(qtd);
912 }
913 }
914
915 #define ENQUEUE_DEPTH 2
916 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
917 {
918 struct isp1760_hcd *priv = hcd_to_priv(hcd);
919 int ptd_offset;
920 struct slotinfo *slots;
921 int curr_slot, free_slot;
922 int n;
923 struct ptd ptd;
924 struct isp1760_qtd *qtd;
925
926 if (unlikely(list_empty(&qh->qtd_list))) {
927 WARN_ON(1);
928 return;
929 }
930
931 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
932 qtd_list)->urb->pipe)) {
933 ptd_offset = INT_PTD_OFFSET;
934 slots = priv->int_slots;
935 } else {
936 ptd_offset = ATL_PTD_OFFSET;
937 slots = priv->atl_slots;
938 }
939
940 free_slot = -1;
941 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
942 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
943 free_slot = curr_slot;
944 if (slots[curr_slot].qh == qh)
945 break;
946 }
947
948 n = 0;
949 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
950 if (qtd->status == QTD_ENQUEUED) {
951 WARN_ON(qtd->payload_addr);
952 alloc_mem(hcd, qtd);
953 if ((qtd->length) && (!qtd->payload_addr))
954 break;
955
956 if ((qtd->length) &&
957 ((qtd->packet_type == SETUP_PID) ||
958 (qtd->packet_type == OUT_PID))) {
959 mem_writes8(hcd->regs, qtd->payload_addr,
960 qtd->data_buffer, qtd->length);
961 }
962
963 qtd->status = QTD_PAYLOAD_ALLOC;
964 }
965
966 if (qtd->status == QTD_PAYLOAD_ALLOC) {
967 /*
968 if ((curr_slot > 31) && (free_slot == -1))
969 dev_dbg(hcd->self.controller, "%s: No slot "
970 "available for transfer\n", __func__);
971 */
972 /* Start xfer for this endpoint if not already done */
973 if ((curr_slot > 31) && (free_slot > -1)) {
974 if (usb_pipeint(qtd->urb->pipe))
975 create_ptd_int(qh, qtd, &ptd);
976 else
977 create_ptd_atl(qh, qtd, &ptd);
978
979 start_bus_transfer(hcd, ptd_offset, free_slot,
980 slots, qtd, qh, &ptd);
981 curr_slot = free_slot;
982 }
983
984 n++;
985 if (n >= ENQUEUE_DEPTH)
986 break;
987 }
988 }
989 }
990
991 void schedule_ptds(struct usb_hcd *hcd)
992 {
993 struct isp1760_hcd *priv;
994 struct isp1760_qh *qh, *qh_next;
995 struct list_head *ep_queue;
996 struct usb_host_endpoint *ep;
997 LIST_HEAD(urb_list);
998 struct urb_listitem *urb_listitem, *urb_listitem_next;
999
1000 if (!hcd) {
1001 WARN_ON(1);
1002 return;
1003 }
1004
1005 priv = hcd_to_priv(hcd);
1006
1007 /*
1008 * check finished/retired xfers, transfer payloads, call urb_done()
1009 */
1010 ep_queue = &priv->interruptqhs;
1011 while (ep_queue) {
1012 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
1013 ep = list_entry(qh->qtd_list.next, struct isp1760_qtd,
1014 qtd_list)->urb->ep;
1015 collect_qtds(hcd, qh, &urb_list);
1016 if (list_empty(&qh->qtd_list)) {
1017 list_del(&qh->qh_list);
1018 if (ep->hcpriv == NULL) {
1019 /* Endpoint has been disabled, so we
1020 can free the associated queue head. */
1021 qh_free(qh);
1022 }
1023 }
1024 }
1025
1026 if (ep_queue == &priv->interruptqhs)
1027 ep_queue = &priv->controlqhs;
1028 else if (ep_queue == &priv->controlqhs)
1029 ep_queue = &priv->bulkqhs;
1030 else
1031 ep_queue = NULL;
1032 }
1033
1034 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
1035 urb_list) {
1036 isp1760_urb_done(hcd, urb_listitem->urb);
1037 kmem_cache_free(urb_listitem_cachep, urb_listitem);
1038 }
1039
1040 /*
1041 * Schedule packets for transfer.
1042 *
1043 * According to USB2.0 specification:
1044 *
1045 * 1st prio: interrupt xfers, up to 80 % of bandwidth
1046 * 2nd prio: control xfers
1047 * 3rd prio: bulk xfers
1048 *
1049 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
1050 * is very unclear on how to prioritize traffic):
1051 *
1052 * 1) Enqueue any queued control transfers, as long as payload chip mem
1053 * and PTD ATL slots are available.
1054 * 2) Enqueue any queued INT transfers, as long as payload chip mem
1055 * and PTD INT slots are available.
1056 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1057 * and PTD ATL slots are available.
1058 *
1059 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1060 * conservation of chip mem and performance.
1061 *
1062 * I'm sure this scheme could be improved upon!
1063 */
1064 ep_queue = &priv->controlqhs;
1065 while (ep_queue) {
1066 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1067 enqueue_qtds(hcd, qh);
1068
1069 if (ep_queue == &priv->controlqhs)
1070 ep_queue = &priv->interruptqhs;
1071 else if (ep_queue == &priv->interruptqhs)
1072 ep_queue = &priv->bulkqhs;
1073 else
1074 ep_queue = NULL;
1075 }
1076 }
1077
1078 #define PTD_STATE_QTD_DONE 1
1079 #define PTD_STATE_QTD_RELOAD 2
1080 #define PTD_STATE_URB_RETIRE 3
1081
1082 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1083 struct urb *urb)
1084 {
1085 __dw dw4;
1086 int i;
1087
1088 dw4 = ptd->dw4;
1089 dw4 >>= 8;
1090
1091 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1092 need to handle these errors? Is it done in hardware? */
1093
1094 if (ptd->dw3 & DW3_HALT_BIT) {
1095
1096 urb->status = -EPROTO; /* Default unknown error */
1097
1098 for (i = 0; i < 8; i++) {
1099 switch (dw4 & 0x7) {
1100 case INT_UNDERRUN:
1101 dev_dbg(hcd->self.controller, "%s: underrun "
1102 "during uFrame %d\n",
1103 __func__, i);
1104 urb->status = -ECOMM; /* Could not write data */
1105 break;
1106 case INT_EXACT:
1107 dev_dbg(hcd->self.controller, "%s: transaction "
1108 "error during uFrame %d\n",
1109 __func__, i);
1110 urb->status = -EPROTO; /* timeout, bad CRC, PID
1111 error etc. */
1112 break;
1113 case INT_BABBLE:
1114 dev_dbg(hcd->self.controller, "%s: babble "
1115 "error during uFrame %d\n",
1116 __func__, i);
1117 urb->status = -EOVERFLOW;
1118 break;
1119 }
1120 dw4 >>= 3;
1121 }
1122
1123 return PTD_STATE_URB_RETIRE;
1124 }
1125
1126 return PTD_STATE_QTD_DONE;
1127 }
1128
1129 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1130 struct urb *urb)
1131 {
1132 WARN_ON(!ptd);
1133 if (ptd->dw3 & DW3_HALT_BIT) {
1134 if (ptd->dw3 & DW3_BABBLE_BIT)
1135 urb->status = -EOVERFLOW;
1136 else if (FROM_DW3_CERR(ptd->dw3))
1137 urb->status = -EPIPE; /* Stall */
1138 else if (ptd->dw3 & DW3_ERROR_BIT)
1139 urb->status = -EPROTO; /* XactErr */
1140 else
1141 urb->status = -EPROTO; /* Unknown */
1142 /*
1143 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1144 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1145 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1146 __func__,
1147 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1148 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1149 */
1150 return PTD_STATE_URB_RETIRE;
1151 }
1152
1153 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1154 /* Transfer Error, *but* active and no HALT -> reload */
1155 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1156 return PTD_STATE_QTD_RELOAD;
1157 }
1158
1159 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1160 /*
1161 * NAKs are handled in HW by the chip. Usually if the
1162 * device is not able to send data fast enough.
1163 * This happens mostly on slower hardware.
1164 */
1165 return PTD_STATE_QTD_RELOAD;
1166 }
1167
1168 return PTD_STATE_QTD_DONE;
1169 }
1170
1171 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1172 {
1173 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1174 u32 imask;
1175 irqreturn_t irqret = IRQ_NONE;
1176 struct ptd ptd;
1177 struct isp1760_qh *qh;
1178 int slot;
1179 int state;
1180 struct slotinfo *slots;
1181 u32 ptd_offset;
1182 struct isp1760_qtd *qtd;
1183 int modified;
1184 static int last_active_ptds;
1185 int int_skip_map, atl_skip_map;
1186
1187 spin_lock(&priv->lock);
1188
1189 if (!(hcd->state & HC_STATE_RUNNING))
1190 goto leave;
1191
1192 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1193 if (unlikely(!imask))
1194 goto leave;
1195 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1196
1197 int_skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1198 atl_skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1199 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1200 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1201 priv->int_done_map &= ~int_skip_map;
1202 priv->atl_done_map &= ~atl_skip_map;
1203
1204 modified = priv->int_done_map | priv->atl_done_map;
1205
1206 while (priv->int_done_map || priv->atl_done_map) {
1207 if (priv->int_done_map) {
1208 /* INT ptd */
1209 slot = __ffs(priv->int_done_map);
1210 priv->int_done_map &= ~(1 << slot);
1211 slots = priv->int_slots;
1212 /* This should not trigger, and could be removed if
1213 noone have any problems with it triggering: */
1214 if (!slots[slot].qh) {
1215 WARN_ON(1);
1216 continue;
1217 }
1218 ptd_offset = INT_PTD_OFFSET;
1219 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1220 state = check_int_transfer(hcd, &ptd,
1221 slots[slot].qtd->urb);
1222 } else {
1223 /* ATL ptd */
1224 slot = __ffs(priv->atl_done_map);
1225 priv->atl_done_map &= ~(1 << slot);
1226 slots = priv->atl_slots;
1227 /* This should not trigger, and could be removed if
1228 noone have any problems with it triggering: */
1229 if (!slots[slot].qh) {
1230 WARN_ON(1);
1231 continue;
1232 }
1233 ptd_offset = ATL_PTD_OFFSET;
1234 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1235 state = check_atl_transfer(hcd, &ptd,
1236 slots[slot].qtd->urb);
1237 }
1238
1239 qtd = slots[slot].qtd;
1240 slots[slot].qtd = NULL;
1241 qh = slots[slot].qh;
1242 slots[slot].qh = NULL;
1243 priv->active_ptds--;
1244 qh->slot = -1;
1245
1246 WARN_ON(qtd->status != QTD_XFER_STARTED);
1247
1248 switch (state) {
1249 case PTD_STATE_QTD_DONE:
1250 if ((usb_pipeint(qtd->urb->pipe)) &&
1251 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1252 qtd->actual_length =
1253 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1254 else
1255 qtd->actual_length =
1256 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1257
1258 qtd->status = QTD_XFER_COMPLETE;
1259 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1260 is_short_bulk(qtd))
1261 qtd = NULL;
1262 else
1263 qtd = list_entry(qtd->qtd_list.next,
1264 typeof(*qtd), qtd_list);
1265
1266 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1267 qh->ping = FROM_DW3_PING(ptd.dw3);
1268 break;
1269
1270 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1271 qtd->status = QTD_PAYLOAD_ALLOC;
1272 ptd.dw0 |= DW0_VALID_BIT;
1273 /* RL counter = ERR counter */
1274 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1275 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1276 ptd.dw3 &= ~TO_DW3_CERR(3);
1277 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1278 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1279 qh->ping = FROM_DW3_PING(ptd.dw3);
1280 break;
1281
1282 case PTD_STATE_URB_RETIRE:
1283 qtd->status = QTD_RETIRE;
1284 qtd = NULL;
1285 qh->toggle = 0;
1286 qh->ping = 0;
1287 break;
1288
1289 default:
1290 WARN_ON(1);
1291 continue;
1292 }
1293
1294 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1295 if (slots == priv->int_slots) {
1296 if (state == PTD_STATE_QTD_RELOAD)
1297 dev_err(hcd->self.controller,
1298 "%s: PTD_STATE_QTD_RELOAD on "
1299 "interrupt packet\n", __func__);
1300 if (state != PTD_STATE_QTD_RELOAD)
1301 create_ptd_int(qh, qtd, &ptd);
1302 } else {
1303 if (state != PTD_STATE_QTD_RELOAD)
1304 create_ptd_atl(qh, qtd, &ptd);
1305 }
1306
1307 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1308 qh, &ptd);
1309 }
1310 }
1311
1312 if (modified)
1313 schedule_ptds(hcd);
1314
1315 /* ISP1760 Errata 2 explains that interrupts may be missed (or not
1316 happen?) if two USB devices are running simultaneously. Perhaps
1317 this happens when a PTD is finished during interrupt handling;
1318 enable SOF interrupts if PTDs are still scheduled when exiting this
1319 interrupt handler, just to be safe. */
1320
1321 if (priv->active_ptds != last_active_ptds) {
1322 if (priv->active_ptds > 0)
1323 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1324 INTERRUPT_ENABLE_SOT_MASK);
1325 else
1326 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1327 INTERRUPT_ENABLE_MASK);
1328 last_active_ptds = priv->active_ptds;
1329 }
1330
1331 irqret = IRQ_HANDLED;
1332 leave:
1333 spin_unlock(&priv->lock);
1334
1335 return irqret;
1336 }
1337
1338 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1339 {
1340 qtd->data_buffer = databuffer;
1341
1342 if (len > MAX_PAYLOAD_SIZE)
1343 len = MAX_PAYLOAD_SIZE;
1344 qtd->length = len;
1345
1346 return qtd->length;
1347 }
1348
1349 static void qtd_list_free(struct list_head *qtd_list)
1350 {
1351 struct isp1760_qtd *qtd, *qtd_next;
1352
1353 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1354 list_del(&qtd->qtd_list);
1355 qtd_free(qtd);
1356 }
1357 }
1358
1359 /*
1360 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1361 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1362 */
1363 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1364 static void packetize_urb(struct usb_hcd *hcd,
1365 struct urb *urb, struct list_head *head, gfp_t flags)
1366 {
1367 struct isp1760_qtd *qtd;
1368 void *buf;
1369 int len, maxpacketsize;
1370 u8 packet_type;
1371
1372 /*
1373 * URBs map to sequences of QTDs: one logical transaction
1374 */
1375
1376 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1377 /* XXX This looks like usb storage / SCSI bug */
1378 dev_err(hcd->self.controller,
1379 "buf is null, dma is %08lx len is %d\n",
1380 (long unsigned)urb->transfer_dma,
1381 urb->transfer_buffer_length);
1382 WARN_ON(1);
1383 }
1384
1385 if (usb_pipein(urb->pipe))
1386 packet_type = IN_PID;
1387 else
1388 packet_type = OUT_PID;
1389
1390 if (usb_pipecontrol(urb->pipe)) {
1391 qtd = qtd_alloc(flags, urb, SETUP_PID);
1392 if (!qtd)
1393 goto cleanup;
1394 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1395 list_add_tail(&qtd->qtd_list, head);
1396
1397 /* for zero length DATA stages, STATUS is always IN */
1398 if (urb->transfer_buffer_length == 0)
1399 packet_type = IN_PID;
1400 }
1401
1402 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1403 usb_pipeout(urb->pipe)));
1404
1405 /*
1406 * buffer gets wrapped in one or more qtds;
1407 * last one may be "short" (including zero len)
1408 * and may serve as a control status ack
1409 */
1410 buf = urb->transfer_buffer;
1411 len = urb->transfer_buffer_length;
1412
1413 for (;;) {
1414 int this_qtd_len;
1415
1416 qtd = qtd_alloc(flags, urb, packet_type);
1417 if (!qtd)
1418 goto cleanup;
1419 this_qtd_len = qtd_fill(qtd, buf, len);
1420 list_add_tail(&qtd->qtd_list, head);
1421
1422 len -= this_qtd_len;
1423 buf += this_qtd_len;
1424
1425 if (len <= 0)
1426 break;
1427 }
1428
1429 /*
1430 * control requests may need a terminating data "status" ack;
1431 * bulk ones may need a terminating short packet (zero length).
1432 */
1433 if (urb->transfer_buffer_length != 0) {
1434 int one_more = 0;
1435
1436 if (usb_pipecontrol(urb->pipe)) {
1437 one_more = 1;
1438 if (packet_type == IN_PID)
1439 packet_type = OUT_PID;
1440 else
1441 packet_type = IN_PID;
1442 } else if (usb_pipebulk(urb->pipe)
1443 && (urb->transfer_flags & URB_ZERO_PACKET)
1444 && !(urb->transfer_buffer_length %
1445 maxpacketsize)) {
1446 one_more = 1;
1447 }
1448 if (one_more) {
1449 qtd = qtd_alloc(flags, urb, packet_type);
1450 if (!qtd)
1451 goto cleanup;
1452
1453 /* never any data in such packets */
1454 qtd_fill(qtd, NULL, 0);
1455 list_add_tail(&qtd->qtd_list, head);
1456 }
1457 }
1458
1459 return;
1460
1461 cleanup:
1462 qtd_list_free(head);
1463 }
1464
1465 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1466 gfp_t mem_flags)
1467 {
1468 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1469 struct list_head *ep_queue;
1470 struct isp1760_qh *qh, *qhit;
1471 unsigned long spinflags;
1472 LIST_HEAD(new_qtds);
1473 int retval;
1474 int qh_in_queue;
1475
1476 switch (usb_pipetype(urb->pipe)) {
1477 case PIPE_CONTROL:
1478 ep_queue = &priv->controlqhs;
1479 break;
1480 case PIPE_BULK:
1481 ep_queue = &priv->bulkqhs;
1482 break;
1483 case PIPE_INTERRUPT:
1484 if (urb->interval < 0)
1485 return -EINVAL;
1486 /* FIXME: Check bandwidth */
1487 ep_queue = &priv->interruptqhs;
1488 break;
1489 case PIPE_ISOCHRONOUS:
1490 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1491 "not yet supported\n",
1492 __func__);
1493 return -EPIPE;
1494 default:
1495 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1496 __func__);
1497 return -EPIPE;
1498 }
1499
1500 if (usb_pipein(urb->pipe))
1501 urb->actual_length = 0;
1502
1503 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1504 if (list_empty(&new_qtds))
1505 return -ENOMEM;
1506 urb->hcpriv = NULL; /* Used to signal unlink to interrupt handler */
1507
1508 retval = 0;
1509 spin_lock_irqsave(&priv->lock, spinflags);
1510
1511 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1512 retval = -ESHUTDOWN;
1513 goto out;
1514 }
1515 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1516 if (retval)
1517 goto out;
1518
1519 qh = urb->ep->hcpriv;
1520 if (qh) {
1521 qh_in_queue = 0;
1522 list_for_each_entry(qhit, ep_queue, qh_list) {
1523 if (qhit == qh) {
1524 qh_in_queue = 1;
1525 break;
1526 }
1527 }
1528 if (!qh_in_queue)
1529 list_add_tail(&qh->qh_list, ep_queue);
1530 } else {
1531 qh = qh_alloc(GFP_ATOMIC);
1532 if (!qh) {
1533 retval = -ENOMEM;
1534 goto out;
1535 }
1536 list_add_tail(&qh->qh_list, ep_queue);
1537 urb->ep->hcpriv = qh;
1538 }
1539
1540 list_splice_tail(&new_qtds, &qh->qtd_list);
1541 schedule_ptds(hcd);
1542
1543 out:
1544 spin_unlock_irqrestore(&priv->lock, spinflags);
1545 return retval;
1546 }
1547
1548 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1549 struct isp1760_qh *qh)
1550 {
1551 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1552 int skip_map;
1553
1554 WARN_ON(qh->slot == -1);
1555
1556 /* We need to forcefully reclaim the slot since some transfers never
1557 return, e.g. interrupt transfers and NAKed bulk transfers. */
1558 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1559 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1560 skip_map |= (1 << qh->slot);
1561 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1562 priv->atl_slots[qh->slot].qh = NULL;
1563 priv->atl_slots[qh->slot].qtd = NULL;
1564 } else {
1565 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1566 skip_map |= (1 << qh->slot);
1567 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1568 priv->int_slots[qh->slot].qh = NULL;
1569 priv->int_slots[qh->slot].qtd = NULL;
1570 }
1571
1572 qh->slot = -1;
1573 priv->active_ptds--;
1574 }
1575
1576 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1577 int status)
1578 {
1579 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1580 unsigned long spinflags;
1581 struct isp1760_qh *qh;
1582 struct isp1760_qtd *qtd;
1583 int retval = 0;
1584
1585 spin_lock_irqsave(&priv->lock, spinflags);
1586 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1587 if (retval)
1588 goto out;
1589
1590 qh = urb->ep->hcpriv;
1591 if (!qh) {
1592 retval = -EINVAL;
1593 goto out;
1594 }
1595
1596 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1597 if (qtd->urb == urb) {
1598 if (qtd->status == QTD_XFER_STARTED)
1599 kill_transfer(hcd, urb, qh);
1600 qtd->status = QTD_RETIRE;
1601 }
1602
1603 urb->status = status;
1604 schedule_ptds(hcd);
1605
1606 out:
1607 spin_unlock_irqrestore(&priv->lock, spinflags);
1608 return retval;
1609 }
1610
1611 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1612 struct usb_host_endpoint *ep)
1613 {
1614 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1615 unsigned long spinflags;
1616 struct isp1760_qh *qh;
1617 struct isp1760_qtd *qtd;
1618
1619 spin_lock_irqsave(&priv->lock, spinflags);
1620
1621 qh = ep->hcpriv;
1622 if (!qh)
1623 goto out;
1624
1625 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1626 if (qtd->status == QTD_XFER_STARTED)
1627 kill_transfer(hcd, qtd->urb, qh);
1628 qtd->status = QTD_RETIRE;
1629 qtd->urb->status = -ECONNRESET;
1630 }
1631
1632 ep->hcpriv = NULL;
1633 /* Cannot free qh here since it will be parsed by schedule_ptds() */
1634
1635 schedule_ptds(hcd);
1636
1637 out:
1638 spin_unlock_irqrestore(&priv->lock, spinflags);
1639 }
1640
1641 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1642 {
1643 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1644 u32 temp, status = 0;
1645 u32 mask;
1646 int retval = 1;
1647 unsigned long flags;
1648
1649 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1650 if (!HC_IS_RUNNING(hcd->state))
1651 return 0;
1652
1653 /* init status to no-changes */
1654 buf[0] = 0;
1655 mask = PORT_CSC;
1656
1657 spin_lock_irqsave(&priv->lock, flags);
1658 temp = reg_read32(hcd->regs, HC_PORTSC1);
1659
1660 if (temp & PORT_OWNER) {
1661 if (temp & PORT_CSC) {
1662 temp &= ~PORT_CSC;
1663 reg_write32(hcd->regs, HC_PORTSC1, temp);
1664 goto done;
1665 }
1666 }
1667
1668 /*
1669 * Return status information even for ports with OWNER set.
1670 * Otherwise khubd wouldn't see the disconnect event when a
1671 * high-speed device is switched over to the companion
1672 * controller by the user.
1673 */
1674
1675 if ((temp & mask) != 0
1676 || ((temp & PORT_RESUME) != 0
1677 && time_after_eq(jiffies,
1678 priv->reset_done))) {
1679 buf [0] |= 1 << (0 + 1);
1680 status = STS_PCD;
1681 }
1682 /* FIXME autosuspend idle root hubs */
1683 done:
1684 spin_unlock_irqrestore(&priv->lock, flags);
1685 return status ? retval : 0;
1686 }
1687
1688 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1689 struct usb_hub_descriptor *desc)
1690 {
1691 int ports = HCS_N_PORTS(priv->hcs_params);
1692 u16 temp;
1693
1694 desc->bDescriptorType = 0x29;
1695 /* priv 1.0, 2.3.9 says 20ms max */
1696 desc->bPwrOn2PwrGood = 10;
1697 desc->bHubContrCurrent = 0;
1698
1699 desc->bNbrPorts = ports;
1700 temp = 1 + (ports / 8);
1701 desc->bDescLength = 7 + 2 * temp;
1702
1703 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1704 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1705 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1706
1707 /* per-port overcurrent reporting */
1708 temp = 0x0008;
1709 if (HCS_PPC(priv->hcs_params))
1710 /* per-port power control */
1711 temp |= 0x0001;
1712 else
1713 /* no power switching */
1714 temp |= 0x0002;
1715 desc->wHubCharacteristics = cpu_to_le16(temp);
1716 }
1717
1718 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1719
1720 static int check_reset_complete(struct usb_hcd *hcd, int index,
1721 int port_status)
1722 {
1723 if (!(port_status & PORT_CONNECT))
1724 return port_status;
1725
1726 /* if reset finished and it's still not enabled -- handoff */
1727 if (!(port_status & PORT_PE)) {
1728
1729 dev_info(hcd->self.controller,
1730 "port %d full speed --> companion\n",
1731 index + 1);
1732
1733 port_status |= PORT_OWNER;
1734 port_status &= ~PORT_RWC_BITS;
1735 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1736
1737 } else
1738 dev_info(hcd->self.controller, "port %d high speed\n",
1739 index + 1);
1740
1741 return port_status;
1742 }
1743
1744 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1745 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1746 {
1747 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1748 int ports = HCS_N_PORTS(priv->hcs_params);
1749 u32 temp, status;
1750 unsigned long flags;
1751 int retval = 0;
1752 unsigned selector;
1753
1754 /*
1755 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1756 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1757 * (track current state ourselves) ... blink for diagnostics,
1758 * power, "this is the one", etc. EHCI spec supports this.
1759 */
1760
1761 spin_lock_irqsave(&priv->lock, flags);
1762 switch (typeReq) {
1763 case ClearHubFeature:
1764 switch (wValue) {
1765 case C_HUB_LOCAL_POWER:
1766 case C_HUB_OVER_CURRENT:
1767 /* no hub-wide feature/status flags */
1768 break;
1769 default:
1770 goto error;
1771 }
1772 break;
1773 case ClearPortFeature:
1774 if (!wIndex || wIndex > ports)
1775 goto error;
1776 wIndex--;
1777 temp = reg_read32(hcd->regs, HC_PORTSC1);
1778
1779 /*
1780 * Even if OWNER is set, so the port is owned by the
1781 * companion controller, khubd needs to be able to clear
1782 * the port-change status bits (especially
1783 * USB_PORT_STAT_C_CONNECTION).
1784 */
1785
1786 switch (wValue) {
1787 case USB_PORT_FEAT_ENABLE:
1788 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1789 break;
1790 case USB_PORT_FEAT_C_ENABLE:
1791 /* XXX error? */
1792 break;
1793 case USB_PORT_FEAT_SUSPEND:
1794 if (temp & PORT_RESET)
1795 goto error;
1796
1797 if (temp & PORT_SUSPEND) {
1798 if ((temp & PORT_PE) == 0)
1799 goto error;
1800 /* resume signaling for 20 msec */
1801 temp &= ~(PORT_RWC_BITS);
1802 reg_write32(hcd->regs, HC_PORTSC1,
1803 temp | PORT_RESUME);
1804 priv->reset_done = jiffies +
1805 msecs_to_jiffies(20);
1806 }
1807 break;
1808 case USB_PORT_FEAT_C_SUSPEND:
1809 /* we auto-clear this feature */
1810 break;
1811 case USB_PORT_FEAT_POWER:
1812 if (HCS_PPC(priv->hcs_params))
1813 reg_write32(hcd->regs, HC_PORTSC1,
1814 temp & ~PORT_POWER);
1815 break;
1816 case USB_PORT_FEAT_C_CONNECTION:
1817 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1818 break;
1819 case USB_PORT_FEAT_C_OVER_CURRENT:
1820 /* XXX error ?*/
1821 break;
1822 case USB_PORT_FEAT_C_RESET:
1823 /* GetPortStatus clears reset */
1824 break;
1825 default:
1826 goto error;
1827 }
1828 reg_read32(hcd->regs, HC_USBCMD);
1829 break;
1830 case GetHubDescriptor:
1831 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1832 buf);
1833 break;
1834 case GetHubStatus:
1835 /* no hub-wide feature/status flags */
1836 memset(buf, 0, 4);
1837 break;
1838 case GetPortStatus:
1839 if (!wIndex || wIndex > ports)
1840 goto error;
1841 wIndex--;
1842 status = 0;
1843 temp = reg_read32(hcd->regs, HC_PORTSC1);
1844
1845 /* wPortChange bits */
1846 if (temp & PORT_CSC)
1847 status |= USB_PORT_STAT_C_CONNECTION << 16;
1848
1849
1850 /* whoever resumes must GetPortStatus to complete it!! */
1851 if (temp & PORT_RESUME) {
1852 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1853
1854 /* Remote Wakeup received? */
1855 if (!priv->reset_done) {
1856 /* resume signaling for 20 msec */
1857 priv->reset_done = jiffies
1858 + msecs_to_jiffies(20);
1859 /* check the port again */
1860 mod_timer(&hcd->rh_timer, priv->reset_done);
1861 }
1862
1863 /* resume completed? */
1864 else if (time_after_eq(jiffies,
1865 priv->reset_done)) {
1866 status |= USB_PORT_STAT_C_SUSPEND << 16;
1867 priv->reset_done = 0;
1868
1869 /* stop resume signaling */
1870 temp = reg_read32(hcd->regs, HC_PORTSC1);
1871 reg_write32(hcd->regs, HC_PORTSC1,
1872 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1873 retval = handshake(hcd, HC_PORTSC1,
1874 PORT_RESUME, 0, 2000 /* 2msec */);
1875 if (retval != 0) {
1876 dev_err(hcd->self.controller,
1877 "port %d resume error %d\n",
1878 wIndex + 1, retval);
1879 goto error;
1880 }
1881 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1882 }
1883 }
1884
1885 /* whoever resets must GetPortStatus to complete it!! */
1886 if ((temp & PORT_RESET)
1887 && time_after_eq(jiffies,
1888 priv->reset_done)) {
1889 status |= USB_PORT_STAT_C_RESET << 16;
1890 priv->reset_done = 0;
1891
1892 /* force reset to complete */
1893 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1894 /* REVISIT: some hardware needs 550+ usec to clear
1895 * this bit; seems too long to spin routinely...
1896 */
1897 retval = handshake(hcd, HC_PORTSC1,
1898 PORT_RESET, 0, 750);
1899 if (retval != 0) {
1900 dev_err(hcd->self.controller, "port %d reset error %d\n",
1901 wIndex + 1, retval);
1902 goto error;
1903 }
1904
1905 /* see what we found out */
1906 temp = check_reset_complete(hcd, wIndex,
1907 reg_read32(hcd->regs, HC_PORTSC1));
1908 }
1909 /*
1910 * Even if OWNER is set, there's no harm letting khubd
1911 * see the wPortStatus values (they should all be 0 except
1912 * for PORT_POWER anyway).
1913 */
1914
1915 if (temp & PORT_OWNER)
1916 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1917
1918 if (temp & PORT_CONNECT) {
1919 status |= USB_PORT_STAT_CONNECTION;
1920 /* status may be from integrated TT */
1921 status |= USB_PORT_STAT_HIGH_SPEED;
1922 }
1923 if (temp & PORT_PE)
1924 status |= USB_PORT_STAT_ENABLE;
1925 if (temp & (PORT_SUSPEND|PORT_RESUME))
1926 status |= USB_PORT_STAT_SUSPEND;
1927 if (temp & PORT_RESET)
1928 status |= USB_PORT_STAT_RESET;
1929 if (temp & PORT_POWER)
1930 status |= USB_PORT_STAT_POWER;
1931
1932 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1933 break;
1934 case SetHubFeature:
1935 switch (wValue) {
1936 case C_HUB_LOCAL_POWER:
1937 case C_HUB_OVER_CURRENT:
1938 /* no hub-wide feature/status flags */
1939 break;
1940 default:
1941 goto error;
1942 }
1943 break;
1944 case SetPortFeature:
1945 selector = wIndex >> 8;
1946 wIndex &= 0xff;
1947 if (!wIndex || wIndex > ports)
1948 goto error;
1949 wIndex--;
1950 temp = reg_read32(hcd->regs, HC_PORTSC1);
1951 if (temp & PORT_OWNER)
1952 break;
1953
1954 /* temp &= ~PORT_RWC_BITS; */
1955 switch (wValue) {
1956 case USB_PORT_FEAT_ENABLE:
1957 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
1958 break;
1959
1960 case USB_PORT_FEAT_SUSPEND:
1961 if ((temp & PORT_PE) == 0
1962 || (temp & PORT_RESET) != 0)
1963 goto error;
1964
1965 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
1966 break;
1967 case USB_PORT_FEAT_POWER:
1968 if (HCS_PPC(priv->hcs_params))
1969 reg_write32(hcd->regs, HC_PORTSC1,
1970 temp | PORT_POWER);
1971 break;
1972 case USB_PORT_FEAT_RESET:
1973 if (temp & PORT_RESUME)
1974 goto error;
1975 /* line status bits may report this as low speed,
1976 * which can be fine if this root hub has a
1977 * transaction translator built in.
1978 */
1979 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
1980 && PORT_USB11(temp)) {
1981 temp |= PORT_OWNER;
1982 } else {
1983 temp |= PORT_RESET;
1984 temp &= ~PORT_PE;
1985
1986 /*
1987 * caller must wait, then call GetPortStatus
1988 * usb 2.0 spec says 50 ms resets on root
1989 */
1990 priv->reset_done = jiffies +
1991 msecs_to_jiffies(50);
1992 }
1993 reg_write32(hcd->regs, HC_PORTSC1, temp);
1994 break;
1995 default:
1996 goto error;
1997 }
1998 reg_read32(hcd->regs, HC_USBCMD);
1999 break;
2000
2001 default:
2002 error:
2003 /* "stall" on error */
2004 retval = -EPIPE;
2005 }
2006 spin_unlock_irqrestore(&priv->lock, flags);
2007 return retval;
2008 }
2009
2010 static int isp1760_get_frame(struct usb_hcd *hcd)
2011 {
2012 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2013 u32 fr;
2014
2015 fr = reg_read32(hcd->regs, HC_FRINDEX);
2016 return (fr >> 3) % priv->periodic_size;
2017 }
2018
2019 static void isp1760_stop(struct usb_hcd *hcd)
2020 {
2021 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2022 u32 temp;
2023
2024 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2025 NULL, 0);
2026 mdelay(20);
2027
2028 spin_lock_irq(&priv->lock);
2029 ehci_reset(hcd);
2030 /* Disable IRQ */
2031 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2032 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2033 spin_unlock_irq(&priv->lock);
2034
2035 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2036 }
2037
2038 static void isp1760_shutdown(struct usb_hcd *hcd)
2039 {
2040 u32 command, temp;
2041
2042 isp1760_stop(hcd);
2043 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2044 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2045
2046 command = reg_read32(hcd->regs, HC_USBCMD);
2047 command &= ~CMD_RUN;
2048 reg_write32(hcd->regs, HC_USBCMD, command);
2049 }
2050
2051 static const struct hc_driver isp1760_hc_driver = {
2052 .description = "isp1760-hcd",
2053 .product_desc = "NXP ISP1760 USB Host Controller",
2054 .hcd_priv_size = sizeof(struct isp1760_hcd),
2055 .irq = isp1760_irq,
2056 .flags = HCD_MEMORY | HCD_USB2,
2057 .reset = isp1760_hc_setup,
2058 .start = isp1760_run,
2059 .stop = isp1760_stop,
2060 .shutdown = isp1760_shutdown,
2061 .urb_enqueue = isp1760_urb_enqueue,
2062 .urb_dequeue = isp1760_urb_dequeue,
2063 .endpoint_disable = isp1760_endpoint_disable,
2064 .get_frame_number = isp1760_get_frame,
2065 .hub_status_data = isp1760_hub_status_data,
2066 .hub_control = isp1760_hub_control,
2067 };
2068
2069 int __init init_kmem_once(void)
2070 {
2071 urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem",
2072 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2073 SLAB_MEM_SPREAD, NULL);
2074
2075 if (!urb_listitem_cachep)
2076 return -ENOMEM;
2077
2078 qtd_cachep = kmem_cache_create("isp1760_qtd",
2079 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2080 SLAB_MEM_SPREAD, NULL);
2081
2082 if (!qtd_cachep)
2083 return -ENOMEM;
2084
2085 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2086 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2087
2088 if (!qh_cachep) {
2089 kmem_cache_destroy(qtd_cachep);
2090 return -ENOMEM;
2091 }
2092
2093 return 0;
2094 }
2095
2096 void deinit_kmem_cache(void)
2097 {
2098 kmem_cache_destroy(qtd_cachep);
2099 kmem_cache_destroy(qh_cachep);
2100 kmem_cache_destroy(urb_listitem_cachep);
2101 }
2102
2103 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2104 int irq, unsigned long irqflags,
2105 struct device *dev, const char *busname,
2106 unsigned int devflags)
2107 {
2108 struct usb_hcd *hcd;
2109 struct isp1760_hcd *priv;
2110 int ret;
2111
2112 if (usb_disabled())
2113 return ERR_PTR(-ENODEV);
2114
2115 /* prevent usb-core allocating DMA pages */
2116 dev->dma_mask = NULL;
2117
2118 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2119 if (!hcd)
2120 return ERR_PTR(-ENOMEM);
2121
2122 priv = hcd_to_priv(hcd);
2123 priv->devflags = devflags;
2124 init_memory(priv);
2125 hcd->regs = ioremap(res_start, res_len);
2126 if (!hcd->regs) {
2127 ret = -EIO;
2128 goto err_put;
2129 }
2130
2131 hcd->irq = irq;
2132 hcd->rsrc_start = res_start;
2133 hcd->rsrc_len = res_len;
2134
2135 ret = usb_add_hcd(hcd, irq, irqflags);
2136 if (ret)
2137 goto err_unmap;
2138
2139 return hcd;
2140
2141 err_unmap:
2142 iounmap(hcd->regs);
2143
2144 err_put:
2145 usb_put_hcd(hcd);
2146
2147 return ERR_PTR(ret);
2148 }
2149
2150 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2151 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2152 MODULE_LICENSE("GPL v2");
Linux Btrfs Development