2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <asm/unaligned.h>
27 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
28 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
29 PORT_RC | PORT_PLC | PORT_PE)
31 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
32 struct usb_hub_descriptor
*desc
, int ports
)
36 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
37 desc
->bHubContrCurrent
= 0;
39 desc
->bNbrPorts
= ports
;
40 /* Ugh, these should be #defines, FIXME */
41 /* Using table 11-13 in USB 2.0 spec. */
43 /* Bits 1:0 - support port power switching, or power always on */
44 if (HCC_PPC(xhci
->hcc_params
))
48 /* Bit 2 - root hubs are not part of a compound device */
49 /* Bits 4:3 - individual port over current protection */
51 /* Bits 6:5 - no TTs in root ports */
52 /* Bit 7 - no port indicators */
53 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
56 /* Fill in the USB 2.0 roothub descriptor */
57 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
58 struct usb_hub_descriptor
*desc
)
62 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
66 ports
= xhci
->num_usb2_ports
;
68 xhci_common_hub_descriptor(xhci
, desc
, ports
);
69 desc
->bDescriptorType
= 0x29;
70 temp
= 1 + (ports
/ 8);
71 desc
->bDescLength
= 7 + 2 * temp
;
73 /* The Device Removable bits are reported on a byte granularity.
74 * If the port doesn't exist within that byte, the bit is set to 0.
76 memset(port_removable
, 0, sizeof(port_removable
));
77 for (i
= 0; i
< ports
; i
++) {
78 portsc
= xhci_readl(xhci
, xhci
->usb3_ports
[i
]);
79 /* If a device is removable, PORTSC reports a 0, same as in the
80 * hub descriptor DeviceRemovable bits.
82 if (portsc
& PORT_DEV_REMOVE
)
83 /* This math is hairy because bit 0 of DeviceRemovable
84 * is reserved, and bit 1 is for port 1, etc.
86 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
89 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
90 * ports on it. The USB 2.0 specification says that there are two
91 * variable length fields at the end of the hub descriptor:
92 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
93 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
94 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
95 * 0xFF, so we initialize the both arrays (DeviceRemovable and
96 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
97 * set of ports that actually exist.
99 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
100 sizeof(desc
->u
.hs
.DeviceRemovable
));
101 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
102 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
104 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
105 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
109 /* Fill in the USB 3.0 roothub descriptor */
110 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
111 struct usb_hub_descriptor
*desc
)
118 ports
= xhci
->num_usb3_ports
;
119 xhci_common_hub_descriptor(xhci
, desc
, ports
);
120 desc
->bDescriptorType
= 0x2a;
121 desc
->bDescLength
= 12;
123 /* header decode latency should be zero for roothubs,
124 * see section 4.23.5.2.
126 desc
->u
.ss
.bHubHdrDecLat
= 0;
127 desc
->u
.ss
.wHubDelay
= 0;
130 /* bit 0 is reserved, bit 1 is for port 1, etc. */
131 for (i
= 0; i
< ports
; i
++) {
132 portsc
= xhci_readl(xhci
, xhci
->usb3_ports
[i
]);
133 if (portsc
& PORT_DEV_REMOVE
)
134 port_removable
|= 1 << (i
+ 1);
136 memset(&desc
->u
.ss
.DeviceRemovable
,
137 (__force __u16
) cpu_to_le16(port_removable
),
141 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
142 struct usb_hub_descriptor
*desc
)
145 if (hcd
->speed
== HCD_USB3
)
146 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
148 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
152 static unsigned int xhci_port_speed(unsigned int port_status
)
154 if (DEV_LOWSPEED(port_status
))
155 return USB_PORT_STAT_LOW_SPEED
;
156 if (DEV_HIGHSPEED(port_status
))
157 return USB_PORT_STAT_HIGH_SPEED
;
159 * FIXME: Yes, we should check for full speed, but the core uses that as
160 * a default in portspeed() in usb/core/hub.c (which is the only place
161 * USB_PORT_STAT_*_SPEED is used).
167 * These bits are Read Only (RO) and should be saved and written to the
168 * registers: 0, 3, 10:13, 30
169 * connect status, over-current status, port speed, and device removable.
170 * connect status and port speed are also sticky - meaning they're in
171 * the AUX well and they aren't changed by a hot, warm, or cold reset.
173 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
175 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
176 * bits 5:8, 9, 14:15, 25:27
177 * link state, port power, port indicator state, "wake on" enable state
179 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
181 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
184 #define XHCI_PORT_RW1S ((1<<4))
186 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
187 * bits 1, 17, 18, 19, 20, 21, 22, 23
188 * port enable/disable, and
189 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
190 * over-current, reset, link state, and L1 change
192 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
194 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
197 #define XHCI_PORT_RW ((1<<16))
199 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
202 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
205 * Given a port state, this function returns a value that would result in the
206 * port being in the same state, if the value was written to the port status
208 * Save Read Only (RO) bits and save read/write bits where
209 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
210 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
212 u32
xhci_port_state_to_neutral(u32 state
)
214 /* Save read-only status and port state */
215 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
219 * find slot id based on port number.
220 * @port: The one-based port number from one of the two split roothubs.
222 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
227 enum usb_device_speed speed
;
230 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
233 speed
= xhci
->devs
[i
]->udev
->speed
;
234 if (((speed
== USB_SPEED_SUPER
) == (hcd
->speed
== HCD_USB3
))
235 && xhci
->devs
[i
]->port
== port
) {
246 * It issues stop endpoint command for EP 0 to 30. And wait the last command
248 * suspend will set to 1, if suspend bit need to set in command.
250 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
252 struct xhci_virt_device
*virt_dev
;
253 struct xhci_command
*cmd
;
260 virt_dev
= xhci
->devs
[slot_id
];
261 cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
263 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
267 spin_lock_irqsave(&xhci
->lock
, flags
);
268 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
269 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
)
270 xhci_queue_stop_endpoint(xhci
, slot_id
, i
, suspend
);
272 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
273 list_add_tail(&cmd
->cmd_list
, &virt_dev
->cmd_list
);
274 xhci_queue_stop_endpoint(xhci
, slot_id
, 0, suspend
);
275 xhci_ring_cmd_db(xhci
);
276 spin_unlock_irqrestore(&xhci
->lock
, flags
);
278 /* Wait for last stop endpoint command to finish */
279 timeleft
= wait_for_completion_interruptible_timeout(
281 USB_CTRL_SET_TIMEOUT
);
283 xhci_warn(xhci
, "%s while waiting for stop endpoint command\n",
284 timeleft
== 0 ? "Timeout" : "Signal");
285 spin_lock_irqsave(&xhci
->lock
, flags
);
286 /* The timeout might have raced with the event ring handler, so
287 * only delete from the list if the item isn't poisoned.
289 if (cmd
->cmd_list
.next
!= LIST_POISON1
)
290 list_del(&cmd
->cmd_list
);
291 spin_unlock_irqrestore(&xhci
->lock
, flags
);
293 goto command_cleanup
;
297 xhci_free_command(xhci
, cmd
);
302 * Ring device, it rings the all doorbells unconditionally.
304 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
308 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++)
309 if (xhci
->devs
[slot_id
]->eps
[i
].ring
&&
310 xhci
->devs
[slot_id
]->eps
[i
].ring
->dequeue
)
311 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
316 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
317 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
319 /* Don't allow the USB core to disable SuperSpeed ports. */
320 if (hcd
->speed
== HCD_USB3
) {
321 xhci_dbg(xhci
, "Ignoring request to disable "
322 "SuperSpeed port.\n");
326 /* Write 1 to disable the port */
327 xhci_writel(xhci
, port_status
| PORT_PE
, addr
);
328 port_status
= xhci_readl(xhci
, addr
);
329 xhci_dbg(xhci
, "disable port, actual port %d status = 0x%x\n",
330 wIndex
, port_status
);
333 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
334 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
336 char *port_change_bit
;
340 case USB_PORT_FEAT_C_RESET
:
342 port_change_bit
= "reset";
344 case USB_PORT_FEAT_C_BH_PORT_RESET
:
346 port_change_bit
= "warm(BH) reset";
348 case USB_PORT_FEAT_C_CONNECTION
:
350 port_change_bit
= "connect";
352 case USB_PORT_FEAT_C_OVER_CURRENT
:
354 port_change_bit
= "over-current";
356 case USB_PORT_FEAT_C_ENABLE
:
358 port_change_bit
= "enable/disable";
360 case USB_PORT_FEAT_C_SUSPEND
:
362 port_change_bit
= "suspend/resume";
364 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
366 port_change_bit
= "link state";
369 /* Should never happen */
372 /* Change bits are all write 1 to clear */
373 xhci_writel(xhci
, port_status
| status
, addr
);
374 port_status
= xhci_readl(xhci
, addr
);
375 xhci_dbg(xhci
, "clear port %s change, actual port %d status = 0x%x\n",
376 port_change_bit
, wIndex
, port_status
);
379 static int xhci_get_ports(struct usb_hcd
*hcd
, __le32 __iomem
***port_array
)
382 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
384 if (hcd
->speed
== HCD_USB3
) {
385 max_ports
= xhci
->num_usb3_ports
;
386 *port_array
= xhci
->usb3_ports
;
388 max_ports
= xhci
->num_usb2_ports
;
389 *port_array
= xhci
->usb2_ports
;
395 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
396 u16 wIndex
, char *buf
, u16 wLength
)
398 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
401 u32 temp
, temp1
, status
;
403 __le32 __iomem
**port_array
;
405 struct xhci_bus_state
*bus_state
;
408 max_ports
= xhci_get_ports(hcd
, &port_array
);
409 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
411 spin_lock_irqsave(&xhci
->lock
, flags
);
414 /* No power source, over-current reported per port */
417 case GetHubDescriptor
:
418 /* Check to make sure userspace is asking for the USB 3.0 hub
419 * descriptor for the USB 3.0 roothub. If not, we stall the
420 * endpoint, like external hubs do.
422 if (hcd
->speed
== HCD_USB3
&&
423 (wLength
< USB_DT_SS_HUB_SIZE
||
424 wValue
!= (USB_DT_SS_HUB
<< 8))) {
425 xhci_dbg(xhci
, "Wrong hub descriptor type for "
426 "USB 3.0 roothub.\n");
429 xhci_hub_descriptor(hcd
, xhci
,
430 (struct usb_hub_descriptor
*) buf
);
433 if (!wIndex
|| wIndex
> max_ports
)
437 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
438 if (temp
== 0xffffffff) {
442 xhci_dbg(xhci
, "get port status, actual port %d status = 0x%x\n", wIndex
, temp
);
444 /* wPortChange bits */
446 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
448 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
449 if ((temp
& PORT_OCC
))
450 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
451 if ((temp
& PORT_RC
))
452 status
|= USB_PORT_STAT_C_RESET
<< 16;
454 if (hcd
->speed
== HCD_USB3
) {
455 if ((temp
& PORT_PLC
))
456 status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
457 if ((temp
& PORT_WRC
))
458 status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
461 if (hcd
->speed
!= HCD_USB3
) {
462 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
463 && (temp
& PORT_POWER
))
464 status
|= USB_PORT_STAT_SUSPEND
;
466 if ((temp
& PORT_PLS_MASK
) == XDEV_RESUME
&&
467 !DEV_SUPERSPEED(temp
)) {
468 if ((temp
& PORT_RESET
) || !(temp
& PORT_PE
))
470 if (time_after_eq(jiffies
,
471 bus_state
->resume_done
[wIndex
])) {
472 xhci_dbg(xhci
, "Resume USB2 port %d\n",
474 bus_state
->resume_done
[wIndex
] = 0;
475 temp1
= xhci_port_state_to_neutral(temp
);
476 temp1
&= ~PORT_PLS_MASK
;
477 temp1
|= PORT_LINK_STROBE
| XDEV_U0
;
478 xhci_writel(xhci
, temp1
, port_array
[wIndex
]);
480 xhci_dbg(xhci
, "set port %d resume\n",
482 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
485 xhci_dbg(xhci
, "slot_id is zero\n");
488 xhci_ring_device(xhci
, slot_id
);
489 bus_state
->port_c_suspend
|= 1 << wIndex
;
490 bus_state
->suspended_ports
&= ~(1 << wIndex
);
493 * The resume has been signaling for less than
494 * 20ms. Report the port status as SUSPEND,
495 * let the usbcore check port status again
496 * and clear resume signaling later.
498 status
|= USB_PORT_STAT_SUSPEND
;
501 if ((temp
& PORT_PLS_MASK
) == XDEV_U0
502 && (temp
& PORT_POWER
)
503 && (bus_state
->suspended_ports
& (1 << wIndex
))) {
504 bus_state
->suspended_ports
&= ~(1 << wIndex
);
505 if (hcd
->speed
!= HCD_USB3
)
506 bus_state
->port_c_suspend
|= 1 << wIndex
;
508 if (temp
& PORT_CONNECT
) {
509 status
|= USB_PORT_STAT_CONNECTION
;
510 status
|= xhci_port_speed(temp
);
513 status
|= USB_PORT_STAT_ENABLE
;
515 status
|= USB_PORT_STAT_OVERCURRENT
;
516 if (temp
& PORT_RESET
)
517 status
|= USB_PORT_STAT_RESET
;
518 if (temp
& PORT_POWER
) {
519 if (hcd
->speed
== HCD_USB3
)
520 status
|= USB_SS_PORT_STAT_POWER
;
522 status
|= USB_PORT_STAT_POWER
;
524 /* Port Link State */
525 if (hcd
->speed
== HCD_USB3
) {
526 /* resume state is a xHCI internal state.
527 * Do not report it to usb core.
529 if ((temp
& PORT_PLS_MASK
) != XDEV_RESUME
)
530 status
|= (temp
& PORT_PLS_MASK
);
532 if (bus_state
->port_c_suspend
& (1 << wIndex
))
533 status
|= 1 << USB_PORT_FEAT_C_SUSPEND
;
534 xhci_dbg(xhci
, "Get port status returned 0x%x\n", status
);
535 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
538 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
539 link_state
= (wIndex
& 0xff00) >> 3;
541 if (!wIndex
|| wIndex
> max_ports
)
544 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
545 if (temp
== 0xffffffff) {
549 temp
= xhci_port_state_to_neutral(temp
);
550 /* FIXME: What new port features do we need to support? */
552 case USB_PORT_FEAT_SUSPEND
:
553 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
554 /* In spec software should not attempt to suspend
555 * a port unless the port reports that it is in the
556 * enabled (PED = ‘1’,PLS < ‘3’) state.
558 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
559 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
560 xhci_warn(xhci
, "USB core suspending device "
561 "not in U0/U1/U2.\n");
565 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
568 xhci_warn(xhci
, "slot_id is zero\n");
571 /* unlock to execute stop endpoint commands */
572 spin_unlock_irqrestore(&xhci
->lock
, flags
);
573 xhci_stop_device(xhci
, slot_id
, 1);
574 spin_lock_irqsave(&xhci
->lock
, flags
);
576 temp
= xhci_port_state_to_neutral(temp
);
577 temp
&= ~PORT_PLS_MASK
;
578 temp
|= PORT_LINK_STROBE
| XDEV_U3
;
579 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
581 spin_unlock_irqrestore(&xhci
->lock
, flags
);
582 msleep(10); /* wait device to enter */
583 spin_lock_irqsave(&xhci
->lock
, flags
);
585 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
586 bus_state
->suspended_ports
|= 1 << wIndex
;
588 case USB_PORT_FEAT_LINK_STATE
:
589 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
590 /* Software should not attempt to set
591 * port link state above '5' (Rx.Detect) and the port
594 if ((temp
& PORT_PE
) == 0 ||
595 (link_state
> USB_SS_PORT_LS_RX_DETECT
)) {
596 xhci_warn(xhci
, "Cannot set link state.\n");
600 if (link_state
== USB_SS_PORT_LS_U3
) {
601 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
604 /* unlock to execute stop endpoint
606 spin_unlock_irqrestore(&xhci
->lock
,
608 xhci_stop_device(xhci
, slot_id
, 1);
609 spin_lock_irqsave(&xhci
->lock
, flags
);
613 temp
= xhci_port_state_to_neutral(temp
);
614 temp
&= ~PORT_PLS_MASK
;
615 temp
|= PORT_LINK_STROBE
| link_state
;
616 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
618 spin_unlock_irqrestore(&xhci
->lock
, flags
);
619 msleep(20); /* wait device to enter */
620 spin_lock_irqsave(&xhci
->lock
, flags
);
622 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
623 if (link_state
== USB_SS_PORT_LS_U3
)
624 bus_state
->suspended_ports
|= 1 << wIndex
;
626 case USB_PORT_FEAT_POWER
:
628 * Turn on ports, even if there isn't per-port switching.
629 * HC will report connect events even before this is set.
630 * However, khubd will ignore the roothub events until
631 * the roothub is registered.
633 xhci_writel(xhci
, temp
| PORT_POWER
,
636 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
637 xhci_dbg(xhci
, "set port power, actual port %d status = 0x%x\n", wIndex
, temp
);
639 case USB_PORT_FEAT_RESET
:
640 temp
= (temp
| PORT_RESET
);
641 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
643 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
644 xhci_dbg(xhci
, "set port reset, actual port %d status = 0x%x\n", wIndex
, temp
);
646 case USB_PORT_FEAT_BH_PORT_RESET
:
648 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
650 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
655 /* unblock any posted writes */
656 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
658 case ClearPortFeature
:
659 if (!wIndex
|| wIndex
> max_ports
)
662 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
663 if (temp
== 0xffffffff) {
667 /* FIXME: What new port features do we need to support? */
668 temp
= xhci_port_state_to_neutral(temp
);
670 case USB_PORT_FEAT_SUSPEND
:
671 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
672 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
673 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
674 if (temp
& PORT_RESET
)
676 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
677 if ((temp
& PORT_PE
) == 0)
680 temp
= xhci_port_state_to_neutral(temp
);
681 temp
&= ~PORT_PLS_MASK
;
682 temp
|= PORT_LINK_STROBE
| XDEV_RESUME
;
683 xhci_writel(xhci
, temp
,
686 spin_unlock_irqrestore(&xhci
->lock
,
689 spin_lock_irqsave(&xhci
->lock
, flags
);
691 temp
= xhci_readl(xhci
,
693 temp
= xhci_port_state_to_neutral(temp
);
694 temp
&= ~PORT_PLS_MASK
;
695 temp
|= PORT_LINK_STROBE
| XDEV_U0
;
696 xhci_writel(xhci
, temp
,
699 bus_state
->port_c_suspend
|= 1 << wIndex
;
701 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
704 xhci_dbg(xhci
, "slot_id is zero\n");
707 xhci_ring_device(xhci
, slot_id
);
709 case USB_PORT_FEAT_C_SUSPEND
:
710 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
711 case USB_PORT_FEAT_C_RESET
:
712 case USB_PORT_FEAT_C_BH_PORT_RESET
:
713 case USB_PORT_FEAT_C_CONNECTION
:
714 case USB_PORT_FEAT_C_OVER_CURRENT
:
715 case USB_PORT_FEAT_C_ENABLE
:
716 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
717 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
718 port_array
[wIndex
], temp
);
720 case USB_PORT_FEAT_ENABLE
:
721 xhci_disable_port(hcd
, xhci
, wIndex
,
722 port_array
[wIndex
], temp
);
730 /* "stall" on error */
733 spin_unlock_irqrestore(&xhci
->lock
, flags
);
738 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
739 * Ports are 0-indexed from the HCD point of view,
740 * and 1-indexed from the USB core pointer of view.
742 * Note that the status change bits will be cleared as soon as a port status
743 * change event is generated, so we use the saved status from that event.
745 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
751 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
753 __le32 __iomem
**port_array
;
754 struct xhci_bus_state
*bus_state
;
756 max_ports
= xhci_get_ports(hcd
, &port_array
);
757 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
759 /* Initial status is no changes */
760 retval
= (max_ports
+ 8) / 8;
761 memset(buf
, 0, retval
);
764 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
;
766 spin_lock_irqsave(&xhci
->lock
, flags
);
767 /* For each port, did anything change? If so, set that bit in buf. */
768 for (i
= 0; i
< max_ports
; i
++) {
769 temp
= xhci_readl(xhci
, port_array
[i
]);
770 if (temp
== 0xffffffff) {
774 if ((temp
& mask
) != 0 ||
775 (bus_state
->port_c_suspend
& 1 << i
) ||
776 (bus_state
->resume_done
[i
] && time_after_eq(
777 jiffies
, bus_state
->resume_done
[i
]))) {
778 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
782 spin_unlock_irqrestore(&xhci
->lock
, flags
);
783 return status
? retval
: 0;
788 int xhci_bus_suspend(struct usb_hcd
*hcd
)
790 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
791 int max_ports
, port_index
;
792 __le32 __iomem
**port_array
;
793 struct xhci_bus_state
*bus_state
;
796 max_ports
= xhci_get_ports(hcd
, &port_array
);
797 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
799 spin_lock_irqsave(&xhci
->lock
, flags
);
801 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
802 port_index
= max_ports
;
803 while (port_index
--) {
804 if (bus_state
->resume_done
[port_index
] != 0) {
805 spin_unlock_irqrestore(&xhci
->lock
, flags
);
806 xhci_dbg(xhci
, "suspend failed because "
807 "port %d is resuming\n",
814 port_index
= max_ports
;
815 bus_state
->bus_suspended
= 0;
816 while (port_index
--) {
817 /* suspend the port if the port is not suspended */
821 t1
= xhci_readl(xhci
, port_array
[port_index
]);
822 t2
= xhci_port_state_to_neutral(t1
);
824 if ((t1
& PORT_PE
) && !(t1
& PORT_PLS_MASK
)) {
825 xhci_dbg(xhci
, "port %d not suspended\n", port_index
);
826 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
829 spin_unlock_irqrestore(&xhci
->lock
, flags
);
830 xhci_stop_device(xhci
, slot_id
, 1);
831 spin_lock_irqsave(&xhci
->lock
, flags
);
833 t2
&= ~PORT_PLS_MASK
;
834 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
835 set_bit(port_index
, &bus_state
->bus_suspended
);
837 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
838 if (t1
& PORT_CONNECT
) {
839 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
840 t2
&= ~PORT_WKCONN_E
;
842 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
843 t2
&= ~PORT_WKDISC_E
;
846 t2
&= ~PORT_WAKE_BITS
;
848 t1
= xhci_port_state_to_neutral(t1
);
850 xhci_writel(xhci
, t2
, port_array
[port_index
]);
852 if (hcd
->speed
!= HCD_USB3
) {
853 /* enable remote wake up for USB 2.0 */
854 __le32 __iomem
*addr
;
857 /* Add one to the port status register address to get
858 * the port power control register address.
860 addr
= port_array
[port_index
] + 1;
861 tmp
= xhci_readl(xhci
, addr
);
863 xhci_writel(xhci
, tmp
, addr
);
866 hcd
->state
= HC_STATE_SUSPENDED
;
867 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
868 spin_unlock_irqrestore(&xhci
->lock
, flags
);
872 int xhci_bus_resume(struct usb_hcd
*hcd
)
874 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
875 int max_ports
, port_index
;
876 __le32 __iomem
**port_array
;
877 struct xhci_bus_state
*bus_state
;
881 max_ports
= xhci_get_ports(hcd
, &port_array
);
882 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
884 if (time_before(jiffies
, bus_state
->next_statechange
))
887 spin_lock_irqsave(&xhci
->lock
, flags
);
888 if (!HCD_HW_ACCESSIBLE(hcd
)) {
889 spin_unlock_irqrestore(&xhci
->lock
, flags
);
894 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
896 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
898 port_index
= max_ports
;
899 while (port_index
--) {
900 /* Check whether need resume ports. If needed
901 resume port and disable remote wakeup */
905 temp
= xhci_readl(xhci
, port_array
[port_index
]);
906 if (DEV_SUPERSPEED(temp
))
907 temp
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
909 temp
&= ~(PORT_RWC_BITS
| PORT_WAKE_BITS
);
910 if (test_bit(port_index
, &bus_state
->bus_suspended
) &&
911 (temp
& PORT_PLS_MASK
)) {
912 if (DEV_SUPERSPEED(temp
)) {
913 temp
= xhci_port_state_to_neutral(temp
);
914 temp
&= ~PORT_PLS_MASK
;
915 temp
|= PORT_LINK_STROBE
| XDEV_U0
;
916 xhci_writel(xhci
, temp
, port_array
[port_index
]);
918 temp
= xhci_port_state_to_neutral(temp
);
919 temp
&= ~PORT_PLS_MASK
;
920 temp
|= PORT_LINK_STROBE
| XDEV_RESUME
;
921 xhci_writel(xhci
, temp
, port_array
[port_index
]);
923 spin_unlock_irqrestore(&xhci
->lock
, flags
);
925 spin_lock_irqsave(&xhci
->lock
, flags
);
927 temp
= xhci_readl(xhci
, port_array
[port_index
]);
928 temp
= xhci_port_state_to_neutral(temp
);
929 temp
&= ~PORT_PLS_MASK
;
930 temp
|= PORT_LINK_STROBE
| XDEV_U0
;
931 xhci_writel(xhci
, temp
, port_array
[port_index
]);
933 /* wait for the port to enter U0 and report port link
936 spin_unlock_irqrestore(&xhci
->lock
, flags
);
938 spin_lock_irqsave(&xhci
->lock
, flags
);
941 temp
= xhci_readl(xhci
, port_array
[port_index
]);
942 if (temp
& PORT_PLC
) {
943 temp
= xhci_port_state_to_neutral(temp
);
945 xhci_writel(xhci
, temp
, port_array
[port_index
]);
948 slot_id
= xhci_find_slot_id_by_port(hcd
,
949 xhci
, port_index
+ 1);
951 xhci_ring_device(xhci
, slot_id
);
953 xhci_writel(xhci
, temp
, port_array
[port_index
]);
955 if (hcd
->speed
!= HCD_USB3
) {
956 /* disable remote wake up for USB 2.0 */
957 __le32 __iomem
*addr
;
960 /* Add one to the port status register address to get
961 * the port power control register address.
963 addr
= port_array
[port_index
] + 1;
964 tmp
= xhci_readl(xhci
, addr
);
966 xhci_writel(xhci
, tmp
, addr
);
970 (void) xhci_readl(xhci
, &xhci
->op_regs
->command
);
972 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
974 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
976 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
977 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
979 spin_unlock_irqrestore(&xhci
->lock
, flags
);
983 #endif /* CONFIG_PM */