drivers/usb/musb/am35x.c

   1 /*
   2  * Texas Instruments AM35x "glue layer"
   3  *
   4  * Copyright (c) 2010, by Texas Instruments
   5  *
   6  * Based on the DA8xx "glue layer" code.
   7  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  * This file is part of the Inventra Controller Driver for Linux.
  10  *
  11  * The Inventra Controller Driver for Linux is free software; you
  12  * can redistribute it and/or modify it under the terms of the GNU
  13  * General Public License version 2 as published by the Free Software
  14  * Foundation.
  15  *
  16  * The Inventra Controller Driver for Linux is distributed in
  17  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  18  * without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20  * License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with The Inventra Controller Driver for Linux ; if not,
  24  * write to the Free Software Foundation, Inc., 59 Temple Place,
  25  * Suite 330, Boston, MA  02111-1307  USA
  26  *
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/dma-mapping.h>
  34
  35 #include <plat/usb.h>
  36
  37 #include "musb_core.h"
  38
  39 /*
  40  * AM35x specific definitions
  41  */
  42 /* USB 2.0 OTG module registers */
  43 #define USB_REVISION_REG        0x00
  44 #define USB_CTRL_REG            0x04
  45 #define USB_STAT_REG            0x08
  46 #define USB_EMULATION_REG       0x0c
  47 /* 0x10 Reserved */
  48 #define USB_AUTOREQ_REG         0x14
  49 #define USB_SRP_FIX_TIME_REG    0x18
  50 #define USB_TEARDOWN_REG        0x1c
  51 #define EP_INTR_SRC_REG         0x20
  52 #define EP_INTR_SRC_SET_REG     0x24
  53 #define EP_INTR_SRC_CLEAR_REG   0x28
  54 #define EP_INTR_MASK_REG        0x2c
  55 #define EP_INTR_MASK_SET_REG    0x30
  56 #define EP_INTR_MASK_CLEAR_REG  0x34
  57 #define EP_INTR_SRC_MASKED_REG  0x38
  58 #define CORE_INTR_SRC_REG       0x40
  59 #define CORE_INTR_SRC_SET_REG   0x44
  60 #define CORE_INTR_SRC_CLEAR_REG 0x48
  61 #define CORE_INTR_MASK_REG      0x4c
  62 #define CORE_INTR_MASK_SET_REG  0x50
  63 #define CORE_INTR_MASK_CLEAR_REG 0x54
  64 #define CORE_INTR_SRC_MASKED_REG 0x58
  65 /* 0x5c Reserved */
  66 #define USB_END_OF_INTR_REG     0x60
  67
  68 /* Control register bits */
  69 #define AM35X_SOFT_RESET_MASK   1
  70
  71 /* USB interrupt register bits */
  72 #define AM35X_INTR_USB_SHIFT    16
  73 #define AM35X_INTR_USB_MASK     (0x1ff << AM35X_INTR_USB_SHIFT)
  74 #define AM35X_INTR_DRVVBUS      0x100
  75 #define AM35X_INTR_RX_SHIFT     16
  76 #define AM35X_INTR_TX_SHIFT     0
  77 #define AM35X_TX_EP_MASK        0xffff          /* EP0 + 15 Tx EPs */
  78 #define AM35X_RX_EP_MASK        0xfffe          /* 15 Rx EPs */
  79 #define AM35X_TX_INTR_MASK      (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  80 #define AM35X_RX_INTR_MASK      (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  81
  82 #define USB_MENTOR_CORE_OFFSET  0x400
  83
  84 struct am35x_glue {
  85         struct device           *dev;
  86         struct platform_device  *musb;
  87         struct clk              *phy_clk;
  88         struct clk              *clk;
  89 };
  90 #define glue_to_musb(g)         platform_get_drvdata(g->musb)
  91
  92 /*
  93  * am35x_musb_enable - enable interrupts
  94  */
  95 static void am35x_musb_enable(struct musb *musb)
  96 {
  97         void __iomem *reg_base = musb->ctrl_base;
  98         u32 epmask;
  99
 100         /* Workaround: setup IRQs through both register sets. */
 101         epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
 102                ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
 103
 104         musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
 105         musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
 106
 107         /* Force the DRVVBUS IRQ so we can start polling for ID change. */
 108         if (is_otg_enabled(musb))
 109                 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
 110                             AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
 111 }
 112
 113 /*
 114  * am35x_musb_disable - disable HDRC and flush interrupts
 115  */
 116 static void am35x_musb_disable(struct musb *musb)
 117 {
 118         void __iomem *reg_base = musb->ctrl_base;
 119
 120         musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
 121         musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
 122                          AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
 123         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 124         musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 125 }
 126
 127 #define portstate(stmt)         stmt
 128
 129 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
 130 {
 131         WARN_ON(is_on && is_peripheral_active(musb));
 132 }
 133
 134 #define POLL_SECONDS    2
 135
 136 static struct timer_list otg_workaround;
 137
 138 static void otg_timer(unsigned long _musb)
 139 {
 140         struct musb             *musb = (void *)_musb;
 141         void __iomem            *mregs = musb->mregs;
 142         u8                      devctl;
 143         unsigned long           flags;
 144
 145         /*
 146          * We poll because AM35x's won't expose several OTG-critical
 147          * status change events (from the transceiver) otherwise.
 148          */
 149         devctl = musb_readb(mregs, MUSB_DEVCTL);
 150         dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 151                 otg_state_string(musb->xceiv->state));
 152
 153         spin_lock_irqsave(&musb->lock, flags);
 154         switch (musb->xceiv->state) {
 155         case OTG_STATE_A_WAIT_BCON:
 156                 devctl &= ~MUSB_DEVCTL_SESSION;
 157                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 158
 159                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 160                 if (devctl & MUSB_DEVCTL_BDEVICE) {
 161                         musb->xceiv->state = OTG_STATE_B_IDLE;
 162                         MUSB_DEV_MODE(musb);
 163                 } else {
 164                         musb->xceiv->state = OTG_STATE_A_IDLE;
 165                         MUSB_HST_MODE(musb);
 166                 }
 167                 break;
 168         case OTG_STATE_A_WAIT_VFALL:
 169                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 170                 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
 171                             MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
 172                 break;
 173         case OTG_STATE_B_IDLE:
 174                 if (!is_peripheral_enabled(musb))
 175                         break;
 176
 177                 devctl = musb_readb(mregs, MUSB_DEVCTL);
 178                 if (devctl & MUSB_DEVCTL_BDEVICE)
 179                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 180                 else
 181                         musb->xceiv->state = OTG_STATE_A_IDLE;
 182                 break;
 183         default:
 184                 break;
 185         }
 186         spin_unlock_irqrestore(&musb->lock, flags);
 187 }
 188
 189 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
 190 {
 191         static unsigned long last_timer;
 192
 193         if (!is_otg_enabled(musb))
 194                 return;
 195
 196         if (timeout == 0)
 197                 timeout = jiffies + msecs_to_jiffies(3);
 198
 199         /* Never idle if active, or when VBUS timeout is not set as host */
 200         if (musb->is_active || (musb->a_wait_bcon == 0 &&
 201                                 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
 202                 dev_dbg(musb->controller, "%s active, deleting timer\n",
 203                         otg_state_string(musb->xceiv->state));
 204                 del_timer(&otg_workaround);
 205                 last_timer = jiffies;
 206                 return;
 207         }
 208
 209         if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
 210                 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
 211                 return;
 212         }
 213         last_timer = timeout;
 214
 215         dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 216                 otg_state_string(musb->xceiv->state),
 217                 jiffies_to_msecs(timeout - jiffies));
 218         mod_timer(&otg_workaround, timeout);
 219 }
 220
 221 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
 222 {
 223         struct musb  *musb = hci;
 224         void __iomem *reg_base = musb->ctrl_base;
 225         struct device *dev = musb->controller;
 226         struct musb_hdrc_platform_data *plat = dev->platform_data;
 227         struct omap_musb_board_data *data = plat->board_data;
 228         unsigned long flags;
 229         irqreturn_t ret = IRQ_NONE;
 230         u32 epintr, usbintr;
 231
 232         spin_lock_irqsave(&musb->lock, flags);
 233
 234         /* Get endpoint interrupts */
 235         epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
 236
 237         if (epintr) {
 238                 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
 239
 240                 musb->int_rx =
 241                         (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
 242                 musb->int_tx =
 243                         (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
 244         }
 245
 246         /* Get usb core interrupts */
 247         usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
 248         if (!usbintr && !epintr)
 249                 goto eoi;
 250
 251         if (usbintr) {
 252                 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
 253
 254                 musb->int_usb =
 255                         (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
 256         }
 257         /*
 258          * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 259          * AM35x's missing ID change IRQ.  We need an ID change IRQ to
 260          * switch appropriately between halves of the OTG state machine.
 261          * Managing DEVCTL.SESSION per Mentor docs requires that we know its
 262          * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 263          * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 264          */
 265         if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
 266                 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
 267                 void __iomem *mregs = musb->mregs;
 268                 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 269                 int err;
 270
 271                 err = is_host_enabled(musb) && (musb->int_usb &
 272                                                 MUSB_INTR_VBUSERROR);
 273                 if (err) {
 274                         /*
 275                          * The Mentor core doesn't debounce VBUS as needed
 276                          * to cope with device connect current spikes. This
 277                          * means it's not uncommon for bus-powered devices
 278                          * to get VBUS errors during enumeration.
 279                          *
 280                          * This is a workaround, but newer RTL from Mentor
 281                          * seems to allow a better one: "re"-starting sessions
 282                          * without waiting for VBUS to stop registering in
 283                          * devctl.
 284                          */
 285                         musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 286                         musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 287                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 288                         WARNING("VBUS error workaround (delay coming)\n");
 289                 } else if (is_host_enabled(musb) && drvvbus) {
 290                         MUSB_HST_MODE(musb);
 291                         musb->xceiv->default_a = 1;
 292                         musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 293                         portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 294                         del_timer(&otg_workaround);
 295                 } else {
 296                         musb->is_active = 0;
 297                         MUSB_DEV_MODE(musb);
 298                         musb->xceiv->default_a = 0;
 299                         musb->xceiv->state = OTG_STATE_B_IDLE;
 300                         portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 301                 }
 302
 303                 /* NOTE: this must complete power-on within 100 ms. */
 304                 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 305                                 drvvbus ? "on" : "off",
 306                                 otg_state_string(musb->xceiv->state),
 307                                 err ? " ERROR" : "",
 308                                 devctl);
 309                 ret = IRQ_HANDLED;
 310         }
 311
 312         if (musb->int_tx || musb->int_rx || musb->int_usb)
 313                 ret |= musb_interrupt(musb);
 314
 315 eoi:
 316         /* EOI needs to be written for the IRQ to be re-asserted. */
 317         if (ret == IRQ_HANDLED || epintr || usbintr) {
 318                 /* clear level interrupt */
 319                 if (data->clear_irq)
 320                         data->clear_irq();
 321                 /* write EOI */
 322                 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 323         }
 324
 325         /* Poll for ID change */
 326         if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
 327                 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 328
 329         spin_unlock_irqrestore(&musb->lock, flags);
 330
 331         return ret;
 332 }
 333
 334 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
 335 {
 336         struct device *dev = musb->controller;
 337         struct musb_hdrc_platform_data *plat = dev->platform_data;
 338         struct omap_musb_board_data *data = plat->board_data;
 339         int     retval = 0;
 340
 341         if (data->set_mode)
 342                 data->set_mode(musb_mode);
 343         else
 344                 retval = -EIO;
 345
 346         return retval;
 347 }
 348
 349 static int am35x_musb_init(struct musb *musb)
 350 {
 351         struct device *dev = musb->controller;
 352         struct musb_hdrc_platform_data *plat = dev->platform_data;
 353         struct omap_musb_board_data *data = plat->board_data;
 354         void __iomem *reg_base = musb->ctrl_base;
 355         u32 rev;
 356
 357         musb->mregs += USB_MENTOR_CORE_OFFSET;
 358
 359         /* Returns zero if e.g. not clocked */
 360         rev = musb_readl(reg_base, USB_REVISION_REG);
 361         if (!rev)
 362                 return -ENODEV;
 363
 364         usb_nop_xceiv_register();
 365         musb->xceiv = otg_get_transceiver();
 366         if (!musb->xceiv)
 367                 return -ENODEV;
 368
 369         if (is_host_enabled(musb))
 370                 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
 371
 372         /* Reset the musb */
 373         if (data->reset)
 374                 data->reset();
 375
 376         /* Reset the controller */
 377         musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
 378
 379         /* Start the on-chip PHY and its PLL. */
 380         if (data->set_phy_power)
 381                 data->set_phy_power(1);
 382
 383         msleep(5);
 384
 385         musb->isr = am35x_musb_interrupt;
 386
 387         /* clear level interrupt */
 388         if (data->clear_irq)
 389                 data->clear_irq();
 390
 391         return 0;
 392 }
 393
 394 static int am35x_musb_exit(struct musb *musb)
 395 {
 396         struct device *dev = musb->controller;
 397         struct musb_hdrc_platform_data *plat = dev->platform_data;
 398         struct omap_musb_board_data *data = plat->board_data;
 399
 400         if (is_host_enabled(musb))
 401                 del_timer_sync(&otg_workaround);
 402
 403         /* Shutdown the on-chip PHY and its PLL. */
 404         if (data->set_phy_power)
 405                 data->set_phy_power(0);
 406
 407         otg_put_transceiver(musb->xceiv);
 408         usb_nop_xceiv_unregister();
 409
 410         return 0;
 411 }
 412
 413 /* AM35x supports only 32bit read operation */
 414 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 415 {
 416         void __iomem *fifo = hw_ep->fifo;
 417         u32             val;
 418         int             i;
 419
 420         /* Read for 32bit-aligned destination address */
 421         if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
 422                 readsl(fifo, dst, len >> 2);
 423                 dst += len & ~0x03;
 424                 len &= 0x03;
 425         }
 426         /*
 427          * Now read the remaining 1 to 3 byte or complete length if
 428          * unaligned address.
 429          */
 430         if (len > 4) {
 431                 for (i = 0; i < (len >> 2); i++) {
 432                         *(u32 *) dst = musb_readl(fifo, 0);
 433                         dst += 4;
 434                 }
 435                 len &= 0x03;
 436         }
 437         if (len > 0) {
 438                 val = musb_readl(fifo, 0);
 439                 memcpy(dst, &val, len);
 440         }
 441 }
 442
 443 static const struct musb_platform_ops am35x_ops = {
 444         .init           = am35x_musb_init,
 445         .exit           = am35x_musb_exit,
 446
 447         .enable         = am35x_musb_enable,
 448         .disable        = am35x_musb_disable,
 449
 450         .set_mode       = am35x_musb_set_mode,
 451         .try_idle       = am35x_musb_try_idle,
 452
 453         .set_vbus       = am35x_musb_set_vbus,
 454 };
 455
 456 static u64 am35x_dmamask = DMA_BIT_MASK(32);
 457
 458 static int __init am35x_probe(struct platform_device *pdev)
 459 {
 460         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
 461         struct platform_device          *musb;
 462         struct am35x_glue               *glue;
 463
 464         struct clk                      *phy_clk;
 465         struct clk                      *clk;
 466
 467         int                             ret = -ENOMEM;
 468
 469         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 470         if (!glue) {
 471                 dev_err(&pdev->dev, "failed to allocate glue context\n");
 472                 goto err0;
 473         }
 474
 475         musb = platform_device_alloc("musb-hdrc", -1);
 476         if (!musb) {
 477                 dev_err(&pdev->dev, "failed to allocate musb device\n");
 478                 goto err1;
 479         }
 480
 481         phy_clk = clk_get(&pdev->dev, "fck");
 482         if (IS_ERR(phy_clk)) {
 483                 dev_err(&pdev->dev, "failed to get PHY clock\n");
 484                 ret = PTR_ERR(phy_clk);
 485                 goto err2;
 486         }
 487
 488         clk = clk_get(&pdev->dev, "ick");
 489         if (IS_ERR(clk)) {
 490                 dev_err(&pdev->dev, "failed to get clock\n");
 491                 ret = PTR_ERR(clk);
 492                 goto err3;
 493         }
 494
 495         ret = clk_enable(phy_clk);
 496         if (ret) {
 497                 dev_err(&pdev->dev, "failed to enable PHY clock\n");
 498                 goto err4;
 499         }
 500
 501         ret = clk_enable(clk);
 502         if (ret) {
 503                 dev_err(&pdev->dev, "failed to enable clock\n");
 504                 goto err5;
 505         }
 506
 507         musb->dev.parent                = &pdev->dev;
 508         musb->dev.dma_mask              = &am35x_dmamask;
 509         musb->dev.coherent_dma_mask     = am35x_dmamask;
 510
 511         glue->dev                       = &pdev->dev;
 512         glue->musb                      = musb;
 513         glue->phy_clk                   = phy_clk;
 514         glue->clk                       = clk;
 515
 516         pdata->platform_ops             = &am35x_ops;
 517
 518         platform_set_drvdata(pdev, glue);
 519
 520         ret = platform_device_add_resources(musb, pdev->resource,
 521                         pdev->num_resources);
 522         if (ret) {
 523                 dev_err(&pdev->dev, "failed to add resources\n");
 524                 goto err6;
 525         }
 526
 527         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 528         if (ret) {
 529                 dev_err(&pdev->dev, "failed to add platform_data\n");
 530                 goto err6;
 531         }
 532
 533         ret = platform_device_add(musb);
 534         if (ret) {
 535                 dev_err(&pdev->dev, "failed to register musb device\n");
 536                 goto err6;
 537         }
 538
 539         return 0;
 540
 541 err6:
 542         clk_disable(clk);
 543
 544 err5:
 545         clk_disable(phy_clk);
 546
 547 err4:
 548         clk_put(clk);
 549
 550 err3:
 551         clk_put(phy_clk);
 552
 553 err2:
 554         platform_device_put(musb);
 555
 556 err1:
 557         kfree(glue);
 558
 559 err0:
 560         return ret;
 561 }
 562
 563 static int __exit am35x_remove(struct platform_device *pdev)
 564 {
 565         struct am35x_glue       *glue = platform_get_drvdata(pdev);
 566
 567         platform_device_del(glue->musb);
 568         platform_device_put(glue->musb);
 569         clk_disable(glue->clk);
 570         clk_disable(glue->phy_clk);
 571         clk_put(glue->clk);
 572         clk_put(glue->phy_clk);
 573         kfree(glue);
 574
 575         return 0;
 576 }
 577
 578 #ifdef CONFIG_PM
 579 static int am35x_suspend(struct device *dev)
 580 {
 581         struct am35x_glue       *glue = dev_get_drvdata(dev);
 582         struct musb_hdrc_platform_data *plat = dev->platform_data;
 583         struct omap_musb_board_data *data = plat->board_data;
 584
 585         /* Shutdown the on-chip PHY and its PLL. */
 586         if (data->set_phy_power)
 587                 data->set_phy_power(0);
 588
 589         clk_disable(glue->phy_clk);
 590         clk_disable(glue->clk);
 591
 592         return 0;
 593 }
 594
 595 static int am35x_resume(struct device *dev)
 596 {
 597         struct am35x_glue       *glue = dev_get_drvdata(dev);
 598         struct musb_hdrc_platform_data *plat = dev->platform_data;
 599         struct omap_musb_board_data *data = plat->board_data;
 600         int                     ret;
 601
 602         /* Start the on-chip PHY and its PLL. */
 603         if (data->set_phy_power)
 604                 data->set_phy_power(1);
 605
 606         ret = clk_enable(glue->phy_clk);
 607         if (ret) {
 608                 dev_err(dev, "failed to enable PHY clock\n");
 609                 return ret;
 610         }
 611
 612         ret = clk_enable(glue->clk);
 613         if (ret) {
 614                 dev_err(dev, "failed to enable clock\n");
 615                 return ret;
 616         }
 617
 618         return 0;
 619 }
 620
 621 static struct dev_pm_ops am35x_pm_ops = {
 622         .suspend        = am35x_suspend,
 623         .resume         = am35x_resume,
 624 };
 625
 626 #define DEV_PM_OPS      &am35x_pm_ops
 627 #else
 628 #define DEV_PM_OPS      NULL
 629 #endif
 630
 631 static struct platform_driver am35x_driver = {
 632         .remove         = __exit_p(am35x_remove),
 633         .driver         = {
 634                 .name   = "musb-am35x",
 635                 .pm     = DEV_PM_OPS,
 636         },
 637 };
 638
 639 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
 640 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
 641 MODULE_LICENSE("GPL v2");
 642
 643 static int __init am35x_init(void)
 644 {
 645         return platform_driver_probe(&am35x_driver, am35x_probe);
 646 }
 647 subsys_initcall(am35x_init);
 648
 649 static void __exit am35x_exit(void)
 650 {
 651         platform_driver_unregister(&am35x_driver);
 652 }
 653 module_exit(am35x_exit);