arch/arm/mach-mx5/board-cpuimx51.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/i2c.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26
  27 #include <mach/eukrea-baseboards.h>
  28 #include <mach/common.h>
  29 #include <mach/hardware.h>
  30 #include <mach/iomux-mx51.h>
  31
  32 #include <asm/irq.h>
  33 #include <asm/setup.h>
  34 #include <asm/mach-types.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/time.h>
  37
  38 #include "devices-imx51.h"
  39 #include "devices.h"
  40
  41 #define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
  42 #define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
  43 #define CPUIMX51_QUARTB_GPIO    IMX_GPIO_NR(3, 25)
  44 #define CPUIMX51_QUARTC_GPIO    IMX_GPIO_NR(3, 26)
  45 #define CPUIMX51_QUARTD_GPIO    IMX_GPIO_NR(3, 27)
  46 #define CPUIMX51_QUART_XTAL     14745600
  47 #define CPUIMX51_QUART_REGSHIFT 17
  48
  49 /* USB_CTRL_1 */
  50 #define MX51_USB_CTRL_1_OFFSET          0x10
  51 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  52
  53 #define MX51_USB_PLLDIV_12_MHZ          0x00
  54 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  55 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  56
  57 static struct plat_serial8250_port serial_platform_data[] = {
  58         {
  59                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
  60                 .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
  61                 .irqflags = IRQF_TRIGGER_HIGH,
  62                 .uartclk = CPUIMX51_QUART_XTAL,
  63                 .regshift = CPUIMX51_QUART_REGSHIFT,
  64                 .iotype = UPIO_MEM,
  65                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  66         }, {
  67                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
  68                 .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
  69                 .irqflags = IRQF_TRIGGER_HIGH,
  70                 .uartclk = CPUIMX51_QUART_XTAL,
  71                 .regshift = CPUIMX51_QUART_REGSHIFT,
  72                 .iotype = UPIO_MEM,
  73                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  74         }, {
  75                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
  76                 .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
  77                 .irqflags = IRQF_TRIGGER_HIGH,
  78                 .uartclk = CPUIMX51_QUART_XTAL,
  79                 .regshift = CPUIMX51_QUART_REGSHIFT,
  80                 .iotype = UPIO_MEM,
  81                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  82         }, {
  83                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
  84                 .irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO),
  85                 .irqflags = IRQF_TRIGGER_HIGH,
  86                 .uartclk = CPUIMX51_QUART_XTAL,
  87                 .regshift = CPUIMX51_QUART_REGSHIFT,
  88                 .iotype = UPIO_MEM,
  89                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  90         }, {
  91         }
  92 };
  93
  94 static struct platform_device serial_device = {
  95         .name = "serial8250",
  96         .id = 0,
  97         .dev = {
  98                 .platform_data = serial_platform_data,
  99         },
 100 };
 101
 102 static struct platform_device *devices[] __initdata = {
 103         &serial_device,
 104 };
 105
 106 static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
 107         /* UART1 */
 108         MX51_PAD_UART1_RXD__UART1_RXD,
 109         MX51_PAD_UART1_TXD__UART1_TXD,
 110         MX51_PAD_UART1_RTS__UART1_RTS,
 111         MX51_PAD_UART1_CTS__UART1_CTS,
 112
 113         /* I2C2 */
 114         MX51_PAD_GPIO1_2__I2C2_SCL,
 115         MX51_PAD_GPIO1_3__I2C2_SDA,
 116         MX51_PAD_NANDF_D10__GPIO3_30,
 117
 118         /* QUART IRQ */
 119         MX51_PAD_NANDF_D15__GPIO3_25,
 120         MX51_PAD_NANDF_D14__GPIO3_26,
 121         MX51_PAD_NANDF_D13__GPIO3_27,
 122         MX51_PAD_NANDF_D12__GPIO3_28,
 123
 124         /* USB HOST1 */
 125         MX51_PAD_USBH1_CLK__USBH1_CLK,
 126         MX51_PAD_USBH1_DIR__USBH1_DIR,
 127         MX51_PAD_USBH1_NXT__USBH1_NXT,
 128         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
 129         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
 130         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
 131         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
 132         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
 133         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
 134         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
 135         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 136         MX51_PAD_USBH1_STP__USBH1_STP,
 137 };
 138
 139 static const struct mxc_nand_platform_data
 140                 eukrea_cpuimx51_nand_board_info __initconst = {
 141         .width          = 1,
 142         .hw_ecc         = 1,
 143         .flash_bbt      = 1,
 144 };
 145
 146 static const struct imxuart_platform_data uart_pdata __initconst = {
 147         .flags = IMXUART_HAVE_RTSCTS,
 148 };
 149
 150 static const
 151 struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
 152         .bitrate = 100000,
 153 };
 154
 155 static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
 156         {
 157                 I2C_BOARD_INFO("pcf8563", 0x51),
 158         },
 159 };
 160
 161 /* This function is board specific as the bit mask for the plldiv will also
 162 be different for other Freescale SoCs, thus a common bitmask is not
 163 possible and cannot get place in /plat-mxc/ehci.c.*/
 164 static int initialize_otg_port(struct platform_device *pdev)
 165 {
 166         u32 v;
 167         void __iomem *usb_base;
 168         void __iomem *usbother_base;
 169
 170         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 171         if (!usb_base)
 172                 return -ENOMEM;
 173         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 174
 175         /* Set the PHY clock to 19.2MHz */
 176         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 177         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 178         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 179         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 180         iounmap(usb_base);
 181
 182         mdelay(10);
 183
 184         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 185 }
 186
 187 static int initialize_usbh1_port(struct platform_device *pdev)
 188 {
 189         u32 v;
 190         void __iomem *usb_base;
 191         void __iomem *usbother_base;
 192
 193         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 194         if (!usb_base)
 195                 return -ENOMEM;
 196         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 197
 198         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
 199         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 200         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
 201         iounmap(usb_base);
 202
 203         mdelay(10);
 204
 205         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 206                         MXC_EHCI_ITC_NO_THRESHOLD);
 207 }
 208
 209 static struct mxc_usbh_platform_data dr_utmi_config = {
 210         .init           = initialize_otg_port,
 211         .portsc = MXC_EHCI_UTMI_16BIT,
 212 };
 213
 214 static struct fsl_usb2_platform_data usb_pdata = {
 215         .operating_mode = FSL_USB2_DR_DEVICE,
 216         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 217 };
 218
 219 static struct mxc_usbh_platform_data usbh1_config = {
 220         .init           = initialize_usbh1_port,
 221         .portsc = MXC_EHCI_MODE_ULPI,
 222 };
 223
 224 static int otg_mode_host;
 225
 226 static int __init eukrea_cpuimx51_otg_mode(char *options)
 227 {
 228         if (!strcmp(options, "host"))
 229                 otg_mode_host = 1;
 230         else if (!strcmp(options, "device"))
 231                 otg_mode_host = 0;
 232         else
 233                 pr_info("otg_mode neither \"host\" nor \"device\". "
 234                         "Defaulting to device\n");
 235         return 0;
 236 }
 237 __setup("otg_mode=", eukrea_cpuimx51_otg_mode);
 238
 239 /*
 240  * Board specific initialization.
 241  */
 242 static void __init eukrea_cpuimx51_init(void)
 243 {
 244         imx51_soc_init();
 245
 246         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
 247                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 248
 249         imx51_add_imx_uart(0, &uart_pdata);
 250         imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
 251
 252         gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
 253         gpio_direction_input(CPUIMX51_QUARTA_GPIO);
 254         gpio_free(CPUIMX51_QUARTA_GPIO);
 255         gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
 256         gpio_direction_input(CPUIMX51_QUARTB_GPIO);
 257         gpio_free(CPUIMX51_QUARTB_GPIO);
 258         gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
 259         gpio_direction_input(CPUIMX51_QUARTC_GPIO);
 260         gpio_free(CPUIMX51_QUARTC_GPIO);
 261         gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
 262         gpio_direction_input(CPUIMX51_QUARTD_GPIO);
 263         gpio_free(CPUIMX51_QUARTD_GPIO);
 264
 265         imx51_add_fec(NULL);
 266         platform_add_devices(devices, ARRAY_SIZE(devices));
 267
 268         imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
 269         i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
 270                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 271
 272         if (otg_mode_host)
 273                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 274         else {
 275                 initialize_otg_port(NULL);
 276                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 277         }
 278         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 279
 280 #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
 281         eukrea_mbimx51_baseboard_init();
 282 #endif
 283 }
 284
 285 static void __init eukrea_cpuimx51_timer_init(void)
 286 {
 287         mx51_clocks_init(32768, 24000000, 22579200, 0);
 288 }
 289
 290 static struct sys_timer mxc_timer = {
 291         .init   = eukrea_cpuimx51_timer_init,
 292 };
 293
 294 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
 295         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 296         .boot_params = MX51_PHYS_OFFSET + 0x100,
 297         .map_io = mx51_map_io,
 298         .init_early = imx51_init_early,
 299         .init_irq = mx51_init_irq,
 300         .timer = &mxc_timer,
 301         .init_machine = eukrea_cpuimx51_init,
 302 MACHINE_END