2 * linux/arch/arm/mach-omap2/prcm.c
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
6 * Copyright (C) 2005 Nokia Corporation
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/clk.h>
25 #include <linux/delay.h>
27 #include <mach/system.h>
28 #include <plat/common.h>
29 #include <plat/prcm.h>
30 #include <plat/irqs.h>
33 #include "clock2xxx.h"
34 #include "cm2xxx_3xxx.h"
35 #include "prm2xxx_3xxx.h"
37 #include "prminst44xx.h"
38 #include "prm-regbits-24xx.h"
39 #include "prm-regbits-44xx.h"
42 void __iomem
*prm_base
;
43 void __iomem
*cm_base
;
44 void __iomem
*cm2_base
;
46 #define MAX_MODULE_ENABLE_WAIT 100000
48 u32
omap_prcm_get_reset_sources(void)
50 /* XXX This presumably needs modification for 34XX */
51 if (cpu_is_omap24xx() || cpu_is_omap34xx())
52 return omap2_prm_read_mod_reg(WKUP_MOD
, OMAP2_RM_RSTST
) & 0x7f;
53 if (cpu_is_omap44xx())
54 return omap2_prm_read_mod_reg(WKUP_MOD
, OMAP4_RM_RSTST
) & 0x7f;
58 EXPORT_SYMBOL(omap_prcm_get_reset_sources
);
60 /* Resets clock rates and reboots the system. Only called from system.h */
61 static void omap_prcm_arch_reset(char mode
, const char *cmd
)
65 if (cpu_is_omap24xx()) {
66 omap2xxx_clk_prepare_for_reboot();
69 } else if (cpu_is_omap34xx()) {
70 prcm_offs
= OMAP3430_GR_MOD
;
71 omap3_ctrl_write_boot_mode((cmd
? (u8
)*cmd
: 0));
72 } else if (cpu_is_omap44xx()) {
73 omap4_prminst_global_warm_sw_reset(); /* never returns */
79 * As per Errata i520, in some cases, user will not be able to
80 * access DDR memory after warm-reset.
81 * This situation occurs while the warm-reset happens during a read
82 * access to DDR memory. In that particular condition, DDR memory
83 * does not respond to a corrupted read command due to the warm
84 * reset occurrence but SDRC is waiting for read completion.
85 * SDRC is not sensitive to the warm reset, but the interconnect is
86 * reset on the fly, thus causing a misalignment between SDRC logic,
87 * interconnect logic and DDR memory state.
89 * Steps to perform before a Warm reset is trigged:
90 * 1. enable self-refresh on idle request
92 * 3. wait until SDRC goes to idle
93 * 4. generate SW reset (Global SW reset)
95 * Steps to be performed after warm reset occurs (in bootloader):
96 * if HW warm reset is the source, apply below steps before any
98 * 1. Reset SMS and SDRC and wait till reset is complete
99 * 2. Re-initialize SMS, SDRC and memory
101 * NOTE: Above work around is required only if arch reset is implemented
102 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
103 * the WA since it resets SDRC as well as part of cold reset.
106 /* XXX should be moved to some OMAP2/3 specific code */
107 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK
, prcm_offs
,
109 omap2_prm_read_mod_reg(prcm_offs
, OMAP2_RM_RSTCTRL
); /* OCP barrier */
112 void (*arch_reset
)(char, const char *) = omap_prcm_arch_reset
;
115 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
116 * @reg: physical address of module IDLEST register
117 * @mask: value to mask against to determine if the module is active
118 * @idlest: idle state indicator (0 or 1) for the clock
119 * @name: name of the clock (for printk)
121 * Returns 1 if the module indicated readiness in time, or 0 if it
122 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
124 * XXX This function is deprecated. It should be removed once the
125 * hwmod conversion is complete.
127 int omap2_cm_wait_idlest(void __iomem
*reg
, u32 mask
, u8 idlest
,
139 omap_test_timeout(((__raw_readl(reg
) & mask
) == ena
),
140 MAX_MODULE_ENABLE_WAIT
, i
);
142 if (i
< MAX_MODULE_ENABLE_WAIT
)
143 pr_debug("cm: Module associated with clock %s ready after %d "
146 pr_err("cm: Module associated with clock %s didn't enable in "
147 "%d tries\n", name
, MAX_MODULE_ENABLE_WAIT
);
149 return (i
< MAX_MODULE_ENABLE_WAIT
) ? 1 : 0;
152 void __init
omap2_set_globals_prcm(struct omap_globals
*omap2_globals
)
154 /* Static mapping, never released */
155 if (omap2_globals
->prm
) {
156 prm_base
= ioremap(omap2_globals
->prm
, SZ_8K
);
159 if (omap2_globals
->cm
) {
160 cm_base
= ioremap(omap2_globals
->cm
, SZ_8K
);
163 if (omap2_globals
->cm2
) {
164 cm2_base
= ioremap(omap2_globals
->cm2
, SZ_8K
);