arch/arm/mach-s3c2412/s3c2412.c

   1 /* linux/arch/arm/mach-s3c2412/s3c2412.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://armlinux.simtec.co.uk/.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/syscore_ops.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/io.h>
  26
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/map.h>
  29 #include <asm/mach/irq.h>
  30
  31 #include <mach/hardware.h>
  32 #include <asm/proc-fns.h>
  33 #include <asm/irq.h>
  34
  35 #include <mach/reset.h>
  36 #include <mach/idle.h>
  37
  38 #include <plat/cpu-freq.h>
  39
  40 #include <mach/regs-clock.h>
  41 #include <plat/regs-serial.h>
  42 #include <mach/regs-power.h>
  43 #include <mach/regs-gpio.h>
  44 #include <mach/regs-gpioj.h>
  45 #include <mach/regs-dsc.h>
  46 #include <plat/regs-spi.h>
  47 #include <mach/regs-s3c2412.h>
  48
  49 #include <plat/s3c2412.h>
  50 #include <plat/cpu.h>
  51 #include <plat/devs.h>
  52 #include <plat/clock.h>
  53 #include <plat/pm.h>
  54 #include <plat/pll.h>
  55 #include <plat/nand-core.h>
  56
  57 #ifndef CONFIG_CPU_S3C2412_ONLY
  58 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
  59
  60 static inline void s3c2412_init_gpio2(void)
  61 {
  62         s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
  63 }
  64 #else
  65 #define s3c2412_init_gpio2() do { } while(0)
  66 #endif
  67
  68 /* Initial IO mappings */
  69
  70 static struct map_desc s3c2412_iodesc[] __initdata = {
  71         IODESC_ENT(CLKPWR),
  72         IODESC_ENT(TIMER),
  73         IODESC_ENT(WATCHDOG),
  74         {
  75                 .virtual = (unsigned long)S3C2412_VA_SSMC,
  76                 .pfn     = __phys_to_pfn(S3C2412_PA_SSMC),
  77                 .length  = SZ_1M,
  78                 .type    = MT_DEVICE,
  79         },
  80         {
  81                 .virtual = (unsigned long)S3C2412_VA_EBI,
  82                 .pfn     = __phys_to_pfn(S3C2412_PA_EBI),
  83                 .length  = SZ_1M,
  84                 .type    = MT_DEVICE,
  85         },
  86 };
  87
  88 /* uart registration process */
  89
  90 void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  91 {
  92         s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
  93
  94         /* rename devices that are s3c2412/s3c2413 specific */
  95         s3c_device_sdi.name  = "s3c2412-sdi";
  96         s3c_device_lcd.name  = "s3c2412-lcd";
  97         s3c_nand_setname("s3c2412-nand");
  98
  99         /* alter IRQ of SDI controller */
 100
 101         s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
 102         s3c_device_sdi.resource[1].end   = IRQ_S3C2412_SDI;
 103
 104         /* spi channel related changes, s3c2412/13 specific */
 105         s3c_device_spi0.name = "s3c2412-spi";
 106         s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
 107         s3c_device_spi1.name = "s3c2412-spi";
 108         s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
 109         s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
 110
 111 }
 112
 113 /* s3c2412_idle
 114  *
 115  * use the standard idle call by ensuring the idle mode
 116  * in power config, then issuing the idle co-processor
 117  * instruction
 118 */
 119
 120 static void s3c2412_idle(void)
 121 {
 122         unsigned long tmp;
 123
 124         /* ensure our idle mode is to go to idle */
 125
 126         tmp = __raw_readl(S3C2412_PWRCFG);
 127         tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
 128         tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
 129         __raw_writel(tmp, S3C2412_PWRCFG);
 130
 131         cpu_do_idle();
 132 }
 133
 134 static void s3c2412_hard_reset(void)
 135 {
 136         /* errata "Watch-dog/Software Reset Problem" specifies that
 137          * this reset must be done with the SYSCLK sourced from
 138          * EXTCLK instead of FOUT to avoid a glitch in the reset
 139          * mechanism.
 140          *
 141          * See the watchdog section of the S3C2412 manual for more
 142          * information on this fix.
 143          */
 144
 145         __raw_writel(0x00, S3C2412_CLKSRC);
 146         __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
 147
 148         mdelay(1);
 149 }
 150
 151 /* s3c2412_map_io
 152  *
 153  * register the standard cpu IO areas, and any passed in from the
 154  * machine specific initialisation.
 155 */
 156
 157 void __init s3c2412_map_io(void)
 158 {
 159         /* move base of IO */
 160
 161         s3c2412_init_gpio2();
 162
 163         /* set our idle function */
 164
 165         s3c24xx_idle = s3c2412_idle;
 166
 167         /* set custom reset hook */
 168
 169         s3c24xx_reset_hook = s3c2412_hard_reset;
 170
 171         /* register our io-tables */
 172
 173         iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
 174 }
 175
 176 void __init_or_cpufreq s3c2412_setup_clocks(void)
 177 {
 178         struct clk *xtal_clk;
 179         unsigned long tmp;
 180         unsigned long xtal;
 181         unsigned long fclk;
 182         unsigned long hclk;
 183         unsigned long pclk;
 184
 185         xtal_clk = clk_get(NULL, "xtal");
 186         xtal = clk_get_rate(xtal_clk);
 187         clk_put(xtal_clk);
 188
 189         /* now we've got our machine bits initialised, work out what
 190          * clocks we've got */
 191
 192         fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
 193
 194         clk_mpll.rate = fclk;
 195
 196         tmp = __raw_readl(S3C2410_CLKDIVN);
 197
 198         /* work out clock scalings */
 199
 200         hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
 201         hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
 202         pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
 203
 204         /* print brieft summary of clocks, etc */
 205
 206         printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
 207                print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
 208
 209         s3c24xx_setup_clocks(fclk, hclk, pclk);
 210 }
 211
 212 void __init s3c2412_init_clocks(int xtal)
 213 {
 214         /* initialise the clocks here, to allow other things like the
 215          * console to use them
 216          */
 217
 218         s3c24xx_register_baseclocks(xtal);
 219         s3c2412_setup_clocks();
 220         s3c2412_baseclk_add();
 221 }
 222
 223 /* need to register class before we actually register the device, and
 224  * we also need to ensure that it has been initialised before any of the
 225  * drivers even try to use it (even if not on an s3c2412 based system)
 226  * as a driver which may support both 2410 and 2440 may try and use it.
 227 */
 228
 229 struct sysdev_class s3c2412_sysclass = {
 230         .name = "s3c2412-core",
 231 };
 232
 233 static int __init s3c2412_core_init(void)
 234 {
 235         return sysdev_class_register(&s3c2412_sysclass);
 236 }
 237
 238 core_initcall(s3c2412_core_init);
 239
 240 static struct sys_device s3c2412_sysdev = {
 241         .cls            = &s3c2412_sysclass,
 242 };
 243
 244 int __init s3c2412_init(void)
 245 {
 246         printk("S3C2412: Initialising architecture\n");
 247
 248 #ifdef CONFIG_PM
 249         register_syscore_ops(&s3c2412_pm_syscore_ops);
 250 #endif
 251         register_syscore_ops(&s3c24xx_irq_syscore_ops);
 252
 253         return sysdev_register(&s3c2412_sysdev);
 254 }