arch/arm/mach-tegra/clock.h

   1 /*
   2  * arch/arm/mach-tegra/include/mach/clock.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #ifndef __MACH_TEGRA_CLOCK_H
  21 #define __MACH_TEGRA_CLOCK_H
  22
  23 #include <linux/clkdev.h>
  24 #include <linux/list.h>
  25 #include <linux/spinlock.h>
  26
  27 #define DIV_BUS                 (1 << 0)
  28 #define DIV_U71                 (1 << 1)
  29 #define DIV_U71_FIXED           (1 << 2)
  30 #define DIV_2                   (1 << 3)
  31 #define DIV_U16                 (1 << 4)
  32 #define PLL_FIXED               (1 << 5)
  33 #define PLL_HAS_CPCON           (1 << 6)
  34 #define MUX                     (1 << 7)
  35 #define PLLD                    (1 << 8)
  36 #define PERIPH_NO_RESET         (1 << 9)
  37 #define PERIPH_NO_ENB           (1 << 10)
  38 #define PERIPH_EMC_ENB          (1 << 11)
  39 #define PERIPH_MANUAL_RESET     (1 << 12)
  40 #define PLL_ALT_MISC_REG        (1 << 13)
  41 #define PLLU                    (1 << 14)
  42 #define ENABLE_ON_INIT          (1 << 28)
  43
  44 struct clk;
  45
  46 struct clk_mux_sel {
  47         struct clk      *input;
  48         u32             value;
  49 };
  50
  51 struct clk_pll_freq_table {
  52         unsigned long   input_rate;
  53         unsigned long   output_rate;
  54         u16             n;
  55         u16             m;
  56         u8              p;
  57         u8              cpcon;
  58 };
  59
  60 struct clk_ops {
  61         void            (*init)(struct clk *);
  62         int             (*enable)(struct clk *);
  63         void            (*disable)(struct clk *);
  64         int             (*set_parent)(struct clk *, struct clk *);
  65         int             (*set_rate)(struct clk *, unsigned long);
  66         long            (*round_rate)(struct clk *, unsigned long);
  67         void            (*reset)(struct clk *, bool);
  68 };
  69
  70 enum clk_state {
  71         UNINITIALIZED = 0,
  72         ON,
  73         OFF,
  74 };
  75
  76 struct clk {
  77         /* node for master clocks list */
  78         struct list_head        node;           /* node for list of all clocks */
  79         struct clk_lookup       lookup;
  80
  81 #ifdef CONFIG_DEBUG_FS
  82         struct dentry           *dent;
  83 #endif
  84         bool                    set;
  85         struct clk_ops          *ops;
  86         unsigned long           rate;
  87         unsigned long           max_rate;
  88         unsigned long           min_rate;
  89         u32                     flags;
  90         const char              *name;
  91
  92         u32                     refcnt;
  93         enum clk_state          state;
  94         struct clk              *parent;
  95         u32                     div;
  96         u32                     mul;
  97
  98         const struct clk_mux_sel        *inputs;
  99         u32                             reg;
 100         u32                             reg_shift;
 101
 102         struct list_head                shared_bus_list;
 103
 104         union {
 105                 struct {
 106                         unsigned int                    clk_num;
 107                 } periph;
 108                 struct {
 109                         unsigned long                   input_min;
 110                         unsigned long                   input_max;
 111                         unsigned long                   cf_min;
 112                         unsigned long                   cf_max;
 113                         unsigned long                   vco_min;
 114                         unsigned long                   vco_max;
 115                         const struct clk_pll_freq_table *freq_table;
 116                         int                             lock_delay;
 117                 } pll;
 118                 struct {
 119                         u32                             sel;
 120                         u32                             reg_mask;
 121                 } mux;
 122                 struct {
 123                         struct clk                      *main;
 124                         struct clk                      *backup;
 125                 } cpu;
 126                 struct {
 127                         struct list_head                node;
 128                         bool                            enabled;
 129                         unsigned long                   rate;
 130                 } shared_bus_user;
 131         } u;
 132
 133         spinlock_t spinlock;
 134 };
 135
 136 struct clk_duplicate {
 137         const char *name;
 138         struct clk_lookup lookup;
 139 };
 140
 141 struct tegra_clk_init_table {
 142         const char *name;
 143         const char *parent;
 144         unsigned long rate;
 145         bool enabled;
 146 };
 147
 148 void tegra2_init_clocks(void);
 149 void tegra2_periph_reset_deassert(struct clk *c);
 150 void tegra2_periph_reset_assert(struct clk *c);
 151 void clk_init(struct clk *clk);
 152 struct clk *tegra_get_clock_by_name(const char *name);
 153 unsigned long clk_measure_input_freq(void);
 154 int clk_reparent(struct clk *c, struct clk *parent);
 155 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 156 unsigned long clk_get_rate_locked(struct clk *c);
 157 int clk_set_rate_locked(struct clk *c, unsigned long rate);
 158 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 159
 160 #endif