arch/arm/plat-orion/time.c

   1 /*
   2  * arch/arm/plat-orion/time.c
   3  *
   4  * Marvell Orion SoC timer handling.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  *
  10  * Timer 0 is used as free-running clocksource, while timer 1 is
  11  * used as clock_event_device.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/timer.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <asm/sched_clock.h>
  21
  22 /*
  23  * MBus bridge block registers.
  24  */
  25 #define BRIDGE_CAUSE_OFF        0x0110
  26 #define BRIDGE_MASK_OFF         0x0114
  27 #define  BRIDGE_INT_TIMER0       0x0002
  28 #define  BRIDGE_INT_TIMER1       0x0004
  29
  30
  31 /*
  32  * Timer block registers.
  33  */
  34 #define TIMER_CTRL_OFF          0x0000
  35 #define  TIMER0_EN               0x0001
  36 #define  TIMER0_RELOAD_EN        0x0002
  37 #define  TIMER1_EN               0x0004
  38 #define  TIMER1_RELOAD_EN        0x0008
  39 #define TIMER0_RELOAD_OFF       0x0010
  40 #define TIMER0_VAL_OFF          0x0014
  41 #define TIMER1_RELOAD_OFF       0x0018
  42 #define TIMER1_VAL_OFF          0x001c
  43
  44
  45 /*
  46  * SoC-specific data.
  47  */
  48 static void __iomem *bridge_base;
  49 static u32 bridge_timer1_clr_mask;
  50 static void __iomem *timer_base;
  51
  52
  53 /*
  54  * Number of timer ticks per jiffy.
  55  */
  56 static u32 ticks_per_jiffy;
  57
  58
  59 /*
  60  * Orion's sched_clock implementation. It has a resolution of
  61  * at least 7.5ns (133MHz TCLK).
  62  */
  63 static DEFINE_CLOCK_DATA(cd);
  64
  65 unsigned long long notrace sched_clock(void)
  66 {
  67         u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
  68         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
  69 }
  70
  71
  72 static void notrace orion_update_sched_clock(void)
  73 {
  74         u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
  75         update_sched_clock(&cd, cyc, (u32)~0);
  76 }
  77
  78 static void __init setup_sched_clock(unsigned long tclk)
  79 {
  80         init_sched_clock(&cd, orion_update_sched_clock, 32, tclk);
  81 }
  82
  83 /*
  84  * Clockevent handling.
  85  */
  86 static int
  87 orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
  88 {
  89         unsigned long flags;
  90         u32 u;
  91
  92         if (delta == 0)
  93                 return -ETIME;
  94
  95         local_irq_save(flags);
  96
  97         /*
  98          * Clear and enable clockevent timer interrupt.
  99          */
 100         writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 101
 102         u = readl(bridge_base + BRIDGE_MASK_OFF);
 103         u |= BRIDGE_INT_TIMER1;
 104         writel(u, bridge_base + BRIDGE_MASK_OFF);
 105
 106         /*
 107          * Setup new clockevent timer value.
 108          */
 109         writel(delta, timer_base + TIMER1_VAL_OFF);
 110
 111         /*
 112          * Enable the timer.
 113          */
 114         u = readl(timer_base + TIMER_CTRL_OFF);
 115         u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
 116         writel(u, timer_base + TIMER_CTRL_OFF);
 117
 118         local_irq_restore(flags);
 119
 120         return 0;
 121 }
 122
 123 static void
 124 orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 125 {
 126         unsigned long flags;
 127         u32 u;
 128
 129         local_irq_save(flags);
 130         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 131                 /*
 132                  * Setup timer to fire at 1/HZ intervals.
 133                  */
 134                 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
 135                 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
 136
 137                 /*
 138                  * Enable timer interrupt.
 139                  */
 140                 u = readl(bridge_base + BRIDGE_MASK_OFF);
 141                 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 142
 143                 /*
 144                  * Enable timer.
 145                  */
 146                 u = readl(timer_base + TIMER_CTRL_OFF);
 147                 writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
 148                        timer_base + TIMER_CTRL_OFF);
 149         } else {
 150                 /*
 151                  * Disable timer.
 152                  */
 153                 u = readl(timer_base + TIMER_CTRL_OFF);
 154                 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
 155
 156                 /*
 157                  * Disable timer interrupt.
 158                  */
 159                 u = readl(bridge_base + BRIDGE_MASK_OFF);
 160                 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 161
 162                 /*
 163                  * ACK pending timer interrupt.
 164                  */
 165                 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 166
 167         }
 168         local_irq_restore(flags);
 169 }
 170
 171 static struct clock_event_device orion_clkevt = {
 172         .name           = "orion_tick",
 173         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 174         .shift          = 32,
 175         .rating         = 300,
 176         .set_next_event = orion_clkevt_next_event,
 177         .set_mode       = orion_clkevt_mode,
 178 };
 179
 180 static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
 181 {
 182         /*
 183          * ACK timer interrupt and call event handler.
 184          */
 185         writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 186         orion_clkevt.event_handler(&orion_clkevt);
 187
 188         return IRQ_HANDLED;
 189 }
 190
 191 static struct irqaction orion_timer_irq = {
 192         .name           = "orion_tick",
 193         .flags          = IRQF_DISABLED | IRQF_TIMER,
 194         .handler        = orion_timer_interrupt
 195 };
 196
 197 void __init
 198 orion_time_set_base(u32 _timer_base)
 199 {
 200         timer_base = (void __iomem *)_timer_base;
 201 }
 202
 203 void __init
 204 orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
 205                 unsigned int irq, unsigned int tclk)
 206 {
 207         u32 u;
 208
 209         /*
 210          * Set SoC-specific data.
 211          */
 212         bridge_base = (void __iomem *)_bridge_base;
 213         bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
 214
 215         ticks_per_jiffy = (tclk + HZ/2) / HZ;
 216
 217         /*
 218          * Set scale and timer for sched_clock.
 219          */
 220         setup_sched_clock(tclk);
 221
 222         /*
 223          * Setup free-running clocksource timer (interrupts
 224          * disabled).
 225          */
 226         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 227         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 228         u = readl(bridge_base + BRIDGE_MASK_OFF);
 229         writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
 230         u = readl(timer_base + TIMER_CTRL_OFF);
 231         writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
 232         clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
 233                 tclk, 300, 32, clocksource_mmio_readl_down);
 234
 235         /*
 236          * Setup clockevent timer (interrupt-driven).
 237          */
 238         setup_irq(irq, &orion_timer_irq);
 239         orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
 240         orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
 241         orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
 242         orion_clkevt.cpumask = cpumask_of(0);
 243         clockevents_register_device(&orion_clkevt);
 244 }