?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: Fix compilation bug in kprobes' twobyte_is_boostable
[linux-btrfs-devel.git] / arch / x86 / kvm / mmu.c
blob8e8da7960dbeed8be684c770a1ba4cc0c7653e08
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
29 #include <linux/mm.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 #include <asm/page.h>
40 #include <asm/cmpxchg.h>
41 #include <asm/io.h>
42 #include <asm/vmx.h>
43
44 /*
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
50 */
51 bool tdp_enabled = false;
52
53 enum {
54 AUDIT_PRE_PAGE_FAULT,
55 AUDIT_POST_PAGE_FAULT,
56 AUDIT_PRE_PTE_WRITE,
57 AUDIT_POST_PTE_WRITE,
58 AUDIT_PRE_SYNC,
59 AUDIT_POST_SYNC
60 };
61
62 char *audit_point_name[] = {
63 "pre page fault",
64 "post page fault",
65 "pre pte write",
66 "post pte write",
67 "pre sync",
68 "post sync"
69 };
70
71 #undef MMU_DEBUG
72
73 #ifdef MMU_DEBUG
74
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
77
78 #else
79
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
82
83 #endif
84
85 #ifdef MMU_DEBUG
86 static int dbg = 0;
87 module_param(dbg, bool, 0644);
88 #endif
89
90 static int oos_shadow = 1;
91 module_param(oos_shadow, bool, 0644);
92
93 #ifndef MMU_DEBUG
94 #define ASSERT(x) do { } while (0)
95 #else
96 #define ASSERT(x) \
97 if (!(x)) { \
98 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
99 __FILE__, __LINE__, #x); \
100 }
101 #endif
102
103 #define PTE_PREFETCH_NUM 8
104
105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
107
108 #define PT64_LEVEL_BITS 9
109
110 #define PT64_LEVEL_SHIFT(level) \
111 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
112
113 #define PT64_INDEX(address, level)\
114 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
115
116
117 #define PT32_LEVEL_BITS 10
118
119 #define PT32_LEVEL_SHIFT(level) \
120 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121
122 #define PT32_LVL_OFFSET_MASK(level) \
123 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT32_LEVEL_BITS))) - 1))
125
126 #define PT32_INDEX(address, level)\
127 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128
129
130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
131 #define PT64_DIR_BASE_ADDR_MASK \
132 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
133 #define PT64_LVL_ADDR_MASK(level) \
134 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135 * PT64_LEVEL_BITS))) - 1))
136 #define PT64_LVL_OFFSET_MASK(level) \
137 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT64_LEVEL_BITS))) - 1))
139
140 #define PT32_BASE_ADDR_MASK PAGE_MASK
141 #define PT32_DIR_BASE_ADDR_MASK \
142 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
143 #define PT32_LVL_ADDR_MASK(level) \
144 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
145 * PT32_LEVEL_BITS))) - 1))
146
147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
148 | PT64_NX_MASK)
149
150 #define PTE_LIST_EXT 4
151
152 #define ACC_EXEC_MASK 1
153 #define ACC_WRITE_MASK PT_WRITABLE_MASK
154 #define ACC_USER_MASK PT_USER_MASK
155 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
156
157 #include <trace/events/kvm.h>
158
159 #define CREATE_TRACE_POINTS
160 #include "mmutrace.h"
161
162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
163
164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
165
166 struct pte_list_desc {
167 u64 *sptes[PTE_LIST_EXT];
168 struct pte_list_desc *more;
169 };
170
171 struct kvm_shadow_walk_iterator {
172 u64 addr;
173 hpa_t shadow_addr;
174 u64 *sptep;
175 int level;
176 unsigned index;
177 };
178
179 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
180 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
181 shadow_walk_okay(&(_walker)); \
182 shadow_walk_next(&(_walker)))
183
184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
185 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
186 shadow_walk_okay(&(_walker)) && \
187 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
188 __shadow_walk_next(&(_walker), spte))
189
190 static struct kmem_cache *pte_list_desc_cache;
191 static struct kmem_cache *mmu_page_header_cache;
192 static struct percpu_counter kvm_total_used_mmu_pages;
193
194 static u64 __read_mostly shadow_nx_mask;
195 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
196 static u64 __read_mostly shadow_user_mask;
197 static u64 __read_mostly shadow_accessed_mask;
198 static u64 __read_mostly shadow_dirty_mask;
199 static u64 __read_mostly shadow_mmio_mask;
200
201 static void mmu_spte_set(u64 *sptep, u64 spte);
202
203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
204 {
205 shadow_mmio_mask = mmio_mask;
206 }
207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
208
209 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
210 {
211 access &= ACC_WRITE_MASK | ACC_USER_MASK;
212
213 trace_mark_mmio_spte(sptep, gfn, access);
214 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
215 }
216
217 static bool is_mmio_spte(u64 spte)
218 {
219 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
220 }
221
222 static gfn_t get_mmio_spte_gfn(u64 spte)
223 {
224 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
225 }
226
227 static unsigned get_mmio_spte_access(u64 spte)
228 {
229 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
230 }
231
232 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
233 {
234 if (unlikely(is_noslot_pfn(pfn))) {
235 mark_mmio_spte(sptep, gfn, access);
236 return true;
237 }
238
239 return false;
240 }
241
242 static inline u64 rsvd_bits(int s, int e)
243 {
244 return ((1ULL << (e - s + 1)) - 1) << s;
245 }
246
247 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
248 u64 dirty_mask, u64 nx_mask, u64 x_mask)
249 {
250 shadow_user_mask = user_mask;
251 shadow_accessed_mask = accessed_mask;
252 shadow_dirty_mask = dirty_mask;
253 shadow_nx_mask = nx_mask;
254 shadow_x_mask = x_mask;
255 }
256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
257
258 static int is_cpuid_PSE36(void)
259 {
260 return 1;
261 }
262
263 static int is_nx(struct kvm_vcpu *vcpu)
264 {
265 return vcpu->arch.efer & EFER_NX;
266 }
267
268 static int is_shadow_present_pte(u64 pte)
269 {
270 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
271 }
272
273 static int is_large_pte(u64 pte)
274 {
275 return pte & PT_PAGE_SIZE_MASK;
276 }
277
278 static int is_dirty_gpte(unsigned long pte)
279 {
280 return pte & PT_DIRTY_MASK;
281 }
282
283 static int is_rmap_spte(u64 pte)
284 {
285 return is_shadow_present_pte(pte);
286 }
287
288 static int is_last_spte(u64 pte, int level)
289 {
290 if (level == PT_PAGE_TABLE_LEVEL)
291 return 1;
292 if (is_large_pte(pte))
293 return 1;
294 return 0;
295 }
296
297 static pfn_t spte_to_pfn(u64 pte)
298 {
299 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
300 }
301
302 static gfn_t pse36_gfn_delta(u32 gpte)
303 {
304 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
305
306 return (gpte & PT32_DIR_PSE36_MASK) << shift;
307 }
308
309 #ifdef CONFIG_X86_64
310 static void __set_spte(u64 *sptep, u64 spte)
311 {
312 *sptep = spte;
313 }
314
315 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
316 {
317 *sptep = spte;
318 }
319
320 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
321 {
322 return xchg(sptep, spte);
323 }
324
325 static u64 __get_spte_lockless(u64 *sptep)
326 {
327 return ACCESS_ONCE(*sptep);
328 }
329
330 static bool __check_direct_spte_mmio_pf(u64 spte)
331 {
332 /* It is valid if the spte is zapped. */
333 return spte == 0ull;
334 }
335 #else
336 union split_spte {
337 struct {
338 u32 spte_low;
339 u32 spte_high;
340 };
341 u64 spte;
342 };
343
344 static void count_spte_clear(u64 *sptep, u64 spte)
345 {
346 struct kvm_mmu_page *sp = page_header(__pa(sptep));
347
348 if (is_shadow_present_pte(spte))
349 return;
350
351 /* Ensure the spte is completely set before we increase the count */
352 smp_wmb();
353 sp->clear_spte_count++;
354 }
355
356 static void __set_spte(u64 *sptep, u64 spte)
357 {
358 union split_spte *ssptep, sspte;
359
360 ssptep = (union split_spte *)sptep;
361 sspte = (union split_spte)spte;
362
363 ssptep->spte_high = sspte.spte_high;
364
365 /*
366 * If we map the spte from nonpresent to present, We should store
367 * the high bits firstly, then set present bit, so cpu can not
368 * fetch this spte while we are setting the spte.
369 */
370 smp_wmb();
371
372 ssptep->spte_low = sspte.spte_low;
373 }
374
375 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
376 {
377 union split_spte *ssptep, sspte;
378
379 ssptep = (union split_spte *)sptep;
380 sspte = (union split_spte)spte;
381
382 ssptep->spte_low = sspte.spte_low;
383
384 /*
385 * If we map the spte from present to nonpresent, we should clear
386 * present bit firstly to avoid vcpu fetch the old high bits.
387 */
388 smp_wmb();
389
390 ssptep->spte_high = sspte.spte_high;
391 count_spte_clear(sptep, spte);
392 }
393
394 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
395 {
396 union split_spte *ssptep, sspte, orig;
397
398 ssptep = (union split_spte *)sptep;
399 sspte = (union split_spte)spte;
400
401 /* xchg acts as a barrier before the setting of the high bits */
402 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
403 orig.spte_high = ssptep->spte_high;
404 ssptep->spte_high = sspte.spte_high;
405 count_spte_clear(sptep, spte);
406
407 return orig.spte;
408 }
409
410 /*
411 * The idea using the light way get the spte on x86_32 guest is from
412 * gup_get_pte(arch/x86/mm/gup.c).
413 * The difference is we can not catch the spte tlb flush if we leave
414 * guest mode, so we emulate it by increase clear_spte_count when spte
415 * is cleared.
416 */
417 static u64 __get_spte_lockless(u64 *sptep)
418 {
419 struct kvm_mmu_page *sp = page_header(__pa(sptep));
420 union split_spte spte, *orig = (union split_spte *)sptep;
421 int count;
422
423 retry:
424 count = sp->clear_spte_count;
425 smp_rmb();
426
427 spte.spte_low = orig->spte_low;
428 smp_rmb();
429
430 spte.spte_high = orig->spte_high;
431 smp_rmb();
432
433 if (unlikely(spte.spte_low != orig->spte_low ||
434 count != sp->clear_spte_count))
435 goto retry;
436
437 return spte.spte;
438 }
439
440 static bool __check_direct_spte_mmio_pf(u64 spte)
441 {
442 union split_spte sspte = (union split_spte)spte;
443 u32 high_mmio_mask = shadow_mmio_mask >> 32;
444
445 /* It is valid if the spte is zapped. */
446 if (spte == 0ull)
447 return true;
448
449 /* It is valid if the spte is being zapped. */
450 if (sspte.spte_low == 0ull &&
451 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
452 return true;
453
454 return false;
455 }
456 #endif
457
458 static bool spte_has_volatile_bits(u64 spte)
459 {
460 if (!shadow_accessed_mask)
461 return false;
462
463 if (!is_shadow_present_pte(spte))
464 return false;
465
466 if ((spte & shadow_accessed_mask) &&
467 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
468 return false;
469
470 return true;
471 }
472
473 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
474 {
475 return (old_spte & bit_mask) && !(new_spte & bit_mask);
476 }
477
478 /* Rules for using mmu_spte_set:
479 * Set the sptep from nonpresent to present.
480 * Note: the sptep being assigned *must* be either not present
481 * or in a state where the hardware will not attempt to update
482 * the spte.
483 */
484 static void mmu_spte_set(u64 *sptep, u64 new_spte)
485 {
486 WARN_ON(is_shadow_present_pte(*sptep));
487 __set_spte(sptep, new_spte);
488 }
489
490 /* Rules for using mmu_spte_update:
491 * Update the state bits, it means the mapped pfn is not changged.
492 */
493 static void mmu_spte_update(u64 *sptep, u64 new_spte)
494 {
495 u64 mask, old_spte = *sptep;
496
497 WARN_ON(!is_rmap_spte(new_spte));
498
499 if (!is_shadow_present_pte(old_spte))
500 return mmu_spte_set(sptep, new_spte);
501
502 new_spte |= old_spte & shadow_dirty_mask;
503
504 mask = shadow_accessed_mask;
505 if (is_writable_pte(old_spte))
506 mask |= shadow_dirty_mask;
507
508 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
509 __update_clear_spte_fast(sptep, new_spte);
510 else
511 old_spte = __update_clear_spte_slow(sptep, new_spte);
512
513 if (!shadow_accessed_mask)
514 return;
515
516 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
517 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
518 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
519 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
520 }
521
522 /*
523 * Rules for using mmu_spte_clear_track_bits:
524 * It sets the sptep from present to nonpresent, and track the
525 * state bits, it is used to clear the last level sptep.
526 */
527 static int mmu_spte_clear_track_bits(u64 *sptep)
528 {
529 pfn_t pfn;
530 u64 old_spte = *sptep;
531
532 if (!spte_has_volatile_bits(old_spte))
533 __update_clear_spte_fast(sptep, 0ull);
534 else
535 old_spte = __update_clear_spte_slow(sptep, 0ull);
536
537 if (!is_rmap_spte(old_spte))
538 return 0;
539
540 pfn = spte_to_pfn(old_spte);
541 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
542 kvm_set_pfn_accessed(pfn);
543 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
544 kvm_set_pfn_dirty(pfn);
545 return 1;
546 }
547
548 /*
549 * Rules for using mmu_spte_clear_no_track:
550 * Directly clear spte without caring the state bits of sptep,
551 * it is used to set the upper level spte.
552 */
553 static void mmu_spte_clear_no_track(u64 *sptep)
554 {
555 __update_clear_spte_fast(sptep, 0ull);
556 }
557
558 static u64 mmu_spte_get_lockless(u64 *sptep)
559 {
560 return __get_spte_lockless(sptep);
561 }
562
563 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
564 {
565 rcu_read_lock();
566 atomic_inc(&vcpu->kvm->arch.reader_counter);
567
568 /* Increase the counter before walking shadow page table */
569 smp_mb__after_atomic_inc();
570 }
571
572 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
573 {
574 /* Decrease the counter after walking shadow page table finished */
575 smp_mb__before_atomic_dec();
576 atomic_dec(&vcpu->kvm->arch.reader_counter);
577 rcu_read_unlock();
578 }
579
580 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
581 struct kmem_cache *base_cache, int min)
582 {
583 void *obj;
584
585 if (cache->nobjs >= min)
586 return 0;
587 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
588 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
589 if (!obj)
590 return -ENOMEM;
591 cache->objects[cache->nobjs++] = obj;
592 }
593 return 0;
594 }
595
596 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
597 struct kmem_cache *cache)
598 {
599 while (mc->nobjs)
600 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
601 }
602
603 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
604 int min)
605 {
606 void *page;
607
608 if (cache->nobjs >= min)
609 return 0;
610 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
611 page = (void *)__get_free_page(GFP_KERNEL);
612 if (!page)
613 return -ENOMEM;
614 cache->objects[cache->nobjs++] = page;
615 }
616 return 0;
617 }
618
619 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
620 {
621 while (mc->nobjs)
622 free_page((unsigned long)mc->objects[--mc->nobjs]);
623 }
624
625 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
626 {
627 int r;
628
629 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
630 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
631 if (r)
632 goto out;
633 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
634 if (r)
635 goto out;
636 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
637 mmu_page_header_cache, 4);
638 out:
639 return r;
640 }
641
642 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
643 {
644 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
645 pte_list_desc_cache);
646 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
647 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
648 mmu_page_header_cache);
649 }
650
651 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
652 size_t size)
653 {
654 void *p;
655
656 BUG_ON(!mc->nobjs);
657 p = mc->objects[--mc->nobjs];
658 return p;
659 }
660
661 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
662 {
663 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
664 sizeof(struct pte_list_desc));
665 }
666
667 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
668 {
669 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
670 }
671
672 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
673 {
674 if (!sp->role.direct)
675 return sp->gfns[index];
676
677 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
678 }
679
680 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
681 {
682 if (sp->role.direct)
683 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
684 else
685 sp->gfns[index] = gfn;
686 }
687
688 /*
689 * Return the pointer to the large page information for a given gfn,
690 * handling slots that are not large page aligned.
691 */
692 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
693 struct kvm_memory_slot *slot,
694 int level)
695 {
696 unsigned long idx;
697
698 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
699 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
700 return &slot->lpage_info[level - 2][idx];
701 }
702
703 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
704 {
705 struct kvm_memory_slot *slot;
706 struct kvm_lpage_info *linfo;
707 int i;
708
709 slot = gfn_to_memslot(kvm, gfn);
710 for (i = PT_DIRECTORY_LEVEL;
711 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
712 linfo = lpage_info_slot(gfn, slot, i);
713 linfo->write_count += 1;
714 }
715 kvm->arch.indirect_shadow_pages++;
716 }
717
718 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
719 {
720 struct kvm_memory_slot *slot;
721 struct kvm_lpage_info *linfo;
722 int i;
723
724 slot = gfn_to_memslot(kvm, gfn);
725 for (i = PT_DIRECTORY_LEVEL;
726 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
727 linfo = lpage_info_slot(gfn, slot, i);
728 linfo->write_count -= 1;
729 WARN_ON(linfo->write_count < 0);
730 }
731 kvm->arch.indirect_shadow_pages--;
732 }
733
734 static int has_wrprotected_page(struct kvm *kvm,
735 gfn_t gfn,
736 int level)
737 {
738 struct kvm_memory_slot *slot;
739 struct kvm_lpage_info *linfo;
740
741 slot = gfn_to_memslot(kvm, gfn);
742 if (slot) {
743 linfo = lpage_info_slot(gfn, slot, level);
744 return linfo->write_count;
745 }
746
747 return 1;
748 }
749
750 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
751 {
752 unsigned long page_size;
753 int i, ret = 0;
754
755 page_size = kvm_host_page_size(kvm, gfn);
756
757 for (i = PT_PAGE_TABLE_LEVEL;
758 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
759 if (page_size >= KVM_HPAGE_SIZE(i))
760 ret = i;
761 else
762 break;
763 }
764
765 return ret;
766 }
767
768 static struct kvm_memory_slot *
769 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
770 bool no_dirty_log)
771 {
772 struct kvm_memory_slot *slot;
773
774 slot = gfn_to_memslot(vcpu->kvm, gfn);
775 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
776 (no_dirty_log && slot->dirty_bitmap))
777 slot = NULL;
778
779 return slot;
780 }
781
782 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
783 {
784 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
785 }
786
787 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
788 {
789 int host_level, level, max_level;
790
791 host_level = host_mapping_level(vcpu->kvm, large_gfn);
792
793 if (host_level == PT_PAGE_TABLE_LEVEL)
794 return host_level;
795
796 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
797 kvm_x86_ops->get_lpage_level() : host_level;
798
799 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
800 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
801 break;
802
803 return level - 1;
804 }
805
806 /*
807 * Pte mapping structures:
808 *
809 * If pte_list bit zero is zero, then pte_list point to the spte.
810 *
811 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
812 * pte_list_desc containing more mappings.
813 *
814 * Returns the number of pte entries before the spte was added or zero if
815 * the spte was not added.
816 *
817 */
818 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
819 unsigned long *pte_list)
820 {
821 struct pte_list_desc *desc;
822 int i, count = 0;
823
824 if (!*pte_list) {
825 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
826 *pte_list = (unsigned long)spte;
827 } else if (!(*pte_list & 1)) {
828 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
829 desc = mmu_alloc_pte_list_desc(vcpu);
830 desc->sptes[0] = (u64 *)*pte_list;
831 desc->sptes[1] = spte;
832 *pte_list = (unsigned long)desc | 1;
833 ++count;
834 } else {
835 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
836 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
837 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
838 desc = desc->more;
839 count += PTE_LIST_EXT;
840 }
841 if (desc->sptes[PTE_LIST_EXT-1]) {
842 desc->more = mmu_alloc_pte_list_desc(vcpu);
843 desc = desc->more;
844 }
845 for (i = 0; desc->sptes[i]; ++i)
846 ++count;
847 desc->sptes[i] = spte;
848 }
849 return count;
850 }
851
852 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
853 {
854 struct pte_list_desc *desc;
855 u64 *prev_spte;
856 int i;
857
858 if (!*pte_list)
859 return NULL;
860 else if (!(*pte_list & 1)) {
861 if (!spte)
862 return (u64 *)*pte_list;
863 return NULL;
864 }
865 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
866 prev_spte = NULL;
867 while (desc) {
868 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
869 if (prev_spte == spte)
870 return desc->sptes[i];
871 prev_spte = desc->sptes[i];
872 }
873 desc = desc->more;
874 }
875 return NULL;
876 }
877
878 static void
879 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
880 int i, struct pte_list_desc *prev_desc)
881 {
882 int j;
883
884 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
885 ;
886 desc->sptes[i] = desc->sptes[j];
887 desc->sptes[j] = NULL;
888 if (j != 0)
889 return;
890 if (!prev_desc && !desc->more)
891 *pte_list = (unsigned long)desc->sptes[0];
892 else
893 if (prev_desc)
894 prev_desc->more = desc->more;
895 else
896 *pte_list = (unsigned long)desc->more | 1;
897 mmu_free_pte_list_desc(desc);
898 }
899
900 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
901 {
902 struct pte_list_desc *desc;
903 struct pte_list_desc *prev_desc;
904 int i;
905
906 if (!*pte_list) {
907 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
908 BUG();
909 } else if (!(*pte_list & 1)) {
910 rmap_printk("pte_list_remove: %p 1->0\n", spte);
911 if ((u64 *)*pte_list != spte) {
912 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
913 BUG();
914 }
915 *pte_list = 0;
916 } else {
917 rmap_printk("pte_list_remove: %p many->many\n", spte);
918 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
919 prev_desc = NULL;
920 while (desc) {
921 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
922 if (desc->sptes[i] == spte) {
923 pte_list_desc_remove_entry(pte_list,
924 desc, i,
925 prev_desc);
926 return;
927 }
928 prev_desc = desc;
929 desc = desc->more;
930 }
931 pr_err("pte_list_remove: %p many->many\n", spte);
932 BUG();
933 }
934 }
935
936 typedef void (*pte_list_walk_fn) (u64 *spte);
937 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
938 {
939 struct pte_list_desc *desc;
940 int i;
941
942 if (!*pte_list)
943 return;
944
945 if (!(*pte_list & 1))
946 return fn((u64 *)*pte_list);
947
948 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
949 while (desc) {
950 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
951 fn(desc->sptes[i]);
952 desc = desc->more;
953 }
954 }
955
956 /*
957 * Take gfn and return the reverse mapping to it.
958 */
959 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
960 {
961 struct kvm_memory_slot *slot;
962 struct kvm_lpage_info *linfo;
963
964 slot = gfn_to_memslot(kvm, gfn);
965 if (likely(level == PT_PAGE_TABLE_LEVEL))
966 return &slot->rmap[gfn - slot->base_gfn];
967
968 linfo = lpage_info_slot(gfn, slot, level);
969
970 return &linfo->rmap_pde;
971 }
972
973 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
974 {
975 struct kvm_mmu_page *sp;
976 unsigned long *rmapp;
977
978 sp = page_header(__pa(spte));
979 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
980 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
981 return pte_list_add(vcpu, spte, rmapp);
982 }
983
984 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
985 {
986 return pte_list_next(rmapp, spte);
987 }
988
989 static void rmap_remove(struct kvm *kvm, u64 *spte)
990 {
991 struct kvm_mmu_page *sp;
992 gfn_t gfn;
993 unsigned long *rmapp;
994
995 sp = page_header(__pa(spte));
996 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
997 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
998 pte_list_remove(spte, rmapp);
999 }
1000
1001 static void drop_spte(struct kvm *kvm, u64 *sptep)
1002 {
1003 if (mmu_spte_clear_track_bits(sptep))
1004 rmap_remove(kvm, sptep);
1005 }
1006
1007 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1008 {
1009 unsigned long *rmapp;
1010 u64 *spte;
1011 int i, write_protected = 0;
1012
1013 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
1014
1015 spte = rmap_next(kvm, rmapp, NULL);
1016 while (spte) {
1017 BUG_ON(!spte);
1018 BUG_ON(!(*spte & PT_PRESENT_MASK));
1019 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1020 if (is_writable_pte(*spte)) {
1021 mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1022 write_protected = 1;
1023 }
1024 spte = rmap_next(kvm, rmapp, spte);
1025 }
1026
1027 /* check for huge page mappings */
1028 for (i = PT_DIRECTORY_LEVEL;
1029 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1030 rmapp = gfn_to_rmap(kvm, gfn, i);
1031 spte = rmap_next(kvm, rmapp, NULL);
1032 while (spte) {
1033 BUG_ON(!spte);
1034 BUG_ON(!(*spte & PT_PRESENT_MASK));
1035 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
1036 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1037 if (is_writable_pte(*spte)) {
1038 drop_spte(kvm, spte);
1039 --kvm->stat.lpages;
1040 spte = NULL;
1041 write_protected = 1;
1042 }
1043 spte = rmap_next(kvm, rmapp, spte);
1044 }
1045 }
1046
1047 return write_protected;
1048 }
1049
1050 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1051 unsigned long data)
1052 {
1053 u64 *spte;
1054 int need_tlb_flush = 0;
1055
1056 while ((spte = rmap_next(kvm, rmapp, NULL))) {
1057 BUG_ON(!(*spte & PT_PRESENT_MASK));
1058 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1059 drop_spte(kvm, spte);
1060 need_tlb_flush = 1;
1061 }
1062 return need_tlb_flush;
1063 }
1064
1065 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1066 unsigned long data)
1067 {
1068 int need_flush = 0;
1069 u64 *spte, new_spte;
1070 pte_t *ptep = (pte_t *)data;
1071 pfn_t new_pfn;
1072
1073 WARN_ON(pte_huge(*ptep));
1074 new_pfn = pte_pfn(*ptep);
1075 spte = rmap_next(kvm, rmapp, NULL);
1076 while (spte) {
1077 BUG_ON(!is_shadow_present_pte(*spte));
1078 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1079 need_flush = 1;
1080 if (pte_write(*ptep)) {
1081 drop_spte(kvm, spte);
1082 spte = rmap_next(kvm, rmapp, NULL);
1083 } else {
1084 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1085 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1086
1087 new_spte &= ~PT_WRITABLE_MASK;
1088 new_spte &= ~SPTE_HOST_WRITEABLE;
1089 new_spte &= ~shadow_accessed_mask;
1090 mmu_spte_clear_track_bits(spte);
1091 mmu_spte_set(spte, new_spte);
1092 spte = rmap_next(kvm, rmapp, spte);
1093 }
1094 }
1095 if (need_flush)
1096 kvm_flush_remote_tlbs(kvm);
1097
1098 return 0;
1099 }
1100
1101 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1102 unsigned long data,
1103 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1104 unsigned long data))
1105 {
1106 int i, j;
1107 int ret;
1108 int retval = 0;
1109 struct kvm_memslots *slots;
1110
1111 slots = kvm_memslots(kvm);
1112
1113 for (i = 0; i < slots->nmemslots; i++) {
1114 struct kvm_memory_slot *memslot = &slots->memslots[i];
1115 unsigned long start = memslot->userspace_addr;
1116 unsigned long end;
1117
1118 end = start + (memslot->npages << PAGE_SHIFT);
1119 if (hva >= start && hva < end) {
1120 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1121 gfn_t gfn = memslot->base_gfn + gfn_offset;
1122
1123 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1124
1125 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1126 struct kvm_lpage_info *linfo;
1127
1128 linfo = lpage_info_slot(gfn, memslot,
1129 PT_DIRECTORY_LEVEL + j);
1130 ret |= handler(kvm, &linfo->rmap_pde, data);
1131 }
1132 trace_kvm_age_page(hva, memslot, ret);
1133 retval |= ret;
1134 }
1135 }
1136
1137 return retval;
1138 }
1139
1140 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1141 {
1142 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1143 }
1144
1145 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1146 {
1147 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1148 }
1149
1150 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1151 unsigned long data)
1152 {
1153 u64 *spte;
1154 int young = 0;
1155
1156 /*
1157 * Emulate the accessed bit for EPT, by checking if this page has
1158 * an EPT mapping, and clearing it if it does. On the next access,
1159 * a new EPT mapping will be established.
1160 * This has some overhead, but not as much as the cost of swapping
1161 * out actively used pages or breaking up actively used hugepages.
1162 */
1163 if (!shadow_accessed_mask)
1164 return kvm_unmap_rmapp(kvm, rmapp, data);
1165
1166 spte = rmap_next(kvm, rmapp, NULL);
1167 while (spte) {
1168 int _young;
1169 u64 _spte = *spte;
1170 BUG_ON(!(_spte & PT_PRESENT_MASK));
1171 _young = _spte & PT_ACCESSED_MASK;
1172 if (_young) {
1173 young = 1;
1174 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1175 }
1176 spte = rmap_next(kvm, rmapp, spte);
1177 }
1178 return young;
1179 }
1180
1181 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1182 unsigned long data)
1183 {
1184 u64 *spte;
1185 int young = 0;
1186
1187 /*
1188 * If there's no access bit in the secondary pte set by the
1189 * hardware it's up to gup-fast/gup to set the access bit in
1190 * the primary pte or in the page structure.
1191 */
1192 if (!shadow_accessed_mask)
1193 goto out;
1194
1195 spte = rmap_next(kvm, rmapp, NULL);
1196 while (spte) {
1197 u64 _spte = *spte;
1198 BUG_ON(!(_spte & PT_PRESENT_MASK));
1199 young = _spte & PT_ACCESSED_MASK;
1200 if (young) {
1201 young = 1;
1202 break;
1203 }
1204 spte = rmap_next(kvm, rmapp, spte);
1205 }
1206 out:
1207 return young;
1208 }
1209
1210 #define RMAP_RECYCLE_THRESHOLD 1000
1211
1212 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1213 {
1214 unsigned long *rmapp;
1215 struct kvm_mmu_page *sp;
1216
1217 sp = page_header(__pa(spte));
1218
1219 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1220
1221 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1222 kvm_flush_remote_tlbs(vcpu->kvm);
1223 }
1224
1225 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1226 {
1227 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1228 }
1229
1230 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1231 {
1232 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1233 }
1234
1235 #ifdef MMU_DEBUG
1236 static int is_empty_shadow_page(u64 *spt)
1237 {
1238 u64 *pos;
1239 u64 *end;
1240
1241 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1242 if (is_shadow_present_pte(*pos)) {
1243 printk(KERN_ERR "%s: %p %llx\n", __func__,
1244 pos, *pos);
1245 return 0;
1246 }
1247 return 1;
1248 }
1249 #endif
1250
1251 /*
1252 * This value is the sum of all of the kvm instances's
1253 * kvm->arch.n_used_mmu_pages values. We need a global,
1254 * aggregate version in order to make the slab shrinker
1255 * faster
1256 */
1257 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1258 {
1259 kvm->arch.n_used_mmu_pages += nr;
1260 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1261 }
1262
1263 /*
1264 * Remove the sp from shadow page cache, after call it,
1265 * we can not find this sp from the cache, and the shadow
1266 * page table is still valid.
1267 * It should be under the protection of mmu lock.
1268 */
1269 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1270 {
1271 ASSERT(is_empty_shadow_page(sp->spt));
1272 hlist_del(&sp->hash_link);
1273 if (!sp->role.direct)
1274 free_page((unsigned long)sp->gfns);
1275 }
1276
1277 /*
1278 * Free the shadow page table and the sp, we can do it
1279 * out of the protection of mmu lock.
1280 */
1281 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1282 {
1283 list_del(&sp->link);
1284 free_page((unsigned long)sp->spt);
1285 kmem_cache_free(mmu_page_header_cache, sp);
1286 }
1287
1288 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1289 {
1290 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1291 }
1292
1293 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1294 struct kvm_mmu_page *sp, u64 *parent_pte)
1295 {
1296 if (!parent_pte)
1297 return;
1298
1299 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1300 }
1301
1302 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1303 u64 *parent_pte)
1304 {
1305 pte_list_remove(parent_pte, &sp->parent_ptes);
1306 }
1307
1308 static void drop_parent_pte(struct kvm_mmu_page *sp,
1309 u64 *parent_pte)
1310 {
1311 mmu_page_remove_parent_pte(sp, parent_pte);
1312 mmu_spte_clear_no_track(parent_pte);
1313 }
1314
1315 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1316 u64 *parent_pte, int direct)
1317 {
1318 struct kvm_mmu_page *sp;
1319 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1320 sizeof *sp);
1321 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1322 if (!direct)
1323 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1324 PAGE_SIZE);
1325 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1326 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1327 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1328 sp->parent_ptes = 0;
1329 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1330 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1331 return sp;
1332 }
1333
1334 static void mark_unsync(u64 *spte);
1335 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1336 {
1337 pte_list_walk(&sp->parent_ptes, mark_unsync);
1338 }
1339
1340 static void mark_unsync(u64 *spte)
1341 {
1342 struct kvm_mmu_page *sp;
1343 unsigned int index;
1344
1345 sp = page_header(__pa(spte));
1346 index = spte - sp->spt;
1347 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1348 return;
1349 if (sp->unsync_children++)
1350 return;
1351 kvm_mmu_mark_parents_unsync(sp);
1352 }
1353
1354 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1355 struct kvm_mmu_page *sp)
1356 {
1357 return 1;
1358 }
1359
1360 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1361 {
1362 }
1363
1364 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1365 struct kvm_mmu_page *sp, u64 *spte,
1366 const void *pte)
1367 {
1368 WARN_ON(1);
1369 }
1370
1371 #define KVM_PAGE_ARRAY_NR 16
1372
1373 struct kvm_mmu_pages {
1374 struct mmu_page_and_offset {
1375 struct kvm_mmu_page *sp;
1376 unsigned int idx;
1377 } page[KVM_PAGE_ARRAY_NR];
1378 unsigned int nr;
1379 };
1380
1381 #define for_each_unsync_children(bitmap, idx) \
1382 for (idx = find_first_bit(bitmap, 512); \
1383 idx < 512; \
1384 idx = find_next_bit(bitmap, 512, idx+1))
1385
1386 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1387 int idx)
1388 {
1389 int i;
1390
1391 if (sp->unsync)
1392 for (i=0; i < pvec->nr; i++)
1393 if (pvec->page[i].sp == sp)
1394 return 0;
1395
1396 pvec->page[pvec->nr].sp = sp;
1397 pvec->page[pvec->nr].idx = idx;
1398 pvec->nr++;
1399 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1400 }
1401
1402 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1403 struct kvm_mmu_pages *pvec)
1404 {
1405 int i, ret, nr_unsync_leaf = 0;
1406
1407 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1408 struct kvm_mmu_page *child;
1409 u64 ent = sp->spt[i];
1410
1411 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1412 goto clear_child_bitmap;
1413
1414 child = page_header(ent & PT64_BASE_ADDR_MASK);
1415
1416 if (child->unsync_children) {
1417 if (mmu_pages_add(pvec, child, i))
1418 return -ENOSPC;
1419
1420 ret = __mmu_unsync_walk(child, pvec);
1421 if (!ret)
1422 goto clear_child_bitmap;
1423 else if (ret > 0)
1424 nr_unsync_leaf += ret;
1425 else
1426 return ret;
1427 } else if (child->unsync) {
1428 nr_unsync_leaf++;
1429 if (mmu_pages_add(pvec, child, i))
1430 return -ENOSPC;
1431 } else
1432 goto clear_child_bitmap;
1433
1434 continue;
1435
1436 clear_child_bitmap:
1437 __clear_bit(i, sp->unsync_child_bitmap);
1438 sp->unsync_children--;
1439 WARN_ON((int)sp->unsync_children < 0);
1440 }
1441
1442
1443 return nr_unsync_leaf;
1444 }
1445
1446 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1447 struct kvm_mmu_pages *pvec)
1448 {
1449 if (!sp->unsync_children)
1450 return 0;
1451
1452 mmu_pages_add(pvec, sp, 0);
1453 return __mmu_unsync_walk(sp, pvec);
1454 }
1455
1456 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1457 {
1458 WARN_ON(!sp->unsync);
1459 trace_kvm_mmu_sync_page(sp);
1460 sp->unsync = 0;
1461 --kvm->stat.mmu_unsync;
1462 }
1463
1464 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1465 struct list_head *invalid_list);
1466 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1467 struct list_head *invalid_list);
1468
1469 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1470 hlist_for_each_entry(sp, pos, \
1471 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1472 if ((sp)->gfn != (gfn)) {} else
1473
1474 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1475 hlist_for_each_entry(sp, pos, \
1476 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1477 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1478 (sp)->role.invalid) {} else
1479
1480 /* @sp->gfn should be write-protected at the call site */
1481 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1482 struct list_head *invalid_list, bool clear_unsync)
1483 {
1484 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1485 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1486 return 1;
1487 }
1488
1489 if (clear_unsync)
1490 kvm_unlink_unsync_page(vcpu->kvm, sp);
1491
1492 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1493 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1494 return 1;
1495 }
1496
1497 kvm_mmu_flush_tlb(vcpu);
1498 return 0;
1499 }
1500
1501 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1502 struct kvm_mmu_page *sp)
1503 {
1504 LIST_HEAD(invalid_list);
1505 int ret;
1506
1507 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1508 if (ret)
1509 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1510
1511 return ret;
1512 }
1513
1514 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1515 struct list_head *invalid_list)
1516 {
1517 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1518 }
1519
1520 /* @gfn should be write-protected at the call site */
1521 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1522 {
1523 struct kvm_mmu_page *s;
1524 struct hlist_node *node;
1525 LIST_HEAD(invalid_list);
1526 bool flush = false;
1527
1528 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1529 if (!s->unsync)
1530 continue;
1531
1532 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1533 kvm_unlink_unsync_page(vcpu->kvm, s);
1534 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1535 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1536 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1537 continue;
1538 }
1539 flush = true;
1540 }
1541
1542 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1543 if (flush)
1544 kvm_mmu_flush_tlb(vcpu);
1545 }
1546
1547 struct mmu_page_path {
1548 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1549 unsigned int idx[PT64_ROOT_LEVEL-1];
1550 };
1551
1552 #define for_each_sp(pvec, sp, parents, i) \
1553 for (i = mmu_pages_next(&pvec, &parents, -1), \
1554 sp = pvec.page[i].sp; \
1555 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1556 i = mmu_pages_next(&pvec, &parents, i))
1557
1558 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1559 struct mmu_page_path *parents,
1560 int i)
1561 {
1562 int n;
1563
1564 for (n = i+1; n < pvec->nr; n++) {
1565 struct kvm_mmu_page *sp = pvec->page[n].sp;
1566
1567 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1568 parents->idx[0] = pvec->page[n].idx;
1569 return n;
1570 }
1571
1572 parents->parent[sp->role.level-2] = sp;
1573 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1574 }
1575
1576 return n;
1577 }
1578
1579 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1580 {
1581 struct kvm_mmu_page *sp;
1582 unsigned int level = 0;
1583
1584 do {
1585 unsigned int idx = parents->idx[level];
1586
1587 sp = parents->parent[level];
1588 if (!sp)
1589 return;
1590
1591 --sp->unsync_children;
1592 WARN_ON((int)sp->unsync_children < 0);
1593 __clear_bit(idx, sp->unsync_child_bitmap);
1594 level++;
1595 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1596 }
1597
1598 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1599 struct mmu_page_path *parents,
1600 struct kvm_mmu_pages *pvec)
1601 {
1602 parents->parent[parent->role.level-1] = NULL;
1603 pvec->nr = 0;
1604 }
1605
1606 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1607 struct kvm_mmu_page *parent)
1608 {
1609 int i;
1610 struct kvm_mmu_page *sp;
1611 struct mmu_page_path parents;
1612 struct kvm_mmu_pages pages;
1613 LIST_HEAD(invalid_list);
1614
1615 kvm_mmu_pages_init(parent, &parents, &pages);
1616 while (mmu_unsync_walk(parent, &pages)) {
1617 int protected = 0;
1618
1619 for_each_sp(pages, sp, parents, i)
1620 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1621
1622 if (protected)
1623 kvm_flush_remote_tlbs(vcpu->kvm);
1624
1625 for_each_sp(pages, sp, parents, i) {
1626 kvm_sync_page(vcpu, sp, &invalid_list);
1627 mmu_pages_clear_parents(&parents);
1628 }
1629 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1630 cond_resched_lock(&vcpu->kvm->mmu_lock);
1631 kvm_mmu_pages_init(parent, &parents, &pages);
1632 }
1633 }
1634
1635 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1636 {
1637 int i;
1638
1639 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1640 sp->spt[i] = 0ull;
1641 }
1642
1643 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1644 gfn_t gfn,
1645 gva_t gaddr,
1646 unsigned level,
1647 int direct,
1648 unsigned access,
1649 u64 *parent_pte)
1650 {
1651 union kvm_mmu_page_role role;
1652 unsigned quadrant;
1653 struct kvm_mmu_page *sp;
1654 struct hlist_node *node;
1655 bool need_sync = false;
1656
1657 role = vcpu->arch.mmu.base_role;
1658 role.level = level;
1659 role.direct = direct;
1660 if (role.direct)
1661 role.cr4_pae = 0;
1662 role.access = access;
1663 if (!vcpu->arch.mmu.direct_map
1664 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1665 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1666 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1667 role.quadrant = quadrant;
1668 }
1669 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1670 if (!need_sync && sp->unsync)
1671 need_sync = true;
1672
1673 if (sp->role.word != role.word)
1674 continue;
1675
1676 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1677 break;
1678
1679 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1680 if (sp->unsync_children) {
1681 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1682 kvm_mmu_mark_parents_unsync(sp);
1683 } else if (sp->unsync)
1684 kvm_mmu_mark_parents_unsync(sp);
1685
1686 trace_kvm_mmu_get_page(sp, false);
1687 return sp;
1688 }
1689 ++vcpu->kvm->stat.mmu_cache_miss;
1690 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1691 if (!sp)
1692 return sp;
1693 sp->gfn = gfn;
1694 sp->role = role;
1695 hlist_add_head(&sp->hash_link,
1696 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1697 if (!direct) {
1698 if (rmap_write_protect(vcpu->kvm, gfn))
1699 kvm_flush_remote_tlbs(vcpu->kvm);
1700 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1701 kvm_sync_pages(vcpu, gfn);
1702
1703 account_shadowed(vcpu->kvm, gfn);
1704 }
1705 init_shadow_page_table(sp);
1706 trace_kvm_mmu_get_page(sp, true);
1707 return sp;
1708 }
1709
1710 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1711 struct kvm_vcpu *vcpu, u64 addr)
1712 {
1713 iterator->addr = addr;
1714 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1715 iterator->level = vcpu->arch.mmu.shadow_root_level;
1716
1717 if (iterator->level == PT64_ROOT_LEVEL &&
1718 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1719 !vcpu->arch.mmu.direct_map)
1720 --iterator->level;
1721
1722 if (iterator->level == PT32E_ROOT_LEVEL) {
1723 iterator->shadow_addr
1724 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1725 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1726 --iterator->level;
1727 if (!iterator->shadow_addr)
1728 iterator->level = 0;
1729 }
1730 }
1731
1732 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1733 {
1734 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1735 return false;
1736
1737 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1738 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1739 return true;
1740 }
1741
1742 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1743 u64 spte)
1744 {
1745 if (is_last_spte(spte, iterator->level)) {
1746 iterator->level = 0;
1747 return;
1748 }
1749
1750 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1751 --iterator->level;
1752 }
1753
1754 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1755 {
1756 return __shadow_walk_next(iterator, *iterator->sptep);
1757 }
1758
1759 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1760 {
1761 u64 spte;
1762
1763 spte = __pa(sp->spt)
1764 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1765 | PT_WRITABLE_MASK | PT_USER_MASK;
1766 mmu_spte_set(sptep, spte);
1767 }
1768
1769 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1770 {
1771 if (is_large_pte(*sptep)) {
1772 drop_spte(vcpu->kvm, sptep);
1773 kvm_flush_remote_tlbs(vcpu->kvm);
1774 }
1775 }
1776
1777 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1778 unsigned direct_access)
1779 {
1780 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1781 struct kvm_mmu_page *child;
1782
1783 /*
1784 * For the direct sp, if the guest pte's dirty bit
1785 * changed form clean to dirty, it will corrupt the
1786 * sp's access: allow writable in the read-only sp,
1787 * so we should update the spte at this point to get
1788 * a new sp with the correct access.
1789 */
1790 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1791 if (child->role.access == direct_access)
1792 return;
1793
1794 drop_parent_pte(child, sptep);
1795 kvm_flush_remote_tlbs(vcpu->kvm);
1796 }
1797 }
1798
1799 static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1800 u64 *spte)
1801 {
1802 u64 pte;
1803 struct kvm_mmu_page *child;
1804
1805 pte = *spte;
1806 if (is_shadow_present_pte(pte)) {
1807 if (is_last_spte(pte, sp->role.level))
1808 drop_spte(kvm, spte);
1809 else {
1810 child = page_header(pte & PT64_BASE_ADDR_MASK);
1811 drop_parent_pte(child, spte);
1812 }
1813 } else if (is_mmio_spte(pte))
1814 mmu_spte_clear_no_track(spte);
1815
1816 if (is_large_pte(pte))
1817 --kvm->stat.lpages;
1818 }
1819
1820 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1821 struct kvm_mmu_page *sp)
1822 {
1823 unsigned i;
1824
1825 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1826 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1827 }
1828
1829 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1830 {
1831 mmu_page_remove_parent_pte(sp, parent_pte);
1832 }
1833
1834 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1835 {
1836 int i;
1837 struct kvm_vcpu *vcpu;
1838
1839 kvm_for_each_vcpu(i, vcpu, kvm)
1840 vcpu->arch.last_pte_updated = NULL;
1841 }
1842
1843 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1844 {
1845 u64 *parent_pte;
1846
1847 while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1848 drop_parent_pte(sp, parent_pte);
1849 }
1850
1851 static int mmu_zap_unsync_children(struct kvm *kvm,
1852 struct kvm_mmu_page *parent,
1853 struct list_head *invalid_list)
1854 {
1855 int i, zapped = 0;
1856 struct mmu_page_path parents;
1857 struct kvm_mmu_pages pages;
1858
1859 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1860 return 0;
1861
1862 kvm_mmu_pages_init(parent, &parents, &pages);
1863 while (mmu_unsync_walk(parent, &pages)) {
1864 struct kvm_mmu_page *sp;
1865
1866 for_each_sp(pages, sp, parents, i) {
1867 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1868 mmu_pages_clear_parents(&parents);
1869 zapped++;
1870 }
1871 kvm_mmu_pages_init(parent, &parents, &pages);
1872 }
1873
1874 return zapped;
1875 }
1876
1877 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1878 struct list_head *invalid_list)
1879 {
1880 int ret;
1881
1882 trace_kvm_mmu_prepare_zap_page(sp);
1883 ++kvm->stat.mmu_shadow_zapped;
1884 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1885 kvm_mmu_page_unlink_children(kvm, sp);
1886 kvm_mmu_unlink_parents(kvm, sp);
1887 if (!sp->role.invalid && !sp->role.direct)
1888 unaccount_shadowed(kvm, sp->gfn);
1889 if (sp->unsync)
1890 kvm_unlink_unsync_page(kvm, sp);
1891 if (!sp->root_count) {
1892 /* Count self */
1893 ret++;
1894 list_move(&sp->link, invalid_list);
1895 kvm_mod_used_mmu_pages(kvm, -1);
1896 } else {
1897 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1898 kvm_reload_remote_mmus(kvm);
1899 }
1900
1901 sp->role.invalid = 1;
1902 kvm_mmu_reset_last_pte_updated(kvm);
1903 return ret;
1904 }
1905
1906 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1907 {
1908 struct kvm_mmu_page *sp;
1909
1910 list_for_each_entry(sp, invalid_list, link)
1911 kvm_mmu_isolate_page(sp);
1912 }
1913
1914 static void free_pages_rcu(struct rcu_head *head)
1915 {
1916 struct kvm_mmu_page *next, *sp;
1917
1918 sp = container_of(head, struct kvm_mmu_page, rcu);
1919 while (sp) {
1920 if (!list_empty(&sp->link))
1921 next = list_first_entry(&sp->link,
1922 struct kvm_mmu_page, link);
1923 else
1924 next = NULL;
1925 kvm_mmu_free_page(sp);
1926 sp = next;
1927 }
1928 }
1929
1930 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1931 struct list_head *invalid_list)
1932 {
1933 struct kvm_mmu_page *sp;
1934
1935 if (list_empty(invalid_list))
1936 return;
1937
1938 kvm_flush_remote_tlbs(kvm);
1939
1940 if (atomic_read(&kvm->arch.reader_counter)) {
1941 kvm_mmu_isolate_pages(invalid_list);
1942 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1943 list_del_init(invalid_list);
1944
1945 trace_kvm_mmu_delay_free_pages(sp);
1946 call_rcu(&sp->rcu, free_pages_rcu);
1947 return;
1948 }
1949
1950 do {
1951 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1952 WARN_ON(!sp->role.invalid || sp->root_count);
1953 kvm_mmu_isolate_page(sp);
1954 kvm_mmu_free_page(sp);
1955 } while (!list_empty(invalid_list));
1956
1957 }
1958
1959 /*
1960 * Changing the number of mmu pages allocated to the vm
1961 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1962 */
1963 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1964 {
1965 LIST_HEAD(invalid_list);
1966 /*
1967 * If we set the number of mmu pages to be smaller be than the
1968 * number of actived pages , we must to free some mmu pages before we
1969 * change the value
1970 */
1971
1972 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1973 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1974 !list_empty(&kvm->arch.active_mmu_pages)) {
1975 struct kvm_mmu_page *page;
1976
1977 page = container_of(kvm->arch.active_mmu_pages.prev,
1978 struct kvm_mmu_page, link);
1979 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1980 }
1981 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1982 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1983 }
1984
1985 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1986 }
1987
1988 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1989 {
1990 struct kvm_mmu_page *sp;
1991 struct hlist_node *node;
1992 LIST_HEAD(invalid_list);
1993 int r;
1994
1995 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1996 r = 0;
1997
1998 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1999 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2000 sp->role.word);
2001 r = 1;
2002 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2003 }
2004 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2005 return r;
2006 }
2007
2008 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
2009 {
2010 struct kvm_mmu_page *sp;
2011 struct hlist_node *node;
2012 LIST_HEAD(invalid_list);
2013
2014 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2015 pgprintk("%s: zap %llx %x\n",
2016 __func__, gfn, sp->role.word);
2017 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2018 }
2019 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2020 }
2021
2022 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2023 {
2024 int slot = memslot_id(kvm, gfn);
2025 struct kvm_mmu_page *sp = page_header(__pa(pte));
2026
2027 __set_bit(slot, sp->slot_bitmap);
2028 }
2029
2030 /*
2031 * The function is based on mtrr_type_lookup() in
2032 * arch/x86/kernel/cpu/mtrr/generic.c
2033 */
2034 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2035 u64 start, u64 end)
2036 {
2037 int i;
2038 u64 base, mask;
2039 u8 prev_match, curr_match;
2040 int num_var_ranges = KVM_NR_VAR_MTRR;
2041
2042 if (!mtrr_state->enabled)
2043 return 0xFF;
2044
2045 /* Make end inclusive end, instead of exclusive */
2046 end--;
2047
2048 /* Look in fixed ranges. Just return the type as per start */
2049 if (mtrr_state->have_fixed && (start < 0x100000)) {
2050 int idx;
2051
2052 if (start < 0x80000) {
2053 idx = 0;
2054 idx += (start >> 16);
2055 return mtrr_state->fixed_ranges[idx];
2056 } else if (start < 0xC0000) {
2057 idx = 1 * 8;
2058 idx += ((start - 0x80000) >> 14);
2059 return mtrr_state->fixed_ranges[idx];
2060 } else if (start < 0x1000000) {
2061 idx = 3 * 8;
2062 idx += ((start - 0xC0000) >> 12);
2063 return mtrr_state->fixed_ranges[idx];
2064 }
2065 }
2066
2067 /*
2068 * Look in variable ranges
2069 * Look of multiple ranges matching this address and pick type
2070 * as per MTRR precedence
2071 */
2072 if (!(mtrr_state->enabled & 2))
2073 return mtrr_state->def_type;
2074
2075 prev_match = 0xFF;
2076 for (i = 0; i < num_var_ranges; ++i) {
2077 unsigned short start_state, end_state;
2078
2079 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2080 continue;
2081
2082 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2083 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2084 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2085 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2086
2087 start_state = ((start & mask) == (base & mask));
2088 end_state = ((end & mask) == (base & mask));
2089 if (start_state != end_state)
2090 return 0xFE;
2091
2092 if ((start & mask) != (base & mask))
2093 continue;
2094
2095 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2096 if (prev_match == 0xFF) {
2097 prev_match = curr_match;
2098 continue;
2099 }
2100
2101 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2102 curr_match == MTRR_TYPE_UNCACHABLE)
2103 return MTRR_TYPE_UNCACHABLE;
2104
2105 if ((prev_match == MTRR_TYPE_WRBACK &&
2106 curr_match == MTRR_TYPE_WRTHROUGH) ||
2107 (prev_match == MTRR_TYPE_WRTHROUGH &&
2108 curr_match == MTRR_TYPE_WRBACK)) {
2109 prev_match = MTRR_TYPE_WRTHROUGH;
2110 curr_match = MTRR_TYPE_WRTHROUGH;
2111 }
2112
2113 if (prev_match != curr_match)
2114 return MTRR_TYPE_UNCACHABLE;
2115 }
2116
2117 if (prev_match != 0xFF)
2118 return prev_match;
2119
2120 return mtrr_state->def_type;
2121 }
2122
2123 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2124 {
2125 u8 mtrr;
2126
2127 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2128 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2129 if (mtrr == 0xfe || mtrr == 0xff)
2130 mtrr = MTRR_TYPE_WRBACK;
2131 return mtrr;
2132 }
2133 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2134
2135 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2136 {
2137 trace_kvm_mmu_unsync_page(sp);
2138 ++vcpu->kvm->stat.mmu_unsync;
2139 sp->unsync = 1;
2140
2141 kvm_mmu_mark_parents_unsync(sp);
2142 }
2143
2144 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2145 {
2146 struct kvm_mmu_page *s;
2147 struct hlist_node *node;
2148
2149 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2150 if (s->unsync)
2151 continue;
2152 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2153 __kvm_unsync_page(vcpu, s);
2154 }
2155 }
2156
2157 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2158 bool can_unsync)
2159 {
2160 struct kvm_mmu_page *s;
2161 struct hlist_node *node;
2162 bool need_unsync = false;
2163
2164 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2165 if (!can_unsync)
2166 return 1;
2167
2168 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2169 return 1;
2170
2171 if (!need_unsync && !s->unsync) {
2172 if (!oos_shadow)
2173 return 1;
2174 need_unsync = true;
2175 }
2176 }
2177 if (need_unsync)
2178 kvm_unsync_pages(vcpu, gfn);
2179 return 0;
2180 }
2181
2182 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2183 unsigned pte_access, int user_fault,
2184 int write_fault, int level,
2185 gfn_t gfn, pfn_t pfn, bool speculative,
2186 bool can_unsync, bool host_writable)
2187 {
2188 u64 spte, entry = *sptep;
2189 int ret = 0;
2190
2191 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2192 return 0;
2193
2194 /*
2195 * We don't set the accessed bit, since we sometimes want to see
2196 * whether the guest actually used the pte (in order to detect
2197 * demand paging).
2198 */
2199 spte = PT_PRESENT_MASK;
2200 if (!speculative)
2201 spte |= shadow_accessed_mask;
2202
2203 if (pte_access & ACC_EXEC_MASK)
2204 spte |= shadow_x_mask;
2205 else
2206 spte |= shadow_nx_mask;
2207 if (pte_access & ACC_USER_MASK)
2208 spte |= shadow_user_mask;
2209 if (level > PT_PAGE_TABLE_LEVEL)
2210 spte |= PT_PAGE_SIZE_MASK;
2211 if (tdp_enabled)
2212 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2213 kvm_is_mmio_pfn(pfn));
2214
2215 if (host_writable)
2216 spte |= SPTE_HOST_WRITEABLE;
2217 else
2218 pte_access &= ~ACC_WRITE_MASK;
2219
2220 spte |= (u64)pfn << PAGE_SHIFT;
2221
2222 if ((pte_access & ACC_WRITE_MASK)
2223 || (!vcpu->arch.mmu.direct_map && write_fault
2224 && !is_write_protection(vcpu) && !user_fault)) {
2225
2226 if (level > PT_PAGE_TABLE_LEVEL &&
2227 has_wrprotected_page(vcpu->kvm, gfn, level)) {
2228 ret = 1;
2229 drop_spte(vcpu->kvm, sptep);
2230 goto done;
2231 }
2232
2233 spte |= PT_WRITABLE_MASK;
2234
2235 if (!vcpu->arch.mmu.direct_map
2236 && !(pte_access & ACC_WRITE_MASK)) {
2237 spte &= ~PT_USER_MASK;
2238 /*
2239 * If we converted a user page to a kernel page,
2240 * so that the kernel can write to it when cr0.wp=0,
2241 * then we should prevent the kernel from executing it
2242 * if SMEP is enabled.
2243 */
2244 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2245 spte |= PT64_NX_MASK;
2246 }
2247
2248 /*
2249 * Optimization: for pte sync, if spte was writable the hash
2250 * lookup is unnecessary (and expensive). Write protection
2251 * is responsibility of mmu_get_page / kvm_sync_page.
2252 * Same reasoning can be applied to dirty page accounting.
2253 */
2254 if (!can_unsync && is_writable_pte(*sptep))
2255 goto set_pte;
2256
2257 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2258 pgprintk("%s: found shadow page for %llx, marking ro\n",
2259 __func__, gfn);
2260 ret = 1;
2261 pte_access &= ~ACC_WRITE_MASK;
2262 if (is_writable_pte(spte))
2263 spte &= ~PT_WRITABLE_MASK;
2264 }
2265 }
2266
2267 if (pte_access & ACC_WRITE_MASK)
2268 mark_page_dirty(vcpu->kvm, gfn);
2269
2270 set_pte:
2271 mmu_spte_update(sptep, spte);
2272 /*
2273 * If we overwrite a writable spte with a read-only one we
2274 * should flush remote TLBs. Otherwise rmap_write_protect
2275 * will find a read-only spte, even though the writable spte
2276 * might be cached on a CPU's TLB.
2277 */
2278 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2279 kvm_flush_remote_tlbs(vcpu->kvm);
2280 done:
2281 return ret;
2282 }
2283
2284 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2285 unsigned pt_access, unsigned pte_access,
2286 int user_fault, int write_fault,
2287 int *emulate, int level, gfn_t gfn,
2288 pfn_t pfn, bool speculative,
2289 bool host_writable)
2290 {
2291 int was_rmapped = 0;
2292 int rmap_count;
2293
2294 pgprintk("%s: spte %llx access %x write_fault %d"
2295 " user_fault %d gfn %llx\n",
2296 __func__, *sptep, pt_access,
2297 write_fault, user_fault, gfn);
2298
2299 if (is_rmap_spte(*sptep)) {
2300 /*
2301 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2302 * the parent of the now unreachable PTE.
2303 */
2304 if (level > PT_PAGE_TABLE_LEVEL &&
2305 !is_large_pte(*sptep)) {
2306 struct kvm_mmu_page *child;
2307 u64 pte = *sptep;
2308
2309 child = page_header(pte & PT64_BASE_ADDR_MASK);
2310 drop_parent_pte(child, sptep);
2311 kvm_flush_remote_tlbs(vcpu->kvm);
2312 } else if (pfn != spte_to_pfn(*sptep)) {
2313 pgprintk("hfn old %llx new %llx\n",
2314 spte_to_pfn(*sptep), pfn);
2315 drop_spte(vcpu->kvm, sptep);
2316 kvm_flush_remote_tlbs(vcpu->kvm);
2317 } else
2318 was_rmapped = 1;
2319 }
2320
2321 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2322 level, gfn, pfn, speculative, true,
2323 host_writable)) {
2324 if (write_fault)
2325 *emulate = 1;
2326 kvm_mmu_flush_tlb(vcpu);
2327 }
2328
2329 if (unlikely(is_mmio_spte(*sptep) && emulate))
2330 *emulate = 1;
2331
2332 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2333 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2334 is_large_pte(*sptep)? "2MB" : "4kB",
2335 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2336 *sptep, sptep);
2337 if (!was_rmapped && is_large_pte(*sptep))
2338 ++vcpu->kvm->stat.lpages;
2339
2340 if (is_shadow_present_pte(*sptep)) {
2341 page_header_update_slot(vcpu->kvm, sptep, gfn);
2342 if (!was_rmapped) {
2343 rmap_count = rmap_add(vcpu, sptep, gfn);
2344 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2345 rmap_recycle(vcpu, sptep, gfn);
2346 }
2347 }
2348 kvm_release_pfn_clean(pfn);
2349 if (speculative) {
2350 vcpu->arch.last_pte_updated = sptep;
2351 vcpu->arch.last_pte_gfn = gfn;
2352 }
2353 }
2354
2355 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2356 {
2357 }
2358
2359 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2360 bool no_dirty_log)
2361 {
2362 struct kvm_memory_slot *slot;
2363 unsigned long hva;
2364
2365 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2366 if (!slot) {
2367 get_page(fault_page);
2368 return page_to_pfn(fault_page);
2369 }
2370
2371 hva = gfn_to_hva_memslot(slot, gfn);
2372
2373 return hva_to_pfn_atomic(vcpu->kvm, hva);
2374 }
2375
2376 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2377 struct kvm_mmu_page *sp,
2378 u64 *start, u64 *end)
2379 {
2380 struct page *pages[PTE_PREFETCH_NUM];
2381 unsigned access = sp->role.access;
2382 int i, ret;
2383 gfn_t gfn;
2384
2385 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2386 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2387 return -1;
2388
2389 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2390 if (ret <= 0)
2391 return -1;
2392
2393 for (i = 0; i < ret; i++, gfn++, start++)
2394 mmu_set_spte(vcpu, start, ACC_ALL,
2395 access, 0, 0, NULL,
2396 sp->role.level, gfn,
2397 page_to_pfn(pages[i]), true, true);
2398
2399 return 0;
2400 }
2401
2402 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2403 struct kvm_mmu_page *sp, u64 *sptep)
2404 {
2405 u64 *spte, *start = NULL;
2406 int i;
2407
2408 WARN_ON(!sp->role.direct);
2409
2410 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2411 spte = sp->spt + i;
2412
2413 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2414 if (is_shadow_present_pte(*spte) || spte == sptep) {
2415 if (!start)
2416 continue;
2417 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2418 break;
2419 start = NULL;
2420 } else if (!start)
2421 start = spte;
2422 }
2423 }
2424
2425 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2426 {
2427 struct kvm_mmu_page *sp;
2428
2429 /*
2430 * Since it's no accessed bit on EPT, it's no way to
2431 * distinguish between actually accessed translations
2432 * and prefetched, so disable pte prefetch if EPT is
2433 * enabled.
2434 */
2435 if (!shadow_accessed_mask)
2436 return;
2437
2438 sp = page_header(__pa(sptep));
2439 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2440 return;
2441
2442 __direct_pte_prefetch(vcpu, sp, sptep);
2443 }
2444
2445 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2446 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2447 bool prefault)
2448 {
2449 struct kvm_shadow_walk_iterator iterator;
2450 struct kvm_mmu_page *sp;
2451 int emulate = 0;
2452 gfn_t pseudo_gfn;
2453
2454 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2455 if (iterator.level == level) {
2456 unsigned pte_access = ACC_ALL;
2457
2458 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2459 0, write, &emulate,
2460 level, gfn, pfn, prefault, map_writable);
2461 direct_pte_prefetch(vcpu, iterator.sptep);
2462 ++vcpu->stat.pf_fixed;
2463 break;
2464 }
2465
2466 if (!is_shadow_present_pte(*iterator.sptep)) {
2467 u64 base_addr = iterator.addr;
2468
2469 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2470 pseudo_gfn = base_addr >> PAGE_SHIFT;
2471 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2472 iterator.level - 1,
2473 1, ACC_ALL, iterator.sptep);
2474 if (!sp) {
2475 pgprintk("nonpaging_map: ENOMEM\n");
2476 kvm_release_pfn_clean(pfn);
2477 return -ENOMEM;
2478 }
2479
2480 mmu_spte_set(iterator.sptep,
2481 __pa(sp->spt)
2482 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2483 | shadow_user_mask | shadow_x_mask
2484 | shadow_accessed_mask);
2485 }
2486 }
2487 return emulate;
2488 }
2489
2490 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2491 {
2492 siginfo_t info;
2493
2494 info.si_signo = SIGBUS;
2495 info.si_errno = 0;
2496 info.si_code = BUS_MCEERR_AR;
2497 info.si_addr = (void __user *)address;
2498 info.si_addr_lsb = PAGE_SHIFT;
2499
2500 send_sig_info(SIGBUS, &info, tsk);
2501 }
2502
2503 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2504 {
2505 kvm_release_pfn_clean(pfn);
2506 if (is_hwpoison_pfn(pfn)) {
2507 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2508 return 0;
2509 }
2510
2511 return -EFAULT;
2512 }
2513
2514 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2515 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2516 {
2517 pfn_t pfn = *pfnp;
2518 gfn_t gfn = *gfnp;
2519 int level = *levelp;
2520
2521 /*
2522 * Check if it's a transparent hugepage. If this would be an
2523 * hugetlbfs page, level wouldn't be set to
2524 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2525 * here.
2526 */
2527 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2528 level == PT_PAGE_TABLE_LEVEL &&
2529 PageTransCompound(pfn_to_page(pfn)) &&
2530 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2531 unsigned long mask;
2532 /*
2533 * mmu_notifier_retry was successful and we hold the
2534 * mmu_lock here, so the pmd can't become splitting
2535 * from under us, and in turn
2536 * __split_huge_page_refcount() can't run from under
2537 * us and we can safely transfer the refcount from
2538 * PG_tail to PG_head as we switch the pfn to tail to
2539 * head.
2540 */
2541 *levelp = level = PT_DIRECTORY_LEVEL;
2542 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2543 VM_BUG_ON((gfn & mask) != (pfn & mask));
2544 if (pfn & mask) {
2545 gfn &= ~mask;
2546 *gfnp = gfn;
2547 kvm_release_pfn_clean(pfn);
2548 pfn &= ~mask;
2549 if (!get_page_unless_zero(pfn_to_page(pfn)))
2550 BUG();
2551 *pfnp = pfn;
2552 }
2553 }
2554 }
2555
2556 static bool mmu_invalid_pfn(pfn_t pfn)
2557 {
2558 return unlikely(is_invalid_pfn(pfn));
2559 }
2560
2561 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2562 pfn_t pfn, unsigned access, int *ret_val)
2563 {
2564 bool ret = true;
2565
2566 /* The pfn is invalid, report the error! */
2567 if (unlikely(is_invalid_pfn(pfn))) {
2568 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2569 goto exit;
2570 }
2571
2572 if (unlikely(is_noslot_pfn(pfn)))
2573 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2574
2575 ret = false;
2576 exit:
2577 return ret;
2578 }
2579
2580 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2581 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2582
2583 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2584 bool prefault)
2585 {
2586 int r;
2587 int level;
2588 int force_pt_level;
2589 pfn_t pfn;
2590 unsigned long mmu_seq;
2591 bool map_writable;
2592
2593 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2594 if (likely(!force_pt_level)) {
2595 level = mapping_level(vcpu, gfn);
2596 /*
2597 * This path builds a PAE pagetable - so we can map
2598 * 2mb pages at maximum. Therefore check if the level
2599 * is larger than that.
2600 */
2601 if (level > PT_DIRECTORY_LEVEL)
2602 level = PT_DIRECTORY_LEVEL;
2603
2604 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2605 } else
2606 level = PT_PAGE_TABLE_LEVEL;
2607
2608 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2609 smp_rmb();
2610
2611 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2612 return 0;
2613
2614 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2615 return r;
2616
2617 spin_lock(&vcpu->kvm->mmu_lock);
2618 if (mmu_notifier_retry(vcpu, mmu_seq))
2619 goto out_unlock;
2620 kvm_mmu_free_some_pages(vcpu);
2621 if (likely(!force_pt_level))
2622 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2623 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2624 prefault);
2625 spin_unlock(&vcpu->kvm->mmu_lock);
2626
2627
2628 return r;
2629
2630 out_unlock:
2631 spin_unlock(&vcpu->kvm->mmu_lock);
2632 kvm_release_pfn_clean(pfn);
2633 return 0;
2634 }
2635
2636
2637 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2638 {
2639 int i;
2640 struct kvm_mmu_page *sp;
2641 LIST_HEAD(invalid_list);
2642
2643 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2644 return;
2645 spin_lock(&vcpu->kvm->mmu_lock);
2646 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2647 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2648 vcpu->arch.mmu.direct_map)) {
2649 hpa_t root = vcpu->arch.mmu.root_hpa;
2650
2651 sp = page_header(root);
2652 --sp->root_count;
2653 if (!sp->root_count && sp->role.invalid) {
2654 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2655 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2656 }
2657 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2658 spin_unlock(&vcpu->kvm->mmu_lock);
2659 return;
2660 }
2661 for (i = 0; i < 4; ++i) {
2662 hpa_t root = vcpu->arch.mmu.pae_root[i];
2663
2664 if (root) {
2665 root &= PT64_BASE_ADDR_MASK;
2666 sp = page_header(root);
2667 --sp->root_count;
2668 if (!sp->root_count && sp->role.invalid)
2669 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2670 &invalid_list);
2671 }
2672 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2673 }
2674 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2675 spin_unlock(&vcpu->kvm->mmu_lock);
2676 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2677 }
2678
2679 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2680 {
2681 int ret = 0;
2682
2683 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2684 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2685 ret = 1;
2686 }
2687
2688 return ret;
2689 }
2690
2691 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2692 {
2693 struct kvm_mmu_page *sp;
2694 unsigned i;
2695
2696 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2697 spin_lock(&vcpu->kvm->mmu_lock);
2698 kvm_mmu_free_some_pages(vcpu);
2699 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2700 1, ACC_ALL, NULL);
2701 ++sp->root_count;
2702 spin_unlock(&vcpu->kvm->mmu_lock);
2703 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2704 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2705 for (i = 0; i < 4; ++i) {
2706 hpa_t root = vcpu->arch.mmu.pae_root[i];
2707
2708 ASSERT(!VALID_PAGE(root));
2709 spin_lock(&vcpu->kvm->mmu_lock);
2710 kvm_mmu_free_some_pages(vcpu);
2711 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2712 i << 30,
2713 PT32_ROOT_LEVEL, 1, ACC_ALL,
2714 NULL);
2715 root = __pa(sp->spt);
2716 ++sp->root_count;
2717 spin_unlock(&vcpu->kvm->mmu_lock);
2718 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2719 }
2720 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2721 } else
2722 BUG();
2723
2724 return 0;
2725 }
2726
2727 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2728 {
2729 struct kvm_mmu_page *sp;
2730 u64 pdptr, pm_mask;
2731 gfn_t root_gfn;
2732 int i;
2733
2734 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2735
2736 if (mmu_check_root(vcpu, root_gfn))
2737 return 1;
2738
2739 /*
2740 * Do we shadow a long mode page table? If so we need to
2741 * write-protect the guests page table root.
2742 */
2743 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2744 hpa_t root = vcpu->arch.mmu.root_hpa;
2745
2746 ASSERT(!VALID_PAGE(root));
2747
2748 spin_lock(&vcpu->kvm->mmu_lock);
2749 kvm_mmu_free_some_pages(vcpu);
2750 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2751 0, ACC_ALL, NULL);
2752 root = __pa(sp->spt);
2753 ++sp->root_count;
2754 spin_unlock(&vcpu->kvm->mmu_lock);
2755 vcpu->arch.mmu.root_hpa = root;
2756 return 0;
2757 }
2758
2759 /*
2760 * We shadow a 32 bit page table. This may be a legacy 2-level
2761 * or a PAE 3-level page table. In either case we need to be aware that
2762 * the shadow page table may be a PAE or a long mode page table.
2763 */
2764 pm_mask = PT_PRESENT_MASK;
2765 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2766 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2767
2768 for (i = 0; i < 4; ++i) {
2769 hpa_t root = vcpu->arch.mmu.pae_root[i];
2770
2771 ASSERT(!VALID_PAGE(root));
2772 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2773 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
2774 if (!is_present_gpte(pdptr)) {
2775 vcpu->arch.mmu.pae_root[i] = 0;
2776 continue;
2777 }
2778 root_gfn = pdptr >> PAGE_SHIFT;
2779 if (mmu_check_root(vcpu, root_gfn))
2780 return 1;
2781 }
2782 spin_lock(&vcpu->kvm->mmu_lock);
2783 kvm_mmu_free_some_pages(vcpu);
2784 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2785 PT32_ROOT_LEVEL, 0,
2786 ACC_ALL, NULL);
2787 root = __pa(sp->spt);
2788 ++sp->root_count;
2789 spin_unlock(&vcpu->kvm->mmu_lock);
2790
2791 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2792 }
2793 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2794
2795 /*
2796 * If we shadow a 32 bit page table with a long mode page
2797 * table we enter this path.
2798 */
2799 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2800 if (vcpu->arch.mmu.lm_root == NULL) {
2801 /*
2802 * The additional page necessary for this is only
2803 * allocated on demand.
2804 */
2805
2806 u64 *lm_root;
2807
2808 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2809 if (lm_root == NULL)
2810 return 1;
2811
2812 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2813
2814 vcpu->arch.mmu.lm_root = lm_root;
2815 }
2816
2817 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2818 }
2819
2820 return 0;
2821 }
2822
2823 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2824 {
2825 if (vcpu->arch.mmu.direct_map)
2826 return mmu_alloc_direct_roots(vcpu);
2827 else
2828 return mmu_alloc_shadow_roots(vcpu);
2829 }
2830
2831 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2832 {
2833 int i;
2834 struct kvm_mmu_page *sp;
2835
2836 if (vcpu->arch.mmu.direct_map)
2837 return;
2838
2839 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2840 return;
2841
2842 vcpu_clear_mmio_info(vcpu, ~0ul);
2843 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2844 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2845 hpa_t root = vcpu->arch.mmu.root_hpa;
2846 sp = page_header(root);
2847 mmu_sync_children(vcpu, sp);
2848 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2849 return;
2850 }
2851 for (i = 0; i < 4; ++i) {
2852 hpa_t root = vcpu->arch.mmu.pae_root[i];
2853
2854 if (root && VALID_PAGE(root)) {
2855 root &= PT64_BASE_ADDR_MASK;
2856 sp = page_header(root);
2857 mmu_sync_children(vcpu, sp);
2858 }
2859 }
2860 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2861 }
2862
2863 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2864 {
2865 spin_lock(&vcpu->kvm->mmu_lock);
2866 mmu_sync_roots(vcpu);
2867 spin_unlock(&vcpu->kvm->mmu_lock);
2868 }
2869
2870 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2871 u32 access, struct x86_exception *exception)
2872 {
2873 if (exception)
2874 exception->error_code = 0;
2875 return vaddr;
2876 }
2877
2878 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2879 u32 access,
2880 struct x86_exception *exception)
2881 {
2882 if (exception)
2883 exception->error_code = 0;
2884 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2885 }
2886
2887 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2888 {
2889 if (direct)
2890 return vcpu_match_mmio_gpa(vcpu, addr);
2891
2892 return vcpu_match_mmio_gva(vcpu, addr);
2893 }
2894
2895
2896 /*
2897 * On direct hosts, the last spte is only allows two states
2898 * for mmio page fault:
2899 * - It is the mmio spte
2900 * - It is zapped or it is being zapped.
2901 *
2902 * This function completely checks the spte when the last spte
2903 * is not the mmio spte.
2904 */
2905 static bool check_direct_spte_mmio_pf(u64 spte)
2906 {
2907 return __check_direct_spte_mmio_pf(spte);
2908 }
2909
2910 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2911 {
2912 struct kvm_shadow_walk_iterator iterator;
2913 u64 spte = 0ull;
2914
2915 walk_shadow_page_lockless_begin(vcpu);
2916 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2917 if (!is_shadow_present_pte(spte))
2918 break;
2919 walk_shadow_page_lockless_end(vcpu);
2920
2921 return spte;
2922 }
2923
2924 /*
2925 * If it is a real mmio page fault, return 1 and emulat the instruction
2926 * directly, return 0 to let CPU fault again on the address, -1 is
2927 * returned if bug is detected.
2928 */
2929 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2930 {
2931 u64 spte;
2932
2933 if (quickly_check_mmio_pf(vcpu, addr, direct))
2934 return 1;
2935
2936 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2937
2938 if (is_mmio_spte(spte)) {
2939 gfn_t gfn = get_mmio_spte_gfn(spte);
2940 unsigned access = get_mmio_spte_access(spte);
2941
2942 if (direct)
2943 addr = 0;
2944
2945 trace_handle_mmio_page_fault(addr, gfn, access);
2946 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2947 return 1;
2948 }
2949
2950 /*
2951 * It's ok if the gva is remapped by other cpus on shadow guest,
2952 * it's a BUG if the gfn is not a mmio page.
2953 */
2954 if (direct && !check_direct_spte_mmio_pf(spte))
2955 return -1;
2956
2957 /*
2958 * If the page table is zapped by other cpus, let CPU fault again on
2959 * the address.
2960 */
2961 return 0;
2962 }
2963 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2964
2965 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2966 u32 error_code, bool direct)
2967 {
2968 int ret;
2969
2970 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2971 WARN_ON(ret < 0);
2972 return ret;
2973 }
2974
2975 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2976 u32 error_code, bool prefault)
2977 {
2978 gfn_t gfn;
2979 int r;
2980
2981 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2982
2983 if (unlikely(error_code & PFERR_RSVD_MASK))
2984 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2985
2986 r = mmu_topup_memory_caches(vcpu);
2987 if (r)
2988 return r;
2989
2990 ASSERT(vcpu);
2991 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2992
2993 gfn = gva >> PAGE_SHIFT;
2994
2995 return nonpaging_map(vcpu, gva & PAGE_MASK,
2996 error_code & PFERR_WRITE_MASK, gfn, prefault);
2997 }
2998
2999 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3000 {
3001 struct kvm_arch_async_pf arch;
3002
3003 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3004 arch.gfn = gfn;
3005 arch.direct_map = vcpu->arch.mmu.direct_map;
3006 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3007
3008 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3009 }
3010
3011 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3012 {
3013 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3014 kvm_event_needs_reinjection(vcpu)))
3015 return false;
3016
3017 return kvm_x86_ops->interrupt_allowed(vcpu);
3018 }
3019
3020 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3021 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3022 {
3023 bool async;
3024
3025 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3026
3027 if (!async)
3028 return false; /* *pfn has correct page already */
3029
3030 put_page(pfn_to_page(*pfn));
3031
3032 if (!prefault && can_do_async_pf(vcpu)) {
3033 trace_kvm_try_async_get_page(gva, gfn);
3034 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3035 trace_kvm_async_pf_doublefault(gva, gfn);
3036 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3037 return true;
3038 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3039 return true;
3040 }
3041
3042 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3043
3044 return false;
3045 }
3046
3047 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3048 bool prefault)
3049 {
3050 pfn_t pfn;
3051 int r;
3052 int level;
3053 int force_pt_level;
3054 gfn_t gfn = gpa >> PAGE_SHIFT;
3055 unsigned long mmu_seq;
3056 int write = error_code & PFERR_WRITE_MASK;
3057 bool map_writable;
3058
3059 ASSERT(vcpu);
3060 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3061
3062 if (unlikely(error_code & PFERR_RSVD_MASK))
3063 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3064
3065 r = mmu_topup_memory_caches(vcpu);
3066 if (r)
3067 return r;
3068
3069 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3070 if (likely(!force_pt_level)) {
3071 level = mapping_level(vcpu, gfn);
3072 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3073 } else
3074 level = PT_PAGE_TABLE_LEVEL;
3075
3076 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3077 smp_rmb();
3078
3079 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3080 return 0;
3081
3082 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3083 return r;
3084
3085 spin_lock(&vcpu->kvm->mmu_lock);
3086 if (mmu_notifier_retry(vcpu, mmu_seq))
3087 goto out_unlock;
3088 kvm_mmu_free_some_pages(vcpu);
3089 if (likely(!force_pt_level))
3090 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3091 r = __direct_map(vcpu, gpa, write, map_writable,
3092 level, gfn, pfn, prefault);
3093 spin_unlock(&vcpu->kvm->mmu_lock);
3094
3095 return r;
3096
3097 out_unlock:
3098 spin_unlock(&vcpu->kvm->mmu_lock);
3099 kvm_release_pfn_clean(pfn);
3100 return 0;
3101 }
3102
3103 static void nonpaging_free(struct kvm_vcpu *vcpu)
3104 {
3105 mmu_free_roots(vcpu);
3106 }
3107
3108 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3109 struct kvm_mmu *context)
3110 {
3111 context->new_cr3 = nonpaging_new_cr3;
3112 context->page_fault = nonpaging_page_fault;
3113 context->gva_to_gpa = nonpaging_gva_to_gpa;
3114 context->free = nonpaging_free;
3115 context->sync_page = nonpaging_sync_page;
3116 context->invlpg = nonpaging_invlpg;
3117 context->update_pte = nonpaging_update_pte;
3118 context->root_level = 0;
3119 context->shadow_root_level = PT32E_ROOT_LEVEL;
3120 context->root_hpa = INVALID_PAGE;
3121 context->direct_map = true;
3122 context->nx = false;
3123 return 0;
3124 }
3125
3126 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3127 {
3128 ++vcpu->stat.tlb_flush;
3129 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3130 }
3131
3132 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3133 {
3134 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3135 mmu_free_roots(vcpu);
3136 }
3137
3138 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3139 {
3140 return kvm_read_cr3(vcpu);
3141 }
3142
3143 static void inject_page_fault(struct kvm_vcpu *vcpu,
3144 struct x86_exception *fault)
3145 {
3146 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3147 }
3148
3149 static void paging_free(struct kvm_vcpu *vcpu)
3150 {
3151 nonpaging_free(vcpu);
3152 }
3153
3154 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3155 {
3156 int bit7;
3157
3158 bit7 = (gpte >> 7) & 1;
3159 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3160 }
3161
3162 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3163 int *nr_present)
3164 {
3165 if (unlikely(is_mmio_spte(*sptep))) {
3166 if (gfn != get_mmio_spte_gfn(*sptep)) {
3167 mmu_spte_clear_no_track(sptep);
3168 return true;
3169 }
3170
3171 (*nr_present)++;
3172 mark_mmio_spte(sptep, gfn, access);
3173 return true;
3174 }
3175
3176 return false;
3177 }
3178
3179 #define PTTYPE 64
3180 #include "paging_tmpl.h"
3181 #undef PTTYPE
3182
3183 #define PTTYPE 32
3184 #include "paging_tmpl.h"
3185 #undef PTTYPE
3186
3187 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3188 struct kvm_mmu *context,
3189 int level)
3190 {
3191 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3192 u64 exb_bit_rsvd = 0;
3193
3194 if (!context->nx)
3195 exb_bit_rsvd = rsvd_bits(63, 63);
3196 switch (level) {
3197 case PT32_ROOT_LEVEL:
3198 /* no rsvd bits for 2 level 4K page table entries */
3199 context->rsvd_bits_mask[0][1] = 0;
3200 context->rsvd_bits_mask[0][0] = 0;
3201 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3202
3203 if (!is_pse(vcpu)) {
3204 context->rsvd_bits_mask[1][1] = 0;
3205 break;
3206 }
3207
3208 if (is_cpuid_PSE36())
3209 /* 36bits PSE 4MB page */
3210 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3211 else
3212 /* 32 bits PSE 4MB page */
3213 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3214 break;
3215 case PT32E_ROOT_LEVEL:
3216 context->rsvd_bits_mask[0][2] =
3217 rsvd_bits(maxphyaddr, 63) |
3218 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3219 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3220 rsvd_bits(maxphyaddr, 62); /* PDE */
3221 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3222 rsvd_bits(maxphyaddr, 62); /* PTE */
3223 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3224 rsvd_bits(maxphyaddr, 62) |
3225 rsvd_bits(13, 20); /* large page */
3226 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3227 break;
3228 case PT64_ROOT_LEVEL:
3229 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3230 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3231 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3232 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3233 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3234 rsvd_bits(maxphyaddr, 51);
3235 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3236 rsvd_bits(maxphyaddr, 51);
3237 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3238 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3239 rsvd_bits(maxphyaddr, 51) |
3240 rsvd_bits(13, 29);
3241 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3242 rsvd_bits(maxphyaddr, 51) |
3243 rsvd_bits(13, 20); /* large page */
3244 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3245 break;
3246 }
3247 }
3248
3249 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3250 struct kvm_mmu *context,
3251 int level)
3252 {
3253 context->nx = is_nx(vcpu);
3254
3255 reset_rsvds_bits_mask(vcpu, context, level);
3256
3257 ASSERT(is_pae(vcpu));
3258 context->new_cr3 = paging_new_cr3;
3259 context->page_fault = paging64_page_fault;
3260 context->gva_to_gpa = paging64_gva_to_gpa;
3261 context->sync_page = paging64_sync_page;
3262 context->invlpg = paging64_invlpg;
3263 context->update_pte = paging64_update_pte;
3264 context->free = paging_free;
3265 context->root_level = level;
3266 context->shadow_root_level = level;
3267 context->root_hpa = INVALID_PAGE;
3268 context->direct_map = false;
3269 return 0;
3270 }
3271
3272 static int paging64_init_context(struct kvm_vcpu *vcpu,
3273 struct kvm_mmu *context)
3274 {
3275 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3276 }
3277
3278 static int paging32_init_context(struct kvm_vcpu *vcpu,
3279 struct kvm_mmu *context)
3280 {
3281 context->nx = false;
3282
3283 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3284
3285 context->new_cr3 = paging_new_cr3;
3286 context->page_fault = paging32_page_fault;
3287 context->gva_to_gpa = paging32_gva_to_gpa;
3288 context->free = paging_free;
3289 context->sync_page = paging32_sync_page;
3290 context->invlpg = paging32_invlpg;
3291 context->update_pte = paging32_update_pte;
3292 context->root_level = PT32_ROOT_LEVEL;
3293 context->shadow_root_level = PT32E_ROOT_LEVEL;
3294 context->root_hpa = INVALID_PAGE;
3295 context->direct_map = false;
3296 return 0;
3297 }
3298
3299 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3300 struct kvm_mmu *context)
3301 {
3302 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3303 }
3304
3305 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3306 {
3307 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3308
3309 context->base_role.word = 0;
3310 context->new_cr3 = nonpaging_new_cr3;
3311 context->page_fault = tdp_page_fault;
3312 context->free = nonpaging_free;
3313 context->sync_page = nonpaging_sync_page;
3314 context->invlpg = nonpaging_invlpg;
3315 context->update_pte = nonpaging_update_pte;
3316 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3317 context->root_hpa = INVALID_PAGE;
3318 context->direct_map = true;
3319 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3320 context->get_cr3 = get_cr3;
3321 context->inject_page_fault = kvm_inject_page_fault;
3322 context->nx = is_nx(vcpu);
3323
3324 if (!is_paging(vcpu)) {
3325 context->nx = false;
3326 context->gva_to_gpa = nonpaging_gva_to_gpa;
3327 context->root_level = 0;
3328 } else if (is_long_mode(vcpu)) {
3329 context->nx = is_nx(vcpu);
3330 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3331 context->gva_to_gpa = paging64_gva_to_gpa;
3332 context->root_level = PT64_ROOT_LEVEL;
3333 } else if (is_pae(vcpu)) {
3334 context->nx = is_nx(vcpu);
3335 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3336 context->gva_to_gpa = paging64_gva_to_gpa;
3337 context->root_level = PT32E_ROOT_LEVEL;
3338 } else {
3339 context->nx = false;
3340 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3341 context->gva_to_gpa = paging32_gva_to_gpa;
3342 context->root_level = PT32_ROOT_LEVEL;
3343 }
3344
3345 return 0;
3346 }
3347
3348 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3349 {
3350 int r;
3351 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3352 ASSERT(vcpu);
3353 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3354
3355 if (!is_paging(vcpu))
3356 r = nonpaging_init_context(vcpu, context);
3357 else if (is_long_mode(vcpu))
3358 r = paging64_init_context(vcpu, context);
3359 else if (is_pae(vcpu))
3360 r = paging32E_init_context(vcpu, context);
3361 else
3362 r = paging32_init_context(vcpu, context);
3363
3364 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3365 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3366 vcpu->arch.mmu.base_role.smep_andnot_wp
3367 = smep && !is_write_protection(vcpu);
3368
3369 return r;
3370 }
3371 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3372
3373 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3374 {
3375 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3376
3377 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3378 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3379 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3380
3381 return r;
3382 }
3383
3384 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3385 {
3386 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3387
3388 g_context->get_cr3 = get_cr3;
3389 g_context->inject_page_fault = kvm_inject_page_fault;
3390
3391 /*
3392 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3393 * translation of l2_gpa to l1_gpa addresses is done using the
3394 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3395 * functions between mmu and nested_mmu are swapped.
3396 */
3397 if (!is_paging(vcpu)) {
3398 g_context->nx = false;
3399 g_context->root_level = 0;
3400 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3401 } else if (is_long_mode(vcpu)) {
3402 g_context->nx = is_nx(vcpu);
3403 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3404 g_context->root_level = PT64_ROOT_LEVEL;
3405 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3406 } else if (is_pae(vcpu)) {
3407 g_context->nx = is_nx(vcpu);
3408 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3409 g_context->root_level = PT32E_ROOT_LEVEL;
3410 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3411 } else {
3412 g_context->nx = false;
3413 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3414 g_context->root_level = PT32_ROOT_LEVEL;
3415 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3416 }
3417
3418 return 0;
3419 }
3420
3421 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3422 {
3423 if (mmu_is_nested(vcpu))
3424 return init_kvm_nested_mmu(vcpu);
3425 else if (tdp_enabled)
3426 return init_kvm_tdp_mmu(vcpu);
3427 else
3428 return init_kvm_softmmu(vcpu);
3429 }
3430
3431 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3432 {
3433 ASSERT(vcpu);
3434 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3435 /* mmu.free() should set root_hpa = INVALID_PAGE */
3436 vcpu->arch.mmu.free(vcpu);
3437 }
3438
3439 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3440 {
3441 destroy_kvm_mmu(vcpu);
3442 return init_kvm_mmu(vcpu);
3443 }
3444 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3445
3446 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3447 {
3448 int r;
3449
3450 r = mmu_topup_memory_caches(vcpu);
3451 if (r)
3452 goto out;
3453 r = mmu_alloc_roots(vcpu);
3454 spin_lock(&vcpu->kvm->mmu_lock);
3455 mmu_sync_roots(vcpu);
3456 spin_unlock(&vcpu->kvm->mmu_lock);
3457 if (r)
3458 goto out;
3459 /* set_cr3() should ensure TLB has been flushed */
3460 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3461 out:
3462 return r;
3463 }
3464 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3465
3466 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3467 {
3468 mmu_free_roots(vcpu);
3469 }
3470 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3471
3472 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3473 struct kvm_mmu_page *sp, u64 *spte,
3474 const void *new)
3475 {
3476 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3477 ++vcpu->kvm->stat.mmu_pde_zapped;
3478 return;
3479 }
3480
3481 ++vcpu->kvm->stat.mmu_pte_updated;
3482 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3483 }
3484
3485 static bool need_remote_flush(u64 old, u64 new)
3486 {
3487 if (!is_shadow_present_pte(old))
3488 return false;
3489 if (!is_shadow_present_pte(new))
3490 return true;
3491 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3492 return true;
3493 old ^= PT64_NX_MASK;
3494 new ^= PT64_NX_MASK;
3495 return (old & ~new & PT64_PERM_MASK) != 0;
3496 }
3497
3498 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3499 bool remote_flush, bool local_flush)
3500 {
3501 if (zap_page)
3502 return;
3503
3504 if (remote_flush)
3505 kvm_flush_remote_tlbs(vcpu->kvm);
3506 else if (local_flush)
3507 kvm_mmu_flush_tlb(vcpu);
3508 }
3509
3510 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3511 {
3512 u64 *spte = vcpu->arch.last_pte_updated;
3513
3514 return !!(spte && (*spte & shadow_accessed_mask));
3515 }
3516
3517 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3518 {
3519 u64 *spte = vcpu->arch.last_pte_updated;
3520
3521 if (spte
3522 && vcpu->arch.last_pte_gfn == gfn
3523 && shadow_accessed_mask
3524 && !(*spte & shadow_accessed_mask)
3525 && is_shadow_present_pte(*spte))
3526 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3527 }
3528
3529 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3530 const u8 *new, int bytes,
3531 bool guest_initiated)
3532 {
3533 gfn_t gfn = gpa >> PAGE_SHIFT;
3534 union kvm_mmu_page_role mask = { .word = 0 };
3535 struct kvm_mmu_page *sp;
3536 struct hlist_node *node;
3537 LIST_HEAD(invalid_list);
3538 u64 entry, gentry, *spte;
3539 unsigned pte_size, page_offset, misaligned, quadrant, offset;
3540 int level, npte, invlpg_counter, r, flooded = 0;
3541 bool remote_flush, local_flush, zap_page;
3542
3543 /*
3544 * If we don't have indirect shadow pages, it means no page is
3545 * write-protected, so we can exit simply.
3546 */
3547 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3548 return;
3549
3550 zap_page = remote_flush = local_flush = false;
3551 offset = offset_in_page(gpa);
3552
3553 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3554
3555 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3556
3557 /*
3558 * Assume that the pte write on a page table of the same type
3559 * as the current vcpu paging mode since we update the sptes only
3560 * when they have the same mode.
3561 */
3562 if ((is_pae(vcpu) && bytes == 4) || !new) {
3563 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3564 if (is_pae(vcpu)) {
3565 gpa &= ~(gpa_t)7;
3566 bytes = 8;
3567 }
3568 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3569 if (r)
3570 gentry = 0;
3571 new = (const u8 *)&gentry;
3572 }
3573
3574 switch (bytes) {
3575 case 4:
3576 gentry = *(const u32 *)new;
3577 break;
3578 case 8:
3579 gentry = *(const u64 *)new;
3580 break;
3581 default:
3582 gentry = 0;
3583 break;
3584 }
3585
3586 spin_lock(&vcpu->kvm->mmu_lock);
3587 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3588 gentry = 0;
3589 kvm_mmu_free_some_pages(vcpu);
3590 ++vcpu->kvm->stat.mmu_pte_write;
3591 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3592 if (guest_initiated) {
3593 kvm_mmu_access_page(vcpu, gfn);
3594 if (gfn == vcpu->arch.last_pt_write_gfn
3595 && !last_updated_pte_accessed(vcpu)) {
3596 ++vcpu->arch.last_pt_write_count;
3597 if (vcpu->arch.last_pt_write_count >= 3)
3598 flooded = 1;
3599 } else {
3600 vcpu->arch.last_pt_write_gfn = gfn;
3601 vcpu->arch.last_pt_write_count = 1;
3602 vcpu->arch.last_pte_updated = NULL;
3603 }
3604 }
3605
3606 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3607 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3608 pte_size = sp->role.cr4_pae ? 8 : 4;
3609 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3610 misaligned |= bytes < 4;
3611 if (misaligned || flooded) {
3612 /*
3613 * Misaligned accesses are too much trouble to fix
3614 * up; also, they usually indicate a page is not used
3615 * as a page table.
3616 *
3617 * If we're seeing too many writes to a page,
3618 * it may no longer be a page table, or we may be
3619 * forking, in which case it is better to unmap the
3620 * page.
3621 */
3622 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3623 gpa, bytes, sp->role.word);
3624 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3625 &invalid_list);
3626 ++vcpu->kvm->stat.mmu_flooded;
3627 continue;
3628 }
3629 page_offset = offset;
3630 level = sp->role.level;
3631 npte = 1;
3632 if (!sp->role.cr4_pae) {
3633 page_offset <<= 1; /* 32->64 */
3634 /*
3635 * A 32-bit pde maps 4MB while the shadow pdes map
3636 * only 2MB. So we need to double the offset again
3637 * and zap two pdes instead of one.
3638 */
3639 if (level == PT32_ROOT_LEVEL) {
3640 page_offset &= ~7; /* kill rounding error */
3641 page_offset <<= 1;
3642 npte = 2;
3643 }
3644 quadrant = page_offset >> PAGE_SHIFT;
3645 page_offset &= ~PAGE_MASK;
3646 if (quadrant != sp->role.quadrant)
3647 continue;
3648 }
3649 local_flush = true;
3650 spte = &sp->spt[page_offset / sizeof(*spte)];
3651 while (npte--) {
3652 entry = *spte;
3653 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3654 if (gentry &&
3655 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3656 & mask.word))
3657 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3658 if (!remote_flush && need_remote_flush(entry, *spte))
3659 remote_flush = true;
3660 ++spte;
3661 }
3662 }
3663 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3664 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3665 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3666 spin_unlock(&vcpu->kvm->mmu_lock);
3667 }
3668
3669 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3670 {
3671 gpa_t gpa;
3672 int r;
3673
3674 if (vcpu->arch.mmu.direct_map)
3675 return 0;
3676
3677 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3678
3679 spin_lock(&vcpu->kvm->mmu_lock);
3680 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3681 spin_unlock(&vcpu->kvm->mmu_lock);
3682 return r;
3683 }
3684 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3685
3686 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3687 {
3688 LIST_HEAD(invalid_list);
3689
3690 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3691 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3692 struct kvm_mmu_page *sp;
3693
3694 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3695 struct kvm_mmu_page, link);
3696 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3697 ++vcpu->kvm->stat.mmu_recycled;
3698 }
3699 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3700 }
3701
3702 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3703 void *insn, int insn_len)
3704 {
3705 int r;
3706 enum emulation_result er;
3707
3708 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3709 if (r < 0)
3710 goto out;
3711
3712 if (!r) {
3713 r = 1;
3714 goto out;
3715 }
3716
3717 r = mmu_topup_memory_caches(vcpu);
3718 if (r)
3719 goto out;
3720
3721 er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3722
3723 switch (er) {
3724 case EMULATE_DONE:
3725 return 1;
3726 case EMULATE_DO_MMIO:
3727 ++vcpu->stat.mmio_exits;
3728 /* fall through */
3729 case EMULATE_FAIL:
3730 return 0;
3731 default:
3732 BUG();
3733 }
3734 out:
3735 return r;
3736 }
3737 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3738
3739 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3740 {
3741 vcpu->arch.mmu.invlpg(vcpu, gva);
3742 kvm_mmu_flush_tlb(vcpu);
3743 ++vcpu->stat.invlpg;
3744 }
3745 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3746
3747 void kvm_enable_tdp(void)
3748 {
3749 tdp_enabled = true;
3750 }
3751 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3752
3753 void kvm_disable_tdp(void)
3754 {
3755 tdp_enabled = false;
3756 }
3757 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3758
3759 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3760 {
3761 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3762 if (vcpu->arch.mmu.lm_root != NULL)
3763 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3764 }
3765
3766 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3767 {
3768 struct page *page;
3769 int i;
3770
3771 ASSERT(vcpu);
3772
3773 /*
3774 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3775 * Therefore we need to allocate shadow page tables in the first
3776 * 4GB of memory, which happens to fit the DMA32 zone.
3777 */
3778 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3779 if (!page)
3780 return -ENOMEM;
3781
3782 vcpu->arch.mmu.pae_root = page_address(page);
3783 for (i = 0; i < 4; ++i)
3784 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3785
3786 return 0;
3787 }
3788
3789 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3790 {
3791 ASSERT(vcpu);
3792 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3793
3794 return alloc_mmu_pages(vcpu);
3795 }
3796
3797 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3798 {
3799 ASSERT(vcpu);
3800 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3801
3802 return init_kvm_mmu(vcpu);
3803 }
3804
3805 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3806 {
3807 struct kvm_mmu_page *sp;
3808
3809 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3810 int i;
3811 u64 *pt;
3812
3813 if (!test_bit(slot, sp->slot_bitmap))
3814 continue;
3815
3816 pt = sp->spt;
3817 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3818 if (!is_shadow_present_pte(pt[i]) ||
3819 !is_last_spte(pt[i], sp->role.level))
3820 continue;
3821
3822 if (is_large_pte(pt[i])) {
3823 drop_spte(kvm, &pt[i]);
3824 --kvm->stat.lpages;
3825 continue;
3826 }
3827
3828 /* avoid RMW */
3829 if (is_writable_pte(pt[i]))
3830 mmu_spte_update(&pt[i],
3831 pt[i] & ~PT_WRITABLE_MASK);
3832 }
3833 }
3834 kvm_flush_remote_tlbs(kvm);
3835 }
3836
3837 void kvm_mmu_zap_all(struct kvm *kvm)
3838 {
3839 struct kvm_mmu_page *sp, *node;
3840 LIST_HEAD(invalid_list);
3841
3842 spin_lock(&kvm->mmu_lock);
3843 restart:
3844 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3845 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3846 goto restart;
3847
3848 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3849 spin_unlock(&kvm->mmu_lock);
3850 }
3851
3852 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3853 struct list_head *invalid_list)
3854 {
3855 struct kvm_mmu_page *page;
3856
3857 page = container_of(kvm->arch.active_mmu_pages.prev,
3858 struct kvm_mmu_page, link);
3859 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3860 }
3861
3862 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3863 {
3864 struct kvm *kvm;
3865 struct kvm *kvm_freed = NULL;
3866 int nr_to_scan = sc->nr_to_scan;
3867
3868 if (nr_to_scan == 0)
3869 goto out;
3870
3871 raw_spin_lock(&kvm_lock);
3872
3873 list_for_each_entry(kvm, &vm_list, vm_list) {
3874 int idx, freed_pages;
3875 LIST_HEAD(invalid_list);
3876
3877 idx = srcu_read_lock(&kvm->srcu);
3878 spin_lock(&kvm->mmu_lock);
3879 if (!kvm_freed && nr_to_scan > 0 &&
3880 kvm->arch.n_used_mmu_pages > 0) {
3881 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3882 &invalid_list);
3883 kvm_freed = kvm;
3884 }
3885 nr_to_scan--;
3886
3887 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3888 spin_unlock(&kvm->mmu_lock);
3889 srcu_read_unlock(&kvm->srcu, idx);
3890 }
3891 if (kvm_freed)
3892 list_move_tail(&kvm_freed->vm_list, &vm_list);
3893
3894 raw_spin_unlock(&kvm_lock);
3895
3896 out:
3897 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3898 }
3899
3900 static struct shrinker mmu_shrinker = {
3901 .shrink = mmu_shrink,
3902 .seeks = DEFAULT_SEEKS * 10,
3903 };
3904
3905 static void mmu_destroy_caches(void)
3906 {
3907 if (pte_list_desc_cache)
3908 kmem_cache_destroy(pte_list_desc_cache);
3909 if (mmu_page_header_cache)
3910 kmem_cache_destroy(mmu_page_header_cache);
3911 }
3912
3913 int kvm_mmu_module_init(void)
3914 {
3915 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3916 sizeof(struct pte_list_desc),
3917 0, 0, NULL);
3918 if (!pte_list_desc_cache)
3919 goto nomem;
3920
3921 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3922 sizeof(struct kvm_mmu_page),
3923 0, 0, NULL);
3924 if (!mmu_page_header_cache)
3925 goto nomem;
3926
3927 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3928 goto nomem;
3929
3930 register_shrinker(&mmu_shrinker);
3931
3932 return 0;
3933
3934 nomem:
3935 mmu_destroy_caches();
3936 return -ENOMEM;
3937 }
3938
3939 /*
3940 * Caculate mmu pages needed for kvm.
3941 */
3942 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3943 {
3944 int i;
3945 unsigned int nr_mmu_pages;
3946 unsigned int nr_pages = 0;
3947 struct kvm_memslots *slots;
3948
3949 slots = kvm_memslots(kvm);
3950
3951 for (i = 0; i < slots->nmemslots; i++)
3952 nr_pages += slots->memslots[i].npages;
3953
3954 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3955 nr_mmu_pages = max(nr_mmu_pages,
3956 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3957
3958 return nr_mmu_pages;
3959 }
3960
3961 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3962 unsigned len)
3963 {
3964 if (len > buffer->len)
3965 return NULL;
3966 return buffer->ptr;
3967 }
3968
3969 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3970 unsigned len)
3971 {
3972 void *ret;
3973
3974 ret = pv_mmu_peek_buffer(buffer, len);
3975 if (!ret)
3976 return ret;
3977 buffer->ptr += len;
3978 buffer->len -= len;
3979 buffer->processed += len;
3980 return ret;
3981 }
3982
3983 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3984 gpa_t addr, gpa_t value)
3985 {
3986 int bytes = 8;
3987 int r;
3988
3989 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3990 bytes = 4;
3991
3992 r = mmu_topup_memory_caches(vcpu);
3993 if (r)
3994 return r;
3995
3996 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3997 return -EFAULT;
3998
3999 return 1;
4000 }
4001
4002 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
4003 {
4004 (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
4005 return 1;
4006 }
4007
4008 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
4009 {
4010 spin_lock(&vcpu->kvm->mmu_lock);
4011 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
4012 spin_unlock(&vcpu->kvm->mmu_lock);
4013 return 1;
4014 }
4015
4016 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
4017 struct kvm_pv_mmu_op_buffer *buffer)
4018 {
4019 struct kvm_mmu_op_header *header;
4020
4021 header = pv_mmu_peek_buffer(buffer, sizeof *header);
4022 if (!header)
4023 return 0;
4024 switch (header->op) {
4025 case KVM_MMU_OP_WRITE_PTE: {
4026 struct kvm_mmu_op_write_pte *wpte;
4027
4028 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
4029 if (!wpte)
4030 return 0;
4031 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
4032 wpte->pte_val);
4033 }
4034 case KVM_MMU_OP_FLUSH_TLB: {
4035 struct kvm_mmu_op_flush_tlb *ftlb;
4036
4037 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
4038 if (!ftlb)
4039 return 0;
4040 return kvm_pv_mmu_flush_tlb(vcpu);
4041 }
4042 case KVM_MMU_OP_RELEASE_PT: {
4043 struct kvm_mmu_op_release_pt *rpt;
4044
4045 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
4046 if (!rpt)
4047 return 0;
4048 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
4049 }
4050 default: return 0;
4051 }
4052 }
4053
4054 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
4055 gpa_t addr, unsigned long *ret)
4056 {
4057 int r;
4058 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
4059
4060 buffer->ptr = buffer->buf;
4061 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
4062 buffer->processed = 0;
4063
4064 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
4065 if (r)
4066 goto out;
4067
4068 while (buffer->len) {
4069 r = kvm_pv_mmu_op_one(vcpu, buffer);
4070 if (r < 0)
4071 goto out;
4072 if (r == 0)
4073 break;
4074 }
4075
4076 r = 1;
4077 out:
4078 *ret = buffer->processed;
4079 return r;
4080 }
4081
4082 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4083 {
4084 struct kvm_shadow_walk_iterator iterator;
4085 u64 spte;
4086 int nr_sptes = 0;
4087
4088 walk_shadow_page_lockless_begin(vcpu);
4089 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4090 sptes[iterator.level-1] = spte;
4091 nr_sptes++;
4092 if (!is_shadow_present_pte(spte))
4093 break;
4094 }
4095 walk_shadow_page_lockless_end(vcpu);
4096
4097 return nr_sptes;
4098 }
4099 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4100
4101 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4102 {
4103 ASSERT(vcpu);
4104
4105 destroy_kvm_mmu(vcpu);
4106 free_mmu_pages(vcpu);
4107 mmu_free_memory_caches(vcpu);
4108 }
4109
4110 #ifdef CONFIG_KVM_MMU_AUDIT
4111 #include "mmu_audit.c"
4112 #else
4113 static void mmu_audit_disable(void) { }
4114 #endif
4115
4116 void kvm_mmu_module_exit(void)
4117 {
4118 mmu_destroy_caches();
4119 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4120 unregister_shrinker(&mmu_shrinker);
4121 mmu_audit_disable();
4122 }
Linux Btrfs Development