arch/arm/mach-s3c2410/pm.c

   1 /* linux/arch/arm/mach-s3c2410/pm.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/init.h>
  24 #include <linux/suspend.h>
  25 #include <linux/errno.h>
  26 #include <linux/time.h>
  27 #include <linux/sysdev.h>
  28 #include <linux/syscore_ops.h>
  29 #include <linux/gpio.h>
  30 #include <linux/io.h>
  31
  32 #include <mach/hardware.h>
  33
  34 #include <asm/mach-types.h>
  35
  36 #include <mach/regs-gpio.h>
  37 #include <mach/h1940.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/pm.h>
  41
  42 static void s3c2410_pm_prepare(void)
  43 {
  44         /* ensure at least GSTATUS3 has the resume address */
  45
  46         __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
  47
  48         S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
  49         S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
  50
  51         if (machine_is_h1940()) {
  52                 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  53                 unsigned long ptr;
  54                 unsigned long calc = 0;
  55
  56                 /* generate check for the bootloader to check on resume */
  57
  58                 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
  59                         calc += __raw_readl(base+ptr);
  60
  61                 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  62         }
  63
  64         /* RX3715 and RX1950 use similar to H1940 code and the
  65          * same offsets for resume and checksum pointers */
  66
  67         if (machine_is_rx3715() || machine_is_rx1950()) {
  68                 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  69                 unsigned long ptr;
  70                 unsigned long calc = 0;
  71
  72                 /* generate check for the bootloader to check on resume */
  73
  74                 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
  75                         calc += __raw_readl(base+ptr);
  76
  77                 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  78         }
  79
  80         if ( machine_is_aml_m5900() )
  81                 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
  82
  83         if (machine_is_rx1950()) {
  84                 /* According to S3C2442 user's manual, page 7-17,
  85                  * when the system is operating in NAND boot mode,
  86                  * the hardware pin configuration - EINT[23:21] –
  87                  * must be set as input for starting up after
  88                  * wakeup from sleep mode
  89                  */
  90                 s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
  91                 s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
  92                 s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
  93         }
  94 }
  95
  96 static void s3c2410_pm_resume(void)
  97 {
  98         unsigned long tmp;
  99
 100         /* unset the return-from-sleep flag, to ensure reset */
 101
 102         tmp = __raw_readl(S3C2410_GSTATUS2);
 103         tmp &= S3C2410_GSTATUS2_OFFRESET;
 104         __raw_writel(tmp, S3C2410_GSTATUS2);
 105
 106         if ( machine_is_aml_m5900() )
 107                 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
 108 }
 109
 110 struct syscore_ops s3c2410_pm_syscore_ops = {
 111         .resume         = s3c2410_pm_resume,
 112 };
 113
 114 static int s3c2410_pm_add(struct sys_device *dev)
 115 {
 116         pm_cpu_prep = s3c2410_pm_prepare;
 117         pm_cpu_sleep = s3c2410_cpu_suspend;
 118
 119         return 0;
 120 }
 121
 122 #if defined(CONFIG_CPU_S3C2410)
 123 static struct sysdev_driver s3c2410_pm_driver = {
 124         .add            = s3c2410_pm_add,
 125 };
 126
 127 /* register ourselves */
 128
 129 static int __init s3c2410_pm_drvinit(void)
 130 {
 131         return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver);
 132 }
 133
 134 arch_initcall(s3c2410_pm_drvinit);
 135
 136 static struct sysdev_driver s3c2410a_pm_driver = {
 137         .add            = s3c2410_pm_add,
 138 };
 139
 140 static int __init s3c2410a_pm_drvinit(void)
 141 {
 142         return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
 143 }
 144
 145 arch_initcall(s3c2410a_pm_drvinit);
 146 #endif
 147
 148 #if defined(CONFIG_CPU_S3C2440)
 149 static struct sysdev_driver s3c2440_pm_driver = {
 150         .add            = s3c2410_pm_add,
 151 };
 152
 153 static int __init s3c2440_pm_drvinit(void)
 154 {
 155         return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver);
 156 }
 157
 158 arch_initcall(s3c2440_pm_drvinit);
 159 #endif
 160
 161 #if defined(CONFIG_CPU_S3C2442)
 162 static struct sysdev_driver s3c2442_pm_driver = {
 163         .add            = s3c2410_pm_add,
 164 };
 165
 166 static int __init s3c2442_pm_drvinit(void)
 167 {
 168         return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver);
 169 }
 170
 171 arch_initcall(s3c2442_pm_drvinit);
 172 #endif