arch/arm/mach-s5pv210/mach-torbreck.c

   1 /* linux/arch/arm/mach-s5pv210/mach-torbreck.c
   2  *
   3  * Copyright (c) 2010 aESOP Community
   4  *              http://www.aesop.or.kr/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/i2c.h>
  14 #include <linux/init.h>
  15 #include <linux/serial_core.h>
  16
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/setup.h>
  20 #include <asm/mach-types.h>
  21
  22 #include <mach/map.h>
  23 #include <mach/regs-clock.h>
  24
  25 #include <plat/regs-serial.h>
  26 #include <plat/s5pv210.h>
  27 #include <plat/devs.h>
  28 #include <plat/cpu.h>
  29 #include <plat/iic.h>
  30 #include <plat/s5p-time.h>
  31
  32 /* Following are default values for UCON, ULCON and UFCON UART registers */
  33 #define TORBRECK_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
  34                                  S3C2410_UCON_RXILEVEL |        \
  35                                  S3C2410_UCON_TXIRQMODE |       \
  36                                  S3C2410_UCON_RXIRQMODE |       \
  37                                  S3C2410_UCON_RXFIFO_TOI |      \
  38                                  S3C2443_UCON_RXERR_IRQEN)
  39
  40 #define TORBRECK_ULCON_DEFAULT  S3C2410_LCON_CS8
  41
  42 #define TORBRECK_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
  43                                  S5PV210_UFCON_TXTRIG4 |        \
  44                                  S5PV210_UFCON_RXTRIG4)
  45
  46 static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
  47         [0] = {
  48                 .hwport         = 0,
  49                 .flags          = 0,
  50                 .ucon           = TORBRECK_UCON_DEFAULT,
  51                 .ulcon          = TORBRECK_ULCON_DEFAULT,
  52                 .ufcon          = TORBRECK_UFCON_DEFAULT,
  53         },
  54         [1] = {
  55                 .hwport         = 1,
  56                 .flags          = 0,
  57                 .ucon           = TORBRECK_UCON_DEFAULT,
  58                 .ulcon          = TORBRECK_ULCON_DEFAULT,
  59                 .ufcon          = TORBRECK_UFCON_DEFAULT,
  60         },
  61         [2] = {
  62                 .hwport         = 2,
  63                 .flags          = 0,
  64                 .ucon           = TORBRECK_UCON_DEFAULT,
  65                 .ulcon          = TORBRECK_ULCON_DEFAULT,
  66                 .ufcon          = TORBRECK_UFCON_DEFAULT,
  67         },
  68         [3] = {
  69                 .hwport         = 3,
  70                 .flags          = 0,
  71                 .ucon           = TORBRECK_UCON_DEFAULT,
  72                 .ulcon          = TORBRECK_ULCON_DEFAULT,
  73                 .ufcon          = TORBRECK_UFCON_DEFAULT,
  74         },
  75 };
  76
  77 static struct platform_device *torbreck_devices[] __initdata = {
  78         &s5pv210_device_iis0,
  79         &s3c_device_cfcon,
  80         &s3c_device_hsmmc0,
  81         &s3c_device_hsmmc1,
  82         &s3c_device_hsmmc2,
  83         &s3c_device_hsmmc3,
  84         &s3c_device_i2c0,
  85         &s3c_device_i2c1,
  86         &s3c_device_i2c2,
  87         &s3c_device_rtc,
  88         &s3c_device_wdt,
  89 };
  90
  91 static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
  92         /* To Be Updated */
  93 };
  94
  95 static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
  96         /* To Be Updated */
  97 };
  98
  99 static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
 100         /* To Be Updated */
 101 };
 102
 103 static void __init torbreck_map_io(void)
 104 {
 105         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
 106         s3c24xx_init_clocks(24000000);
 107         s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
 108         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 109 }
 110
 111 static void __init torbreck_machine_init(void)
 112 {
 113         s3c_i2c0_set_platdata(NULL);
 114         s3c_i2c1_set_platdata(NULL);
 115         s3c_i2c2_set_platdata(NULL);
 116         i2c_register_board_info(0, torbreck_i2c_devs0,
 117                         ARRAY_SIZE(torbreck_i2c_devs0));
 118         i2c_register_board_info(1, torbreck_i2c_devs1,
 119                         ARRAY_SIZE(torbreck_i2c_devs1));
 120         i2c_register_board_info(2, torbreck_i2c_devs2,
 121                         ARRAY_SIZE(torbreck_i2c_devs2));
 122
 123         platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
 124 }
 125
 126 MACHINE_START(TORBRECK, "TORBRECK")
 127         /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
 128         .boot_params    = S5P_PA_SDRAM + 0x100,
 129         .init_irq       = s5pv210_init_irq,
 130         .map_io         = torbreck_map_io,
 131         .init_machine   = torbreck_machine_init,
 132         .timer          = &s5p_timer,
 133 MACHINE_END