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ARM: tegra: fix compilation error due to mach/hardware.h removal
[linux-btrfs-devel.git] / arch / arm / mach-davinci / devices-da8xx.c
blob2f7e719636f1333ce7ef3120a8393e6cd896d0dd
1 /*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
19
20 #include <mach/cputype.h>
21 #include <mach/common.h>
22 #include <mach/time.h>
23 #include <mach/da8xx.h>
24 #include <mach/cpuidle.h>
25
26 #include "clock.h"
27
28 #define DA8XX_TPCC_BASE 0x01c00000
29 #define DA8XX_TPTC0_BASE 0x01c08000
30 #define DA8XX_TPTC1_BASE 0x01c08400
31 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
32 #define DA8XX_I2C0_BASE 0x01c22000
33 #define DA8XX_RTC_BASE 0x01c23000
34 #define DA8XX_MMCSD0_BASE 0x01c40000
35 #define DA8XX_SPI0_BASE 0x01c41000
36 #define DA830_SPI1_BASE 0x01e12000
37 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
38 #define DA850_SATA_BASE 0x01e18000
39 #define DA850_MMCSD1_BASE 0x01e1b000
40 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
41 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
42 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
43 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
44 #define DA8XX_I2C1_BASE 0x01e28000
45 #define DA850_TPCC1_BASE 0x01e30000
46 #define DA850_TPTC2_BASE 0x01e38000
47 #define DA850_SPI1_BASE 0x01f0e000
48 #define DA8XX_DDR2_CTL_BASE 0xb0000000
49
50 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
51 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
52 #define DA8XX_EMAC_RAM_OFFSET 0x0000
53 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
54
55 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
56 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
57 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
58 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
59 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
60 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
61 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
62 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
63
64 void __iomem *da8xx_syscfg0_base;
65 void __iomem *da8xx_syscfg1_base;
66
67 static struct plat_serial8250_port da8xx_serial_pdata[] = {
68 {
69 .mapbase = DA8XX_UART0_BASE,
70 .irq = IRQ_DA8XX_UARTINT0,
71 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
72 UPF_IOREMAP,
73 .iotype = UPIO_MEM,
74 .regshift = 2,
75 },
76 {
77 .mapbase = DA8XX_UART1_BASE,
78 .irq = IRQ_DA8XX_UARTINT1,
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 UPF_IOREMAP,
81 .iotype = UPIO_MEM,
82 .regshift = 2,
83 },
84 {
85 .mapbase = DA8XX_UART2_BASE,
86 .irq = IRQ_DA8XX_UARTINT2,
87 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
88 UPF_IOREMAP,
89 .iotype = UPIO_MEM,
90 .regshift = 2,
91 },
92 {
93 .flags = 0,
94 },
95 };
96
97 struct platform_device da8xx_serial_device = {
98 .name = "serial8250",
99 .id = PLAT8250_DEV_PLATFORM,
100 .dev = {
101 .platform_data = da8xx_serial_pdata,
102 },
103 };
104
105 static const s8 da8xx_queue_tc_mapping[][2] = {
106 /* {event queue no, TC no} */
107 {0, 0},
108 {1, 1},
109 {-1, -1}
110 };
111
112 static const s8 da8xx_queue_priority_mapping[][2] = {
113 /* {event queue no, Priority} */
114 {0, 3},
115 {1, 7},
116 {-1, -1}
117 };
118
119 static const s8 da850_queue_tc_mapping[][2] = {
120 /* {event queue no, TC no} */
121 {0, 0},
122 {-1, -1}
123 };
124
125 static const s8 da850_queue_priority_mapping[][2] = {
126 /* {event queue no, Priority} */
127 {0, 3},
128 {-1, -1}
129 };
130
131 static struct edma_soc_info da830_edma_cc0_info = {
132 .n_channel = 32,
133 .n_region = 4,
134 .n_slot = 128,
135 .n_tc = 2,
136 .n_cc = 1,
137 .queue_tc_mapping = da8xx_queue_tc_mapping,
138 .queue_priority_mapping = da8xx_queue_priority_mapping,
139 };
140
141 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
142 &da830_edma_cc0_info,
143 };
144
145 static struct edma_soc_info da850_edma_cc_info[] = {
146 {
147 .n_channel = 32,
148 .n_region = 4,
149 .n_slot = 128,
150 .n_tc = 2,
151 .n_cc = 1,
152 .queue_tc_mapping = da8xx_queue_tc_mapping,
153 .queue_priority_mapping = da8xx_queue_priority_mapping,
154 },
155 {
156 .n_channel = 32,
157 .n_region = 4,
158 .n_slot = 128,
159 .n_tc = 1,
160 .n_cc = 1,
161 .queue_tc_mapping = da850_queue_tc_mapping,
162 .queue_priority_mapping = da850_queue_priority_mapping,
163 },
164 };
165
166 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
167 &da850_edma_cc_info[0],
168 &da850_edma_cc_info[1],
169 };
170
171 static struct resource da830_edma_resources[] = {
172 {
173 .name = "edma_cc0",
174 .start = DA8XX_TPCC_BASE,
175 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
176 .flags = IORESOURCE_MEM,
177 },
178 {
179 .name = "edma_tc0",
180 .start = DA8XX_TPTC0_BASE,
181 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
182 .flags = IORESOURCE_MEM,
183 },
184 {
185 .name = "edma_tc1",
186 .start = DA8XX_TPTC1_BASE,
187 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
188 .flags = IORESOURCE_MEM,
189 },
190 {
191 .name = "edma0",
192 .start = IRQ_DA8XX_CCINT0,
193 .flags = IORESOURCE_IRQ,
194 },
195 {
196 .name = "edma0_err",
197 .start = IRQ_DA8XX_CCERRINT,
198 .flags = IORESOURCE_IRQ,
199 },
200 };
201
202 static struct resource da850_edma_resources[] = {
203 {
204 .name = "edma_cc0",
205 .start = DA8XX_TPCC_BASE,
206 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
207 .flags = IORESOURCE_MEM,
208 },
209 {
210 .name = "edma_tc0",
211 .start = DA8XX_TPTC0_BASE,
212 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
213 .flags = IORESOURCE_MEM,
214 },
215 {
216 .name = "edma_tc1",
217 .start = DA8XX_TPTC1_BASE,
218 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .name = "edma_cc1",
223 .start = DA850_TPCC1_BASE,
224 .end = DA850_TPCC1_BASE + SZ_32K - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 {
228 .name = "edma_tc2",
229 .start = DA850_TPTC2_BASE,
230 .end = DA850_TPTC2_BASE + SZ_1K - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 {
234 .name = "edma0",
235 .start = IRQ_DA8XX_CCINT0,
236 .flags = IORESOURCE_IRQ,
237 },
238 {
239 .name = "edma0_err",
240 .start = IRQ_DA8XX_CCERRINT,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .name = "edma1",
245 .start = IRQ_DA850_CCINT1,
246 .flags = IORESOURCE_IRQ,
247 },
248 {
249 .name = "edma1_err",
250 .start = IRQ_DA850_CCERRINT1,
251 .flags = IORESOURCE_IRQ,
252 },
253 };
254
255 static struct platform_device da830_edma_device = {
256 .name = "edma",
257 .id = -1,
258 .dev = {
259 .platform_data = da830_edma_info,
260 },
261 .num_resources = ARRAY_SIZE(da830_edma_resources),
262 .resource = da830_edma_resources,
263 };
264
265 static struct platform_device da850_edma_device = {
266 .name = "edma",
267 .id = -1,
268 .dev = {
269 .platform_data = da850_edma_info,
270 },
271 .num_resources = ARRAY_SIZE(da850_edma_resources),
272 .resource = da850_edma_resources,
273 };
274
275 int __init da830_register_edma(struct edma_rsv_info *rsv)
276 {
277 da830_edma_cc0_info.rsv = rsv;
278
279 return platform_device_register(&da830_edma_device);
280 }
281
282 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
283 {
284 if (rsv) {
285 da850_edma_cc_info[0].rsv = rsv[0];
286 da850_edma_cc_info[1].rsv = rsv[1];
287 }
288
289 return platform_device_register(&da850_edma_device);
290 }
291
292 static struct resource da8xx_i2c_resources0[] = {
293 {
294 .start = DA8XX_I2C0_BASE,
295 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .start = IRQ_DA8XX_I2CINT0,
300 .end = IRQ_DA8XX_I2CINT0,
301 .flags = IORESOURCE_IRQ,
302 },
303 };
304
305 static struct platform_device da8xx_i2c_device0 = {
306 .name = "i2c_davinci",
307 .id = 1,
308 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
309 .resource = da8xx_i2c_resources0,
310 };
311
312 static struct resource da8xx_i2c_resources1[] = {
313 {
314 .start = DA8XX_I2C1_BASE,
315 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
316 .flags = IORESOURCE_MEM,
317 },
318 {
319 .start = IRQ_DA8XX_I2CINT1,
320 .end = IRQ_DA8XX_I2CINT1,
321 .flags = IORESOURCE_IRQ,
322 },
323 };
324
325 static struct platform_device da8xx_i2c_device1 = {
326 .name = "i2c_davinci",
327 .id = 2,
328 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
329 .resource = da8xx_i2c_resources1,
330 };
331
332 int __init da8xx_register_i2c(int instance,
333 struct davinci_i2c_platform_data *pdata)
334 {
335 struct platform_device *pdev;
336
337 if (instance == 0)
338 pdev = &da8xx_i2c_device0;
339 else if (instance == 1)
340 pdev = &da8xx_i2c_device1;
341 else
342 return -EINVAL;
343
344 pdev->dev.platform_data = pdata;
345 return platform_device_register(pdev);
346 }
347
348 static struct resource da8xx_watchdog_resources[] = {
349 {
350 .start = DA8XX_WDOG_BASE,
351 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
352 .flags = IORESOURCE_MEM,
353 },
354 };
355
356 struct platform_device da8xx_wdt_device = {
357 .name = "watchdog",
358 .id = -1,
359 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
360 .resource = da8xx_watchdog_resources,
361 };
362
363 int __init da8xx_register_watchdog(void)
364 {
365 return platform_device_register(&da8xx_wdt_device);
366 }
367
368 static struct resource da8xx_emac_resources[] = {
369 {
370 .start = DA8XX_EMAC_CPPI_PORT_BASE,
371 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
372 .flags = IORESOURCE_MEM,
373 },
374 {
375 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
376 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
377 .flags = IORESOURCE_IRQ,
378 },
379 {
380 .start = IRQ_DA8XX_C0_RX_PULSE,
381 .end = IRQ_DA8XX_C0_RX_PULSE,
382 .flags = IORESOURCE_IRQ,
383 },
384 {
385 .start = IRQ_DA8XX_C0_TX_PULSE,
386 .end = IRQ_DA8XX_C0_TX_PULSE,
387 .flags = IORESOURCE_IRQ,
388 },
389 {
390 .start = IRQ_DA8XX_C0_MISC_PULSE,
391 .end = IRQ_DA8XX_C0_MISC_PULSE,
392 .flags = IORESOURCE_IRQ,
393 },
394 };
395
396 struct emac_platform_data da8xx_emac_pdata = {
397 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
398 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
399 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
400 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
401 .version = EMAC_VERSION_2,
402 };
403
404 static struct platform_device da8xx_emac_device = {
405 .name = "davinci_emac",
406 .id = 1,
407 .dev = {
408 .platform_data = &da8xx_emac_pdata,
409 },
410 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
411 .resource = da8xx_emac_resources,
412 };
413
414 static struct resource da8xx_mdio_resources[] = {
415 {
416 .start = DA8XX_EMAC_MDIO_BASE,
417 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
418 .flags = IORESOURCE_MEM,
419 },
420 };
421
422 static struct platform_device da8xx_mdio_device = {
423 .name = "davinci_mdio",
424 .id = 0,
425 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
426 .resource = da8xx_mdio_resources,
427 };
428
429 int __init da8xx_register_emac(void)
430 {
431 int ret;
432
433 ret = platform_device_register(&da8xx_mdio_device);
434 if (ret < 0)
435 return ret;
436 ret = platform_device_register(&da8xx_emac_device);
437 if (ret < 0)
438 return ret;
439 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
440 NULL, &da8xx_emac_device.dev);
441 return ret;
442 }
443
444 static struct resource da830_mcasp1_resources[] = {
445 {
446 .name = "mcasp1",
447 .start = DAVINCI_DA830_MCASP1_REG_BASE,
448 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
449 .flags = IORESOURCE_MEM,
450 },
451 /* TX event */
452 {
453 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
454 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
455 .flags = IORESOURCE_DMA,
456 },
457 /* RX event */
458 {
459 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
460 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
461 .flags = IORESOURCE_DMA,
462 },
463 };
464
465 static struct platform_device da830_mcasp1_device = {
466 .name = "davinci-mcasp",
467 .id = 1,
468 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
469 .resource = da830_mcasp1_resources,
470 };
471
472 static struct resource da850_mcasp_resources[] = {
473 {
474 .name = "mcasp",
475 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
476 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 /* TX event */
480 {
481 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
482 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
483 .flags = IORESOURCE_DMA,
484 },
485 /* RX event */
486 {
487 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
488 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
489 .flags = IORESOURCE_DMA,
490 },
491 };
492
493 static struct platform_device da850_mcasp_device = {
494 .name = "davinci-mcasp",
495 .id = 0,
496 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
497 .resource = da850_mcasp_resources,
498 };
499
500 static struct platform_device davinci_pcm_device = {
501 .name = "davinci-pcm-audio",
502 .id = -1,
503 };
504
505 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
506 {
507 platform_device_register(&davinci_pcm_device);
508
509 /* DA830/OMAP-L137 has 3 instances of McASP */
510 if (cpu_is_davinci_da830() && id == 1) {
511 da830_mcasp1_device.dev.platform_data = pdata;
512 platform_device_register(&da830_mcasp1_device);
513 } else if (cpu_is_davinci_da850()) {
514 da850_mcasp_device.dev.platform_data = pdata;
515 platform_device_register(&da850_mcasp_device);
516 }
517 }
518
519 static const struct display_panel disp_panel = {
520 QVGA,
521 16,
522 16,
523 COLOR_ACTIVE,
524 };
525
526 static struct lcd_ctrl_config lcd_cfg = {
527 &disp_panel,
528 .ac_bias = 255,
529 .ac_bias_intrpt = 0,
530 .dma_burst_sz = 16,
531 .bpp = 16,
532 .fdd = 255,
533 .tft_alt_mode = 0,
534 .stn_565_mode = 0,
535 .mono_8bit_mode = 0,
536 .invert_line_clock = 1,
537 .invert_frm_clock = 1,
538 .sync_edge = 0,
539 .sync_ctrl = 1,
540 .raster_order = 0,
541 };
542
543 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
544 .manu_name = "sharp",
545 .controller_data = &lcd_cfg,
546 .type = "Sharp_LCD035Q3DG01",
547 };
548
549 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
550 .manu_name = "sharp",
551 .controller_data = &lcd_cfg,
552 .type = "Sharp_LK043T1DG01",
553 };
554
555 static struct resource da8xx_lcdc_resources[] = {
556 [0] = { /* registers */
557 .start = DA8XX_LCD_CNTRL_BASE,
558 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
559 .flags = IORESOURCE_MEM,
560 },
561 [1] = { /* interrupt */
562 .start = IRQ_DA8XX_LCDINT,
563 .end = IRQ_DA8XX_LCDINT,
564 .flags = IORESOURCE_IRQ,
565 },
566 };
567
568 static struct platform_device da8xx_lcdc_device = {
569 .name = "da8xx_lcdc",
570 .id = 0,
571 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
572 .resource = da8xx_lcdc_resources,
573 };
574
575 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
576 {
577 da8xx_lcdc_device.dev.platform_data = pdata;
578 return platform_device_register(&da8xx_lcdc_device);
579 }
580
581 static struct resource da8xx_mmcsd0_resources[] = {
582 { /* registers */
583 .start = DA8XX_MMCSD0_BASE,
584 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
585 .flags = IORESOURCE_MEM,
586 },
587 { /* interrupt */
588 .start = IRQ_DA8XX_MMCSDINT0,
589 .end = IRQ_DA8XX_MMCSDINT0,
590 .flags = IORESOURCE_IRQ,
591 },
592 { /* DMA RX */
593 .start = DA8XX_DMA_MMCSD0_RX,
594 .end = DA8XX_DMA_MMCSD0_RX,
595 .flags = IORESOURCE_DMA,
596 },
597 { /* DMA TX */
598 .start = DA8XX_DMA_MMCSD0_TX,
599 .end = DA8XX_DMA_MMCSD0_TX,
600 .flags = IORESOURCE_DMA,
601 },
602 };
603
604 static struct platform_device da8xx_mmcsd0_device = {
605 .name = "davinci_mmc",
606 .id = 0,
607 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
608 .resource = da8xx_mmcsd0_resources,
609 };
610
611 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
612 {
613 da8xx_mmcsd0_device.dev.platform_data = config;
614 return platform_device_register(&da8xx_mmcsd0_device);
615 }
616
617 #ifdef CONFIG_ARCH_DAVINCI_DA850
618 static struct resource da850_mmcsd1_resources[] = {
619 { /* registers */
620 .start = DA850_MMCSD1_BASE,
621 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
622 .flags = IORESOURCE_MEM,
623 },
624 { /* interrupt */
625 .start = IRQ_DA850_MMCSDINT0_1,
626 .end = IRQ_DA850_MMCSDINT0_1,
627 .flags = IORESOURCE_IRQ,
628 },
629 { /* DMA RX */
630 .start = DA850_DMA_MMCSD1_RX,
631 .end = DA850_DMA_MMCSD1_RX,
632 .flags = IORESOURCE_DMA,
633 },
634 { /* DMA TX */
635 .start = DA850_DMA_MMCSD1_TX,
636 .end = DA850_DMA_MMCSD1_TX,
637 .flags = IORESOURCE_DMA,
638 },
639 };
640
641 static struct platform_device da850_mmcsd1_device = {
642 .name = "davinci_mmc",
643 .id = 1,
644 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
645 .resource = da850_mmcsd1_resources,
646 };
647
648 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
649 {
650 da850_mmcsd1_device.dev.platform_data = config;
651 return platform_device_register(&da850_mmcsd1_device);
652 }
653 #endif
654
655 static struct resource da8xx_rtc_resources[] = {
656 {
657 .start = DA8XX_RTC_BASE,
658 .end = DA8XX_RTC_BASE + SZ_4K - 1,
659 .flags = IORESOURCE_MEM,
660 },
661 { /* timer irq */
662 .start = IRQ_DA8XX_RTC,
663 .end = IRQ_DA8XX_RTC,
664 .flags = IORESOURCE_IRQ,
665 },
666 { /* alarm irq */
667 .start = IRQ_DA8XX_RTC,
668 .end = IRQ_DA8XX_RTC,
669 .flags = IORESOURCE_IRQ,
670 },
671 };
672
673 static struct platform_device da8xx_rtc_device = {
674 .name = "omap_rtc",
675 .id = -1,
676 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
677 .resource = da8xx_rtc_resources,
678 };
679
680 int da8xx_register_rtc(void)
681 {
682 int ret;
683 void __iomem *base;
684
685 base = ioremap(DA8XX_RTC_BASE, SZ_4K);
686 if (WARN_ON(!base))
687 return -ENOMEM;
688
689 /* Unlock the rtc's registers */
690 __raw_writel(0x83e70b13, base + 0x6c);
691 __raw_writel(0x95a4f1e0, base + 0x70);
692
693 iounmap(base);
694
695 ret = platform_device_register(&da8xx_rtc_device);
696 if (!ret)
697 /* Atleast on DA850, RTC is a wakeup source */
698 device_init_wakeup(&da8xx_rtc_device.dev, true);
699
700 return ret;
701 }
702
703 static void __iomem *da8xx_ddr2_ctlr_base;
704 void __iomem * __init da8xx_get_mem_ctlr(void)
705 {
706 if (da8xx_ddr2_ctlr_base)
707 return da8xx_ddr2_ctlr_base;
708
709 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
710 if (!da8xx_ddr2_ctlr_base)
711 pr_warning("%s: Unable to map DDR2 controller", __func__);
712
713 return da8xx_ddr2_ctlr_base;
714 }
715
716 static struct resource da8xx_cpuidle_resources[] = {
717 {
718 .start = DA8XX_DDR2_CTL_BASE,
719 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
720 .flags = IORESOURCE_MEM,
721 },
722 };
723
724 /* DA8XX devices support DDR2 power down */
725 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
726 .ddr2_pdown = 1,
727 };
728
729
730 static struct platform_device da8xx_cpuidle_device = {
731 .name = "cpuidle-davinci",
732 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
733 .resource = da8xx_cpuidle_resources,
734 .dev = {
735 .platform_data = &da8xx_cpuidle_pdata,
736 },
737 };
738
739 int __init da8xx_register_cpuidle(void)
740 {
741 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
742
743 return platform_device_register(&da8xx_cpuidle_device);
744 }
745
746 static struct resource da8xx_spi0_resources[] = {
747 [0] = {
748 .start = DA8XX_SPI0_BASE,
749 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
750 .flags = IORESOURCE_MEM,
751 },
752 [1] = {
753 .start = IRQ_DA8XX_SPINT0,
754 .end = IRQ_DA8XX_SPINT0,
755 .flags = IORESOURCE_IRQ,
756 },
757 [2] = {
758 .start = DA8XX_DMA_SPI0_RX,
759 .end = DA8XX_DMA_SPI0_RX,
760 .flags = IORESOURCE_DMA,
761 },
762 [3] = {
763 .start = DA8XX_DMA_SPI0_TX,
764 .end = DA8XX_DMA_SPI0_TX,
765 .flags = IORESOURCE_DMA,
766 },
767 };
768
769 static struct resource da8xx_spi1_resources[] = {
770 [0] = {
771 .start = DA830_SPI1_BASE,
772 .end = DA830_SPI1_BASE + SZ_4K - 1,
773 .flags = IORESOURCE_MEM,
774 },
775 [1] = {
776 .start = IRQ_DA8XX_SPINT1,
777 .end = IRQ_DA8XX_SPINT1,
778 .flags = IORESOURCE_IRQ,
779 },
780 [2] = {
781 .start = DA8XX_DMA_SPI1_RX,
782 .end = DA8XX_DMA_SPI1_RX,
783 .flags = IORESOURCE_DMA,
784 },
785 [3] = {
786 .start = DA8XX_DMA_SPI1_TX,
787 .end = DA8XX_DMA_SPI1_TX,
788 .flags = IORESOURCE_DMA,
789 },
790 };
791
792 struct davinci_spi_platform_data da8xx_spi_pdata[] = {
793 [0] = {
794 .version = SPI_VERSION_2,
795 .intr_line = 1,
796 .dma_event_q = EVENTQ_0,
797 },
798 [1] = {
799 .version = SPI_VERSION_2,
800 .intr_line = 1,
801 .dma_event_q = EVENTQ_0,
802 },
803 };
804
805 static struct platform_device da8xx_spi_device[] = {
806 [0] = {
807 .name = "spi_davinci",
808 .id = 0,
809 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
810 .resource = da8xx_spi0_resources,
811 .dev = {
812 .platform_data = &da8xx_spi_pdata[0],
813 },
814 },
815 [1] = {
816 .name = "spi_davinci",
817 .id = 1,
818 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
819 .resource = da8xx_spi1_resources,
820 .dev = {
821 .platform_data = &da8xx_spi_pdata[1],
822 },
823 },
824 };
825
826 int __init da8xx_register_spi(int instance, struct spi_board_info *info,
827 unsigned len)
828 {
829 int ret;
830
831 if (instance < 0 || instance > 1)
832 return -EINVAL;
833
834 ret = spi_register_board_info(info, len);
835 if (ret)
836 pr_warning("%s: failed to register board info for spi %d :"
837 " %d\n", __func__, instance, ret);
838
839 da8xx_spi_pdata[instance].num_chipselect = len;
840
841 if (instance == 1 && cpu_is_davinci_da850()) {
842 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
843 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
844 }
845
846 return platform_device_register(&da8xx_spi_device[instance]);
847 }
848
849 #ifdef CONFIG_ARCH_DAVINCI_DA850
850
851 static struct resource da850_sata_resources[] = {
852 {
853 .start = DA850_SATA_BASE,
854 .end = DA850_SATA_BASE + 0x1fff,
855 .flags = IORESOURCE_MEM,
856 },
857 {
858 .start = IRQ_DA850_SATAINT,
859 .flags = IORESOURCE_IRQ,
860 },
861 };
862
863 /* SATA PHY Control Register offset from AHCI base */
864 #define SATA_P0PHYCR_REG 0x178
865
866 #define SATA_PHY_MPY(x) ((x) << 0)
867 #define SATA_PHY_LOS(x) ((x) << 6)
868 #define SATA_PHY_RXCDR(x) ((x) << 10)
869 #define SATA_PHY_RXEQ(x) ((x) << 13)
870 #define SATA_PHY_TXSWING(x) ((x) << 19)
871 #define SATA_PHY_ENPLL(x) ((x) << 31)
872
873 static struct clk *da850_sata_clk;
874 static unsigned long da850_sata_refclkpn;
875
876 /* Supported DA850 SATA crystal frequencies */
877 #define KHZ_TO_HZ(freq) ((freq) * 1000)
878 static unsigned long da850_sata_xtal[] = {
879 KHZ_TO_HZ(300000),
880 KHZ_TO_HZ(250000),
881 0, /* Reserved */
882 KHZ_TO_HZ(187500),
883 KHZ_TO_HZ(150000),
884 KHZ_TO_HZ(125000),
885 KHZ_TO_HZ(120000),
886 KHZ_TO_HZ(100000),
887 KHZ_TO_HZ(75000),
888 KHZ_TO_HZ(60000),
889 };
890
891 static int da850_sata_init(struct device *dev, void __iomem *addr)
892 {
893 int i, ret;
894 unsigned int val;
895
896 da850_sata_clk = clk_get(dev, NULL);
897 if (IS_ERR(da850_sata_clk))
898 return PTR_ERR(da850_sata_clk);
899
900 ret = clk_enable(da850_sata_clk);
901 if (ret)
902 goto err0;
903
904 /* Enable SATA clock receiver */
905 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
906 val &= ~BIT(0);
907 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
908
909 /* Get the multiplier needed for 1.5GHz PLL output */
910 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
911 if (da850_sata_xtal[i] == da850_sata_refclkpn)
912 break;
913
914 if (i == ARRAY_SIZE(da850_sata_xtal)) {
915 ret = -EINVAL;
916 goto err1;
917 }
918
919 val = SATA_PHY_MPY(i + 1) |
920 SATA_PHY_LOS(1) |
921 SATA_PHY_RXCDR(4) |
922 SATA_PHY_RXEQ(1) |
923 SATA_PHY_TXSWING(3) |
924 SATA_PHY_ENPLL(1);
925
926 __raw_writel(val, addr + SATA_P0PHYCR_REG);
927
928 return 0;
929
930 err1:
931 clk_disable(da850_sata_clk);
932 err0:
933 clk_put(da850_sata_clk);
934 return ret;
935 }
936
937 static void da850_sata_exit(struct device *dev)
938 {
939 clk_disable(da850_sata_clk);
940 clk_put(da850_sata_clk);
941 }
942
943 static struct ahci_platform_data da850_sata_pdata = {
944 .init = da850_sata_init,
945 .exit = da850_sata_exit,
946 };
947
948 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
949
950 static struct platform_device da850_sata_device = {
951 .name = "ahci",
952 .id = -1,
953 .dev = {
954 .platform_data = &da850_sata_pdata,
955 .dma_mask = &da850_sata_dmamask,
956 .coherent_dma_mask = DMA_BIT_MASK(32),
957 },
958 .num_resources = ARRAY_SIZE(da850_sata_resources),
959 .resource = da850_sata_resources,
960 };
961
962 int __init da850_register_sata(unsigned long refclkpn)
963 {
964 da850_sata_refclkpn = refclkpn;
965 if (!da850_sata_refclkpn)
966 return -EINVAL;
967
968 return platform_device_register(&da850_sata_device);
969 }
970 #endif
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