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ARM: tegra: fix compilation error due to mach/hardware.h removal
[linux-btrfs-devel.git] / arch / arm / mach-omap2 / board-3430sdp.c
blobbd600cfb7f80cf1041faa89c76af1ea023e9a4ad
1 /*
2 * linux/arch/arm/mach-omap2/board-3430sdp.c
3 *
4 * Copyright (C) 2007 Texas Instruments
5 *
6 * Modified from mach-omap2/board-generic.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/input.h>
20 #include <linux/input/matrix_keypad.h>
21 #include <linux/spi/spi.h>
22 #include <linux/i2c/twl.h>
23 #include <linux/regulator/machine.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/mmc/host.h>
27
28 #include <mach/hardware.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32
33 #include <plat/mcspi.h>
34 #include <plat/board.h>
35 #include <plat/usb.h>
36 #include <plat/common.h>
37 #include <plat/dma.h>
38 #include <plat/gpmc.h>
39 #include <video/omapdss.h>
40 #include <video/omap-panel-generic-dpi.h>
41
42 #include <plat/gpmc-smc91x.h>
43
44 #include "board-flash.h"
45 #include "mux.h"
46 #include "sdram-qimonda-hyb18m512160af-6.h"
47 #include "hsmmc.h"
48 #include "pm.h"
49 #include "control.h"
50 #include "common-board-devices.h"
51
52 #define CONFIG_DISABLE_HFCLK 1
53
54 #define SDP3430_TS_GPIO_IRQ_SDPV1 3
55 #define SDP3430_TS_GPIO_IRQ_SDPV2 2
56
57 #define ENABLE_VAUX3_DEDICATED 0x03
58 #define ENABLE_VAUX3_DEV_GRP 0x20
59
60 #define TWL4030_MSECURE_GPIO 22
61
62 static uint32_t board_keymap[] = {
63 KEY(0, 0, KEY_LEFT),
64 KEY(0, 1, KEY_RIGHT),
65 KEY(0, 2, KEY_A),
66 KEY(0, 3, KEY_B),
67 KEY(0, 4, KEY_C),
68 KEY(1, 0, KEY_DOWN),
69 KEY(1, 1, KEY_UP),
70 KEY(1, 2, KEY_E),
71 KEY(1, 3, KEY_F),
72 KEY(1, 4, KEY_G),
73 KEY(2, 0, KEY_ENTER),
74 KEY(2, 1, KEY_I),
75 KEY(2, 2, KEY_J),
76 KEY(2, 3, KEY_K),
77 KEY(2, 4, KEY_3),
78 KEY(3, 0, KEY_M),
79 KEY(3, 1, KEY_N),
80 KEY(3, 2, KEY_O),
81 KEY(3, 3, KEY_P),
82 KEY(3, 4, KEY_Q),
83 KEY(4, 0, KEY_R),
84 KEY(4, 1, KEY_4),
85 KEY(4, 2, KEY_T),
86 KEY(4, 3, KEY_U),
87 KEY(4, 4, KEY_D),
88 KEY(5, 0, KEY_V),
89 KEY(5, 1, KEY_W),
90 KEY(5, 2, KEY_L),
91 KEY(5, 3, KEY_S),
92 KEY(5, 4, KEY_H),
93 0
94 };
95
96 static struct matrix_keymap_data board_map_data = {
97 .keymap = board_keymap,
98 .keymap_size = ARRAY_SIZE(board_keymap),
99 };
100
101 static struct twl4030_keypad_data sdp3430_kp_data = {
102 .keymap_data = &board_map_data,
103 .rows = 5,
104 .cols = 6,
105 .rep = 1,
106 };
107
108 #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
109 #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
110
111 static struct gpio sdp3430_dss_gpios[] __initdata = {
112 {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
113 {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
114 };
115
116 static int lcd_enabled;
117 static int dvi_enabled;
118
119 static void __init sdp3430_display_init(void)
120 {
121 int r;
122
123 r = gpio_request_array(sdp3430_dss_gpios,
124 ARRAY_SIZE(sdp3430_dss_gpios));
125 if (r)
126 printk(KERN_ERR "failed to get LCD control GPIOs\n");
127
128 }
129
130 static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
131 {
132 if (dvi_enabled) {
133 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
134 return -EINVAL;
135 }
136
137 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
138 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
139
140 lcd_enabled = 1;
141
142 return 0;
143 }
144
145 static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
146 {
147 lcd_enabled = 0;
148
149 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
150 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
151 }
152
153 static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
154 {
155 if (lcd_enabled) {
156 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
157 return -EINVAL;
158 }
159
160 dvi_enabled = 1;
161
162 return 0;
163 }
164
165 static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
166 {
167 dvi_enabled = 0;
168 }
169
170 static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
171 {
172 return 0;
173 }
174
175 static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
176 {
177 }
178
179
180 static struct omap_dss_device sdp3430_lcd_device = {
181 .name = "lcd",
182 .driver_name = "sharp_ls_panel",
183 .type = OMAP_DISPLAY_TYPE_DPI,
184 .phy.dpi.data_lines = 16,
185 .platform_enable = sdp3430_panel_enable_lcd,
186 .platform_disable = sdp3430_panel_disable_lcd,
187 };
188
189 static struct panel_generic_dpi_data dvi_panel = {
190 .name = "generic",
191 .platform_enable = sdp3430_panel_enable_dvi,
192 .platform_disable = sdp3430_panel_disable_dvi,
193 };
194
195 static struct omap_dss_device sdp3430_dvi_device = {
196 .name = "dvi",
197 .type = OMAP_DISPLAY_TYPE_DPI,
198 .driver_name = "generic_dpi_panel",
199 .data = &dvi_panel,
200 .phy.dpi.data_lines = 24,
201 };
202
203 static struct omap_dss_device sdp3430_tv_device = {
204 .name = "tv",
205 .driver_name = "venc",
206 .type = OMAP_DISPLAY_TYPE_VENC,
207 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
208 .platform_enable = sdp3430_panel_enable_tv,
209 .platform_disable = sdp3430_panel_disable_tv,
210 };
211
212
213 static struct omap_dss_device *sdp3430_dss_devices[] = {
214 &sdp3430_lcd_device,
215 &sdp3430_dvi_device,
216 &sdp3430_tv_device,
217 };
218
219 static struct omap_dss_board_info sdp3430_dss_data = {
220 .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
221 .devices = sdp3430_dss_devices,
222 .default_device = &sdp3430_lcd_device,
223 };
224
225 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
226 };
227
228 static void __init omap_3430sdp_init_early(void)
229 {
230 omap2_init_common_infrastructure();
231 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
232 }
233
234 static struct omap2_hsmmc_info mmc[] = {
235 {
236 .mmc = 1,
237 /* 8 bits (default) requires S6.3 == ON,
238 * so the SIM card isn't used; else 4 bits.
239 */
240 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
241 .gpio_wp = 4,
242 },
243 {
244 .mmc = 2,
245 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
246 .gpio_wp = 7,
247 },
248 {} /* Terminator */
249 };
250
251 static int sdp3430_twl_gpio_setup(struct device *dev,
252 unsigned gpio, unsigned ngpio)
253 {
254 /* gpio + 0 is "mmc0_cd" (input/IRQ),
255 * gpio + 1 is "mmc1_cd" (input/IRQ)
256 */
257 mmc[0].gpio_cd = gpio + 0;
258 mmc[1].gpio_cd = gpio + 1;
259 omap2_hsmmc_init(mmc);
260
261 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
262 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
263
264 /* gpio + 15 is "sub_lcd_nRST" (output) */
265 gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
266
267 return 0;
268 }
269
270 static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
271 .gpio_base = OMAP_MAX_GPIO_LINES,
272 .irq_base = TWL4030_GPIO_IRQ_BASE,
273 .irq_end = TWL4030_GPIO_IRQ_END,
274 .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
275 | BIT(16) | BIT(17),
276 .setup = sdp3430_twl_gpio_setup,
277 };
278
279 /* regulator consumer mappings */
280
281 /* ads7846 on SPI */
282 static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
283 REGULATOR_SUPPLY("vcc", "spi1.0"),
284 };
285
286 static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
287 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
288 };
289
290 static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
291 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
292 };
293
294 static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
295 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
296 };
297
298 /*
299 * Apply all the fixed voltages since most versions of U-Boot
300 * don't bother with that initialization.
301 */
302
303 /* VAUX1 for mainboard (irda and sub-lcd) */
304 static struct regulator_init_data sdp3430_vaux1 = {
305 .constraints = {
306 .min_uV = 2800000,
307 .max_uV = 2800000,
308 .apply_uV = true,
309 .valid_modes_mask = REGULATOR_MODE_NORMAL
310 | REGULATOR_MODE_STANDBY,
311 .valid_ops_mask = REGULATOR_CHANGE_MODE
312 | REGULATOR_CHANGE_STATUS,
313 },
314 };
315
316 /* VAUX2 for camera module */
317 static struct regulator_init_data sdp3430_vaux2 = {
318 .constraints = {
319 .min_uV = 2800000,
320 .max_uV = 2800000,
321 .apply_uV = true,
322 .valid_modes_mask = REGULATOR_MODE_NORMAL
323 | REGULATOR_MODE_STANDBY,
324 .valid_ops_mask = REGULATOR_CHANGE_MODE
325 | REGULATOR_CHANGE_STATUS,
326 },
327 };
328
329 /* VAUX3 for LCD board */
330 static struct regulator_init_data sdp3430_vaux3 = {
331 .constraints = {
332 .min_uV = 2800000,
333 .max_uV = 2800000,
334 .apply_uV = true,
335 .valid_modes_mask = REGULATOR_MODE_NORMAL
336 | REGULATOR_MODE_STANDBY,
337 .valid_ops_mask = REGULATOR_CHANGE_MODE
338 | REGULATOR_CHANGE_STATUS,
339 },
340 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
341 .consumer_supplies = sdp3430_vaux3_supplies,
342 };
343
344 /* VAUX4 for OMAP VDD_CSI2 (camera) */
345 static struct regulator_init_data sdp3430_vaux4 = {
346 .constraints = {
347 .min_uV = 1800000,
348 .max_uV = 1800000,
349 .apply_uV = true,
350 .valid_modes_mask = REGULATOR_MODE_NORMAL
351 | REGULATOR_MODE_STANDBY,
352 .valid_ops_mask = REGULATOR_CHANGE_MODE
353 | REGULATOR_CHANGE_STATUS,
354 },
355 };
356
357 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
358 static struct regulator_init_data sdp3430_vmmc1 = {
359 .constraints = {
360 .min_uV = 1850000,
361 .max_uV = 3150000,
362 .valid_modes_mask = REGULATOR_MODE_NORMAL
363 | REGULATOR_MODE_STANDBY,
364 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
365 | REGULATOR_CHANGE_MODE
366 | REGULATOR_CHANGE_STATUS,
367 },
368 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
369 .consumer_supplies = sdp3430_vmmc1_supplies,
370 };
371
372 /* VMMC2 for MMC2 card */
373 static struct regulator_init_data sdp3430_vmmc2 = {
374 .constraints = {
375 .min_uV = 1850000,
376 .max_uV = 1850000,
377 .apply_uV = true,
378 .valid_modes_mask = REGULATOR_MODE_NORMAL
379 | REGULATOR_MODE_STANDBY,
380 .valid_ops_mask = REGULATOR_CHANGE_MODE
381 | REGULATOR_CHANGE_STATUS,
382 },
383 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
384 .consumer_supplies = sdp3430_vmmc2_supplies,
385 };
386
387 /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
388 static struct regulator_init_data sdp3430_vsim = {
389 .constraints = {
390 .min_uV = 1800000,
391 .max_uV = 3000000,
392 .valid_modes_mask = REGULATOR_MODE_NORMAL
393 | REGULATOR_MODE_STANDBY,
394 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
395 | REGULATOR_CHANGE_MODE
396 | REGULATOR_CHANGE_STATUS,
397 },
398 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
399 .consumer_supplies = sdp3430_vsim_supplies,
400 };
401
402 static struct twl4030_platform_data sdp3430_twldata = {
403 /* platform_data for children goes here */
404 .gpio = &sdp3430_gpio_data,
405 .keypad = &sdp3430_kp_data,
406
407 .vaux1 = &sdp3430_vaux1,
408 .vaux2 = &sdp3430_vaux2,
409 .vaux3 = &sdp3430_vaux3,
410 .vaux4 = &sdp3430_vaux4,
411 .vmmc1 = &sdp3430_vmmc1,
412 .vmmc2 = &sdp3430_vmmc2,
413 .vsim = &sdp3430_vsim,
414 };
415
416 static int __init omap3430_i2c_init(void)
417 {
418 /* i2c1 for PMIC only */
419 omap3_pmic_get_config(&sdp3430_twldata,
420 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
421 TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
422 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
423 sdp3430_twldata.vdac->constraints.apply_uV = true;
424 sdp3430_twldata.vpll2->constraints.apply_uV = true;
425 sdp3430_twldata.vpll2->constraints.name = "VDVI";
426
427 omap3_pmic_init("twl4030", &sdp3430_twldata);
428
429 /* i2c2 on camera connector (for sensor control) and optional isp1301 */
430 omap_register_i2c_bus(2, 400, NULL, 0);
431 /* i2c3 on display connector (for DVI, tfp410) */
432 omap_register_i2c_bus(3, 400, NULL, 0);
433 return 0;
434 }
435
436 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
437
438 static struct omap_smc91x_platform_data board_smc91x_data = {
439 .cs = 3,
440 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
441 IORESOURCE_IRQ_LOWLEVEL,
442 };
443
444 static void __init board_smc91x_init(void)
445 {
446 if (omap_rev() > OMAP3430_REV_ES1_0)
447 board_smc91x_data.gpio_irq = 6;
448 else
449 board_smc91x_data.gpio_irq = 29;
450
451 gpmc_smc91x_init(&board_smc91x_data);
452 }
453
454 #else
455
456 static inline void board_smc91x_init(void)
457 {
458 }
459
460 #endif
461
462 static void enable_board_wakeup_source(void)
463 {
464 /* T2 interrupt line (keypad) */
465 omap_mux_init_signal("sys_nirq",
466 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
467 }
468
469 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
470
471 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
472 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
473 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
474
475 .phy_reset = true,
476 .reset_gpio_port[0] = 57,
477 .reset_gpio_port[1] = 61,
478 .reset_gpio_port[2] = -EINVAL
479 };
480
481 #ifdef CONFIG_OMAP_MUX
482 static struct omap_board_mux board_mux[] __initdata = {
483 { .reg_offset = OMAP_MUX_TERMINATOR },
484 };
485
486 static struct omap_device_pad serial1_pads[] __initdata = {
487 /*
488 * Note that off output enable is an active low
489 * signal. So setting this means pin is a
490 * input enabled in off mode
491 */
492 OMAP_MUX_STATIC("uart1_cts.uart1_cts",
493 OMAP_PIN_INPUT |
494 OMAP_PIN_OFF_INPUT_PULLDOWN |
495 OMAP_OFFOUT_EN |
496 OMAP_MUX_MODE0),
497 OMAP_MUX_STATIC("uart1_rts.uart1_rts",
498 OMAP_PIN_OUTPUT |
499 OMAP_OFF_EN |
500 OMAP_MUX_MODE0),
501 OMAP_MUX_STATIC("uart1_rx.uart1_rx",
502 OMAP_PIN_INPUT |
503 OMAP_PIN_OFF_INPUT_PULLDOWN |
504 OMAP_OFFOUT_EN |
505 OMAP_MUX_MODE0),
506 OMAP_MUX_STATIC("uart1_tx.uart1_tx",
507 OMAP_PIN_OUTPUT |
508 OMAP_OFF_EN |
509 OMAP_MUX_MODE0),
510 };
511
512 static struct omap_device_pad serial2_pads[] __initdata = {
513 OMAP_MUX_STATIC("uart2_cts.uart2_cts",
514 OMAP_PIN_INPUT_PULLUP |
515 OMAP_PIN_OFF_INPUT_PULLDOWN |
516 OMAP_OFFOUT_EN |
517 OMAP_MUX_MODE0),
518 OMAP_MUX_STATIC("uart2_rts.uart2_rts",
519 OMAP_PIN_OUTPUT |
520 OMAP_OFF_EN |
521 OMAP_MUX_MODE0),
522 OMAP_MUX_STATIC("uart2_rx.uart2_rx",
523 OMAP_PIN_INPUT |
524 OMAP_PIN_OFF_INPUT_PULLDOWN |
525 OMAP_OFFOUT_EN |
526 OMAP_MUX_MODE0),
527 OMAP_MUX_STATIC("uart2_tx.uart2_tx",
528 OMAP_PIN_OUTPUT |
529 OMAP_OFF_EN |
530 OMAP_MUX_MODE0),
531 };
532
533 static struct omap_device_pad serial3_pads[] __initdata = {
534 OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
535 OMAP_PIN_INPUT_PULLDOWN |
536 OMAP_PIN_OFF_INPUT_PULLDOWN |
537 OMAP_OFFOUT_EN |
538 OMAP_MUX_MODE0),
539 OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
540 OMAP_PIN_OUTPUT |
541 OMAP_OFF_EN |
542 OMAP_MUX_MODE0),
543 OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
544 OMAP_PIN_INPUT |
545 OMAP_PIN_OFF_INPUT_PULLDOWN |
546 OMAP_OFFOUT_EN |
547 OMAP_MUX_MODE0),
548 OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
549 OMAP_PIN_OUTPUT |
550 OMAP_OFF_EN |
551 OMAP_MUX_MODE0),
552 };
553
554 static struct omap_board_data serial1_data __initdata = {
555 .id = 0,
556 .pads = serial1_pads,
557 .pads_cnt = ARRAY_SIZE(serial1_pads),
558 };
559
560 static struct omap_board_data serial2_data __initdata = {
561 .id = 1,
562 .pads = serial2_pads,
563 .pads_cnt = ARRAY_SIZE(serial2_pads),
564 };
565
566 static struct omap_board_data serial3_data __initdata = {
567 .id = 2,
568 .pads = serial3_pads,
569 .pads_cnt = ARRAY_SIZE(serial3_pads),
570 };
571
572 static inline void board_serial_init(void)
573 {
574 omap_serial_init_port(&serial1_data);
575 omap_serial_init_port(&serial2_data);
576 omap_serial_init_port(&serial3_data);
577 }
578 #else
579 #define board_mux NULL
580
581 static inline void board_serial_init(void)
582 {
583 omap_serial_init();
584 }
585 #endif
586
587 /*
588 * SDP3430 V2 Board CS organization
589 * Different from SDP3430 V1. Now 4 switches used to specify CS
590 *
591 * See also the Switch S8 settings in the comments.
592 */
593 static char chip_sel_3430[][GPMC_CS_NUM] = {
594 {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
595 {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
596 {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
597 };
598
599 static struct mtd_partition sdp_nor_partitions[] = {
600 /* bootloader (U-Boot, etc) in first sector */
601 {
602 .name = "Bootloader-NOR",
603 .offset = 0,
604 .size = SZ_256K,
605 .mask_flags = MTD_WRITEABLE, /* force read-only */
606 },
607 /* bootloader params in the next sector */
608 {
609 .name = "Params-NOR",
610 .offset = MTDPART_OFS_APPEND,
611 .size = SZ_256K,
612 .mask_flags = 0,
613 },
614 /* kernel */
615 {
616 .name = "Kernel-NOR",
617 .offset = MTDPART_OFS_APPEND,
618 .size = SZ_2M,
619 .mask_flags = 0
620 },
621 /* file system */
622 {
623 .name = "Filesystem-NOR",
624 .offset = MTDPART_OFS_APPEND,
625 .size = MTDPART_SIZ_FULL,
626 .mask_flags = 0
627 }
628 };
629
630 static struct mtd_partition sdp_onenand_partitions[] = {
631 {
632 .name = "X-Loader-OneNAND",
633 .offset = 0,
634 .size = 4 * (64 * 2048),
635 .mask_flags = MTD_WRITEABLE /* force read-only */
636 },
637 {
638 .name = "U-Boot-OneNAND",
639 .offset = MTDPART_OFS_APPEND,
640 .size = 2 * (64 * 2048),
641 .mask_flags = MTD_WRITEABLE /* force read-only */
642 },
643 {
644 .name = "U-Boot Environment-OneNAND",
645 .offset = MTDPART_OFS_APPEND,
646 .size = 1 * (64 * 2048),
647 },
648 {
649 .name = "Kernel-OneNAND",
650 .offset = MTDPART_OFS_APPEND,
651 .size = 16 * (64 * 2048),
652 },
653 {
654 .name = "File System-OneNAND",
655 .offset = MTDPART_OFS_APPEND,
656 .size = MTDPART_SIZ_FULL,
657 },
658 };
659
660 static struct mtd_partition sdp_nand_partitions[] = {
661 /* All the partition sizes are listed in terms of NAND block size */
662 {
663 .name = "X-Loader-NAND",
664 .offset = 0,
665 .size = 4 * (64 * 2048),
666 .mask_flags = MTD_WRITEABLE, /* force read-only */
667 },
668 {
669 .name = "U-Boot-NAND",
670 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
671 .size = 10 * (64 * 2048),
672 .mask_flags = MTD_WRITEABLE, /* force read-only */
673 },
674 {
675 .name = "Boot Env-NAND",
676
677 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
678 .size = 6 * (64 * 2048),
679 },
680 {
681 .name = "Kernel-NAND",
682 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
683 .size = 40 * (64 * 2048),
684 },
685 {
686 .name = "File System - NAND",
687 .size = MTDPART_SIZ_FULL,
688 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
689 },
690 };
691
692 static struct flash_partitions sdp_flash_partitions[] = {
693 {
694 .parts = sdp_nor_partitions,
695 .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
696 },
697 {
698 .parts = sdp_onenand_partitions,
699 .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
700 },
701 {
702 .parts = sdp_nand_partitions,
703 .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
704 },
705 };
706
707 static void __init omap_3430sdp_init(void)
708 {
709 int gpio_pendown;
710
711 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
712 omap_board_config = sdp3430_config;
713 omap_board_config_size = ARRAY_SIZE(sdp3430_config);
714 omap3430_i2c_init();
715 omap_display_init(&sdp3430_dss_data);
716 if (omap_rev() > OMAP3430_REV_ES1_0)
717 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
718 else
719 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
720 omap_ads7846_init(1, gpio_pendown, 310, NULL);
721 board_serial_init();
722 usb_musb_init(NULL);
723 board_smc91x_init();
724 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
725 sdp3430_display_init();
726 enable_board_wakeup_source();
727 usbhs_init(&usbhs_bdata);
728 }
729
730 MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
731 /* Maintainer: Syed Khasim - Texas Instruments Inc */
732 .boot_params = 0x80000100,
733 .reserve = omap_reserve,
734 .map_io = omap3_map_io,
735 .init_early = omap_3430sdp_init_early,
736 .init_irq = omap3_init_irq,
737 .init_machine = omap_3430sdp_init,
738 .timer = &omap3_timer,
739 MACHINE_END
Linux Btrfs Development