?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: tegra: fix compilation error due to mach/hardware.h removal
[linux-btrfs-devel.git] / arch / arm / mach-s5pc100 / clock.c
blobff5cbb30de5bb5fc200928018fdfc3f9f7b0f58b
1 /* linux/arch/arm/mach-s5pc100/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PC100 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20
21 #include <mach/map.h>
22
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
26 #include <plat/cpu.h>
27 #include <plat/pll.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
30 #include <plat/s5pc100.h>
31
32 static struct clk s5p_clk_otgphy = {
33 .name = "otg_phy",
34 };
35
36 static struct clk *clk_src_mout_href_list[] = {
37 [0] = &s5p_clk_27m,
38 [1] = &clk_fin_hpll,
39 };
40
41 static struct clksrc_sources clk_src_mout_href = {
42 .sources = clk_src_mout_href_list,
43 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
44 };
45
46 static struct clksrc_clk clk_mout_href = {
47 .clk = {
48 .name = "mout_href",
49 },
50 .sources = &clk_src_mout_href,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
52 };
53
54 static struct clk *clk_src_mout_48m_list[] = {
55 [0] = &clk_xusbxti,
56 [1] = &s5p_clk_otgphy,
57 };
58
59 static struct clksrc_sources clk_src_mout_48m = {
60 .sources = clk_src_mout_48m_list,
61 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
62 };
63
64 static struct clksrc_clk clk_mout_48m = {
65 .clk = {
66 .name = "mout_48m",
67 },
68 .sources = &clk_src_mout_48m,
69 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
70 };
71
72 static struct clksrc_clk clk_mout_mpll = {
73 .clk = {
74 .name = "mout_mpll",
75 },
76 .sources = &clk_src_mpll,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
78 };
79
80
81 static struct clksrc_clk clk_mout_apll = {
82 .clk = {
83 .name = "mout_apll",
84 },
85 .sources = &clk_src_apll,
86 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
87 };
88
89 static struct clksrc_clk clk_mout_epll = {
90 .clk = {
91 .name = "mout_epll",
92 },
93 .sources = &clk_src_epll,
94 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
95 };
96
97 static struct clk *clk_src_mout_hpll_list[] = {
98 [0] = &s5p_clk_27m,
99 };
100
101 static struct clksrc_sources clk_src_mout_hpll = {
102 .sources = clk_src_mout_hpll_list,
103 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
104 };
105
106 static struct clksrc_clk clk_mout_hpll = {
107 .clk = {
108 .name = "mout_hpll",
109 },
110 .sources = &clk_src_mout_hpll,
111 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
112 };
113
114 static struct clksrc_clk clk_div_apll = {
115 .clk = {
116 .name = "div_apll",
117 .parent = &clk_mout_apll.clk,
118 },
119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
120 };
121
122 static struct clksrc_clk clk_div_arm = {
123 .clk = {
124 .name = "div_arm",
125 .parent = &clk_div_apll.clk,
126 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
128 };
129
130 static struct clksrc_clk clk_div_d0_bus = {
131 .clk = {
132 .name = "div_d0_bus",
133 .parent = &clk_div_arm.clk,
134 },
135 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
136 };
137
138 static struct clksrc_clk clk_div_pclkd0 = {
139 .clk = {
140 .name = "div_pclkd0",
141 .parent = &clk_div_d0_bus.clk,
142 },
143 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
144 };
145
146 static struct clksrc_clk clk_div_secss = {
147 .clk = {
148 .name = "div_secss",
149 .parent = &clk_div_d0_bus.clk,
150 },
151 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
152 };
153
154 static struct clksrc_clk clk_div_apll2 = {
155 .clk = {
156 .name = "div_apll2",
157 .parent = &clk_mout_apll.clk,
158 },
159 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
160 };
161
162 static struct clk *clk_src_mout_am_list[] = {
163 [0] = &clk_mout_mpll.clk,
164 [1] = &clk_div_apll2.clk,
165 };
166
167 struct clksrc_sources clk_src_mout_am = {
168 .sources = clk_src_mout_am_list,
169 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
170 };
171
172 static struct clksrc_clk clk_mout_am = {
173 .clk = {
174 .name = "mout_am",
175 },
176 .sources = &clk_src_mout_am,
177 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
178 };
179
180 static struct clksrc_clk clk_div_d1_bus = {
181 .clk = {
182 .name = "div_d1_bus",
183 .parent = &clk_mout_am.clk,
184 },
185 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
186 };
187
188 static struct clksrc_clk clk_div_mpll2 = {
189 .clk = {
190 .name = "div_mpll2",
191 .parent = &clk_mout_am.clk,
192 },
193 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
194 };
195
196 static struct clksrc_clk clk_div_mpll = {
197 .clk = {
198 .name = "div_mpll",
199 .parent = &clk_mout_am.clk,
200 },
201 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
202 };
203
204 static struct clk *clk_src_mout_onenand_list[] = {
205 [0] = &clk_div_d0_bus.clk,
206 [1] = &clk_div_d1_bus.clk,
207 };
208
209 struct clksrc_sources clk_src_mout_onenand = {
210 .sources = clk_src_mout_onenand_list,
211 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
212 };
213
214 static struct clksrc_clk clk_mout_onenand = {
215 .clk = {
216 .name = "mout_onenand",
217 },
218 .sources = &clk_src_mout_onenand,
219 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
220 };
221
222 static struct clksrc_clk clk_div_onenand = {
223 .clk = {
224 .name = "div_onenand",
225 .parent = &clk_mout_onenand.clk,
226 },
227 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
228 };
229
230 static struct clksrc_clk clk_div_pclkd1 = {
231 .clk = {
232 .name = "div_pclkd1",
233 .parent = &clk_div_d1_bus.clk,
234 },
235 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
236 };
237
238 static struct clksrc_clk clk_div_cam = {
239 .clk = {
240 .name = "div_cam",
241 .parent = &clk_div_mpll2.clk,
242 },
243 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
244 };
245
246 static struct clksrc_clk clk_div_hdmi = {
247 .clk = {
248 .name = "div_hdmi",
249 .parent = &clk_mout_hpll.clk,
250 },
251 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
252 };
253
254 static u32 epll_div[][4] = {
255 { 32750000, 131, 3, 4 },
256 { 32768000, 131, 3, 4 },
257 { 36000000, 72, 3, 3 },
258 { 45000000, 90, 3, 3 },
259 { 45158000, 90, 3, 3 },
260 { 45158400, 90, 3, 3 },
261 { 48000000, 96, 3, 3 },
262 { 49125000, 131, 4, 3 },
263 { 49152000, 131, 4, 3 },
264 { 60000000, 120, 3, 3 },
265 { 67737600, 226, 5, 3 },
266 { 67738000, 226, 5, 3 },
267 { 73800000, 246, 5, 3 },
268 { 73728000, 246, 5, 3 },
269 { 72000000, 144, 3, 3 },
270 { 84000000, 168, 3, 3 },
271 { 96000000, 96, 3, 2 },
272 { 144000000, 144, 3, 2 },
273 { 192000000, 96, 3, 1 }
274 };
275
276 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
277 {
278 unsigned int epll_con;
279 unsigned int i;
280
281 if (clk->rate == rate) /* Return if nothing changed */
282 return 0;
283
284 epll_con = __raw_readl(S5P_EPLL_CON);
285
286 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
287
288 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
289 if (epll_div[i][0] == rate) {
290 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
291 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
292 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
293 break;
294 }
295 }
296
297 if (i == ARRAY_SIZE(epll_div)) {
298 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
299 return -EINVAL;
300 }
301
302 __raw_writel(epll_con, S5P_EPLL_CON);
303
304 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
305 clk->rate, rate);
306
307 clk->rate = rate;
308
309 return 0;
310 }
311
312 static struct clk_ops s5pc100_epll_ops = {
313 .get_rate = s5p_epll_get_rate,
314 .set_rate = s5pc100_epll_set_rate,
315 };
316
317 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
318 {
319 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
320 }
321
322 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
323 {
324 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
325 }
326
327 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
328 {
329 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
330 }
331
332 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
333 {
334 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
335 }
336
337 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
338 {
339 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
340 }
341
342 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
343 {
344 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
345 }
346
347 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
348 {
349 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
350 }
351
352 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
353 {
354 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
355 }
356
357 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
358 {
359 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
360 }
361
362 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
363 {
364 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
365 }
366
367 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
368 {
369 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
370 }
371
372 /*
373 * The following clocks will be disabled during clock initialization. It is
374 * recommended to keep the following clocks disabled until the driver requests
375 * for enabling the clock.
376 */
377 static struct clk init_clocks_off[] = {
378 {
379 .name = "cssys",
380 .parent = &clk_div_d0_bus.clk,
381 .enable = s5pc100_d0_0_ctrl,
382 .ctrlbit = (1 << 6),
383 }, {
384 .name = "secss",
385 .parent = &clk_div_d0_bus.clk,
386 .enable = s5pc100_d0_0_ctrl,
387 .ctrlbit = (1 << 5),
388 }, {
389 .name = "g2d",
390 .parent = &clk_div_d0_bus.clk,
391 .enable = s5pc100_d0_0_ctrl,
392 .ctrlbit = (1 << 4),
393 }, {
394 .name = "mdma",
395 .parent = &clk_div_d0_bus.clk,
396 .enable = s5pc100_d0_0_ctrl,
397 .ctrlbit = (1 << 3),
398 }, {
399 .name = "cfcon",
400 .parent = &clk_div_d0_bus.clk,
401 .enable = s5pc100_d0_0_ctrl,
402 .ctrlbit = (1 << 2),
403 }, {
404 .name = "nfcon",
405 .parent = &clk_div_d0_bus.clk,
406 .enable = s5pc100_d0_1_ctrl,
407 .ctrlbit = (1 << 3),
408 }, {
409 .name = "onenandc",
410 .parent = &clk_div_d0_bus.clk,
411 .enable = s5pc100_d0_1_ctrl,
412 .ctrlbit = (1 << 2),
413 }, {
414 .name = "sdm",
415 .parent = &clk_div_d0_bus.clk,
416 .enable = s5pc100_d0_2_ctrl,
417 .ctrlbit = (1 << 2),
418 }, {
419 .name = "seckey",
420 .parent = &clk_div_d0_bus.clk,
421 .enable = s5pc100_d0_2_ctrl,
422 .ctrlbit = (1 << 1),
423 }, {
424 .name = "hsmmc",
425 .devname = "s3c-sdhci.2",
426 .parent = &clk_div_d1_bus.clk,
427 .enable = s5pc100_d1_0_ctrl,
428 .ctrlbit = (1 << 7),
429 }, {
430 .name = "hsmmc",
431 .devname = "s3c-sdhci.1",
432 .parent = &clk_div_d1_bus.clk,
433 .enable = s5pc100_d1_0_ctrl,
434 .ctrlbit = (1 << 6),
435 }, {
436 .name = "hsmmc",
437 .devname = "s3c-sdhci.0",
438 .parent = &clk_div_d1_bus.clk,
439 .enable = s5pc100_d1_0_ctrl,
440 .ctrlbit = (1 << 5),
441 }, {
442 .name = "modemif",
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
445 .ctrlbit = (1 << 4),
446 }, {
447 .name = "otg",
448 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl,
450 .ctrlbit = (1 << 3),
451 }, {
452 .name = "usbhost",
453 .parent = &clk_div_d1_bus.clk,
454 .enable = s5pc100_d1_0_ctrl,
455 .ctrlbit = (1 << 2),
456 }, {
457 .name = "pdma",
458 .devname = "s3c-pl330.1",
459 .parent = &clk_div_d1_bus.clk,
460 .enable = s5pc100_d1_0_ctrl,
461 .ctrlbit = (1 << 1),
462 }, {
463 .name = "pdma",
464 .devname = "s3c-pl330.0",
465 .parent = &clk_div_d1_bus.clk,
466 .enable = s5pc100_d1_0_ctrl,
467 .ctrlbit = (1 << 0),
468 }, {
469 .name = "lcd",
470 .parent = &clk_div_d1_bus.clk,
471 .enable = s5pc100_d1_1_ctrl,
472 .ctrlbit = (1 << 0),
473 }, {
474 .name = "rotator",
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_1_ctrl,
477 .ctrlbit = (1 << 1),
478 }, {
479 .name = "fimc",
480 .devname = "s5p-fimc.0",
481 .parent = &clk_div_d1_bus.clk,
482 .enable = s5pc100_d1_1_ctrl,
483 .ctrlbit = (1 << 2),
484 }, {
485 .name = "fimc",
486 .devname = "s5p-fimc.1",
487 .parent = &clk_div_d1_bus.clk,
488 .enable = s5pc100_d1_1_ctrl,
489 .ctrlbit = (1 << 3),
490 }, {
491 .name = "fimc",
492 .devname = "s5p-fimc.2",
493 .enable = s5pc100_d1_1_ctrl,
494 .ctrlbit = (1 << 4),
495 }, {
496 .name = "jpeg",
497 .parent = &clk_div_d1_bus.clk,
498 .enable = s5pc100_d1_1_ctrl,
499 .ctrlbit = (1 << 5),
500 }, {
501 .name = "mipi-dsim",
502 .parent = &clk_div_d1_bus.clk,
503 .enable = s5pc100_d1_1_ctrl,
504 .ctrlbit = (1 << 6),
505 }, {
506 .name = "mipi-csis",
507 .parent = &clk_div_d1_bus.clk,
508 .enable = s5pc100_d1_1_ctrl,
509 .ctrlbit = (1 << 7),
510 }, {
511 .name = "g3d",
512 .parent = &clk_div_d1_bus.clk,
513 .enable = s5pc100_d1_0_ctrl,
514 .ctrlbit = (1 << 8),
515 }, {
516 .name = "tv",
517 .parent = &clk_div_d1_bus.clk,
518 .enable = s5pc100_d1_2_ctrl,
519 .ctrlbit = (1 << 0),
520 }, {
521 .name = "vp",
522 .parent = &clk_div_d1_bus.clk,
523 .enable = s5pc100_d1_2_ctrl,
524 .ctrlbit = (1 << 1),
525 }, {
526 .name = "mixer",
527 .parent = &clk_div_d1_bus.clk,
528 .enable = s5pc100_d1_2_ctrl,
529 .ctrlbit = (1 << 2),
530 }, {
531 .name = "hdmi",
532 .parent = &clk_div_d1_bus.clk,
533 .enable = s5pc100_d1_2_ctrl,
534 .ctrlbit = (1 << 3),
535 }, {
536 .name = "mfc",
537 .parent = &clk_div_d1_bus.clk,
538 .enable = s5pc100_d1_2_ctrl,
539 .ctrlbit = (1 << 4),
540 }, {
541 .name = "apc",
542 .parent = &clk_div_d1_bus.clk,
543 .enable = s5pc100_d1_3_ctrl,
544 .ctrlbit = (1 << 2),
545 }, {
546 .name = "iec",
547 .parent = &clk_div_d1_bus.clk,
548 .enable = s5pc100_d1_3_ctrl,
549 .ctrlbit = (1 << 3),
550 }, {
551 .name = "systimer",
552 .parent = &clk_div_d1_bus.clk,
553 .enable = s5pc100_d1_3_ctrl,
554 .ctrlbit = (1 << 7),
555 }, {
556 .name = "watchdog",
557 .parent = &clk_div_d1_bus.clk,
558 .enable = s5pc100_d1_3_ctrl,
559 .ctrlbit = (1 << 8),
560 }, {
561 .name = "rtc",
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_3_ctrl,
564 .ctrlbit = (1 << 9),
565 }, {
566 .name = "i2c",
567 .devname = "s3c2440-i2c.0",
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl,
570 .ctrlbit = (1 << 4),
571 }, {
572 .name = "i2c",
573 .devname = "s3c2440-i2c.1",
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl,
576 .ctrlbit = (1 << 5),
577 }, {
578 .name = "spi",
579 .devname = "s3c64xx-spi.0",
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl,
582 .ctrlbit = (1 << 6),
583 }, {
584 .name = "spi",
585 .devname = "s3c64xx-spi.1",
586 .parent = &clk_div_d1_bus.clk,
587 .enable = s5pc100_d1_4_ctrl,
588 .ctrlbit = (1 << 7),
589 }, {
590 .name = "spi",
591 .devname = "s3c64xx-spi.2",
592 .parent = &clk_div_d1_bus.clk,
593 .enable = s5pc100_d1_4_ctrl,
594 .ctrlbit = (1 << 8),
595 }, {
596 .name = "irda",
597 .parent = &clk_div_d1_bus.clk,
598 .enable = s5pc100_d1_4_ctrl,
599 .ctrlbit = (1 << 9),
600 }, {
601 .name = "ccan",
602 .parent = &clk_div_d1_bus.clk,
603 .enable = s5pc100_d1_4_ctrl,
604 .ctrlbit = (1 << 10),
605 }, {
606 .name = "ccan",
607 .parent = &clk_div_d1_bus.clk,
608 .enable = s5pc100_d1_4_ctrl,
609 .ctrlbit = (1 << 11),
610 }, {
611 .name = "hsitx",
612 .parent = &clk_div_d1_bus.clk,
613 .enable = s5pc100_d1_4_ctrl,
614 .ctrlbit = (1 << 12),
615 }, {
616 .name = "hsirx",
617 .parent = &clk_div_d1_bus.clk,
618 .enable = s5pc100_d1_4_ctrl,
619 .ctrlbit = (1 << 13),
620 }, {
621 .name = "iis",
622 .devname = "samsung-i2s.0",
623 .parent = &clk_div_pclkd1.clk,
624 .enable = s5pc100_d1_5_ctrl,
625 .ctrlbit = (1 << 0),
626 }, {
627 .name = "iis",
628 .devname = "samsung-i2s.1",
629 .parent = &clk_div_pclkd1.clk,
630 .enable = s5pc100_d1_5_ctrl,
631 .ctrlbit = (1 << 1),
632 }, {
633 .name = "iis",
634 .devname = "samsung-i2s.2",
635 .parent = &clk_div_pclkd1.clk,
636 .enable = s5pc100_d1_5_ctrl,
637 .ctrlbit = (1 << 2),
638 }, {
639 .name = "ac97",
640 .parent = &clk_div_pclkd1.clk,
641 .enable = s5pc100_d1_5_ctrl,
642 .ctrlbit = (1 << 3),
643 }, {
644 .name = "pcm",
645 .devname = "samsung-pcm.0",
646 .parent = &clk_div_pclkd1.clk,
647 .enable = s5pc100_d1_5_ctrl,
648 .ctrlbit = (1 << 4),
649 }, {
650 .name = "pcm",
651 .devname = "samsung-pcm.1",
652 .parent = &clk_div_pclkd1.clk,
653 .enable = s5pc100_d1_5_ctrl,
654 .ctrlbit = (1 << 5),
655 }, {
656 .name = "spdif",
657 .parent = &clk_div_pclkd1.clk,
658 .enable = s5pc100_d1_5_ctrl,
659 .ctrlbit = (1 << 6),
660 }, {
661 .name = "adc",
662 .parent = &clk_div_pclkd1.clk,
663 .enable = s5pc100_d1_5_ctrl,
664 .ctrlbit = (1 << 7),
665 }, {
666 .name = "keypad",
667 .parent = &clk_div_pclkd1.clk,
668 .enable = s5pc100_d1_5_ctrl,
669 .ctrlbit = (1 << 8),
670 }, {
671 .name = "spi_48m",
672 .devname = "s3c64xx-spi.0",
673 .parent = &clk_mout_48m.clk,
674 .enable = s5pc100_sclk0_ctrl,
675 .ctrlbit = (1 << 7),
676 }, {
677 .name = "spi_48m",
678 .devname = "s3c64xx-spi.1",
679 .parent = &clk_mout_48m.clk,
680 .enable = s5pc100_sclk0_ctrl,
681 .ctrlbit = (1 << 8),
682 }, {
683 .name = "spi_48m",
684 .devname = "s3c64xx-spi.2",
685 .parent = &clk_mout_48m.clk,
686 .enable = s5pc100_sclk0_ctrl,
687 .ctrlbit = (1 << 9),
688 }, {
689 .name = "mmc_48m",
690 .devname = "s3c-sdhci.0",
691 .parent = &clk_mout_48m.clk,
692 .enable = s5pc100_sclk0_ctrl,
693 .ctrlbit = (1 << 15),
694 }, {
695 .name = "mmc_48m",
696 .devname = "s3c-sdhci.1",
697 .parent = &clk_mout_48m.clk,
698 .enable = s5pc100_sclk0_ctrl,
699 .ctrlbit = (1 << 16),
700 }, {
701 .name = "mmc_48m",
702 .devname = "s3c-sdhci.2",
703 .parent = &clk_mout_48m.clk,
704 .enable = s5pc100_sclk0_ctrl,
705 .ctrlbit = (1 << 17),
706 },
707 };
708
709 static struct clk clk_vclk54m = {
710 .name = "vclk_54m",
711 .rate = 54000000,
712 };
713
714 static struct clk clk_i2scdclk0 = {
715 .name = "i2s_cdclk0",
716 };
717
718 static struct clk clk_i2scdclk1 = {
719 .name = "i2s_cdclk1",
720 };
721
722 static struct clk clk_i2scdclk2 = {
723 .name = "i2s_cdclk2",
724 };
725
726 static struct clk clk_pcmcdclk0 = {
727 .name = "pcm_cdclk0",
728 };
729
730 static struct clk clk_pcmcdclk1 = {
731 .name = "pcm_cdclk1",
732 };
733
734 static struct clk *clk_src_group1_list[] = {
735 [0] = &clk_mout_epll.clk,
736 [1] = &clk_div_mpll2.clk,
737 [2] = &clk_fin_epll,
738 [3] = &clk_mout_hpll.clk,
739 };
740
741 struct clksrc_sources clk_src_group1 = {
742 .sources = clk_src_group1_list,
743 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
744 };
745
746 static struct clk *clk_src_group2_list[] = {
747 [0] = &clk_mout_epll.clk,
748 [1] = &clk_div_mpll.clk,
749 };
750
751 struct clksrc_sources clk_src_group2 = {
752 .sources = clk_src_group2_list,
753 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
754 };
755
756 static struct clk *clk_src_group3_list[] = {
757 [0] = &clk_mout_epll.clk,
758 [1] = &clk_div_mpll.clk,
759 [2] = &clk_fin_epll,
760 [3] = &clk_i2scdclk0,
761 [4] = &clk_pcmcdclk0,
762 [5] = &clk_mout_hpll.clk,
763 };
764
765 struct clksrc_sources clk_src_group3 = {
766 .sources = clk_src_group3_list,
767 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
768 };
769
770 static struct clksrc_clk clk_sclk_audio0 = {
771 .clk = {
772 .name = "sclk_audio",
773 .devname = "samsung-pcm.0",
774 .ctrlbit = (1 << 8),
775 .enable = s5pc100_sclk1_ctrl,
776 },
777 .sources = &clk_src_group3,
778 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
779 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
780 };
781
782 static struct clk *clk_src_group4_list[] = {
783 [0] = &clk_mout_epll.clk,
784 [1] = &clk_div_mpll.clk,
785 [2] = &clk_fin_epll,
786 [3] = &clk_i2scdclk1,
787 [4] = &clk_pcmcdclk1,
788 [5] = &clk_mout_hpll.clk,
789 };
790
791 struct clksrc_sources clk_src_group4 = {
792 .sources = clk_src_group4_list,
793 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
794 };
795
796 static struct clksrc_clk clk_sclk_audio1 = {
797 .clk = {
798 .name = "sclk_audio",
799 .devname = "samsung-pcm.1",
800 .ctrlbit = (1 << 9),
801 .enable = s5pc100_sclk1_ctrl,
802 },
803 .sources = &clk_src_group4,
804 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
805 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
806 };
807
808 static struct clk *clk_src_group5_list[] = {
809 [0] = &clk_mout_epll.clk,
810 [1] = &clk_div_mpll.clk,
811 [2] = &clk_fin_epll,
812 [3] = &clk_i2scdclk2,
813 [4] = &clk_mout_hpll.clk,
814 };
815
816 struct clksrc_sources clk_src_group5 = {
817 .sources = clk_src_group5_list,
818 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
819 };
820
821 static struct clksrc_clk clk_sclk_audio2 = {
822 .clk = {
823 .name = "sclk_audio",
824 .devname = "samsung-pcm.2",
825 .ctrlbit = (1 << 10),
826 .enable = s5pc100_sclk1_ctrl,
827 },
828 .sources = &clk_src_group5,
829 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
830 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
831 };
832
833 static struct clk *clk_src_group6_list[] = {
834 [0] = &s5p_clk_27m,
835 [1] = &clk_vclk54m,
836 [2] = &clk_div_hdmi.clk,
837 };
838
839 struct clksrc_sources clk_src_group6 = {
840 .sources = clk_src_group6_list,
841 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
842 };
843
844 static struct clk *clk_src_group7_list[] = {
845 [0] = &clk_mout_epll.clk,
846 [1] = &clk_div_mpll.clk,
847 [2] = &clk_mout_hpll.clk,
848 [3] = &clk_vclk54m,
849 };
850
851 struct clksrc_sources clk_src_group7 = {
852 .sources = clk_src_group7_list,
853 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
854 };
855
856 static struct clk *clk_src_mmc0_list[] = {
857 [0] = &clk_mout_epll.clk,
858 [1] = &clk_div_mpll.clk,
859 [2] = &clk_fin_epll,
860 };
861
862 struct clksrc_sources clk_src_mmc0 = {
863 .sources = clk_src_mmc0_list,
864 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
865 };
866
867 static struct clk *clk_src_mmc12_list[] = {
868 [0] = &clk_mout_epll.clk,
869 [1] = &clk_div_mpll.clk,
870 [2] = &clk_fin_epll,
871 [3] = &clk_mout_hpll.clk,
872 };
873
874 struct clksrc_sources clk_src_mmc12 = {
875 .sources = clk_src_mmc12_list,
876 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
877 };
878
879 static struct clk *clk_src_irda_usb_list[] = {
880 [0] = &clk_mout_epll.clk,
881 [1] = &clk_div_mpll.clk,
882 [2] = &clk_fin_epll,
883 [3] = &clk_mout_hpll.clk,
884 };
885
886 struct clksrc_sources clk_src_irda_usb = {
887 .sources = clk_src_irda_usb_list,
888 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
889 };
890
891 static struct clk *clk_src_pwi_list[] = {
892 [0] = &clk_fin_epll,
893 [1] = &clk_mout_epll.clk,
894 [2] = &clk_div_mpll.clk,
895 };
896
897 struct clksrc_sources clk_src_pwi = {
898 .sources = clk_src_pwi_list,
899 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
900 };
901
902 static struct clk *clk_sclk_spdif_list[] = {
903 [0] = &clk_sclk_audio0.clk,
904 [1] = &clk_sclk_audio1.clk,
905 [2] = &clk_sclk_audio2.clk,
906 };
907
908 struct clksrc_sources clk_src_sclk_spdif = {
909 .sources = clk_sclk_spdif_list,
910 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
911 };
912
913 static struct clksrc_clk clk_sclk_spdif = {
914 .clk = {
915 .name = "sclk_spdif",
916 .ctrlbit = (1 << 11),
917 .enable = s5pc100_sclk1_ctrl,
918 .ops = &s5p_sclk_spdif_ops,
919 },
920 .sources = &clk_src_sclk_spdif,
921 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
922 };
923
924 static struct clksrc_clk clksrcs[] = {
925 {
926 .clk = {
927 .name = "sclk_spi",
928 .devname = "s3c64xx-spi.0",
929 .ctrlbit = (1 << 4),
930 .enable = s5pc100_sclk0_ctrl,
931
932 },
933 .sources = &clk_src_group1,
934 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
935 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
936 }, {
937 .clk = {
938 .name = "sclk_spi",
939 .devname = "s3c64xx-spi.1",
940 .ctrlbit = (1 << 5),
941 .enable = s5pc100_sclk0_ctrl,
942
943 },
944 .sources = &clk_src_group1,
945 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
946 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
947 }, {
948 .clk = {
949 .name = "sclk_spi",
950 .devname = "s3c64xx-spi.2",
951 .ctrlbit = (1 << 6),
952 .enable = s5pc100_sclk0_ctrl,
953
954 },
955 .sources = &clk_src_group1,
956 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
957 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
958 }, {
959 .clk = {
960 .name = "uclk1",
961 .ctrlbit = (1 << 3),
962 .enable = s5pc100_sclk0_ctrl,
963
964 },
965 .sources = &clk_src_group2,
966 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
967 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
968 }, {
969 .clk = {
970 .name = "sclk_mixer",
971 .ctrlbit = (1 << 6),
972 .enable = s5pc100_sclk0_ctrl,
973
974 },
975 .sources = &clk_src_group6,
976 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
977 }, {
978 .clk = {
979 .name = "sclk_lcd",
980 .ctrlbit = (1 << 0),
981 .enable = s5pc100_sclk1_ctrl,
982
983 },
984 .sources = &clk_src_group7,
985 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
986 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
987 }, {
988 .clk = {
989 .name = "sclk_fimc",
990 .devname = "s5p-fimc.0",
991 .ctrlbit = (1 << 1),
992 .enable = s5pc100_sclk1_ctrl,
993
994 },
995 .sources = &clk_src_group7,
996 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
997 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
998 }, {
999 .clk = {
1000 .name = "sclk_fimc",
1001 .devname = "s5p-fimc.1",
1002 .ctrlbit = (1 << 2),
1003 .enable = s5pc100_sclk1_ctrl,
1004
1005 },
1006 .sources = &clk_src_group7,
1007 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1008 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1009 }, {
1010 .clk = {
1011 .name = "sclk_fimc",
1012 .devname = "s5p-fimc.2",
1013 .ctrlbit = (1 << 3),
1014 .enable = s5pc100_sclk1_ctrl,
1015
1016 },
1017 .sources = &clk_src_group7,
1018 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1019 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1020 }, {
1021 .clk = {
1022 .name = "sclk_mmc",
1023 .devname = "s3c-sdhci.0",
1024 .ctrlbit = (1 << 12),
1025 .enable = s5pc100_sclk1_ctrl,
1026
1027 },
1028 .sources = &clk_src_mmc0,
1029 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1030 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1031 }, {
1032 .clk = {
1033 .name = "sclk_mmc",
1034 .devname = "s3c-sdhci.1",
1035 .ctrlbit = (1 << 13),
1036 .enable = s5pc100_sclk1_ctrl,
1037
1038 },
1039 .sources = &clk_src_mmc12,
1040 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1041 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1042 }, {
1043 .clk = {
1044 .name = "sclk_mmc",
1045 .devname = "s3c-sdhci.2",
1046 .ctrlbit = (1 << 14),
1047 .enable = s5pc100_sclk1_ctrl,
1048
1049 },
1050 .sources = &clk_src_mmc12,
1051 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1052 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1053 }, {
1054 .clk = {
1055 .name = "sclk_irda",
1056 .ctrlbit = (1 << 10),
1057 .enable = s5pc100_sclk0_ctrl,
1058
1059 },
1060 .sources = &clk_src_irda_usb,
1061 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1062 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1063 }, {
1064 .clk = {
1065 .name = "sclk_irda",
1066 .ctrlbit = (1 << 10),
1067 .enable = s5pc100_sclk0_ctrl,
1068
1069 },
1070 .sources = &clk_src_mmc12,
1071 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1072 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1073 }, {
1074 .clk = {
1075 .name = "sclk_pwi",
1076 .ctrlbit = (1 << 1),
1077 .enable = s5pc100_sclk0_ctrl,
1078
1079 },
1080 .sources = &clk_src_pwi,
1081 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1082 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1083 }, {
1084 .clk = {
1085 .name = "sclk_uhost",
1086 .ctrlbit = (1 << 11),
1087 .enable = s5pc100_sclk0_ctrl,
1088
1089 },
1090 .sources = &clk_src_irda_usb,
1091 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1092 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1093 },
1094 };
1095
1096 /* Clock initialisation code */
1097 static struct clksrc_clk *sysclks[] = {
1098 &clk_mout_apll,
1099 &clk_mout_epll,
1100 &clk_mout_mpll,
1101 &clk_mout_hpll,
1102 &clk_mout_href,
1103 &clk_mout_48m,
1104 &clk_div_apll,
1105 &clk_div_arm,
1106 &clk_div_d0_bus,
1107 &clk_div_pclkd0,
1108 &clk_div_secss,
1109 &clk_div_apll2,
1110 &clk_mout_am,
1111 &clk_div_d1_bus,
1112 &clk_div_mpll2,
1113 &clk_div_mpll,
1114 &clk_mout_onenand,
1115 &clk_div_onenand,
1116 &clk_div_pclkd1,
1117 &clk_div_cam,
1118 &clk_div_hdmi,
1119 &clk_sclk_audio0,
1120 &clk_sclk_audio1,
1121 &clk_sclk_audio2,
1122 &clk_sclk_spdif,
1123 };
1124
1125 void __init_or_cpufreq s5pc100_setup_clocks(void)
1126 {
1127 unsigned long xtal;
1128 unsigned long arm;
1129 unsigned long hclkd0;
1130 unsigned long hclkd1;
1131 unsigned long pclkd0;
1132 unsigned long pclkd1;
1133 unsigned long apll;
1134 unsigned long mpll;
1135 unsigned long epll;
1136 unsigned long hpll;
1137 unsigned int ptr;
1138
1139 /* Set S5PC100 functions for clk_fout_epll */
1140 clk_fout_epll.enable = s5p_epll_enable;
1141 clk_fout_epll.ops = &s5pc100_epll_ops;
1142
1143 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1144
1145 xtal = clk_get_rate(&clk_xtal);
1146
1147 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1148
1149 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1150 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1151 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1152 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1153
1154 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1155 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1156
1157 clk_fout_apll.rate = apll;
1158 clk_fout_mpll.rate = mpll;
1159 clk_fout_epll.rate = epll;
1160 clk_mout_hpll.clk.rate = hpll;
1161
1162 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1163 s3c_set_clksrc(&clksrcs[ptr], true);
1164
1165 arm = clk_get_rate(&clk_div_arm.clk);
1166 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1167 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1168 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1169 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1170
1171 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1172 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1173
1174 clk_f.rate = arm;
1175 clk_h.rate = hclkd1;
1176 clk_p.rate = pclkd1;
1177 }
1178
1179 /*
1180 * The following clocks will be enabled during clock initialization.
1181 */
1182 static struct clk init_clocks[] = {
1183 {
1184 .name = "tzic",
1185 .parent = &clk_div_d0_bus.clk,
1186 .enable = s5pc100_d0_0_ctrl,
1187 .ctrlbit = (1 << 1),
1188 }, {
1189 .name = "intc",
1190 .parent = &clk_div_d0_bus.clk,
1191 .enable = s5pc100_d0_0_ctrl,
1192 .ctrlbit = (1 << 0),
1193 }, {
1194 .name = "ebi",
1195 .parent = &clk_div_d0_bus.clk,
1196 .enable = s5pc100_d0_1_ctrl,
1197 .ctrlbit = (1 << 5),
1198 }, {
1199 .name = "intmem",
1200 .parent = &clk_div_d0_bus.clk,
1201 .enable = s5pc100_d0_1_ctrl,
1202 .ctrlbit = (1 << 4),
1203 }, {
1204 .name = "sromc",
1205 .parent = &clk_div_d0_bus.clk,
1206 .enable = s5pc100_d0_1_ctrl,
1207 .ctrlbit = (1 << 1),
1208 }, {
1209 .name = "dmc",
1210 .parent = &clk_div_d0_bus.clk,
1211 .enable = s5pc100_d0_1_ctrl,
1212 .ctrlbit = (1 << 0),
1213 }, {
1214 .name = "chipid",
1215 .parent = &clk_div_d0_bus.clk,
1216 .enable = s5pc100_d0_1_ctrl,
1217 .ctrlbit = (1 << 0),
1218 }, {
1219 .name = "gpio",
1220 .parent = &clk_div_d1_bus.clk,
1221 .enable = s5pc100_d1_3_ctrl,
1222 .ctrlbit = (1 << 1),
1223 }, {
1224 .name = "uart",
1225 .devname = "s3c6400-uart.0",
1226 .parent = &clk_div_d1_bus.clk,
1227 .enable = s5pc100_d1_4_ctrl,
1228 .ctrlbit = (1 << 0),
1229 }, {
1230 .name = "uart",
1231 .devname = "s3c6400-uart.1",
1232 .parent = &clk_div_d1_bus.clk,
1233 .enable = s5pc100_d1_4_ctrl,
1234 .ctrlbit = (1 << 1),
1235 }, {
1236 .name = "uart",
1237 .devname = "s3c6400-uart.2",
1238 .parent = &clk_div_d1_bus.clk,
1239 .enable = s5pc100_d1_4_ctrl,
1240 .ctrlbit = (1 << 2),
1241 }, {
1242 .name = "uart",
1243 .devname = "s3c6400-uart.3",
1244 .parent = &clk_div_d1_bus.clk,
1245 .enable = s5pc100_d1_4_ctrl,
1246 .ctrlbit = (1 << 3),
1247 }, {
1248 .name = "timers",
1249 .parent = &clk_div_d1_bus.clk,
1250 .enable = s5pc100_d1_3_ctrl,
1251 .ctrlbit = (1 << 6),
1252 },
1253 };
1254
1255 static struct clk *clks[] __initdata = {
1256 &clk_ext,
1257 &clk_i2scdclk0,
1258 &clk_i2scdclk1,
1259 &clk_i2scdclk2,
1260 &clk_pcmcdclk0,
1261 &clk_pcmcdclk1,
1262 };
1263
1264 void __init s5pc100_register_clocks(void)
1265 {
1266 int ptr;
1267
1268 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1269
1270 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1271 s3c_register_clksrc(sysclks[ptr], 1);
1272
1273 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1274 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1275
1276 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1277 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1278
1279 s3c_pwmclk_init();
1280 }
Linux Btrfs Development