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ARM: tegra: fix compilation error due to mach/hardware.h removal
[linux-btrfs-devel.git] / arch / arm / mach-versatile / core.c
blobe340a54251df5d1245f1e913c91587fb23f48fd7
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/irqdomain.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/clcd.h>
32 #include <linux/amba/pl061.h>
33 #include <linux/amba/mmci.h>
34 #include <linux/amba/pl022.h>
35 #include <linux/io.h>
36 #include <linux/gfp.h>
37 #include <linux/clkdev.h>
38 #include <linux/mtd/physmap.h>
39
40 #include <asm/system.h>
41 #include <asm/irq.h>
42 #include <asm/leds.h>
43 #include <asm/hardware/arm_timer.h>
44 #include <asm/hardware/icst.h>
45 #include <asm/hardware/vic.h>
46 #include <asm/mach-types.h>
47
48 #include <asm/mach/arch.h>
49 #include <asm/mach/irq.h>
50 #include <asm/mach/time.h>
51 #include <asm/mach/map.h>
52 #include <mach/hardware.h>
53 #include <mach/platform.h>
54 #include <asm/hardware/timer-sp.h>
55
56 #include <plat/clcd.h>
57 #include <plat/fpga-irq.h>
58 #include <plat/sched_clock.h>
59
60 #include "core.h"
61
62 /*
63 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
64 * is the (PA >> 12).
65 *
66 * Setup a VA for the Versatile Vectored Interrupt Controller.
67 */
68 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
69 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
70
71 static struct fpga_irq_data sic_irq = {
72 .base = VA_SIC_BASE,
73 .irq_start = IRQ_SIC_START,
74 .chip.name = "SIC",
75 };
76
77 #if 1
78 #define IRQ_MMCI0A IRQ_VICSOURCE22
79 #define IRQ_AACI IRQ_VICSOURCE24
80 #define IRQ_ETH IRQ_VICSOURCE25
81 #define PIC_MASK 0xFFD00000
82 #else
83 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
84 #define IRQ_AACI IRQ_SIC_AACI
85 #define IRQ_ETH IRQ_SIC_ETH
86 #define PIC_MASK 0
87 #endif
88
89 /* Lookup table for finding a DT node that represents the vic instance */
90 static const struct of_device_id vic_of_match[] __initconst = {
91 { .compatible = "arm,versatile-vic", },
92 {}
93 };
94
95 static const struct of_device_id sic_of_match[] __initconst = {
96 { .compatible = "arm,versatile-sic", },
97 {}
98 };
99
100 void __init versatile_init_irq(void)
101 {
102 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
103 irq_domain_generate_simple(vic_of_match, VERSATILE_VIC_BASE, IRQ_VIC_START);
104
105 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
106
107 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
108 irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
109
110 /*
111 * Interrupts on secondary controller from 0 to 8 are routed to
112 * source 31 on PIC.
113 * Interrupts from 21 to 31 are routed directly to the VIC on
114 * the corresponding number on primary controller. This is controlled
115 * by setting PIC_ENABLEx.
116 */
117 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
118 }
119
120 static struct map_desc versatile_io_desc[] __initdata = {
121 {
122 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
123 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
124 .length = SZ_4K,
125 .type = MT_DEVICE
126 }, {
127 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
128 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
129 .length = SZ_4K,
130 .type = MT_DEVICE
131 }, {
132 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
133 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
134 .length = SZ_4K,
135 .type = MT_DEVICE
136 }, {
137 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
138 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
139 .length = SZ_4K * 9,
140 .type = MT_DEVICE
141 },
142 #ifdef CONFIG_MACH_VERSATILE_AB
143 {
144 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
145 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
146 .length = SZ_4K,
147 .type = MT_DEVICE
148 }, {
149 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
150 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
151 .length = SZ_64M,
152 .type = MT_DEVICE
153 },
154 #endif
155 #ifdef CONFIG_DEBUG_LL
156 {
157 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
158 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
159 .length = SZ_4K,
160 .type = MT_DEVICE
161 },
162 #endif
163 #ifdef CONFIG_PCI
164 {
165 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
166 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
167 .length = SZ_4K,
168 .type = MT_DEVICE
169 }, {
170 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
171 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
172 .length = VERSATILE_PCI_BASE_SIZE,
173 .type = MT_DEVICE
174 }, {
175 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
176 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
177 .length = VERSATILE_PCI_CFG_BASE_SIZE,
178 .type = MT_DEVICE
179 },
180 #if 0
181 {
182 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
183 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
184 .length = SZ_16M,
185 .type = MT_DEVICE
186 }, {
187 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
188 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
189 .length = SZ_16M,
190 .type = MT_DEVICE
191 }, {
192 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
193 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
194 .length = SZ_16M,
195 .type = MT_DEVICE
196 },
197 #endif
198 #endif
199 };
200
201 void __init versatile_map_io(void)
202 {
203 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
204 }
205
206
207 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
208
209 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
210 {
211 u32 val;
212
213 val = __raw_readl(VERSATILE_FLASHCTRL);
214 if (on)
215 val |= VERSATILE_FLASHPROG_FLVPPEN;
216 else
217 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
218 __raw_writel(val, VERSATILE_FLASHCTRL);
219 }
220
221 static struct physmap_flash_data versatile_flash_data = {
222 .width = 4,
223 .set_vpp = versatile_flash_set_vpp,
224 };
225
226 static struct resource versatile_flash_resource = {
227 .start = VERSATILE_FLASH_BASE,
228 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
229 .flags = IORESOURCE_MEM,
230 };
231
232 static struct platform_device versatile_flash_device = {
233 .name = "physmap-flash",
234 .id = 0,
235 .dev = {
236 .platform_data = &versatile_flash_data,
237 },
238 .num_resources = 1,
239 .resource = &versatile_flash_resource,
240 };
241
242 static struct resource smc91x_resources[] = {
243 [0] = {
244 .start = VERSATILE_ETH_BASE,
245 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = IRQ_ETH,
250 .end = IRQ_ETH,
251 .flags = IORESOURCE_IRQ,
252 },
253 };
254
255 static struct platform_device smc91x_device = {
256 .name = "smc91x",
257 .id = 0,
258 .num_resources = ARRAY_SIZE(smc91x_resources),
259 .resource = smc91x_resources,
260 };
261
262 static struct resource versatile_i2c_resource = {
263 .start = VERSATILE_I2C_BASE,
264 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
265 .flags = IORESOURCE_MEM,
266 };
267
268 static struct platform_device versatile_i2c_device = {
269 .name = "versatile-i2c",
270 .id = 0,
271 .num_resources = 1,
272 .resource = &versatile_i2c_resource,
273 };
274
275 static struct i2c_board_info versatile_i2c_board_info[] = {
276 {
277 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
278 },
279 };
280
281 static int __init versatile_i2c_init(void)
282 {
283 return i2c_register_board_info(0, versatile_i2c_board_info,
284 ARRAY_SIZE(versatile_i2c_board_info));
285 }
286 arch_initcall(versatile_i2c_init);
287
288 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
289
290 unsigned int mmc_status(struct device *dev)
291 {
292 struct amba_device *adev = container_of(dev, struct amba_device, dev);
293 u32 mask;
294
295 if (adev->res.start == VERSATILE_MMCI0_BASE)
296 mask = 1;
297 else
298 mask = 2;
299
300 return readl(VERSATILE_SYSMCI) & mask;
301 }
302
303 static struct mmci_platform_data mmc0_plat_data = {
304 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
305 .status = mmc_status,
306 .gpio_wp = -1,
307 .gpio_cd = -1,
308 };
309
310 static struct resource char_lcd_resources[] = {
311 {
312 .start = VERSATILE_CHAR_LCD_BASE,
313 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
314 .flags = IORESOURCE_MEM,
315 },
316 };
317
318 static struct platform_device char_lcd_device = {
319 .name = "arm-charlcd",
320 .id = -1,
321 .num_resources = ARRAY_SIZE(char_lcd_resources),
322 .resource = char_lcd_resources,
323 };
324
325 /*
326 * Clock handling
327 */
328 static const struct icst_params versatile_oscvco_params = {
329 .ref = 24000000,
330 .vco_max = ICST307_VCO_MAX,
331 .vco_min = ICST307_VCO_MIN,
332 .vd_min = 4 + 8,
333 .vd_max = 511 + 8,
334 .rd_min = 1 + 2,
335 .rd_max = 127 + 2,
336 .s2div = icst307_s2div,
337 .idx2s = icst307_idx2s,
338 };
339
340 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
341 {
342 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
343 u32 val;
344
345 val = readl(clk->vcoreg) & ~0x7ffff;
346 val |= vco.v | (vco.r << 9) | (vco.s << 16);
347
348 writel(0xa05f, sys_lock);
349 writel(val, clk->vcoreg);
350 writel(0, sys_lock);
351 }
352
353 static const struct clk_ops osc4_clk_ops = {
354 .round = icst_clk_round,
355 .set = icst_clk_set,
356 .setvco = versatile_oscvco_set,
357 };
358
359 static struct clk osc4_clk = {
360 .ops = &osc4_clk_ops,
361 .params = &versatile_oscvco_params,
362 };
363
364 /*
365 * These are fixed clocks.
366 */
367 static struct clk ref24_clk = {
368 .rate = 24000000,
369 };
370
371 static struct clk sp804_clk = {
372 .rate = 1000000,
373 };
374
375 static struct clk dummy_apb_pclk;
376
377 static struct clk_lookup lookups[] = {
378 { /* AMBA bus clock */
379 .con_id = "apb_pclk",
380 .clk = &dummy_apb_pclk,
381 }, { /* UART0 */
382 .dev_id = "dev:f1",
383 .clk = &ref24_clk,
384 }, { /* UART1 */
385 .dev_id = "dev:f2",
386 .clk = &ref24_clk,
387 }, { /* UART2 */
388 .dev_id = "dev:f3",
389 .clk = &ref24_clk,
390 }, { /* UART3 */
391 .dev_id = "fpga:09",
392 .clk = &ref24_clk,
393 }, { /* KMI0 */
394 .dev_id = "fpga:06",
395 .clk = &ref24_clk,
396 }, { /* KMI1 */
397 .dev_id = "fpga:07",
398 .clk = &ref24_clk,
399 }, { /* MMC0 */
400 .dev_id = "fpga:05",
401 .clk = &ref24_clk,
402 }, { /* MMC1 */
403 .dev_id = "fpga:0b",
404 .clk = &ref24_clk,
405 }, { /* SSP */
406 .dev_id = "dev:f4",
407 .clk = &ref24_clk,
408 }, { /* CLCD */
409 .dev_id = "dev:20",
410 .clk = &osc4_clk,
411 }, { /* SP804 timers */
412 .dev_id = "sp804",
413 .clk = &sp804_clk,
414 },
415 };
416
417 /*
418 * CLCD support.
419 */
420 #define SYS_CLCD_MODE_MASK (3 << 0)
421 #define SYS_CLCD_MODE_888 (0 << 0)
422 #define SYS_CLCD_MODE_5551 (1 << 0)
423 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
424 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
425 #define SYS_CLCD_NLCDIOON (1 << 2)
426 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
427 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
428 #define SYS_CLCD_ID_MASK (0x1f << 8)
429 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
430 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
431 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
432 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
433 #define SYS_CLCD_ID_VGA (0x1f << 8)
434
435 static bool is_sanyo_2_5_lcd;
436
437 /*
438 * Disable all display connectors on the interface module.
439 */
440 static void versatile_clcd_disable(struct clcd_fb *fb)
441 {
442 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
443 u32 val;
444
445 val = readl(sys_clcd);
446 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
447 writel(val, sys_clcd);
448
449 #ifdef CONFIG_MACH_VERSATILE_AB
450 /*
451 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
452 */
453 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
454 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
455 unsigned long ctrl;
456
457 ctrl = readl(versatile_ib2_ctrl);
458 ctrl &= ~0x01;
459 writel(ctrl, versatile_ib2_ctrl);
460 }
461 #endif
462 }
463
464 /*
465 * Enable the relevant connector on the interface module.
466 */
467 static void versatile_clcd_enable(struct clcd_fb *fb)
468 {
469 struct fb_var_screeninfo *var = &fb->fb.var;
470 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
471 u32 val;
472
473 val = readl(sys_clcd);
474 val &= ~SYS_CLCD_MODE_MASK;
475
476 switch (var->green.length) {
477 case 5:
478 val |= SYS_CLCD_MODE_5551;
479 break;
480 case 6:
481 if (var->red.offset == 0)
482 val |= SYS_CLCD_MODE_565_RLSB;
483 else
484 val |= SYS_CLCD_MODE_565_BLSB;
485 break;
486 case 8:
487 val |= SYS_CLCD_MODE_888;
488 break;
489 }
490
491 /*
492 * Set the MUX
493 */
494 writel(val, sys_clcd);
495
496 /*
497 * And now enable the PSUs
498 */
499 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
500 writel(val, sys_clcd);
501
502 #ifdef CONFIG_MACH_VERSATILE_AB
503 /*
504 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
505 */
506 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
507 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
508 unsigned long ctrl;
509
510 ctrl = readl(versatile_ib2_ctrl);
511 ctrl |= 0x01;
512 writel(ctrl, versatile_ib2_ctrl);
513 }
514 #endif
515 }
516
517 /*
518 * Detect which LCD panel is connected, and return the appropriate
519 * clcd_panel structure. Note: we do not have any information on
520 * the required timings for the 8.4in panel, so we presently assume
521 * VGA timings.
522 */
523 static int versatile_clcd_setup(struct clcd_fb *fb)
524 {
525 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
526 const char *panel_name;
527 u32 val;
528
529 is_sanyo_2_5_lcd = false;
530
531 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
532 if (val == SYS_CLCD_ID_SANYO_3_8)
533 panel_name = "Sanyo TM38QV67A02A";
534 else if (val == SYS_CLCD_ID_SANYO_2_5) {
535 panel_name = "Sanyo QVGA Portrait";
536 is_sanyo_2_5_lcd = true;
537 } else if (val == SYS_CLCD_ID_EPSON_2_2)
538 panel_name = "Epson L2F50113T00";
539 else if (val == SYS_CLCD_ID_VGA)
540 panel_name = "VGA";
541 else {
542 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
543 val);
544 panel_name = "VGA";
545 }
546
547 fb->panel = versatile_clcd_get_panel(panel_name);
548 if (!fb->panel)
549 return -EINVAL;
550
551 return versatile_clcd_setup_dma(fb, SZ_1M);
552 }
553
554 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
555 {
556 clcdfb_decode(fb, regs);
557
558 /* Always clear BGR for RGB565: we do the routing externally */
559 if (fb->fb.var.green.length == 6)
560 regs->cntl &= ~CNTL_BGR;
561 }
562
563 static struct clcd_board clcd_plat_data = {
564 .name = "Versatile",
565 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
566 .check = clcdfb_check,
567 .decode = versatile_clcd_decode,
568 .disable = versatile_clcd_disable,
569 .enable = versatile_clcd_enable,
570 .setup = versatile_clcd_setup,
571 .mmap = versatile_clcd_mmap_dma,
572 .remove = versatile_clcd_remove_dma,
573 };
574
575 static struct pl061_platform_data gpio0_plat_data = {
576 .gpio_base = 0,
577 .irq_base = IRQ_GPIO0_START,
578 };
579
580 static struct pl061_platform_data gpio1_plat_data = {
581 .gpio_base = 8,
582 .irq_base = IRQ_GPIO1_START,
583 };
584
585 static struct pl022_ssp_controller ssp0_plat_data = {
586 .bus_id = 0,
587 .enable_dma = 0,
588 .num_chipselect = 1,
589 };
590
591 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
592 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
593 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
594 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
595
596 /*
597 * These devices are connected directly to the multi-layer AHB switch
598 */
599 #define SMC_IRQ { NO_IRQ, NO_IRQ }
600 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
601 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
602 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
603
604 /*
605 * These devices are connected via the core APB bridge
606 */
607 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
608 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
609 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
610 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
611 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
612
613 /*
614 * These devices are connected via the DMA APB bridge
615 */
616 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
617 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
618 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
619 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
620 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
621
622 /* FPGA Primecells */
623 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
624 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
625 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
626 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
627
628 /* DevChip Primecells */
629 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
630 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
631 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
632 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
633 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
634 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
635 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
636 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
637 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
638 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
639 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
640 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
641 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
642 AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
643
644 static struct amba_device *amba_devs[] __initdata = {
645 &dmac_device,
646 &uart0_device,
647 &uart1_device,
648 &uart2_device,
649 &smc_device,
650 &mpmc_device,
651 &clcd_device,
652 &sctl_device,
653 &wdog_device,
654 &gpio0_device,
655 &gpio1_device,
656 &rtc_device,
657 &sci0_device,
658 &ssp0_device,
659 &aaci_device,
660 &mmc0_device,
661 &kmi0_device,
662 &kmi1_device,
663 };
664
665 #ifdef CONFIG_OF
666 /*
667 * Lookup table for attaching a specific name and platform_data pointer to
668 * devices as they get created by of_platform_populate(). Ideally this table
669 * would not exist, but the current clock implementation depends on some devices
670 * having a specific name.
671 */
672 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
678
679 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
680 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
681 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
682 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
683 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
684
685 #if 0
686 /*
687 * These entries are unnecessary because no clocks referencing
688 * them. I've left them in for now as place holders in case
689 * any of them need to be added back, but they should be
690 * removed before actually committing this patch. --gcl
691 */
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
695 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
696 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
697
698 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
699 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
700 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
701 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
702 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
703 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
704 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
705 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
706 #endif
707 {}
708 };
709 #endif
710
711 #ifdef CONFIG_LEDS
712 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
713
714 static void versatile_leds_event(led_event_t ledevt)
715 {
716 unsigned long flags;
717 u32 val;
718
719 local_irq_save(flags);
720 val = readl(VA_LEDS_BASE);
721
722 switch (ledevt) {
723 case led_idle_start:
724 val = val & ~VERSATILE_SYS_LED0;
725 break;
726
727 case led_idle_end:
728 val = val | VERSATILE_SYS_LED0;
729 break;
730
731 case led_timer:
732 val = val ^ VERSATILE_SYS_LED1;
733 break;
734
735 case led_halted:
736 val = 0;
737 break;
738
739 default:
740 break;
741 }
742
743 writel(val, VA_LEDS_BASE);
744 local_irq_restore(flags);
745 }
746 #endif /* CONFIG_LEDS */
747
748 /* Early initializations */
749 void __init versatile_init_early(void)
750 {
751 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
752
753 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
754 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
755
756 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
757 }
758
759 void __init versatile_init(void)
760 {
761 int i;
762
763 platform_device_register(&versatile_flash_device);
764 platform_device_register(&versatile_i2c_device);
765 platform_device_register(&smc91x_device);
766 platform_device_register(&char_lcd_device);
767
768 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
769 struct amba_device *d = amba_devs[i];
770 amba_device_register(d, &iomem_resource);
771 }
772
773 #ifdef CONFIG_LEDS
774 leds_event = versatile_leds_event;
775 #endif
776 }
777
778 /*
779 * Where is the timer (VA)?
780 */
781 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
782 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
783 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
784 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
785
786 /*
787 * Set up timer interrupt, and return the current time in seconds.
788 */
789 static void __init versatile_timer_init(void)
790 {
791 u32 val;
792
793 /*
794 * set clock frequency:
795 * VERSATILE_REFCLK is 32KHz
796 * VERSATILE_TIMCLK is 1MHz
797 */
798 val = readl(__io_address(VERSATILE_SCTL_BASE));
799 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
800 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
801 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
802 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
803 __io_address(VERSATILE_SCTL_BASE));
804
805 /*
806 * Initialise to a known state (all timers off)
807 */
808 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
809 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
810 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
811 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
812
813 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
814 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
815 }
816
817 struct sys_timer versatile_timer = {
818 .init = versatile_timer_init,
819 };
820
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