arch/arm/plat-omap/counter_32k.c

   1 /*
   2  * OMAP 32ksynctimer/counter_32k-related code
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Tony Lindgren <tony@atomide.com>
   7  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/sched.h>
  21 #include <linux/clocksource.h>
  22
  23 #include <asm/sched_clock.h>
  24
  25 #include <plat/common.h>
  26 #include <plat/board.h>
  27
  28 #include <plat/clock.h>
  29
  30 /*
  31  * 32KHz clocksource ... always available, on pretty most chips except
  32  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
  33  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
  34  * but systems won't necessarily want to spend resources that way.
  35  */
  36 static void __iomem *timer_32k_base;
  37
  38 #define OMAP16XX_TIMER_32K_SYNCHRONIZED         0xfffbc410
  39
  40 /*
  41  * Returns current time from boot in nsecs. It's OK for this to wrap
  42  * around for now, as it's just a relative time stamp.
  43  */
  44 static DEFINE_CLOCK_DATA(cd);
  45
  46 /*
  47  * Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC, 60).
  48  * This gives a resolution of about 30us and a wrap period of about 36hrs.
  49  */
  50 #define SC_MULT         4000000000u
  51 #define SC_SHIFT        17
  52
  53 static inline unsigned long long notrace _omap_32k_sched_clock(void)
  54 {
  55         u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
  56         return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
  57 }
  58
  59 #if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
  60 unsigned long long notrace sched_clock(void)
  61 {
  62         return _omap_32k_sched_clock();
  63 }
  64 #else
  65 unsigned long long notrace omap_32k_sched_clock(void)
  66 {
  67         return _omap_32k_sched_clock();
  68 }
  69 #endif
  70
  71 static void notrace omap_update_sched_clock(void)
  72 {
  73         u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
  74         update_sched_clock(&cd, cyc, (u32)~0);
  75 }
  76
  77 /**
  78  * read_persistent_clock -  Return time from a persistent clock.
  79  *
  80  * Reads the time from a source which isn't disabled during PM, the
  81  * 32k sync timer.  Convert the cycles elapsed since last read into
  82  * nsecs and adds to a monotonically increasing timespec.
  83  */
  84 static struct timespec persistent_ts;
  85 static cycles_t cycles, last_cycles;
  86 static unsigned int persistent_mult, persistent_shift;
  87 void read_persistent_clock(struct timespec *ts)
  88 {
  89         unsigned long long nsecs;
  90         cycles_t delta;
  91         struct timespec *tsp = &persistent_ts;
  92
  93         last_cycles = cycles;
  94         cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
  95         delta = cycles - last_cycles;
  96
  97         nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
  98
  99         timespec_add_ns(tsp, nsecs);
 100         *ts = *tsp;
 101 }
 102
 103 int __init omap_init_clocksource_32k(void)
 104 {
 105         static char err[] __initdata = KERN_ERR
 106                         "%s: can't register clocksource!\n";
 107
 108         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
 109                 u32 pbase;
 110                 unsigned long size = SZ_4K;
 111                 void __iomem *base;
 112                 struct clk *sync_32k_ick;
 113
 114                 if (cpu_is_omap16xx()) {
 115                         pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
 116                         size = SZ_1K;
 117                 } else if (cpu_is_omap2420())
 118                         pbase = OMAP2420_32KSYNCT_BASE + 0x10;
 119                 else if (cpu_is_omap2430())
 120                         pbase = OMAP2430_32KSYNCT_BASE + 0x10;
 121                 else if (cpu_is_omap34xx())
 122                         pbase = OMAP3430_32KSYNCT_BASE + 0x10;
 123                 else if (cpu_is_omap44xx())
 124                         pbase = OMAP4430_32KSYNCT_BASE + 0x10;
 125                 else
 126                         return -ENODEV;
 127
 128                 /* For this to work we must have a static mapping in io.c for this area */
 129                 base = ioremap(pbase, size);
 130                 if (!base)
 131                         return -ENODEV;
 132
 133                 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
 134                 if (!IS_ERR(sync_32k_ick))
 135                         clk_enable(sync_32k_ick);
 136
 137                 timer_32k_base = base;
 138
 139                 /*
 140                  * 120000 rough estimate from the calculations in
 141                  * __clocksource_updatefreq_scale.
 142                  */
 143                 clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
 144                                 32768, NSEC_PER_SEC, 120000);
 145
 146                 if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
 147                                           clocksource_mmio_readl_up))
 148                         printk(err, "32k_counter");
 149
 150                 init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
 151                                        32768, SC_MULT, SC_SHIFT);
 152         }
 153         return 0;
 154 }