arch/arm/plat-omap/include/plat/mcbsp.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mcbsp.h
   3  *
   4  * Defines for Multi-Channel Buffered Serial Port
   5  *
   6  * Copyright (C) 2002 RidgeRun, Inc.
   7  * Author: Steve Johnson
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  *
  23  */
  24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
  25 #define __ASM_ARCH_OMAP_MCBSP_H
  26
  27 #include <linux/spinlock.h>
  28
  29 #include <mach/hardware.h>
  30 #include <plat/clock.h>
  31
  32 /* macro for building platform_device for McBSP ports */
  33 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
  34 static struct platform_device omap_mcbsp##port_nr = {   \
  35         .name   = "omap-mcbsp-dai",                     \
  36         .id     = port_nr - 1,                  \
  37 }
  38
  39 #define MCBSP_CONFIG_TYPE2      0x2
  40 #define MCBSP_CONFIG_TYPE3      0x3
  41 #define MCBSP_CONFIG_TYPE4      0x4
  42
  43 #define OMAP7XX_MCBSP1_BASE     0xfffb1000
  44 #define OMAP7XX_MCBSP2_BASE     0xfffb1800
  45
  46 #define OMAP1510_MCBSP1_BASE    0xe1011800
  47 #define OMAP1510_MCBSP2_BASE    0xfffb1000
  48 #define OMAP1510_MCBSP3_BASE    0xe1017000
  49
  50 #define OMAP1610_MCBSP1_BASE    0xe1011800
  51 #define OMAP1610_MCBSP2_BASE    0xfffb1000
  52 #define OMAP1610_MCBSP3_BASE    0xe1017000
  53
  54 #ifdef CONFIG_ARCH_OMAP1
  55
  56 #define OMAP_MCBSP_REG_DRR2     0x00
  57 #define OMAP_MCBSP_REG_DRR1     0x02
  58 #define OMAP_MCBSP_REG_DXR2     0x04
  59 #define OMAP_MCBSP_REG_DXR1     0x06
  60 #define OMAP_MCBSP_REG_DRR      0x02
  61 #define OMAP_MCBSP_REG_DXR      0x06
  62 #define OMAP_MCBSP_REG_SPCR2    0x08
  63 #define OMAP_MCBSP_REG_SPCR1    0x0a
  64 #define OMAP_MCBSP_REG_RCR2     0x0c
  65 #define OMAP_MCBSP_REG_RCR1     0x0e
  66 #define OMAP_MCBSP_REG_XCR2     0x10
  67 #define OMAP_MCBSP_REG_XCR1     0x12
  68 #define OMAP_MCBSP_REG_SRGR2    0x14
  69 #define OMAP_MCBSP_REG_SRGR1    0x16
  70 #define OMAP_MCBSP_REG_MCR2     0x18
  71 #define OMAP_MCBSP_REG_MCR1     0x1a
  72 #define OMAP_MCBSP_REG_RCERA    0x1c
  73 #define OMAP_MCBSP_REG_RCERB    0x1e
  74 #define OMAP_MCBSP_REG_XCERA    0x20
  75 #define OMAP_MCBSP_REG_XCERB    0x22
  76 #define OMAP_MCBSP_REG_PCR0     0x24
  77 #define OMAP_MCBSP_REG_RCERC    0x26
  78 #define OMAP_MCBSP_REG_RCERD    0x28
  79 #define OMAP_MCBSP_REG_XCERC    0x2A
  80 #define OMAP_MCBSP_REG_XCERD    0x2C
  81 #define OMAP_MCBSP_REG_RCERE    0x2E
  82 #define OMAP_MCBSP_REG_RCERF    0x30
  83 #define OMAP_MCBSP_REG_XCERE    0x32
  84 #define OMAP_MCBSP_REG_XCERF    0x34
  85 #define OMAP_MCBSP_REG_RCERG    0x36
  86 #define OMAP_MCBSP_REG_RCERH    0x38
  87 #define OMAP_MCBSP_REG_XCERG    0x3A
  88 #define OMAP_MCBSP_REG_XCERH    0x3C
  89
  90 /* Dummy defines, these are not available on omap1 */
  91 #define OMAP_MCBSP_REG_XCCR     0x00
  92 #define OMAP_MCBSP_REG_RCCR     0x00
  93
  94 #else
  95
  96 #define OMAP_MCBSP_REG_DRR2     0x00
  97 #define OMAP_MCBSP_REG_DRR1     0x04
  98 #define OMAP_MCBSP_REG_DXR2     0x08
  99 #define OMAP_MCBSP_REG_DXR1     0x0C
 100 #define OMAP_MCBSP_REG_DRR      0x00
 101 #define OMAP_MCBSP_REG_DXR      0x08
 102 #define OMAP_MCBSP_REG_SPCR2    0x10
 103 #define OMAP_MCBSP_REG_SPCR1    0x14
 104 #define OMAP_MCBSP_REG_RCR2     0x18
 105 #define OMAP_MCBSP_REG_RCR1     0x1C
 106 #define OMAP_MCBSP_REG_XCR2     0x20
 107 #define OMAP_MCBSP_REG_XCR1     0x24
 108 #define OMAP_MCBSP_REG_SRGR2    0x28
 109 #define OMAP_MCBSP_REG_SRGR1    0x2C
 110 #define OMAP_MCBSP_REG_MCR2     0x30
 111 #define OMAP_MCBSP_REG_MCR1     0x34
 112 #define OMAP_MCBSP_REG_RCERA    0x38
 113 #define OMAP_MCBSP_REG_RCERB    0x3C
 114 #define OMAP_MCBSP_REG_XCERA    0x40
 115 #define OMAP_MCBSP_REG_XCERB    0x44
 116 #define OMAP_MCBSP_REG_PCR0     0x48
 117 #define OMAP_MCBSP_REG_RCERC    0x4C
 118 #define OMAP_MCBSP_REG_RCERD    0x50
 119 #define OMAP_MCBSP_REG_XCERC    0x54
 120 #define OMAP_MCBSP_REG_XCERD    0x58
 121 #define OMAP_MCBSP_REG_RCERE    0x5C
 122 #define OMAP_MCBSP_REG_RCERF    0x60
 123 #define OMAP_MCBSP_REG_XCERE    0x64
 124 #define OMAP_MCBSP_REG_XCERF    0x68
 125 #define OMAP_MCBSP_REG_RCERG    0x6C
 126 #define OMAP_MCBSP_REG_RCERH    0x70
 127 #define OMAP_MCBSP_REG_XCERG    0x74
 128 #define OMAP_MCBSP_REG_XCERH    0x78
 129 #define OMAP_MCBSP_REG_SYSCON   0x8C
 130 #define OMAP_MCBSP_REG_THRSH2   0x90
 131 #define OMAP_MCBSP_REG_THRSH1   0x94
 132 #define OMAP_MCBSP_REG_IRQST    0xA0
 133 #define OMAP_MCBSP_REG_IRQEN    0xA4
 134 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 135 #define OMAP_MCBSP_REG_XCCR     0xAC
 136 #define OMAP_MCBSP_REG_RCCR     0xB0
 137 #define OMAP_MCBSP_REG_XBUFFSTAT        0xB4
 138 #define OMAP_MCBSP_REG_RBUFFSTAT        0xB8
 139 #define OMAP_MCBSP_REG_SSELCR   0xBC
 140
 141 #define OMAP_ST_REG_REV         0x00
 142 #define OMAP_ST_REG_SYSCONFIG   0x10
 143 #define OMAP_ST_REG_IRQSTATUS   0x18
 144 #define OMAP_ST_REG_IRQENABLE   0x1C
 145 #define OMAP_ST_REG_SGAINCR     0x24
 146 #define OMAP_ST_REG_SFIRCR      0x28
 147 #define OMAP_ST_REG_SSELCR      0x2C
 148
 149 #endif
 150
 151 /************************** McBSP SPCR1 bit definitions ***********************/
 152 #define RRST                    0x0001
 153 #define RRDY                    0x0002
 154 #define RFULL                   0x0004
 155 #define RSYNC_ERR               0x0008
 156 #define RINTM(value)            ((value)<<4)    /* bits 4:5 */
 157 #define ABIS                    0x0040
 158 #define DXENA                   0x0080
 159 #define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
 160 #define RJUST(value)            ((value)<<13)   /* bits 13:14 */
 161 #define ALB                     0x8000
 162 #define DLB                     0x8000
 163
 164 /************************** McBSP SPCR2 bit definitions ***********************/
 165 #define XRST            0x0001
 166 #define XRDY            0x0002
 167 #define XEMPTY          0x0004
 168 #define XSYNC_ERR       0x0008
 169 #define XINTM(value)    ((value)<<4)            /* bits 4:5 */
 170 #define GRST            0x0040
 171 #define FRST            0x0080
 172 #define SOFT            0x0100
 173 #define FREE            0x0200
 174
 175 /************************** McBSP PCR bit definitions *************************/
 176 #define CLKRP           0x0001
 177 #define CLKXP           0x0002
 178 #define FSRP            0x0004
 179 #define FSXP            0x0008
 180 #define DR_STAT         0x0010
 181 #define DX_STAT         0x0020
 182 #define CLKS_STAT       0x0040
 183 #define SCLKME          0x0080
 184 #define CLKRM           0x0100
 185 #define CLKXM           0x0200
 186 #define FSRM            0x0400
 187 #define FSXM            0x0800
 188 #define RIOEN           0x1000
 189 #define XIOEN           0x2000
 190 #define IDLE_EN         0x4000
 191
 192 /************************** McBSP RCR1 bit definitions ************************/
 193 #define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 194 #define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 195
 196 /************************** McBSP XCR1 bit definitions ************************/
 197 #define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 198 #define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 199
 200 /*************************** McBSP RCR2 bit definitions ***********************/
 201 #define RDATDLY(value)          (value)         /* Bits 0:1 */
 202 #define RFIG                    0x0004
 203 #define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 204 #define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 205 #define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 206 #define RPHASE                  0x8000
 207
 208 /*************************** McBSP XCR2 bit definitions ***********************/
 209 #define XDATDLY(value)          (value)         /* Bits 0:1 */
 210 #define XFIG                    0x0004
 211 #define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 212 #define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 213 #define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 214 #define XPHASE                  0x8000
 215
 216 /************************* McBSP SRGR1 bit definitions ************************/
 217 #define CLKGDV(value)           (value)         /* Bits 0:7 */
 218 #define FWID(value)             ((value)<<8)    /* Bits 8:15 */
 219
 220 /************************* McBSP SRGR2 bit definitions ************************/
 221 #define FPER(value)             (value)         /* Bits 0:11 */
 222 #define FSGM                    0x1000
 223 #define CLKSM                   0x2000
 224 #define CLKSP                   0x4000
 225 #define GSYNC                   0x8000
 226
 227 /************************* McBSP MCR1 bit definitions *************************/
 228 #define RMCM                    0x0001
 229 #define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 230 #define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 231 #define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 232
 233 /************************* McBSP MCR2 bit definitions *************************/
 234 #define XMCM(value)             (value)         /* Bits 0:1 */
 235 #define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 236 #define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 237 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 238
 239 /*********************** McBSP XCCR bit definitions *************************/
 240 #define EXTCLKGATE              0x8000
 241 #define PPCONNECT               0x4000
 242 #define DXENDLY(value)          ((value)<<12)   /* Bits 12:13 */
 243 #define XFULL_CYCLE             0x0800
 244 #define DILB                    0x0020
 245 #define XDMAEN                  0x0008
 246 #define XDISABLE                0x0001
 247
 248 /********************** McBSP RCCR bit definitions *************************/
 249 #define RFULL_CYCLE             0x0800
 250 #define RDMAEN                  0x0008
 251 #define RDISABLE                0x0001
 252
 253 /********************** McBSP SYSCONFIG bit definitions ********************/
 254 #define CLOCKACTIVITY(value)    ((value)<<8)
 255 #define SIDLEMODE(value)        ((value)<<3)
 256 #define ENAWAKEUP               0x0004
 257 #define SOFTRST                 0x0002
 258
 259 /********************** McBSP SSELCR bit definitions ***********************/
 260 #define SIDETONEEN              0x0400
 261
 262 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
 263 #define ST_AUTOIDLE             0x0001
 264
 265 /********************** McBSP Sidetone SGAINCR bit definitions *************/
 266 #define ST_CH1GAIN(value)       ((value<<16))   /* Bits 16:31 */
 267 #define ST_CH0GAIN(value)       (value)         /* Bits 0:15 */
 268
 269 /********************** McBSP Sidetone SFIRCR bit definitions **************/
 270 #define ST_FIRCOEFF(value)      (value)         /* Bits 0:15 */
 271
 272 /********************** McBSP Sidetone SSELCR bit definitions **************/
 273 #define ST_COEFFWRDONE          0x0004
 274 #define ST_COEFFWREN            0x0002
 275 #define ST_SIDETONEEN           0x0001
 276
 277 /********************** McBSP DMA operating modes **************************/
 278 #define MCBSP_DMA_MODE_ELEMENT          0
 279 #define MCBSP_DMA_MODE_THRESHOLD        1
 280 #define MCBSP_DMA_MODE_FRAME            2
 281
 282 /********************** McBSP WAKEUPEN bit definitions *********************/
 283 #define XEMPTYEOFEN             0x4000
 284 #define XRDYEN                  0x0400
 285 #define XEOFEN                  0x0200
 286 #define XFSXEN                  0x0100
 287 #define XSYNCERREN              0x0080
 288 #define RRDYEN                  0x0008
 289 #define REOFEN                  0x0004
 290 #define RFSREN                  0x0002
 291 #define RSYNCERREN              0x0001
 292
 293 /* CLKR signal muxing options */
 294 #define CLKR_SRC_CLKR           0
 295 #define CLKR_SRC_CLKX           1
 296
 297 /* FSR signal muxing options */
 298 #define FSR_SRC_FSR             0
 299 #define FSR_SRC_FSX             1
 300
 301 /* McBSP functional clock sources */
 302 #define MCBSP_CLKS_PRCM_SRC     0
 303 #define MCBSP_CLKS_PAD_SRC      1
 304
 305 /* we don't do multichannel for now */
 306 struct omap_mcbsp_reg_cfg {
 307         u16 spcr2;
 308         u16 spcr1;
 309         u16 rcr2;
 310         u16 rcr1;
 311         u16 xcr2;
 312         u16 xcr1;
 313         u16 srgr2;
 314         u16 srgr1;
 315         u16 mcr2;
 316         u16 mcr1;
 317         u16 pcr0;
 318         u16 rcerc;
 319         u16 rcerd;
 320         u16 xcerc;
 321         u16 xcerd;
 322         u16 rcere;
 323         u16 rcerf;
 324         u16 xcere;
 325         u16 xcerf;
 326         u16 rcerg;
 327         u16 rcerh;
 328         u16 xcerg;
 329         u16 xcerh;
 330         u16 xccr;
 331         u16 rccr;
 332 };
 333
 334 typedef enum {
 335         OMAP_MCBSP_WORD_8 = 0,
 336         OMAP_MCBSP_WORD_12,
 337         OMAP_MCBSP_WORD_16,
 338         OMAP_MCBSP_WORD_20,
 339         OMAP_MCBSP_WORD_24,
 340         OMAP_MCBSP_WORD_32,
 341 } omap_mcbsp_word_length;
 342
 343 /* Platform specific configuration */
 344 struct omap_mcbsp_ops {
 345         void (*request)(unsigned int);
 346         void (*free)(unsigned int);
 347         int (*set_clks_src)(u8, u8);
 348 };
 349
 350 struct omap_mcbsp_platform_data {
 351         unsigned long phys_base;
 352         u8 dma_rx_sync, dma_tx_sync;
 353         u16 rx_irq, tx_irq;
 354         struct omap_mcbsp_ops *ops;
 355 #ifdef CONFIG_ARCH_OMAP3
 356         /* Sidetone block for McBSP 2 and 3 */
 357         unsigned long phys_base_st;
 358 #endif
 359         u16 buffer_size;
 360         unsigned int mcbsp_config_type;
 361 };
 362
 363 struct omap_mcbsp_st_data {
 364         void __iomem *io_base_st;
 365         bool running;
 366         bool enabled;
 367         s16 taps[128];  /* Sidetone filter coefficients */
 368         int nr_taps;    /* Number of filter coefficients in use */
 369         s16 ch0gain;
 370         s16 ch1gain;
 371 };
 372
 373 struct omap_mcbsp {
 374         struct device *dev;
 375         unsigned long phys_base;
 376         unsigned long phys_dma_base;
 377         void __iomem *io_base;
 378         u8 id;
 379         u8 free;
 380
 381         int rx_irq;
 382         int tx_irq;
 383
 384         /* DMA stuff */
 385         u8 dma_rx_sync;
 386         u8 dma_tx_sync;
 387
 388         /* Protect the field .free, while checking if the mcbsp is in use */
 389         spinlock_t lock;
 390         struct omap_mcbsp_platform_data *pdata;
 391         struct clk *fclk;
 392 #ifdef CONFIG_ARCH_OMAP3
 393         struct omap_mcbsp_st_data *st_data;
 394         int dma_op_mode;
 395         u16 max_tx_thres;
 396         u16 max_rx_thres;
 397 #endif
 398         void *reg_cache;
 399         unsigned int mcbsp_config_type;
 400 };
 401
 402 /**
 403  * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
 404  * @sidetone: name of the sidetone device
 405  */
 406 struct omap_mcbsp_dev_attr {
 407         const char *sidetone;
 408 };
 409
 410 extern struct omap_mcbsp **mcbsp_ptr;
 411 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 412
 413 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
 414 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 415
 416 int omap_mcbsp_init(void);
 417 void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
 418                         struct omap_mcbsp_platform_data *config, int size);
 419 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 420 #ifdef CONFIG_ARCH_OMAP3
 421 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 422 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 423 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
 424 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
 425 u16 omap_mcbsp_get_fifo_size(unsigned int id);
 426 u16 omap_mcbsp_get_tx_delay(unsigned int id);
 427 u16 omap_mcbsp_get_rx_delay(unsigned int id);
 428 int omap_mcbsp_get_dma_op_mode(unsigned int id);
 429 #else
 430 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 431 { }
 432 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 433 { }
 434 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
 435 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
 436 static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
 437 static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
 438 static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
 439 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
 440 #endif
 441 int omap_mcbsp_request(unsigned int id);
 442 void omap_mcbsp_free(unsigned int id);
 443 void omap_mcbsp_start(unsigned int id, int tx, int rx);
 444 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
 445
 446 /* McBSP functional clock source changing function */
 447 extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
 448
 449 /* McBSP signal muxing API */
 450 void omap2_mcbsp1_mux_clkr_src(u8 mux);
 451 void omap2_mcbsp1_mux_fsr_src(u8 mux);
 452
 453 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
 454 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
 455
 456 #ifdef CONFIG_ARCH_OMAP3
 457 /* Sidetone specific API */
 458 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
 459 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
 460 int omap_st_enable(unsigned int id);
 461 int omap_st_disable(unsigned int id);
 462 int omap_st_is_enabled(unsigned int id);
 463 #else
 464 static inline int omap_st_set_chgain(unsigned int id, int channel,
 465                                      s16 chgain) { return 0; }
 466 static inline int omap_st_get_chgain(unsigned int id, int channel,
 467                                      s16 *chgain) { return 0; }
 468 static inline int omap_st_enable(unsigned int id) { return 0; }
 469 static inline int omap_st_disable(unsigned int id) { return 0; }
 470 static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
 471 #endif
 472
 473 #endif