arch/mips/alchemy/common/pci.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Alchemy/AMD Au1x00 PCI support.
   4  *
   5  * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc. <source@mvista.com>
   7  *
   8  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
   9  *
  10  *  Support for all devices (greater than 16) added by David Gathright.
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  *
  17  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *  You should have received a copy of the  GNU General Public License along
  29  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30  *  675 Mass Ave, Cambridge, MA 02139, USA.
  31  */
  32
  33 #include <linux/pci.h>
  34 #include <linux/kernel.h>
  35 #include <linux/init.h>
  36
  37 #include <asm/mach-au1x00/au1000.h>
  38
  39 /* TBD */
  40 static struct resource pci_io_resource = {
  41         .start  = PCI_IO_START,
  42         .end    = PCI_IO_END,
  43         .name   = "PCI IO space",
  44         .flags  = IORESOURCE_IO
  45 };
  46
  47 static struct resource pci_mem_resource = {
  48         .start  = PCI_MEM_START,
  49         .end    = PCI_MEM_END,
  50         .name   = "PCI memory space",
  51         .flags  = IORESOURCE_MEM
  52 };
  53
  54 extern struct pci_ops au1x_pci_ops;
  55
  56 static struct pci_controller au1x_controller = {
  57         .pci_ops        = &au1x_pci_ops,
  58         .io_resource    = &pci_io_resource,
  59         .mem_resource   = &pci_mem_resource,
  60 };
  61
  62 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
  63 static unsigned long virt_io_addr;
  64 #endif
  65
  66 static int __init au1x_pci_setup(void)
  67 {
  68         extern void au1x_pci_cfg_init(void);
  69
  70 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
  71         virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
  72                         Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
  73
  74         if (!virt_io_addr) {
  75                 printk(KERN_ERR "Unable to ioremap pci space\n");
  76                 return 1;
  77         }
  78         au1x_controller.io_map_base = virt_io_addr;
  79
  80 #ifdef CONFIG_DMA_NONCOHERENT
  81         {
  82                 /*
  83                  *  Set the NC bit in controller for Au1500 pre-AC silicon
  84                  */
  85                 u32 prid = read_c0_prid();
  86
  87                 if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
  88                         au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
  89                                   Au1500_PCI_CFG);
  90                         printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
  91                 }
  92         }
  93 #endif
  94
  95         set_io_port_base(virt_io_addr);
  96 #endif
  97
  98         au1x_pci_cfg_init();
  99
 100         register_pci_controller(&au1x_controller);
 101         return 0;
 102 }
 103
 104 arch_initcall(au1x_pci_setup);