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PCI: Disable MPS configuration by default
[linux-btrfs-devel.git] / include / linux / pci.h
blob9fc01226055b5f8378d5004bdc398cd22d21f55a
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215 };
216
217 struct pci_cap_saved_data {
218 char cap_nr;
219 unsigned int size;
220 u32 data[0];
221 };
222
223 struct pci_cap_saved_state {
224 struct hlist_node next;
225 struct pci_cap_saved_data cap;
226 };
227
228 struct pcie_link_state;
229 struct pci_vpd;
230 struct pci_sriov;
231 struct pci_ats;
232
233 /*
234 * The pci_dev structure is used to describe PCI devices.
235 */
236 struct pci_dev {
237 struct list_head bus_list; /* node in per-bus list */
238 struct pci_bus *bus; /* bus this device is on */
239 struct pci_bus *subordinate; /* bus this device bridges to */
240
241 void *sysdata; /* hook for sys-specific extension */
242 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
243 struct pci_slot *slot; /* Physical slot this device is in */
244
245 unsigned int devfn; /* encoded device & function index */
246 unsigned short vendor;
247 unsigned short device;
248 unsigned short subsystem_vendor;
249 unsigned short subsystem_device;
250 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
251 u8 revision; /* PCI revision, low byte of class word */
252 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
253 u8 pcie_cap; /* PCI-E capability offset */
254 u8 pcie_type:4; /* PCI-E device/port type */
255 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
256 u8 rom_base_reg; /* which config register controls the ROM */
257 u8 pin; /* which interrupt pin this device uses */
258
259 struct pci_driver *driver; /* which driver has allocated this device */
260 u64 dma_mask; /* Mask of the bits of bus address this
261 device implements. Normally this is
262 0xffffffff. You only need to change
263 this if your device has broken DMA
264 or supports 64-bit transfers. */
265
266 struct device_dma_parameters dma_parms;
267
268 pci_power_t current_state; /* Current operating state. In ACPI-speak,
269 this is D0-D3, D0 being fully functional,
270 and D3 being off. */
271 int pm_cap; /* PM capability offset in the
272 configuration space */
273 unsigned int pme_support:5; /* Bitmask of states from which PME#
274 can be generated */
275 unsigned int pme_interrupt:1;
276 unsigned int d1_support:1; /* Low power state D1 is supported */
277 unsigned int d2_support:1; /* Low power state D2 is supported */
278 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
279 unsigned int mmio_always_on:1; /* disallow turning off io/mem
280 decoding during bar sizing */
281 unsigned int wakeup_prepared:1;
282 unsigned int d3_delay; /* D3->D0 transition time in ms */
283
284 #ifdef CONFIG_PCIEASPM
285 struct pcie_link_state *link_state; /* ASPM link state. */
286 #endif
287
288 pci_channel_state_t error_state; /* current connectivity state */
289 struct device dev; /* Generic device interface */
290
291 int cfg_size; /* Size of configuration space */
292
293 /*
294 * Instead of touching interrupt line and base address registers
295 * directly, use the values stored here. They might be different!
296 */
297 unsigned int irq;
298 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
299 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
300
301 /* These fields are used by common fixups */
302 unsigned int transparent:1; /* Transparent PCI bridge */
303 unsigned int multifunction:1;/* Part of multi-function device */
304 /* keep track of device state */
305 unsigned int is_added:1;
306 unsigned int is_busmaster:1; /* device is busmaster */
307 unsigned int no_msi:1; /* device may not use msi */
308 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
309 unsigned int broken_parity_status:1; /* Device generates false positive parity */
310 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
311 unsigned int msi_enabled:1;
312 unsigned int msix_enabled:1;
313 unsigned int ari_enabled:1; /* ARI forwarding */
314 unsigned int is_managed:1;
315 unsigned int is_pcie:1; /* Obsolete. Will be removed.
316 Use pci_is_pcie() instead */
317 unsigned int needs_freset:1; /* Dev requires fundamental reset */
318 unsigned int state_saved:1;
319 unsigned int is_physfn:1;
320 unsigned int is_virtfn:1;
321 unsigned int reset_fn:1;
322 unsigned int is_hotplug_bridge:1;
323 unsigned int __aer_firmware_first_valid:1;
324 unsigned int __aer_firmware_first:1;
325 pci_dev_flags_t dev_flags;
326 atomic_t enable_cnt; /* pci_enable_device has been called */
327
328 u32 saved_config_space[16]; /* config space saved at suspend time */
329 struct hlist_head saved_cap_space;
330 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
331 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
332 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
333 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
334 #ifdef CONFIG_PCI_MSI
335 struct list_head msi_list;
336 #endif
337 struct pci_vpd *vpd;
338 #ifdef CONFIG_PCI_IOV
339 union {
340 struct pci_sriov *sriov; /* SR-IOV capability related */
341 struct pci_dev *physfn; /* the PF this VF is associated with */
342 };
343 struct pci_ats *ats; /* Address Translation Service */
344 #endif
345 };
346
347 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
348 {
349 #ifdef CONFIG_PCI_IOV
350 if (dev->is_virtfn)
351 dev = dev->physfn;
352 #endif
353
354 return dev;
355 }
356
357 extern struct pci_dev *alloc_pci_dev(void);
358
359 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
360 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
361 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
362
363 static inline int pci_channel_offline(struct pci_dev *pdev)
364 {
365 return (pdev->error_state != pci_channel_io_normal);
366 }
367
368 static inline struct pci_cap_saved_state *pci_find_saved_cap(
369 struct pci_dev *pci_dev, char cap)
370 {
371 struct pci_cap_saved_state *tmp;
372 struct hlist_node *pos;
373
374 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
375 if (tmp->cap.cap_nr == cap)
376 return tmp;
377 }
378 return NULL;
379 }
380
381 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
382 struct pci_cap_saved_state *new_cap)
383 {
384 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
385 }
386
387 /*
388 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
389 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
390 * buses below host bridges or subtractive decode bridges) go in the list.
391 * Use pci_bus_for_each_resource() to iterate through all the resources.
392 */
393
394 /*
395 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
396 * and there's no way to program the bridge with the details of the window.
397 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
398 * decode bit set, because they are explicit and can be programmed with _SRS.
399 */
400 #define PCI_SUBTRACTIVE_DECODE 0x1
401
402 struct pci_bus_resource {
403 struct list_head list;
404 struct resource *res;
405 unsigned int flags;
406 };
407
408 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
409
410 struct pci_bus {
411 struct list_head node; /* node in list of buses */
412 struct pci_bus *parent; /* parent bus this bridge is on */
413 struct list_head children; /* list of child buses */
414 struct list_head devices; /* list of devices on this bus */
415 struct pci_dev *self; /* bridge device as seen by parent */
416 struct list_head slots; /* list of slots on this bus */
417 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
418 struct list_head resources; /* address space routed to this bus */
419
420 struct pci_ops *ops; /* configuration access functions */
421 void *sysdata; /* hook for sys-specific extension */
422 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
423
424 unsigned char number; /* bus number */
425 unsigned char primary; /* number of primary bridge */
426 unsigned char secondary; /* number of secondary bridge */
427 unsigned char subordinate; /* max number of subordinate buses */
428 unsigned char max_bus_speed; /* enum pci_bus_speed */
429 unsigned char cur_bus_speed; /* enum pci_bus_speed */
430
431 char name[48];
432
433 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
434 pci_bus_flags_t bus_flags; /* Inherited by child busses */
435 struct device *bridge;
436 struct device dev;
437 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
438 struct bin_attribute *legacy_mem; /* legacy mem */
439 unsigned int is_added:1;
440 };
441
442 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
443 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
444
445 /*
446 * Returns true if the pci bus is root (behind host-pci bridge),
447 * false otherwise
448 */
449 static inline bool pci_is_root_bus(struct pci_bus *pbus)
450 {
451 return !(pbus->parent);
452 }
453
454 #ifdef CONFIG_PCI_MSI
455 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
456 {
457 return pci_dev->msi_enabled || pci_dev->msix_enabled;
458 }
459 #else
460 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
461 #endif
462
463 /*
464 * Error values that may be returned by PCI functions.
465 */
466 #define PCIBIOS_SUCCESSFUL 0x00
467 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
468 #define PCIBIOS_BAD_VENDOR_ID 0x83
469 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
470 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
471 #define PCIBIOS_SET_FAILED 0x88
472 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
473
474 /* Low-level architecture-dependent routines */
475
476 struct pci_ops {
477 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
478 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
479 };
480
481 /*
482 * ACPI needs to be able to access PCI config space before we've done a
483 * PCI bus scan and created pci_bus structures.
484 */
485 extern int raw_pci_read(unsigned int domain, unsigned int bus,
486 unsigned int devfn, int reg, int len, u32 *val);
487 extern int raw_pci_write(unsigned int domain, unsigned int bus,
488 unsigned int devfn, int reg, int len, u32 val);
489
490 struct pci_bus_region {
491 resource_size_t start;
492 resource_size_t end;
493 };
494
495 struct pci_dynids {
496 spinlock_t lock; /* protects list, index */
497 struct list_head list; /* for IDs added at runtime */
498 };
499
500 /* ---------------------------------------------------------------- */
501 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
502 * a set of callbacks in struct pci_error_handlers, then that device driver
503 * will be notified of PCI bus errors, and will be driven to recovery
504 * when an error occurs.
505 */
506
507 typedef unsigned int __bitwise pci_ers_result_t;
508
509 enum pci_ers_result {
510 /* no result/none/not supported in device driver */
511 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
512
513 /* Device driver can recover without slot reset */
514 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
515
516 /* Device driver wants slot to be reset. */
517 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
518
519 /* Device has completely failed, is unrecoverable */
520 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
521
522 /* Device driver is fully recovered and operational */
523 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
524 };
525
526 /* PCI bus error event callbacks */
527 struct pci_error_handlers {
528 /* PCI bus error detected on this device */
529 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
530 enum pci_channel_state error);
531
532 /* MMIO has been re-enabled, but not DMA */
533 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
534
535 /* PCI Express link has been reset */
536 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
537
538 /* PCI slot has been reset */
539 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
540
541 /* Device driver may resume normal operations */
542 void (*resume)(struct pci_dev *dev);
543 };
544
545 /* ---------------------------------------------------------------- */
546
547 struct module;
548 struct pci_driver {
549 struct list_head node;
550 const char *name;
551 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
552 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
553 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
554 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
555 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
556 int (*resume_early) (struct pci_dev *dev);
557 int (*resume) (struct pci_dev *dev); /* Device woken up */
558 void (*shutdown) (struct pci_dev *dev);
559 struct pci_error_handlers *err_handler;
560 struct device_driver driver;
561 struct pci_dynids dynids;
562 };
563
564 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
565
566 /**
567 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
568 * @_table: device table name
569 *
570 * This macro is used to create a struct pci_device_id array (a device table)
571 * in a generic manner.
572 */
573 #define DEFINE_PCI_DEVICE_TABLE(_table) \
574 const struct pci_device_id _table[] __devinitconst
575
576 /**
577 * PCI_DEVICE - macro used to describe a specific pci device
578 * @vend: the 16 bit PCI Vendor ID
579 * @dev: the 16 bit PCI Device ID
580 *
581 * This macro is used to create a struct pci_device_id that matches a
582 * specific device. The subvendor and subdevice fields will be set to
583 * PCI_ANY_ID.
584 */
585 #define PCI_DEVICE(vend,dev) \
586 .vendor = (vend), .device = (dev), \
587 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
588
589 /**
590 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
591 * @dev_class: the class, subclass, prog-if triple for this device
592 * @dev_class_mask: the class mask for this device
593 *
594 * This macro is used to create a struct pci_device_id that matches a
595 * specific PCI class. The vendor, device, subvendor, and subdevice
596 * fields will be set to PCI_ANY_ID.
597 */
598 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
599 .class = (dev_class), .class_mask = (dev_class_mask), \
600 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
601 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
602
603 /**
604 * PCI_VDEVICE - macro used to describe a specific pci device in short form
605 * @vendor: the vendor name
606 * @device: the 16 bit PCI Device ID
607 *
608 * This macro is used to create a struct pci_device_id that matches a
609 * specific PCI device. The subvendor, and subdevice fields will be set
610 * to PCI_ANY_ID. The macro allows the next field to follow as the device
611 * private data.
612 */
613
614 #define PCI_VDEVICE(vendor, device) \
615 PCI_VENDOR_ID_##vendor, (device), \
616 PCI_ANY_ID, PCI_ANY_ID, 0, 0
617
618 /* these external functions are only available when PCI support is enabled */
619 #ifdef CONFIG_PCI
620
621 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
622
623 enum pcie_bus_config_types {
624 PCIE_BUS_TUNE_OFF,
625 PCIE_BUS_SAFE,
626 PCIE_BUS_PERFORMANCE,
627 PCIE_BUS_PEER2PEER,
628 };
629
630 extern enum pcie_bus_config_types pcie_bus_config;
631
632 extern struct bus_type pci_bus_type;
633
634 /* Do NOT directly access these two variables, unless you are arch specific pci
635 * code, or pci core code. */
636 extern struct list_head pci_root_buses; /* list of all known PCI buses */
637 /* Some device drivers need know if pci is initiated */
638 extern int no_pci_devices(void);
639
640 void pcibios_fixup_bus(struct pci_bus *);
641 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
642 char *pcibios_setup(char *str);
643
644 /* Used only when drivers/pci/setup.c is used */
645 resource_size_t pcibios_align_resource(void *, const struct resource *,
646 resource_size_t,
647 resource_size_t);
648 void pcibios_update_irq(struct pci_dev *, int irq);
649
650 /* Weak but can be overriden by arch */
651 void pci_fixup_cardbus(struct pci_bus *);
652
653 /* Generic PCI functions used internally */
654
655 void pcibios_scan_specific_bus(int busn);
656 extern struct pci_bus *pci_find_bus(int domain, int busnr);
657 void pci_bus_add_devices(const struct pci_bus *bus);
658 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
659 struct pci_ops *ops, void *sysdata);
660 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
661 void *sysdata)
662 {
663 struct pci_bus *root_bus;
664 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
665 if (root_bus)
666 pci_bus_add_devices(root_bus);
667 return root_bus;
668 }
669 struct pci_bus *pci_create_bus(struct device *parent, int bus,
670 struct pci_ops *ops, void *sysdata);
671 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
672 int busnr);
673 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
674 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
675 const char *name,
676 struct hotplug_slot *hotplug);
677 void pci_destroy_slot(struct pci_slot *slot);
678 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
679 int pci_scan_slot(struct pci_bus *bus, int devfn);
680 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
681 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
682 unsigned int pci_scan_child_bus(struct pci_bus *bus);
683 int __must_check pci_bus_add_device(struct pci_dev *dev);
684 void pci_read_bridge_bases(struct pci_bus *child);
685 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
686 struct resource *res);
687 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
688 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
689 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
690 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
691 extern void pci_dev_put(struct pci_dev *dev);
692 extern void pci_remove_bus(struct pci_bus *b);
693 extern void pci_remove_bus_device(struct pci_dev *dev);
694 extern void pci_stop_bus_device(struct pci_dev *dev);
695 void pci_setup_cardbus(struct pci_bus *bus);
696 extern void pci_sort_breadthfirst(void);
697 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
698 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
699 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
700
701 /* Generic PCI functions exported to card drivers */
702
703 enum pci_lost_interrupt_reason {
704 PCI_LOST_IRQ_NO_INFORMATION = 0,
705 PCI_LOST_IRQ_DISABLE_MSI,
706 PCI_LOST_IRQ_DISABLE_MSIX,
707 PCI_LOST_IRQ_DISABLE_ACPI,
708 };
709 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
710 int pci_find_capability(struct pci_dev *dev, int cap);
711 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
712 int pci_find_ext_capability(struct pci_dev *dev, int cap);
713 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
714 int cap);
715 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
716 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
717 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
718
719 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
720 struct pci_dev *from);
721 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
722 unsigned int ss_vendor, unsigned int ss_device,
723 struct pci_dev *from);
724 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
725 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
726 unsigned int devfn);
727 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
728 unsigned int devfn)
729 {
730 return pci_get_domain_bus_and_slot(0, bus, devfn);
731 }
732 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
733 int pci_dev_present(const struct pci_device_id *ids);
734
735 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
736 int where, u8 *val);
737 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
738 int where, u16 *val);
739 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
740 int where, u32 *val);
741 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
742 int where, u8 val);
743 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
744 int where, u16 val);
745 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
746 int where, u32 val);
747 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
748
749 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
750 {
751 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
752 }
753 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
754 {
755 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
756 }
757 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
758 u32 *val)
759 {
760 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
761 }
762 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
763 {
764 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
765 }
766 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
767 {
768 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
769 }
770 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
771 u32 val)
772 {
773 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
774 }
775
776 int __must_check pci_enable_device(struct pci_dev *dev);
777 int __must_check pci_enable_device_io(struct pci_dev *dev);
778 int __must_check pci_enable_device_mem(struct pci_dev *dev);
779 int __must_check pci_reenable_device(struct pci_dev *);
780 int __must_check pcim_enable_device(struct pci_dev *pdev);
781 void pcim_pin_device(struct pci_dev *pdev);
782
783 static inline int pci_is_enabled(struct pci_dev *pdev)
784 {
785 return (atomic_read(&pdev->enable_cnt) > 0);
786 }
787
788 static inline int pci_is_managed(struct pci_dev *pdev)
789 {
790 return pdev->is_managed;
791 }
792
793 void pci_disable_device(struct pci_dev *dev);
794 void pci_set_master(struct pci_dev *dev);
795 void pci_clear_master(struct pci_dev *dev);
796 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
797 int pci_set_cacheline_size(struct pci_dev *dev);
798 #define HAVE_PCI_SET_MWI
799 int __must_check pci_set_mwi(struct pci_dev *dev);
800 int pci_try_set_mwi(struct pci_dev *dev);
801 void pci_clear_mwi(struct pci_dev *dev);
802 void pci_intx(struct pci_dev *dev, int enable);
803 void pci_msi_off(struct pci_dev *dev);
804 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
805 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
806 int pcix_get_max_mmrbc(struct pci_dev *dev);
807 int pcix_get_mmrbc(struct pci_dev *dev);
808 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
809 int pcie_get_readrq(struct pci_dev *dev);
810 int pcie_set_readrq(struct pci_dev *dev, int rq);
811 int pcie_get_mps(struct pci_dev *dev);
812 int pcie_set_mps(struct pci_dev *dev, int mps);
813 int __pci_reset_function(struct pci_dev *dev);
814 int pci_reset_function(struct pci_dev *dev);
815 void pci_update_resource(struct pci_dev *dev, int resno);
816 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
817 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
818 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
819
820 /* ROM control related routines */
821 int pci_enable_rom(struct pci_dev *pdev);
822 void pci_disable_rom(struct pci_dev *pdev);
823 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
824 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
825 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
826
827 /* Power management related routines */
828 int pci_save_state(struct pci_dev *dev);
829 void pci_restore_state(struct pci_dev *dev);
830 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
831 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
832 int pci_load_and_free_saved_state(struct pci_dev *dev,
833 struct pci_saved_state **state);
834 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
835 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
836 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
837 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
838 void pci_pme_active(struct pci_dev *dev, bool enable);
839 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
840 bool runtime, bool enable);
841 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
842 pci_power_t pci_target_state(struct pci_dev *dev);
843 int pci_prepare_to_sleep(struct pci_dev *dev);
844 int pci_back_from_sleep(struct pci_dev *dev);
845 bool pci_dev_run_wake(struct pci_dev *dev);
846 bool pci_check_pme_status(struct pci_dev *dev);
847 void pci_pme_wakeup_bus(struct pci_bus *bus);
848
849 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
850 bool enable)
851 {
852 return __pci_enable_wake(dev, state, false, enable);
853 }
854
855 #define PCI_EXP_IDO_REQUEST (1<<0)
856 #define PCI_EXP_IDO_COMPLETION (1<<1)
857 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
858 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
859
860 enum pci_obff_signal_type {
861 PCI_EXP_OBFF_SIGNAL_L0 = 0,
862 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
863 };
864 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
865 void pci_disable_obff(struct pci_dev *dev);
866
867 bool pci_ltr_supported(struct pci_dev *dev);
868 int pci_enable_ltr(struct pci_dev *dev);
869 void pci_disable_ltr(struct pci_dev *dev);
870 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
871
872 /* For use by arch with custom probe code */
873 void set_pcie_port_type(struct pci_dev *pdev);
874 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
875
876 /* Functions for PCI Hotplug drivers to use */
877 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
878 #ifdef CONFIG_HOTPLUG
879 unsigned int pci_rescan_bus(struct pci_bus *bus);
880 #endif
881
882 /* Vital product data routines */
883 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
884 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
885 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
886
887 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
888 void pci_bus_assign_resources(const struct pci_bus *bus);
889 void pci_bus_size_bridges(struct pci_bus *bus);
890 int pci_claim_resource(struct pci_dev *, int);
891 void pci_assign_unassigned_resources(void);
892 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
893 void pdev_enable_device(struct pci_dev *);
894 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
895 int pci_enable_resources(struct pci_dev *, int mask);
896 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
897 int (*)(const struct pci_dev *, u8, u8));
898 #define HAVE_PCI_REQ_REGIONS 2
899 int __must_check pci_request_regions(struct pci_dev *, const char *);
900 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
901 void pci_release_regions(struct pci_dev *);
902 int __must_check pci_request_region(struct pci_dev *, int, const char *);
903 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
904 void pci_release_region(struct pci_dev *, int);
905 int pci_request_selected_regions(struct pci_dev *, int, const char *);
906 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
907 void pci_release_selected_regions(struct pci_dev *, int);
908
909 /* drivers/pci/bus.c */
910 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
911 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
912 void pci_bus_remove_resources(struct pci_bus *bus);
913
914 #define pci_bus_for_each_resource(bus, res, i) \
915 for (i = 0; \
916 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
917 i++)
918
919 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
920 struct resource *res, resource_size_t size,
921 resource_size_t align, resource_size_t min,
922 unsigned int type_mask,
923 resource_size_t (*alignf)(void *,
924 const struct resource *,
925 resource_size_t,
926 resource_size_t),
927 void *alignf_data);
928 void pci_enable_bridges(struct pci_bus *bus);
929
930 /* Proper probing supporting hot-pluggable devices */
931 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
932 const char *mod_name);
933
934 /*
935 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
936 */
937 #define pci_register_driver(driver) \
938 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
939
940 void pci_unregister_driver(struct pci_driver *dev);
941 void pci_remove_behind_bridge(struct pci_dev *dev);
942 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
943 int pci_add_dynid(struct pci_driver *drv,
944 unsigned int vendor, unsigned int device,
945 unsigned int subvendor, unsigned int subdevice,
946 unsigned int class, unsigned int class_mask,
947 unsigned long driver_data);
948 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
949 struct pci_dev *dev);
950 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
951 int pass);
952
953 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
954 void *userdata);
955 int pci_cfg_space_size_ext(struct pci_dev *dev);
956 int pci_cfg_space_size(struct pci_dev *dev);
957 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
958
959 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
960 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
961
962 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
963 unsigned int command_bits, u32 flags);
964 /* kmem_cache style wrapper around pci_alloc_consistent() */
965
966 #include <linux/pci-dma.h>
967 #include <linux/dmapool.h>
968
969 #define pci_pool dma_pool
970 #define pci_pool_create(name, pdev, size, align, allocation) \
971 dma_pool_create(name, &pdev->dev, size, align, allocation)
972 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
973 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
974 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
975
976 enum pci_dma_burst_strategy {
977 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
978 strategy_parameter is N/A */
979 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
980 byte boundaries */
981 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
982 strategy_parameter byte boundaries */
983 };
984
985 struct msix_entry {
986 u32 vector; /* kernel uses to write allocated vector */
987 u16 entry; /* driver uses to specify entry, OS writes */
988 };
989
990
991 #ifndef CONFIG_PCI_MSI
992 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
993 {
994 return -1;
995 }
996
997 static inline void pci_msi_shutdown(struct pci_dev *dev)
998 { }
999 static inline void pci_disable_msi(struct pci_dev *dev)
1000 { }
1001
1002 static inline int pci_msix_table_size(struct pci_dev *dev)
1003 {
1004 return 0;
1005 }
1006 static inline int pci_enable_msix(struct pci_dev *dev,
1007 struct msix_entry *entries, int nvec)
1008 {
1009 return -1;
1010 }
1011
1012 static inline void pci_msix_shutdown(struct pci_dev *dev)
1013 { }
1014 static inline void pci_disable_msix(struct pci_dev *dev)
1015 { }
1016
1017 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1018 { }
1019
1020 static inline void pci_restore_msi_state(struct pci_dev *dev)
1021 { }
1022 static inline int pci_msi_enabled(void)
1023 {
1024 return 0;
1025 }
1026 #else
1027 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1028 extern void pci_msi_shutdown(struct pci_dev *dev);
1029 extern void pci_disable_msi(struct pci_dev *dev);
1030 extern int pci_msix_table_size(struct pci_dev *dev);
1031 extern int pci_enable_msix(struct pci_dev *dev,
1032 struct msix_entry *entries, int nvec);
1033 extern void pci_msix_shutdown(struct pci_dev *dev);
1034 extern void pci_disable_msix(struct pci_dev *dev);
1035 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1036 extern void pci_restore_msi_state(struct pci_dev *dev);
1037 extern int pci_msi_enabled(void);
1038 #endif
1039
1040 #ifdef CONFIG_PCIEPORTBUS
1041 extern bool pcie_ports_disabled;
1042 extern bool pcie_ports_auto;
1043 #else
1044 #define pcie_ports_disabled true
1045 #define pcie_ports_auto false
1046 #endif
1047
1048 #ifndef CONFIG_PCIEASPM
1049 static inline int pcie_aspm_enabled(void) { return 0; }
1050 static inline bool pcie_aspm_support_enabled(void) { return false; }
1051 #else
1052 extern int pcie_aspm_enabled(void);
1053 extern bool pcie_aspm_support_enabled(void);
1054 #endif
1055
1056 #ifdef CONFIG_PCIEAER
1057 void pci_no_aer(void);
1058 bool pci_aer_available(void);
1059 #else
1060 static inline void pci_no_aer(void) { }
1061 static inline bool pci_aer_available(void) { return false; }
1062 #endif
1063
1064 #ifndef CONFIG_PCIE_ECRC
1065 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1066 {
1067 return;
1068 }
1069 static inline void pcie_ecrc_get_policy(char *str) {};
1070 #else
1071 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1072 extern void pcie_ecrc_get_policy(char *str);
1073 #endif
1074
1075 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1076
1077 #ifdef CONFIG_HT_IRQ
1078 /* The functions a driver should call */
1079 int ht_create_irq(struct pci_dev *dev, int idx);
1080 void ht_destroy_irq(unsigned int irq);
1081 #endif /* CONFIG_HT_IRQ */
1082
1083 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1084 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1085
1086 /*
1087 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1088 * a PCI domain is defined to be a set of PCI busses which share
1089 * configuration space.
1090 */
1091 #ifdef CONFIG_PCI_DOMAINS
1092 extern int pci_domains_supported;
1093 #else
1094 enum { pci_domains_supported = 0 };
1095 static inline int pci_domain_nr(struct pci_bus *bus)
1096 {
1097 return 0;
1098 }
1099
1100 static inline int pci_proc_domain(struct pci_bus *bus)
1101 {
1102 return 0;
1103 }
1104 #endif /* CONFIG_PCI_DOMAINS */
1105
1106 /* some architectures require additional setup to direct VGA traffic */
1107 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1108 unsigned int command_bits, u32 flags);
1109 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1110
1111 #else /* CONFIG_PCI is not enabled */
1112
1113 /*
1114 * If the system does not have PCI, clearly these return errors. Define
1115 * these as simple inline functions to avoid hair in drivers.
1116 */
1117
1118 #define _PCI_NOP(o, s, t) \
1119 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1120 int where, t val) \
1121 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1122
1123 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1124 _PCI_NOP(o, word, u16 x) \
1125 _PCI_NOP(o, dword, u32 x)
1126 _PCI_NOP_ALL(read, *)
1127 _PCI_NOP_ALL(write,)
1128
1129 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1130 unsigned int device,
1131 struct pci_dev *from)
1132 {
1133 return NULL;
1134 }
1135
1136 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1137 unsigned int device,
1138 unsigned int ss_vendor,
1139 unsigned int ss_device,
1140 struct pci_dev *from)
1141 {
1142 return NULL;
1143 }
1144
1145 static inline struct pci_dev *pci_get_class(unsigned int class,
1146 struct pci_dev *from)
1147 {
1148 return NULL;
1149 }
1150
1151 #define pci_dev_present(ids) (0)
1152 #define no_pci_devices() (1)
1153 #define pci_dev_put(dev) do { } while (0)
1154
1155 static inline void pci_set_master(struct pci_dev *dev)
1156 { }
1157
1158 static inline int pci_enable_device(struct pci_dev *dev)
1159 {
1160 return -EIO;
1161 }
1162
1163 static inline void pci_disable_device(struct pci_dev *dev)
1164 { }
1165
1166 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1167 {
1168 return -EIO;
1169 }
1170
1171 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1172 {
1173 return -EIO;
1174 }
1175
1176 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1177 unsigned int size)
1178 {
1179 return -EIO;
1180 }
1181
1182 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1183 unsigned long mask)
1184 {
1185 return -EIO;
1186 }
1187
1188 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1189 {
1190 return -EBUSY;
1191 }
1192
1193 static inline int __pci_register_driver(struct pci_driver *drv,
1194 struct module *owner)
1195 {
1196 return 0;
1197 }
1198
1199 static inline int pci_register_driver(struct pci_driver *drv)
1200 {
1201 return 0;
1202 }
1203
1204 static inline void pci_unregister_driver(struct pci_driver *drv)
1205 { }
1206
1207 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1208 {
1209 return 0;
1210 }
1211
1212 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1213 int cap)
1214 {
1215 return 0;
1216 }
1217
1218 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1219 {
1220 return 0;
1221 }
1222
1223 /* Power management related routines */
1224 static inline int pci_save_state(struct pci_dev *dev)
1225 {
1226 return 0;
1227 }
1228
1229 static inline void pci_restore_state(struct pci_dev *dev)
1230 { }
1231
1232 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1233 {
1234 return 0;
1235 }
1236
1237 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1238 {
1239 return 0;
1240 }
1241
1242 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1243 pm_message_t state)
1244 {
1245 return PCI_D0;
1246 }
1247
1248 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1249 int enable)
1250 {
1251 return 0;
1252 }
1253
1254 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1255 {
1256 }
1257
1258 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1259 {
1260 }
1261
1262 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1263 {
1264 return 0;
1265 }
1266
1267 static inline void pci_disable_obff(struct pci_dev *dev)
1268 {
1269 }
1270
1271 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1272 {
1273 return -EIO;
1274 }
1275
1276 static inline void pci_release_regions(struct pci_dev *dev)
1277 { }
1278
1279 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1280
1281 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1282 { }
1283
1284 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1285 { }
1286
1287 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1288 { return NULL; }
1289
1290 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1291 unsigned int devfn)
1292 { return NULL; }
1293
1294 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1295 unsigned int devfn)
1296 { return NULL; }
1297
1298 static inline int pci_domain_nr(struct pci_bus *bus)
1299 { return 0; }
1300
1301 #define dev_is_pci(d) (false)
1302 #define dev_is_pf(d) (false)
1303 #define dev_num_vf(d) (0)
1304 #endif /* CONFIG_PCI */
1305
1306 /* Include architecture-dependent settings and functions */
1307
1308 #include <asm/pci.h>
1309
1310 #ifndef PCIBIOS_MAX_MEM_32
1311 #define PCIBIOS_MAX_MEM_32 (-1)
1312 #endif
1313
1314 /* these helpers provide future and backwards compatibility
1315 * for accessing popular PCI BAR info */
1316 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1317 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1318 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1319 #define pci_resource_len(dev,bar) \
1320 ((pci_resource_start((dev), (bar)) == 0 && \
1321 pci_resource_end((dev), (bar)) == \
1322 pci_resource_start((dev), (bar))) ? 0 : \
1323 \
1324 (pci_resource_end((dev), (bar)) - \
1325 pci_resource_start((dev), (bar)) + 1))
1326
1327 /* Similar to the helpers above, these manipulate per-pci_dev
1328 * driver-specific data. They are really just a wrapper around
1329 * the generic device structure functions of these calls.
1330 */
1331 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1332 {
1333 return dev_get_drvdata(&pdev->dev);
1334 }
1335
1336 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1337 {
1338 dev_set_drvdata(&pdev->dev, data);
1339 }
1340
1341 /* If you want to know what to call your pci_dev, ask this function.
1342 * Again, it's a wrapper around the generic device.
1343 */
1344 static inline const char *pci_name(const struct pci_dev *pdev)
1345 {
1346 return dev_name(&pdev->dev);
1347 }
1348
1349
1350 /* Some archs don't want to expose struct resource to userland as-is
1351 * in sysfs and /proc
1352 */
1353 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1354 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1355 const struct resource *rsrc, resource_size_t *start,
1356 resource_size_t *end)
1357 {
1358 *start = rsrc->start;
1359 *end = rsrc->end;
1360 }
1361 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1362
1363
1364 /*
1365 * The world is not perfect and supplies us with broken PCI devices.
1366 * For at least a part of these bugs we need a work-around, so both
1367 * generic (drivers/pci/quirks.c) and per-architecture code can define
1368 * fixup hooks to be called for particular buggy devices.
1369 */
1370
1371 struct pci_fixup {
1372 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1373 void (*hook)(struct pci_dev *dev);
1374 };
1375
1376 enum pci_fixup_pass {
1377 pci_fixup_early, /* Before probing BARs */
1378 pci_fixup_header, /* After reading configuration header */
1379 pci_fixup_final, /* Final phase of device fixups */
1380 pci_fixup_enable, /* pci_enable_device() time */
1381 pci_fixup_resume, /* pci_device_resume() */
1382 pci_fixup_suspend, /* pci_device_suspend */
1383 pci_fixup_resume_early, /* pci_device_resume_early() */
1384 };
1385
1386 /* Anonymous variables would be nice... */
1387 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1388 static const struct pci_fixup __pci_fixup_##name __used \
1389 __attribute__((__section__(#section))) = { vendor, device, hook };
1390 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1391 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1392 vendor##device##hook, vendor, device, hook)
1393 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1394 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1395 vendor##device##hook, vendor, device, hook)
1396 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1397 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1398 vendor##device##hook, vendor, device, hook)
1399 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1400 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1401 vendor##device##hook, vendor, device, hook)
1402 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1403 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1404 resume##vendor##device##hook, vendor, device, hook)
1405 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1406 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1407 resume_early##vendor##device##hook, vendor, device, hook)
1408 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1409 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1410 suspend##vendor##device##hook, vendor, device, hook)
1411
1412 #ifdef CONFIG_PCI_QUIRKS
1413 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1414 #else
1415 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1416 struct pci_dev *dev) {}
1417 #endif
1418
1419 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1420 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1421 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1422 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1423 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1424 const char *name);
1425 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1426
1427 extern int pci_pci_problems;
1428 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1429 #define PCIPCI_TRITON 2
1430 #define PCIPCI_NATOMA 4
1431 #define PCIPCI_VIAETBF 8
1432 #define PCIPCI_VSFX 16
1433 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1434 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1435
1436 extern unsigned long pci_cardbus_io_size;
1437 extern unsigned long pci_cardbus_mem_size;
1438 extern u8 __devinitdata pci_dfl_cache_line_size;
1439 extern u8 pci_cache_line_size;
1440
1441 extern unsigned long pci_hotplug_io_size;
1442 extern unsigned long pci_hotplug_mem_size;
1443
1444 int pcibios_add_platform_entries(struct pci_dev *dev);
1445 void pcibios_disable_device(struct pci_dev *dev);
1446 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1447 enum pcie_reset_state state);
1448
1449 #ifdef CONFIG_PCI_MMCONFIG
1450 extern void __init pci_mmcfg_early_init(void);
1451 extern void __init pci_mmcfg_late_init(void);
1452 #else
1453 static inline void pci_mmcfg_early_init(void) { }
1454 static inline void pci_mmcfg_late_init(void) { }
1455 #endif
1456
1457 int pci_ext_cfg_avail(struct pci_dev *dev);
1458
1459 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1460
1461 #ifdef CONFIG_PCI_IOV
1462 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1463 extern void pci_disable_sriov(struct pci_dev *dev);
1464 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1465 extern int pci_num_vf(struct pci_dev *dev);
1466 #else
1467 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1468 {
1469 return -ENODEV;
1470 }
1471 static inline void pci_disable_sriov(struct pci_dev *dev)
1472 {
1473 }
1474 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1475 {
1476 return IRQ_NONE;
1477 }
1478 static inline int pci_num_vf(struct pci_dev *dev)
1479 {
1480 return 0;
1481 }
1482 #endif
1483
1484 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1485 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1486 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1487 #endif
1488
1489 /**
1490 * pci_pcie_cap - get the saved PCIe capability offset
1491 * @dev: PCI device
1492 *
1493 * PCIe capability offset is calculated at PCI device initialization
1494 * time and saved in the data structure. This function returns saved
1495 * PCIe capability offset. Using this instead of pci_find_capability()
1496 * reduces unnecessary search in the PCI configuration space. If you
1497 * need to calculate PCIe capability offset from raw device for some
1498 * reasons, please use pci_find_capability() instead.
1499 */
1500 static inline int pci_pcie_cap(struct pci_dev *dev)
1501 {
1502 return dev->pcie_cap;
1503 }
1504
1505 /**
1506 * pci_is_pcie - check if the PCI device is PCI Express capable
1507 * @dev: PCI device
1508 *
1509 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1510 */
1511 static inline bool pci_is_pcie(struct pci_dev *dev)
1512 {
1513 return !!pci_pcie_cap(dev);
1514 }
1515
1516 void pci_request_acs(void);
1517
1518
1519 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1520 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1521
1522 /* Large Resource Data Type Tag Item Names */
1523 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1524 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1525 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1526
1527 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1528 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1529 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1530
1531 /* Small Resource Data Type Tag Item Names */
1532 #define PCI_VPD_STIN_END 0x78 /* End */
1533
1534 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1535
1536 #define PCI_VPD_SRDT_TIN_MASK 0x78
1537 #define PCI_VPD_SRDT_LEN_MASK 0x07
1538
1539 #define PCI_VPD_LRDT_TAG_SIZE 3
1540 #define PCI_VPD_SRDT_TAG_SIZE 1
1541
1542 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1543
1544 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1545 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1546 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1547 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1548
1549 /**
1550 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1551 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1552 *
1553 * Returns the extracted Large Resource Data Type length.
1554 */
1555 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1556 {
1557 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1558 }
1559
1560 /**
1561 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1562 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1563 *
1564 * Returns the extracted Small Resource Data Type length.
1565 */
1566 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1567 {
1568 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1569 }
1570
1571 /**
1572 * pci_vpd_info_field_size - Extracts the information field length
1573 * @lrdt: Pointer to the beginning of an information field header
1574 *
1575 * Returns the extracted information field length.
1576 */
1577 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1578 {
1579 return info_field[2];
1580 }
1581
1582 /**
1583 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1584 * @buf: Pointer to buffered vpd data
1585 * @off: The offset into the buffer at which to begin the search
1586 * @len: The length of the vpd buffer
1587 * @rdt: The Resource Data Type to search for
1588 *
1589 * Returns the index where the Resource Data Type was found or
1590 * -ENOENT otherwise.
1591 */
1592 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1593
1594 /**
1595 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1596 * @buf: Pointer to buffered vpd data
1597 * @off: The offset into the buffer at which to begin the search
1598 * @len: The length of the buffer area, relative to off, in which to search
1599 * @kw: The keyword to search for
1600 *
1601 * Returns the index where the information field keyword was found or
1602 * -ENOENT otherwise.
1603 */
1604 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1605 unsigned int len, const char *kw);
1606
1607 /* PCI <-> OF binding helpers */
1608 #ifdef CONFIG_OF
1609 struct device_node;
1610 extern void pci_set_of_node(struct pci_dev *dev);
1611 extern void pci_release_of_node(struct pci_dev *dev);
1612 extern void pci_set_bus_of_node(struct pci_bus *bus);
1613 extern void pci_release_bus_of_node(struct pci_bus *bus);
1614
1615 /* Arch may override this (weak) */
1616 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1617
1618 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1619 {
1620 return pdev ? pdev->dev.of_node : NULL;
1621 }
1622
1623 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1624 {
1625 return bus ? bus->dev.of_node : NULL;
1626 }
1627
1628 #else /* CONFIG_OF */
1629 static inline void pci_set_of_node(struct pci_dev *dev) { }
1630 static inline void pci_release_of_node(struct pci_dev *dev) { }
1631 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1632 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1633 #endif /* CONFIG_OF */
1634
1635 /**
1636 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1637 * @pdev: the PCI device
1638 *
1639 * if the device is PCIE, return NULL
1640 * if the device isn't connected to a PCIe bridge (that is its parent is a
1641 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1642 * parent
1643 */
1644 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1645
1646 #endif /* __KERNEL__ */
1647 #endif /* LINUX_PCI_H */
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