PCI: Disable MPS configuration by default
[linux-btrfs-devel.git] / sound / i2c / cs8427.c
blob04ae8704cdcdac72f515ddc94077a99b28b38710
1 /*
2 * Routines for control of the CS8427 via i2c bus
3 * IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/slab.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/bitrev.h>
27 #include <asm/unaligned.h>
28 #include <sound/core.h>
29 #include <sound/control.h>
30 #include <sound/pcm.h>
31 #include <sound/cs8427.h>
32 #include <sound/asoundef.h>
34 static void snd_cs8427_reset(struct snd_i2c_device *cs8427);
36 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
37 MODULE_DESCRIPTION("IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic");
38 MODULE_LICENSE("GPL");
40 #define CS8427_ADDR (0x20>>1) /* fixed address */
42 struct cs8427_stream {
43 struct snd_pcm_substream *substream;
44 char hw_status[24]; /* hardware status */
45 char def_status[24]; /* default status */
46 char pcm_status[24]; /* PCM private status */
47 char hw_udata[32];
48 struct snd_kcontrol *pcm_ctl;
51 struct cs8427 {
52 unsigned char regmap[0x14]; /* map of first 1 + 13 registers */
53 unsigned int rate;
54 unsigned int reset_timeout;
55 struct cs8427_stream playback;
56 struct cs8427_stream capture;
59 int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg,
60 unsigned char val)
62 int err;
63 unsigned char buf[2];
65 buf[0] = reg & 0x7f;
66 buf[1] = val;
67 if ((err = snd_i2c_sendbytes(device, buf, 2)) != 2) {
68 snd_printk(KERN_ERR "unable to send bytes 0x%02x:0x%02x "
69 "to CS8427 (%i)\n", buf[0], buf[1], err);
70 return err < 0 ? err : -EIO;
72 return 0;
75 EXPORT_SYMBOL(snd_cs8427_reg_write);
77 static int snd_cs8427_reg_read(struct snd_i2c_device *device, unsigned char reg)
79 int err;
80 unsigned char buf;
82 if ((err = snd_i2c_sendbytes(device, &reg, 1)) != 1) {
83 snd_printk(KERN_ERR "unable to send register 0x%x byte "
84 "to CS8427\n", reg);
85 return err < 0 ? err : -EIO;
87 if ((err = snd_i2c_readbytes(device, &buf, 1)) != 1) {
88 snd_printk(KERN_ERR "unable to read register 0x%x byte "
89 "from CS8427\n", reg);
90 return err < 0 ? err : -EIO;
92 return buf;
95 static int snd_cs8427_select_corudata(struct snd_i2c_device *device, int udata)
97 struct cs8427 *chip = device->private_data;
98 int err;
100 udata = udata ? CS8427_BSEL : 0;
101 if (udata != (chip->regmap[CS8427_REG_CSDATABUF] & udata)) {
102 chip->regmap[CS8427_REG_CSDATABUF] &= ~CS8427_BSEL;
103 chip->regmap[CS8427_REG_CSDATABUF] |= udata;
104 err = snd_cs8427_reg_write(device, CS8427_REG_CSDATABUF,
105 chip->regmap[CS8427_REG_CSDATABUF]);
106 if (err < 0)
107 return err;
109 return 0;
112 static int snd_cs8427_send_corudata(struct snd_i2c_device *device,
113 int udata,
114 unsigned char *ndata,
115 int count)
117 struct cs8427 *chip = device->private_data;
118 char *hw_data = udata ?
119 chip->playback.hw_udata : chip->playback.hw_status;
120 char data[32];
121 int err, idx;
123 if (!memcmp(hw_data, ndata, count))
124 return 0;
125 if ((err = snd_cs8427_select_corudata(device, udata)) < 0)
126 return err;
127 memcpy(hw_data, ndata, count);
128 if (udata) {
129 memset(data, 0, sizeof(data));
130 if (memcmp(hw_data, data, count) == 0) {
131 chip->regmap[CS8427_REG_UDATABUF] &= ~CS8427_UBMMASK;
132 chip->regmap[CS8427_REG_UDATABUF] |= CS8427_UBMZEROS |
133 CS8427_EFTUI;
134 err = snd_cs8427_reg_write(device, CS8427_REG_UDATABUF,
135 chip->regmap[CS8427_REG_UDATABUF]);
136 return err < 0 ? err : 0;
139 data[0] = CS8427_REG_AUTOINC | CS8427_REG_CORU_DATABUF;
140 for (idx = 0; idx < count; idx++)
141 data[idx + 1] = bitrev8(ndata[idx]);
142 if (snd_i2c_sendbytes(device, data, count + 1) != count + 1)
143 return -EIO;
144 return 1;
147 static void snd_cs8427_free(struct snd_i2c_device *device)
149 kfree(device->private_data);
152 int snd_cs8427_create(struct snd_i2c_bus *bus,
153 unsigned char addr,
154 unsigned int reset_timeout,
155 struct snd_i2c_device **r_cs8427)
157 static unsigned char initvals1[] = {
158 CS8427_REG_CONTROL1 | CS8427_REG_AUTOINC,
159 /* CS8427_REG_CONTROL1: RMCK to OMCK, valid PCM audio, disable mutes,
160 TCBL=output */
161 CS8427_SWCLK | CS8427_TCBLDIR,
162 /* CS8427_REG_CONTROL2: hold last valid audio sample, RMCK=256*Fs,
163 normal stereo operation */
164 0x00,
165 /* CS8427_REG_DATAFLOW: output drivers normal operation, Tx<=serial,
166 Rx=>serial */
167 CS8427_TXDSERIAL | CS8427_SPDAES3RECEIVER,
168 /* CS8427_REG_CLOCKSOURCE: Run off, CMCK=256*Fs,
169 output time base = OMCK, input time base = recovered input clock,
170 recovered input clock source is ILRCK changed to AES3INPUT
171 (workaround, see snd_cs8427_reset) */
172 CS8427_RXDILRCK,
173 /* CS8427_REG_SERIALINPUT: Serial audio input port data format = I2S,
174 24-bit, 64*Fsi */
175 CS8427_SIDEL | CS8427_SILRPOL,
176 /* CS8427_REG_SERIALOUTPUT: Serial audio output port data format
177 = I2S, 24-bit, 64*Fsi */
178 CS8427_SODEL | CS8427_SOLRPOL,
180 static unsigned char initvals2[] = {
181 CS8427_REG_RECVERRMASK | CS8427_REG_AUTOINC,
182 /* CS8427_REG_RECVERRMASK: unmask the input PLL clock, V, confidence,
183 biphase, parity status bits */
184 /* CS8427_UNLOCK | CS8427_V | CS8427_CONF | CS8427_BIP | CS8427_PAR,*/
185 0xff, /* set everything */
186 /* CS8427_REG_CSDATABUF:
187 Registers 32-55 window to CS buffer
188 Inhibit D->E transfers from overwriting first 5 bytes of CS data.
189 Inhibit D->E transfers (all) of CS data.
190 Allow E->F transfer of CS data.
191 One byte mode; both A/B channels get same written CB data.
192 A channel info is output to chip's EMPH* pin. */
193 CS8427_CBMR | CS8427_DETCI,
194 /* CS8427_REG_UDATABUF:
195 Use internal buffer to transmit User (U) data.
196 Chip's U pin is an output.
197 Transmit all O's for user data.
198 Inhibit D->E transfers.
199 Inhibit E->F transfers. */
200 CS8427_UD | CS8427_EFTUI | CS8427_DETUI,
202 int err;
203 struct cs8427 *chip;
204 struct snd_i2c_device *device;
205 unsigned char buf[24];
207 if ((err = snd_i2c_device_create(bus, "CS8427",
208 CS8427_ADDR | (addr & 7),
209 &device)) < 0)
210 return err;
211 chip = device->private_data = kzalloc(sizeof(*chip), GFP_KERNEL);
212 if (chip == NULL) {
213 snd_i2c_device_free(device);
214 return -ENOMEM;
216 device->private_free = snd_cs8427_free;
218 snd_i2c_lock(bus);
219 err = snd_cs8427_reg_read(device, CS8427_REG_ID_AND_VER);
220 if (err != CS8427_VER8427A) {
221 /* give second chance */
222 snd_printk(KERN_WARNING "invalid CS8427 signature 0x%x: "
223 "let me try again...\n", err);
224 err = snd_cs8427_reg_read(device, CS8427_REG_ID_AND_VER);
226 if (err != CS8427_VER8427A) {
227 snd_i2c_unlock(bus);
228 snd_printk(KERN_ERR "unable to find CS8427 signature "
229 "(expected 0x%x, read 0x%x),\n",
230 CS8427_VER8427A, err);
231 snd_printk(KERN_ERR " initialization is not completed\n");
232 return -EFAULT;
234 /* turn off run bit while making changes to configuration */
235 err = snd_cs8427_reg_write(device, CS8427_REG_CLOCKSOURCE, 0x00);
236 if (err < 0)
237 goto __fail;
238 /* send initial values */
239 memcpy(chip->regmap + (initvals1[0] & 0x7f), initvals1 + 1, 6);
240 if ((err = snd_i2c_sendbytes(device, initvals1, 7)) != 7) {
241 err = err < 0 ? err : -EIO;
242 goto __fail;
244 /* Turn off CS8427 interrupt stuff that is not used in hardware */
245 memset(buf, 0, 7);
246 /* from address 9 to 15 */
247 buf[0] = 9; /* register */
248 if ((err = snd_i2c_sendbytes(device, buf, 7)) != 7)
249 goto __fail;
250 /* send transfer initialization sequence */
251 memcpy(chip->regmap + (initvals2[0] & 0x7f), initvals2 + 1, 3);
252 if ((err = snd_i2c_sendbytes(device, initvals2, 4)) != 4) {
253 err = err < 0 ? err : -EIO;
254 goto __fail;
256 /* write default channel status bytes */
257 put_unaligned_le32(SNDRV_PCM_DEFAULT_CON_SPDIF, buf);
258 memset(buf + 4, 0, 24 - 4);
259 if (snd_cs8427_send_corudata(device, 0, buf, 24) < 0)
260 goto __fail;
261 memcpy(chip->playback.def_status, buf, 24);
262 memcpy(chip->playback.pcm_status, buf, 24);
263 snd_i2c_unlock(bus);
265 /* turn on run bit and rock'n'roll */
266 if (reset_timeout < 1)
267 reset_timeout = 1;
268 chip->reset_timeout = reset_timeout;
269 snd_cs8427_reset(device);
271 #if 0 // it's nice for read tests
273 char buf[128];
274 int xx;
275 buf[0] = 0x81;
276 snd_i2c_sendbytes(device, buf, 1);
277 snd_i2c_readbytes(device, buf, 127);
278 for (xx = 0; xx < 127; xx++)
279 printk(KERN_DEBUG "reg[0x%x] = 0x%x\n", xx+1, buf[xx]);
281 #endif
283 if (r_cs8427)
284 *r_cs8427 = device;
285 return 0;
287 __fail:
288 snd_i2c_unlock(bus);
289 snd_i2c_device_free(device);
290 return err < 0 ? err : -EIO;
293 EXPORT_SYMBOL(snd_cs8427_create);
296 * Reset the chip using run bit, also lock PLL using ILRCK and
297 * put back AES3INPUT. This workaround is described in latest
298 * CS8427 datasheet, otherwise TXDSERIAL will not work.
300 static void snd_cs8427_reset(struct snd_i2c_device *cs8427)
302 struct cs8427 *chip;
303 unsigned long end_time;
304 int data, aes3input = 0;
306 if (snd_BUG_ON(!cs8427))
307 return;
308 chip = cs8427->private_data;
309 snd_i2c_lock(cs8427->bus);
310 if ((chip->regmap[CS8427_REG_CLOCKSOURCE] & CS8427_RXDAES3INPUT) ==
311 CS8427_RXDAES3INPUT) /* AES3 bit is set */
312 aes3input = 1;
313 chip->regmap[CS8427_REG_CLOCKSOURCE] &= ~(CS8427_RUN | CS8427_RXDMASK);
314 snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
315 chip->regmap[CS8427_REG_CLOCKSOURCE]);
316 udelay(200);
317 chip->regmap[CS8427_REG_CLOCKSOURCE] |= CS8427_RUN | CS8427_RXDILRCK;
318 snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
319 chip->regmap[CS8427_REG_CLOCKSOURCE]);
320 udelay(200);
321 snd_i2c_unlock(cs8427->bus);
322 end_time = jiffies + chip->reset_timeout;
323 while (time_after_eq(end_time, jiffies)) {
324 snd_i2c_lock(cs8427->bus);
325 data = snd_cs8427_reg_read(cs8427, CS8427_REG_RECVERRORS);
326 snd_i2c_unlock(cs8427->bus);
327 if (!(data & CS8427_UNLOCK))
328 break;
329 schedule_timeout_uninterruptible(1);
331 snd_i2c_lock(cs8427->bus);
332 chip->regmap[CS8427_REG_CLOCKSOURCE] &= ~CS8427_RXDMASK;
333 if (aes3input)
334 chip->regmap[CS8427_REG_CLOCKSOURCE] |= CS8427_RXDAES3INPUT;
335 snd_cs8427_reg_write(cs8427, CS8427_REG_CLOCKSOURCE,
336 chip->regmap[CS8427_REG_CLOCKSOURCE]);
337 snd_i2c_unlock(cs8427->bus);
340 static int snd_cs8427_in_status_info(struct snd_kcontrol *kcontrol,
341 struct snd_ctl_elem_info *uinfo)
343 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
344 uinfo->count = 1;
345 uinfo->value.integer.min = 0;
346 uinfo->value.integer.max = 255;
347 return 0;
350 static int snd_cs8427_in_status_get(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
353 struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
354 int data;
356 snd_i2c_lock(device->bus);
357 data = snd_cs8427_reg_read(device, kcontrol->private_value);
358 snd_i2c_unlock(device->bus);
359 if (data < 0)
360 return data;
361 ucontrol->value.integer.value[0] = data;
362 return 0;
365 static int snd_cs8427_qsubcode_info(struct snd_kcontrol *kcontrol,
366 struct snd_ctl_elem_info *uinfo)
368 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
369 uinfo->count = 10;
370 return 0;
373 static int snd_cs8427_qsubcode_get(struct snd_kcontrol *kcontrol,
374 struct snd_ctl_elem_value *ucontrol)
376 struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
377 unsigned char reg = CS8427_REG_QSUBCODE;
378 int err;
380 snd_i2c_lock(device->bus);
381 if ((err = snd_i2c_sendbytes(device, &reg, 1)) != 1) {
382 snd_printk(KERN_ERR "unable to send register 0x%x byte "
383 "to CS8427\n", reg);
384 snd_i2c_unlock(device->bus);
385 return err < 0 ? err : -EIO;
387 err = snd_i2c_readbytes(device, ucontrol->value.bytes.data, 10);
388 if (err != 10) {
389 snd_printk(KERN_ERR "unable to read Q-subcode bytes "
390 "from CS8427\n");
391 snd_i2c_unlock(device->bus);
392 return err < 0 ? err : -EIO;
394 snd_i2c_unlock(device->bus);
395 return 0;
398 static int snd_cs8427_spdif_info(struct snd_kcontrol *kcontrol,
399 struct snd_ctl_elem_info *uinfo)
401 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
402 uinfo->count = 1;
403 return 0;
406 static int snd_cs8427_spdif_get(struct snd_kcontrol *kcontrol,
407 struct snd_ctl_elem_value *ucontrol)
409 struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
410 struct cs8427 *chip = device->private_data;
412 snd_i2c_lock(device->bus);
413 memcpy(ucontrol->value.iec958.status, chip->playback.def_status, 24);
414 snd_i2c_unlock(device->bus);
415 return 0;
418 static int snd_cs8427_spdif_put(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
421 struct snd_i2c_device *device = snd_kcontrol_chip(kcontrol);
422 struct cs8427 *chip = device->private_data;
423 unsigned char *status = kcontrol->private_value ?
424 chip->playback.pcm_status : chip->playback.def_status;
425 struct snd_pcm_runtime *runtime = chip->playback.substream ?
426 chip->playback.substream->runtime : NULL;
427 int err, change;
429 snd_i2c_lock(device->bus);
430 change = memcmp(ucontrol->value.iec958.status, status, 24) != 0;
431 memcpy(status, ucontrol->value.iec958.status, 24);
432 if (change && (kcontrol->private_value ?
433 runtime != NULL : runtime == NULL)) {
434 err = snd_cs8427_send_corudata(device, 0, status, 24);
435 if (err < 0)
436 change = err;
438 snd_i2c_unlock(device->bus);
439 return change;
442 static int snd_cs8427_spdif_mask_info(struct snd_kcontrol *kcontrol,
443 struct snd_ctl_elem_info *uinfo)
445 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
446 uinfo->count = 1;
447 return 0;
450 static int snd_cs8427_spdif_mask_get(struct snd_kcontrol *kcontrol,
451 struct snd_ctl_elem_value *ucontrol)
453 memset(ucontrol->value.iec958.status, 0xff, 24);
454 return 0;
457 static struct snd_kcontrol_new snd_cs8427_iec958_controls[] = {
459 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
460 .info = snd_cs8427_in_status_info,
461 .name = "IEC958 CS8427 Input Status",
462 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
463 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
464 .get = snd_cs8427_in_status_get,
465 .private_value = 15,
468 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
469 .info = snd_cs8427_in_status_info,
470 .name = "IEC958 CS8427 Error Status",
471 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
472 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
473 .get = snd_cs8427_in_status_get,
474 .private_value = 16,
477 .access = SNDRV_CTL_ELEM_ACCESS_READ,
478 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
479 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
480 .info = snd_cs8427_spdif_mask_info,
481 .get = snd_cs8427_spdif_mask_get,
484 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
485 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
486 .info = snd_cs8427_spdif_info,
487 .get = snd_cs8427_spdif_get,
488 .put = snd_cs8427_spdif_put,
489 .private_value = 0
492 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
493 SNDRV_CTL_ELEM_ACCESS_INACTIVE),
494 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
495 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
496 .info = snd_cs8427_spdif_info,
497 .get = snd_cs8427_spdif_get,
498 .put = snd_cs8427_spdif_put,
499 .private_value = 1
502 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
503 .info = snd_cs8427_qsubcode_info,
504 .name = "IEC958 Q-subcode Capture Default",
505 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
506 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
507 .get = snd_cs8427_qsubcode_get
510 int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427,
511 struct snd_pcm_substream *play_substream,
512 struct snd_pcm_substream *cap_substream)
514 struct cs8427 *chip = cs8427->private_data;
515 struct snd_kcontrol *kctl;
516 unsigned int idx;
517 int err;
519 if (snd_BUG_ON(!play_substream || !cap_substream))
520 return -EINVAL;
521 for (idx = 0; idx < ARRAY_SIZE(snd_cs8427_iec958_controls); idx++) {
522 kctl = snd_ctl_new1(&snd_cs8427_iec958_controls[idx], cs8427);
523 if (kctl == NULL)
524 return -ENOMEM;
525 kctl->id.device = play_substream->pcm->device;
526 kctl->id.subdevice = play_substream->number;
527 err = snd_ctl_add(cs8427->bus->card, kctl);
528 if (err < 0)
529 return err;
530 if (! strcmp(kctl->id.name,
531 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM)))
532 chip->playback.pcm_ctl = kctl;
535 chip->playback.substream = play_substream;
536 chip->capture.substream = cap_substream;
537 if (snd_BUG_ON(!chip->playback.pcm_ctl))
538 return -EIO;
539 return 0;
542 EXPORT_SYMBOL(snd_cs8427_iec958_build);
544 int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active)
546 struct cs8427 *chip;
548 if (snd_BUG_ON(!cs8427))
549 return -ENXIO;
550 chip = cs8427->private_data;
551 if (active)
552 memcpy(chip->playback.pcm_status,
553 chip->playback.def_status, 24);
554 chip->playback.pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
555 snd_ctl_notify(cs8427->bus->card,
556 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
557 &chip->playback.pcm_ctl->id);
558 return 0;
561 EXPORT_SYMBOL(snd_cs8427_iec958_active);
563 int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate)
565 struct cs8427 *chip;
566 char *status;
567 int err, reset;
569 if (snd_BUG_ON(!cs8427))
570 return -ENXIO;
571 chip = cs8427->private_data;
572 status = chip->playback.pcm_status;
573 snd_i2c_lock(cs8427->bus);
574 if (status[0] & IEC958_AES0_PROFESSIONAL) {
575 status[0] &= ~IEC958_AES0_PRO_FS;
576 switch (rate) {
577 case 32000: status[0] |= IEC958_AES0_PRO_FS_32000; break;
578 case 44100: status[0] |= IEC958_AES0_PRO_FS_44100; break;
579 case 48000: status[0] |= IEC958_AES0_PRO_FS_48000; break;
580 default: status[0] |= IEC958_AES0_PRO_FS_NOTID; break;
582 } else {
583 status[3] &= ~IEC958_AES3_CON_FS;
584 switch (rate) {
585 case 32000: status[3] |= IEC958_AES3_CON_FS_32000; break;
586 case 44100: status[3] |= IEC958_AES3_CON_FS_44100; break;
587 case 48000: status[3] |= IEC958_AES3_CON_FS_48000; break;
590 err = snd_cs8427_send_corudata(cs8427, 0, status, 24);
591 if (err > 0)
592 snd_ctl_notify(cs8427->bus->card,
593 SNDRV_CTL_EVENT_MASK_VALUE,
594 &chip->playback.pcm_ctl->id);
595 reset = chip->rate != rate;
596 chip->rate = rate;
597 snd_i2c_unlock(cs8427->bus);
598 if (reset)
599 snd_cs8427_reset(cs8427);
600 return err < 0 ? err : 0;
603 EXPORT_SYMBOL(snd_cs8427_iec958_pcm);
605 static int __init alsa_cs8427_module_init(void)
607 return 0;
610 static void __exit alsa_cs8427_module_exit(void)
614 module_init(alsa_cs8427_module_init)
615 module_exit(alsa_cs8427_module_exit)