drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37
  38 #define EDAC_MC_LABEL_LEN       31
  39 #define EDAC_DEVICE_NAME_LEN    31
  40 #define EDAC_ATTRIB_VALUE_LEN   15
  41 #define MC_PROC_NAME_MAX_LEN    7
  42
  43 #if PAGE_SHIFT < 20
  44 #define PAGES_TO_MiB(pages)     ((pages) >> (20 - PAGE_SHIFT))
  45 #define MiB_TO_PAGES(mb)        ((mb) << (20 - PAGE_SHIFT))
  46 #else                           /* PAGE_SHIFT > 20 */
  47 #define PAGES_TO_MiB(pages)     ((pages) << (PAGE_SHIFT - 20))
  48 #define MiB_TO_PAGES(mb)        ((mb) >> (PAGE_SHIFT - 20))
  49 #endif
  50
  51 #define edac_printk(level, prefix, fmt, arg...) \
  52         printk(level "EDAC " prefix ": " fmt, ##arg)
  53
  54 #define edac_mc_printk(mci, level, fmt, arg...) \
  55         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  56
  57 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  58         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  59
  60 #define edac_device_printk(ctl, level, fmt, arg...) \
  61         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  62
  63 #define edac_pci_printk(ctl, level, fmt, arg...) \
  64         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  65
  66 /* prefixes for edac_printk() and edac_mc_printk() */
  67 #define EDAC_MC "MC"
  68 #define EDAC_PCI "PCI"
  69 #define EDAC_DEBUG "DEBUG"
  70
  71 extern const char *edac_mem_types[];
  72
  73 #ifdef CONFIG_EDAC_DEBUG
  74 extern int edac_debug_level;
  75
  76 #define edac_debug_printk(level, fmt, arg...)                           \
  77         do {                                                            \
  78                 if (level <= edac_debug_level)                          \
  79                         edac_printk(KERN_DEBUG, EDAC_DEBUG,             \
  80                                     "%s: " fmt, __func__, ##arg);       \
  81         } while (0)
  82
  83 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  84 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  85 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  86 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  87 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  88
  89 #else                           /* !CONFIG_EDAC_DEBUG */
  90
  91 #define debugf0( ... )
  92 #define debugf1( ... )
  93 #define debugf2( ... )
  94 #define debugf3( ... )
  95 #define debugf4( ... )
  96
  97 #endif                          /* !CONFIG_EDAC_DEBUG */
  98
  99 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
 100         PCI_DEVICE_ID_ ## vend ## _ ## dev
 101
 102 #define edac_dev_name(dev) (dev)->dev_name
 103
 104 /* memory devices */
 105 enum dev_type {
 106         DEV_UNKNOWN = 0,
 107         DEV_X1,
 108         DEV_X2,
 109         DEV_X4,
 110         DEV_X8,
 111         DEV_X16,
 112         DEV_X32,                /* Do these parts exist? */
 113         DEV_X64                 /* Do these parts exist? */
 114 };
 115
 116 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 117 #define DEV_FLAG_X1             BIT(DEV_X1)
 118 #define DEV_FLAG_X2             BIT(DEV_X2)
 119 #define DEV_FLAG_X4             BIT(DEV_X4)
 120 #define DEV_FLAG_X8             BIT(DEV_X8)
 121 #define DEV_FLAG_X16            BIT(DEV_X16)
 122 #define DEV_FLAG_X32            BIT(DEV_X32)
 123 #define DEV_FLAG_X64            BIT(DEV_X64)
 124
 125 /* memory types */
 126 enum mem_type {
 127         MEM_EMPTY = 0,          /* Empty csrow */
 128         MEM_RESERVED,           /* Reserved csrow type */
 129         MEM_UNKNOWN,            /* Unknown csrow type */
 130         MEM_FPM,                /* Fast page mode */
 131         MEM_EDO,                /* Extended data out */
 132         MEM_BEDO,               /* Burst Extended data out */
 133         MEM_SDR,                /* Single data rate SDRAM */
 134         MEM_RDR,                /* Registered single data rate SDRAM */
 135         MEM_DDR,                /* Double data rate SDRAM */
 136         MEM_RDDR,               /* Registered Double data rate SDRAM */
 137         MEM_RMBS,               /* Rambus DRAM */
 138         MEM_DDR2,               /* DDR2 RAM */
 139         MEM_FB_DDR2,            /* fully buffered DDR2 */
 140         MEM_RDDR2,              /* Registered DDR2 RAM */
 141         MEM_XDR,                /* Rambus XDR */
 142         MEM_DDR3,               /* DDR3 RAM */
 143         MEM_RDDR3,              /* Registered DDR3 RAM */
 144 };
 145
 146 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 147 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 148 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 149 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 150 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 151 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 152 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 153 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 154 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 155 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 156 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 157 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 158 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 159 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 160 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 161 #define MEM_FLAG_DDR3            BIT(MEM_DDR3)
 162 #define MEM_FLAG_RDDR3           BIT(MEM_RDDR3)
 163
 164 /* chipset Error Detection and Correction capabilities and mode */
 165 enum edac_type {
 166         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 167         EDAC_NONE,              /* Doesn't support ECC */
 168         EDAC_RESERVED,          /* Reserved ECC type */
 169         EDAC_PARITY,            /* Detects parity errors */
 170         EDAC_EC,                /* Error Checking - no correction */
 171         EDAC_SECDED,            /* Single bit error correction, Double detection */
 172         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 173         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 174         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 175         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 176 };
 177
 178 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 179 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 180 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 181 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 182 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 183 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 184 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 185 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 186 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 187
 188 /* scrubbing capabilities */
 189 enum scrub_type {
 190         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 191         SCRUB_NONE,             /* No scrubber */
 192         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 193         SCRUB_SW_SRC,           /* Software scrub only errors */
 194         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 195         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 196         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 197         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 198         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 199         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 200 };
 201
 202 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 203 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 204 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 205 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 206 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 207 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 208 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 209 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 210
 211 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 212
 213 /* EDAC internal operation states */
 214 #define OP_ALLOC                0x100
 215 #define OP_RUNNING_POLL         0x201
 216 #define OP_RUNNING_INTERRUPT    0x202
 217 #define OP_RUNNING_POLL_INTR    0x203
 218 #define OP_OFFLINE              0x300
 219
 220 /*
 221  * There are several things to be aware of that aren't at all obvious:
 222  *
 223  *
 224  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 225  *
 226  * These are some of the many terms that are thrown about that don't always
 227  * mean what people think they mean (Inconceivable!).  In the interest of
 228  * creating a common ground for discussion, terms and their definitions
 229  * will be established.
 230  *
 231  * Memory devices:      The individual chip on a memory stick.  These devices
 232  *                      commonly output 4 and 8 bits each.  Grouping several
 233  *                      of these in parallel provides 64 bits which is common
 234  *                      for a memory stick.
 235  *
 236  * Memory Stick:        A printed circuit board that aggregates multiple
 237  *                      memory devices in parallel.  This is the atomic
 238  *                      memory component that is purchaseable by Joe consumer
 239  *                      and loaded into a memory socket.
 240  *
 241  * Socket:              A physical connector on the motherboard that accepts
 242  *                      a single memory stick.
 243  *
 244  * Channel:             Set of memory devices on a memory stick that must be
 245  *                      grouped in parallel with one or more additional
 246  *                      channels from other memory sticks.  This parallel
 247  *                      grouping of the output from multiple channels are
 248  *                      necessary for the smallest granularity of memory access.
 249  *                      Some memory controllers are capable of single channel -
 250  *                      which means that memory sticks can be loaded
 251  *                      individually.  Other memory controllers are only
 252  *                      capable of dual channel - which means that memory
 253  *                      sticks must be loaded as pairs (see "socket set").
 254  *
 255  * Chip-select row:     All of the memory devices that are selected together.
 256  *                      for a single, minimum grain of memory access.
 257  *                      This selects all of the parallel memory devices across
 258  *                      all of the parallel channels.  Common chip-select rows
 259  *                      for single channel are 64 bits, for dual channel 128
 260  *                      bits.
 261  *
 262  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
 263  *                      Motherboards commonly drive two chip-select pins to
 264  *                      a memory stick. A single-ranked stick, will occupy
 265  *                      only one of those rows. The other will be unused.
 266  *
 267  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 268  *                      access different sets of memory devices.  The two
 269  *                      rows cannot be accessed concurrently.
 270  *
 271  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 272  *                      A double-sided stick has two chip-select rows which
 273  *                      access different sets of memory devices.  The two
 274  *                      rows cannot be accessed concurrently.  "Double-sided"
 275  *                      is irrespective of the memory devices being mounted
 276  *                      on both sides of the memory stick.
 277  *
 278  * Socket set:          All of the memory sticks that are required for
 279  *                      a single memory access or all of the memory sticks
 280  *                      spanned by a chip-select row.  A single socket set
 281  *                      has two chip-select rows and if double-sided sticks
 282  *                      are used these will occupy those chip-select rows.
 283  *
 284  * Bank:                This term is avoided because it is unclear when
 285  *                      needing to distinguish between chip-select rows and
 286  *                      socket sets.
 287  *
 288  * Controller pages:
 289  *
 290  * Physical pages:
 291  *
 292  * Virtual pages:
 293  *
 294  *
 295  * STRUCTURE ORGANIZATION AND CHOICES
 296  *
 297  *
 298  *
 299  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 300  */
 301
 302 struct channel_info {
 303         int chan_idx;           /* channel index */
 304         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 305         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 306         struct csrow_info *csrow;       /* the parent */
 307 };
 308
 309 struct csrow_info {
 310         unsigned long first_page;       /* first page number in dimm */
 311         unsigned long last_page;        /* last page number in dimm */
 312         unsigned long page_mask;        /* used for interleaving -
 313                                          * 0UL for non intlv
 314                                          */
 315         u32 nr_pages;           /* number of pages in csrow */
 316         u32 grain;              /* granularity of reported error in bytes */
 317         int csrow_idx;          /* the chip-select row */
 318         enum dev_type dtype;    /* memory device type */
 319         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 320         u32 ce_count;           /* Correctable Errors for this csrow */
 321         enum mem_type mtype;    /* memory csrow type */
 322         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 323         struct mem_ctl_info *mci;       /* the parent */
 324
 325         struct kobject kobj;    /* sysfs kobject for this csrow */
 326
 327         /* channel information for this csrow */
 328         u32 nr_channels;
 329         struct channel_info *channels;
 330 };
 331
 332 struct mcidev_sysfs_group {
 333         const char *name;                               /* group name */
 334         const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
 335 };
 336
 337 struct mcidev_sysfs_group_kobj {
 338         struct list_head list;          /* list for all instances within a mc */
 339
 340         struct kobject kobj;            /* kobj for the group */
 341
 342         const struct mcidev_sysfs_group *grp;   /* group description table */
 343         struct mem_ctl_info *mci;       /* the parent */
 344 };
 345
 346 /* mcidev_sysfs_attribute structure
 347  *      used for driver sysfs attributes and in mem_ctl_info
 348  *      sysfs top level entries
 349  */
 350 struct mcidev_sysfs_attribute {
 351         /* It should use either attr or grp */
 352         struct attribute attr;
 353         const struct mcidev_sysfs_group *grp;   /* Points to a group of attributes */
 354
 355         /* Ops for show/store values at the attribute - not used on group */
 356         ssize_t (*show)(struct mem_ctl_info *,char *);
 357         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 358 };
 359
 360 /* MEMORY controller information structure
 361  */
 362 struct mem_ctl_info {
 363         struct list_head link;  /* for global list of mem_ctl_info structs */
 364
 365         struct module *owner;   /* Module owner of this control struct */
 366
 367         unsigned long mtype_cap;        /* memory types supported by mc */
 368         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 369         unsigned long edac_cap; /* configuration capabilities - this is
 370                                  * closely related to edac_ctl_cap.  The
 371                                  * difference is that the controller may be
 372                                  * capable of s4ecd4ed which would be listed
 373                                  * in edac_ctl_cap, but if channels aren't
 374                                  * capable of s4ecd4ed then the edac_cap would
 375                                  * not have that capability.
 376                                  */
 377         unsigned long scrub_cap;        /* chipset scrub capabilities */
 378         enum scrub_type scrub_mode;     /* current scrub mode */
 379
 380         /* Translates sdram memory scrub rate given in bytes/sec to the
 381            internal representation and configures whatever else needs
 382            to be configured.
 383          */
 384         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
 385
 386         /* Get the current sdram memory scrub rate from the internal
 387            representation and converts it to the closest matching
 388            bandwidth in bytes/sec.
 389          */
 390         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
 391
 392
 393         /* pointer to edac checking routine */
 394         void (*edac_check) (struct mem_ctl_info * mci);
 395
 396         /*
 397          * Remaps memory pages: controller pages to physical pages.
 398          * For most MC's, this will be NULL.
 399          */
 400         /* FIXME - why not send the phys page to begin with? */
 401         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 402                                            unsigned long page);
 403         int mc_idx;
 404         int nr_csrows;
 405         struct csrow_info *csrows;
 406         /*
 407          * FIXME - what about controllers on other busses? - IDs must be
 408          * unique.  dev pointer should be sufficiently unique, but
 409          * BUS:SLOT.FUNC numbers may not be unique.
 410          */
 411         struct device *dev;
 412         const char *mod_name;
 413         const char *mod_ver;
 414         const char *ctl_name;
 415         const char *dev_name;
 416         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 417         void *pvt_info;
 418         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 419         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 420         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 421         u32 ce_count;           /* Total Correctable Errors for this MC */
 422         unsigned long start_time;       /* mci load start time (in jiffies) */
 423
 424         struct completion complete;
 425
 426         /* edac sysfs device control */
 427         struct kobject edac_mci_kobj;
 428
 429         /* list for all grp instances within a mc */
 430         struct list_head grp_kobj_list;
 431
 432         /* Additional top controller level attributes, but specified
 433          * by the low level driver.
 434          *
 435          * Set by the low level driver to provide attributes at the
 436          * controller level, same level as 'ue_count' and 'ce_count' above.
 437          * An array of structures, NULL terminated
 438          *
 439          * If attributes are desired, then set to array of attributes
 440          * If no attributes are desired, leave NULL
 441          */
 442         const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 443
 444         /* work struct for this MC */
 445         struct delayed_work work;
 446
 447         /* the internal state of this controller instance */
 448         int op_state;
 449 };
 450
 451 /*
 452  * The following are the structures to provide for a generic
 453  * or abstract 'edac_device'. This set of structures and the
 454  * code that implements the APIs for the same, provide for
 455  * registering EDAC type devices which are NOT standard memory.
 456  *
 457  * CPU caches (L1 and L2)
 458  * DMA engines
 459  * Core CPU swithces
 460  * Fabric switch units
 461  * PCIe interface controllers
 462  * other EDAC/ECC type devices that can be monitored for
 463  * errors, etc.
 464  *
 465  * It allows for a 2 level set of hiearchry. For example:
 466  *
 467  * cache could be composed of L1, L2 and L3 levels of cache.
 468  * Each CPU core would have its own L1 cache, while sharing
 469  * L2 and maybe L3 caches.
 470  *
 471  * View them arranged, via the sysfs presentation:
 472  * /sys/devices/system/edac/..
 473  *
 474  *      mc/             <existing memory device directory>
 475  *      cpu/cpu0/..     <L1 and L2 block directory>
 476  *              /L1-cache/ce_count
 477  *                       /ue_count
 478  *              /L2-cache/ce_count
 479  *                       /ue_count
 480  *      cpu/cpu1/..     <L1 and L2 block directory>
 481  *              /L1-cache/ce_count
 482  *                       /ue_count
 483  *              /L2-cache/ce_count
 484  *                       /ue_count
 485  *      ...
 486  *
 487  *      the L1 and L2 directories would be "edac_device_block's"
 488  */
 489
 490 struct edac_device_counter {
 491         u32 ue_count;
 492         u32 ce_count;
 493 };
 494
 495 /* forward reference */
 496 struct edac_device_ctl_info;
 497 struct edac_device_block;
 498
 499 /* edac_dev_sysfs_attribute structure
 500  *      used for driver sysfs attributes in mem_ctl_info
 501  *      for extra controls and attributes:
 502  *              like high level error Injection controls
 503  */
 504 struct edac_dev_sysfs_attribute {
 505         struct attribute attr;
 506         ssize_t (*show)(struct edac_device_ctl_info *, char *);
 507         ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
 508 };
 509
 510 /* edac_dev_sysfs_block_attribute structure
 511  *
 512  *      used in leaf 'block' nodes for adding controls/attributes
 513  *
 514  *      each block in each instance of the containing control structure
 515  *      can have an array of the following. The show and store functions
 516  *      will be filled in with the show/store function in the
 517  *      low level driver.
 518  *
 519  *      The 'value' field will be the actual value field used for
 520  *      counting
 521  */
 522 struct edac_dev_sysfs_block_attribute {
 523         struct attribute attr;
 524         ssize_t (*show)(struct kobject *, struct attribute *, char *);
 525         ssize_t (*store)(struct kobject *, struct attribute *,
 526                         const char *, size_t);
 527         struct edac_device_block *block;
 528
 529         unsigned int value;
 530 };
 531
 532 /* device block control structure */
 533 struct edac_device_block {
 534         struct edac_device_instance *instance;  /* Up Pointer */
 535         char name[EDAC_DEVICE_NAME_LEN + 1];
 536
 537         struct edac_device_counter counters;    /* basic UE and CE counters */
 538
 539         int nr_attribs;         /* how many attributes */
 540
 541         /* this block's attributes, could be NULL */
 542         struct edac_dev_sysfs_block_attribute *block_attributes;
 543
 544         /* edac sysfs device control */
 545         struct kobject kobj;
 546 };
 547
 548 /* device instance control structure */
 549 struct edac_device_instance {
 550         struct edac_device_ctl_info *ctl;       /* Up pointer */
 551         char name[EDAC_DEVICE_NAME_LEN + 4];
 552
 553         struct edac_device_counter counters;    /* instance counters */
 554
 555         u32 nr_blocks;          /* how many blocks */
 556         struct edac_device_block *blocks;       /* block array */
 557
 558         /* edac sysfs device control */
 559         struct kobject kobj;
 560 };
 561
 562
 563 /*
 564  * Abstract edac_device control info structure
 565  *
 566  */
 567 struct edac_device_ctl_info {
 568         /* for global list of edac_device_ctl_info structs */
 569         struct list_head link;
 570
 571         struct module *owner;   /* Module owner of this control struct */
 572
 573         int dev_idx;
 574
 575         /* Per instance controls for this edac_device */
 576         int log_ue;             /* boolean for logging UEs */
 577         int log_ce;             /* boolean for logging CEs */
 578         int panic_on_ue;        /* boolean for panic'ing on an UE */
 579         unsigned poll_msec;     /* number of milliseconds to poll interval */
 580         unsigned long delay;    /* number of jiffies for poll_msec */
 581
 582         /* Additional top controller level attributes, but specified
 583          * by the low level driver.
 584          *
 585          * Set by the low level driver to provide attributes at the
 586          * controller level, same level as 'ue_count' and 'ce_count' above.
 587          * An array of structures, NULL terminated
 588          *
 589          * If attributes are desired, then set to array of attributes
 590          * If no attributes are desired, leave NULL
 591          */
 592         struct edac_dev_sysfs_attribute *sysfs_attributes;
 593
 594         /* pointer to main 'edac' class in sysfs */
 595         struct sysdev_class *edac_class;
 596
 597         /* the internal state of this controller instance */
 598         int op_state;
 599         /* work struct for this instance */
 600         struct delayed_work work;
 601
 602         /* pointer to edac polling checking routine:
 603          *      If NOT NULL: points to polling check routine
 604          *      If NULL: Then assumes INTERRUPT operation, where
 605          *              MC driver will receive events
 606          */
 607         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 608
 609         struct device *dev;     /* pointer to device structure */
 610
 611         const char *mod_name;   /* module name */
 612         const char *ctl_name;   /* edac controller  name */
 613         const char *dev_name;   /* pci/platform/etc... name */
 614
 615         void *pvt_info;         /* pointer to 'private driver' info */
 616
 617         unsigned long start_time;       /* edac_device load start time (jiffies) */
 618
 619         struct completion removal_complete;
 620
 621         /* sysfs top name under 'edac' directory
 622          * and instance name:
 623          *      cpu/cpu0/...
 624          *      cpu/cpu1/...
 625          *      cpu/cpu2/...
 626          *      ...
 627          */
 628         char name[EDAC_DEVICE_NAME_LEN + 1];
 629
 630         /* Number of instances supported on this control structure
 631          * and the array of those instances
 632          */
 633         u32 nr_instances;
 634         struct edac_device_instance *instances;
 635
 636         /* Event counters for the this whole EDAC Device */
 637         struct edac_device_counter counters;
 638
 639         /* edac sysfs device control for the 'name'
 640          * device this structure controls
 641          */
 642         struct kobject kobj;
 643 };
 644
 645 /* To get from the instance's wq to the beginning of the ctl structure */
 646 #define to_edac_mem_ctl_work(w) \
 647                 container_of(w, struct mem_ctl_info, work)
 648
 649 #define to_edac_device_ctl_work(w) \
 650                 container_of(w,struct edac_device_ctl_info,work)
 651
 652 /*
 653  * The alloc() and free() functions for the 'edac_device' control info
 654  * structure. A MC driver will allocate one of these for each edac_device
 655  * it is going to control/register with the EDAC CORE.
 656  */
 657 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 658                 unsigned sizeof_private,
 659                 char *edac_device_name, unsigned nr_instances,
 660                 char *edac_block_name, unsigned nr_blocks,
 661                 unsigned offset_value,
 662                 struct edac_dev_sysfs_block_attribute *block_attributes,
 663                 unsigned nr_attribs,
 664                 int device_index);
 665
 666 /* The offset value can be:
 667  *      -1 indicating no offset value
 668  *      0 for zero-based block numbers
 669  *      1 for 1-based block number
 670  *      other for other-based block number
 671  */
 672 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 673
 674 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 675
 676 #ifdef CONFIG_PCI
 677
 678 struct edac_pci_counter {
 679         atomic_t pe_count;
 680         atomic_t npe_count;
 681 };
 682
 683 /*
 684  * Abstract edac_pci control info structure
 685  *
 686  */
 687 struct edac_pci_ctl_info {
 688         /* for global list of edac_pci_ctl_info structs */
 689         struct list_head link;
 690
 691         int pci_idx;
 692
 693         struct sysdev_class *edac_class;        /* pointer to class */
 694
 695         /* the internal state of this controller instance */
 696         int op_state;
 697         /* work struct for this instance */
 698         struct delayed_work work;
 699
 700         /* pointer to edac polling checking routine:
 701          *      If NOT NULL: points to polling check routine
 702          *      If NULL: Then assumes INTERRUPT operation, where
 703          *              MC driver will receive events
 704          */
 705         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 706
 707         struct device *dev;     /* pointer to device structure */
 708
 709         const char *mod_name;   /* module name */
 710         const char *ctl_name;   /* edac controller  name */
 711         const char *dev_name;   /* pci/platform/etc... name */
 712
 713         void *pvt_info;         /* pointer to 'private driver' info */
 714
 715         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 716
 717         struct completion complete;
 718
 719         /* sysfs top name under 'edac' directory
 720          * and instance name:
 721          *      cpu/cpu0/...
 722          *      cpu/cpu1/...
 723          *      cpu/cpu2/...
 724          *      ...
 725          */
 726         char name[EDAC_DEVICE_NAME_LEN + 1];
 727
 728         /* Event counters for the this whole EDAC Device */
 729         struct edac_pci_counter counters;
 730
 731         /* edac sysfs device control for the 'name'
 732          * device this structure controls
 733          */
 734         struct kobject kobj;
 735         struct completion kobj_complete;
 736 };
 737
 738 #define to_edac_pci_ctl_work(w) \
 739                 container_of(w, struct edac_pci_ctl_info,work)
 740
 741 /* write all or some bits in a byte-register*/
 742 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 743                                    u8 mask)
 744 {
 745         if (mask != 0xff) {
 746                 u8 buf;
 747
 748                 pci_read_config_byte(pdev, offset, &buf);
 749                 value &= mask;
 750                 buf &= ~mask;
 751                 value |= buf;
 752         }
 753
 754         pci_write_config_byte(pdev, offset, value);
 755 }
 756
 757 /* write all or some bits in a word-register*/
 758 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 759                                     u16 value, u16 mask)
 760 {
 761         if (mask != 0xffff) {
 762                 u16 buf;
 763
 764                 pci_read_config_word(pdev, offset, &buf);
 765                 value &= mask;
 766                 buf &= ~mask;
 767                 value |= buf;
 768         }
 769
 770         pci_write_config_word(pdev, offset, value);
 771 }
 772
 773 /*
 774  * pci_write_bits32
 775  *
 776  * edac local routine to do pci_write_config_dword, but adds
 777  * a mask parameter. If mask is all ones, ignore the mask.
 778  * Otherwise utilize the mask to isolate specified bits
 779  *
 780  * write all or some bits in a dword-register
 781  */
 782 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 783                                     u32 value, u32 mask)
 784 {
 785         if (mask != 0xffffffff) {
 786                 u32 buf;
 787
 788                 pci_read_config_dword(pdev, offset, &buf);
 789                 value &= mask;
 790                 buf &= ~mask;
 791                 value |= buf;
 792         }
 793
 794         pci_write_config_dword(pdev, offset, value);
 795 }
 796
 797 #endif                          /* CONFIG_PCI */
 798
 799 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 800                                           unsigned nr_chans, int edac_index);
 801 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 802 extern void edac_mc_free(struct mem_ctl_info *mci);
 803 extern struct mem_ctl_info *edac_mc_find(int idx);
 804 extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
 805 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 806 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 807                                       unsigned long page);
 808
 809 /*
 810  * The no info errors are used when error overflows are reported.
 811  * There are a limited number of error logging registers that can
 812  * be exausted.  When all registers are exhausted and an additional
 813  * error occurs then an error overflow register records that an
 814  * error occurred and the type of error, but doesn't have any
 815  * further information.  The ce/ue versions make for cleaner
 816  * reporting logic and function interface - reduces conditional
 817  * statement clutter and extra function arguments.
 818  */
 819 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 820                               unsigned long page_frame_number,
 821                               unsigned long offset_in_page,
 822                               unsigned long syndrome, int row, int channel,
 823                               const char *msg);
 824 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 825                                       const char *msg);
 826 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 827                               unsigned long page_frame_number,
 828                               unsigned long offset_in_page, int row,
 829                               const char *msg);
 830 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 831                                       const char *msg);
 832 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 833                                   unsigned int channel0, unsigned int channel1,
 834                                   char *msg);
 835 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 836                                   unsigned int channel, char *msg);
 837
 838 /*
 839  * edac_device APIs
 840  */
 841 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
 842 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 843 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 844                                 int inst_nr, int block_nr, const char *msg);
 845 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 846                                 int inst_nr, int block_nr, const char *msg);
 847 extern int edac_device_alloc_index(void);
 848
 849 /*
 850  * edac_pci APIs
 851  */
 852 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
 853                                 const char *edac_pci_name);
 854
 855 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 856
 857 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
 858                                 unsigned long value);
 859
 860 extern int edac_pci_alloc_index(void);
 861 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 862 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 863
 864 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
 865                                 struct device *dev,
 866                                 const char *mod_name);
 867
 868 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 869 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 870 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 871
 872 /*
 873  * edac misc APIs
 874  */
 875 extern char *edac_op_state_to_string(int op_state);
 876
 877 #endif                          /* _EDAC_CORE_H_ */