drivers/scsi/advansys.c

   1 #define DRV_NAME "advansys"
   2 #define ASC_VERSION "3.4"       /* AdvanSys Driver Version */
   3
   4 /*
   5  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   6  *
   7  * Copyright (c) 1995-2000 Advanced System Products, Inc.
   8  * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
   9  * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
  10  * All Rights Reserved.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  */
  17
  18 /*
  19  * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
  20  * changed its name to ConnectCom Solutions, Inc.
  21  * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/ioport.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32 #include <linux/mm.h>
  33 #include <linux/proc_fs.h>
  34 #include <linux/init.h>
  35 #include <linux/blkdev.h>
  36 #include <linux/isa.h>
  37 #include <linux/eisa.h>
  38 #include <linux/pci.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/firmware.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/system.h>
  45 #include <asm/dma.h>
  46
  47 #include <scsi/scsi_cmnd.h>
  48 #include <scsi/scsi_device.h>
  49 #include <scsi/scsi_tcq.h>
  50 #include <scsi/scsi.h>
  51 #include <scsi/scsi_host.h>
  52
  53 /* FIXME:
  54  *
  55  *  1. Although all of the necessary command mapping places have the
  56  *     appropriate dma_map.. APIs, the driver still processes its internal
  57  *     queue using bus_to_virt() and virt_to_bus() which are illegal under
  58  *     the API.  The entire queue processing structure will need to be
  59  *     altered to fix this.
  60  *  2. Need to add memory mapping workaround. Test the memory mapping.
  61  *     If it doesn't work revert to I/O port access. Can a test be done
  62  *     safely?
  63  *  3. Handle an interrupt not working. Keep an interrupt counter in
  64  *     the interrupt handler. In the timeout function if the interrupt
  65  *     has not occurred then print a message and run in polled mode.
  66  *  4. Need to add support for target mode commands, cf. CAM XPT.
  67  *  5. check DMA mapping functions for failure
  68  *  6. Use scsi_transport_spi
  69  *  7. advansys_info is not safe against multiple simultaneous callers
  70  *  8. Add module_param to override ISA/VLB ioport array
  71  */
  72 #warning this driver is still not properly converted to the DMA API
  73
  74 /* Enable driver /proc statistics. */
  75 #define ADVANSYS_STATS
  76
  77 /* Enable driver tracing. */
  78 #undef ADVANSYS_DEBUG
  79
  80 /*
  81  * Portable Data Types
  82  *
  83  * Any instance where a 32-bit long or pointer type is assumed
  84  * for precision or HW defined structures, the following define
  85  * types must be used. In Linux the char, short, and int types
  86  * are all consistent at 8, 16, and 32 bits respectively. Pointers
  87  * and long types are 64 bits on Alpha and UltraSPARC.
  88  */
  89 #define ASC_PADDR __u32         /* Physical/Bus address data type. */
  90 #define ASC_VADDR __u32         /* Virtual address data type. */
  91 #define ASC_DCNT  __u32         /* Unsigned Data count type. */
  92 #define ASC_SDCNT __s32         /* Signed Data count type. */
  93
  94 typedef unsigned char uchar;
  95
  96 #ifndef TRUE
  97 #define TRUE     (1)
  98 #endif
  99 #ifndef FALSE
 100 #define FALSE    (0)
 101 #endif
 102
 103 #define ERR      (-1)
 104 #define UW_ERR   (uint)(0xFFFF)
 105 #define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
 106
 107 #define PCI_VENDOR_ID_ASP               0x10cd
 108 #define PCI_DEVICE_ID_ASP_1200A         0x1100
 109 #define PCI_DEVICE_ID_ASP_ABP940        0x1200
 110 #define PCI_DEVICE_ID_ASP_ABP940U       0x1300
 111 #define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
 112 #define PCI_DEVICE_ID_38C0800_REV1      0x2500
 113 #define PCI_DEVICE_ID_38C1600_REV1      0x2700
 114
 115 /*
 116  * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
 117  * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
 118  * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
 119  * SRB structure.
 120  */
 121 #define CC_VERY_LONG_SG_LIST 0
 122 #define ASC_SRB2SCSIQ(srb_ptr)  (srb_ptr)
 123
 124 #define PortAddr                 unsigned int   /* port address size  */
 125 #define inp(port)                inb(port)
 126 #define outp(port, byte)         outb((byte), (port))
 127
 128 #define inpw(port)               inw(port)
 129 #define outpw(port, word)        outw((word), (port))
 130
 131 #define ASC_MAX_SG_QUEUE    7
 132 #define ASC_MAX_SG_LIST     255
 133
 134 #define ASC_CS_TYPE  unsigned short
 135
 136 #define ASC_IS_ISA          (0x0001)
 137 #define ASC_IS_ISAPNP       (0x0081)
 138 #define ASC_IS_EISA         (0x0002)
 139 #define ASC_IS_PCI          (0x0004)
 140 #define ASC_IS_PCI_ULTRA    (0x0104)
 141 #define ASC_IS_PCMCIA       (0x0008)
 142 #define ASC_IS_MCA          (0x0020)
 143 #define ASC_IS_VL           (0x0040)
 144 #define ASC_IS_WIDESCSI_16  (0x0100)
 145 #define ASC_IS_WIDESCSI_32  (0x0200)
 146 #define ASC_IS_BIG_ENDIAN   (0x8000)
 147
 148 #define ASC_CHIP_MIN_VER_VL      (0x01)
 149 #define ASC_CHIP_MAX_VER_VL      (0x07)
 150 #define ASC_CHIP_MIN_VER_PCI     (0x09)
 151 #define ASC_CHIP_MAX_VER_PCI     (0x0F)
 152 #define ASC_CHIP_VER_PCI_BIT     (0x08)
 153 #define ASC_CHIP_MIN_VER_ISA     (0x11)
 154 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
 155 #define ASC_CHIP_MAX_VER_ISA     (0x27)
 156 #define ASC_CHIP_VER_ISA_BIT     (0x30)
 157 #define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
 158 #define ASC_CHIP_VER_ASYN_BUG    (0x21)
 159 #define ASC_CHIP_VER_PCI             0x08
 160 #define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
 161 #define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
 162 #define ASC_CHIP_MIN_VER_EISA (0x41)
 163 #define ASC_CHIP_MAX_VER_EISA (0x47)
 164 #define ASC_CHIP_VER_EISA_BIT (0x40)
 165 #define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
 166 #define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
 167 #define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
 168 #define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
 169
 170 #define ASC_SCSI_ID_BITS  3
 171 #define ASC_SCSI_TIX_TYPE     uchar
 172 #define ASC_ALL_DEVICE_BIT_SET  0xFF
 173 #define ASC_SCSI_BIT_ID_TYPE  uchar
 174 #define ASC_MAX_TID       7
 175 #define ASC_MAX_LUN       7
 176 #define ASC_SCSI_WIDTH_BIT_SET  0xFF
 177 #define ASC_MAX_SENSE_LEN   32
 178 #define ASC_MIN_SENSE_LEN   14
 179 #define ASC_SCSI_RESET_HOLD_TIME_US  60
 180
 181 /*
 182  * Narrow boards only support 12-byte commands, while wide boards
 183  * extend to 16-byte commands.
 184  */
 185 #define ASC_MAX_CDB_LEN     12
 186 #define ADV_MAX_CDB_LEN     16
 187
 188 #define MS_SDTR_LEN    0x03
 189 #define MS_WDTR_LEN    0x02
 190
 191 #define ASC_SG_LIST_PER_Q   7
 192 #define QS_FREE        0x00
 193 #define QS_READY       0x01
 194 #define QS_DISC1       0x02
 195 #define QS_DISC2       0x04
 196 #define QS_BUSY        0x08
 197 #define QS_ABORTED     0x40
 198 #define QS_DONE        0x80
 199 #define QC_NO_CALLBACK   0x01
 200 #define QC_SG_SWAP_QUEUE 0x02
 201 #define QC_SG_HEAD       0x04
 202 #define QC_DATA_IN       0x08
 203 #define QC_DATA_OUT      0x10
 204 #define QC_URGENT        0x20
 205 #define QC_MSG_OUT       0x40
 206 #define QC_REQ_SENSE     0x80
 207 #define QCSG_SG_XFER_LIST  0x02
 208 #define QCSG_SG_XFER_MORE  0x04
 209 #define QCSG_SG_XFER_END   0x08
 210 #define QD_IN_PROGRESS       0x00
 211 #define QD_NO_ERROR          0x01
 212 #define QD_ABORTED_BY_HOST   0x02
 213 #define QD_WITH_ERROR        0x04
 214 #define QD_INVALID_REQUEST   0x80
 215 #define QD_INVALID_HOST_NUM  0x81
 216 #define QD_INVALID_DEVICE    0x82
 217 #define QD_ERR_INTERNAL      0xFF
 218 #define QHSTA_NO_ERROR               0x00
 219 #define QHSTA_M_SEL_TIMEOUT          0x11
 220 #define QHSTA_M_DATA_OVER_RUN        0x12
 221 #define QHSTA_M_DATA_UNDER_RUN       0x12
 222 #define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
 223 #define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
 224 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
 225 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
 226 #define QHSTA_D_HOST_ABORT_FAILED       0x23
 227 #define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
 228 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
 229 #define QHSTA_D_ASPI_NO_BUF_POOL        0x26
 230 #define QHSTA_M_WTM_TIMEOUT         0x41
 231 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
 232 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
 233 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
 234 #define QHSTA_M_TARGET_STATUS_BUSY  0x45
 235 #define QHSTA_M_BAD_TAG_CODE        0x46
 236 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
 237 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
 238 #define QHSTA_D_LRAM_CMP_ERROR        0x81
 239 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
 240 #define ASC_FLAG_SCSIQ_REQ        0x01
 241 #define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
 242 #define ASC_FLAG_BIOS_ASYNC_IO    0x04
 243 #define ASC_FLAG_SRB_LINEAR_ADDR  0x08
 244 #define ASC_FLAG_WIN16            0x10
 245 #define ASC_FLAG_WIN32            0x20
 246 #define ASC_FLAG_ISA_OVER_16MB    0x40
 247 #define ASC_FLAG_DOS_VM_CALLBACK  0x80
 248 #define ASC_TAG_FLAG_EXTRA_BYTES               0x10
 249 #define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
 250 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
 251 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
 252 #define ASC_SCSIQ_CPY_BEG              4
 253 #define ASC_SCSIQ_SGHD_CPY_BEG         2
 254 #define ASC_SCSIQ_B_FWD                0
 255 #define ASC_SCSIQ_B_BWD                1
 256 #define ASC_SCSIQ_B_STATUS             2
 257 #define ASC_SCSIQ_B_QNO                3
 258 #define ASC_SCSIQ_B_CNTL               4
 259 #define ASC_SCSIQ_B_SG_QUEUE_CNT       5
 260 #define ASC_SCSIQ_D_DATA_ADDR          8
 261 #define ASC_SCSIQ_D_DATA_CNT          12
 262 #define ASC_SCSIQ_B_SENSE_LEN         20
 263 #define ASC_SCSIQ_DONE_INFO_BEG       22
 264 #define ASC_SCSIQ_D_SRBPTR            22
 265 #define ASC_SCSIQ_B_TARGET_IX         26
 266 #define ASC_SCSIQ_B_CDB_LEN           28
 267 #define ASC_SCSIQ_B_TAG_CODE          29
 268 #define ASC_SCSIQ_W_VM_ID             30
 269 #define ASC_SCSIQ_DONE_STATUS         32
 270 #define ASC_SCSIQ_HOST_STATUS         33
 271 #define ASC_SCSIQ_SCSI_STATUS         34
 272 #define ASC_SCSIQ_CDB_BEG             36
 273 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
 274 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
 275 #define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
 276 #define ASC_SCSIQ_B_SG_WK_QP          49
 277 #define ASC_SCSIQ_B_SG_WK_IX          50
 278 #define ASC_SCSIQ_W_ALT_DC1           52
 279 #define ASC_SCSIQ_B_LIST_CNT          6
 280 #define ASC_SCSIQ_B_CUR_LIST_CNT      7
 281 #define ASC_SGQ_B_SG_CNTL             4
 282 #define ASC_SGQ_B_SG_HEAD_QP          5
 283 #define ASC_SGQ_B_SG_LIST_CNT         6
 284 #define ASC_SGQ_B_SG_CUR_LIST_CNT     7
 285 #define ASC_SGQ_LIST_BEG              8
 286 #define ASC_DEF_SCSI1_QNG    4
 287 #define ASC_MAX_SCSI1_QNG    4
 288 #define ASC_DEF_SCSI2_QNG    16
 289 #define ASC_MAX_SCSI2_QNG    32
 290 #define ASC_TAG_CODE_MASK    0x23
 291 #define ASC_STOP_REQ_RISC_STOP      0x01
 292 #define ASC_STOP_ACK_RISC_STOP      0x03
 293 #define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
 294 #define ASC_STOP_CLEAN_UP_DISC_Q    0x20
 295 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
 296 #define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
 297 #define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
 298 #define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
 299 #define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
 300 #define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
 301 #define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
 302 #define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
 303
 304 typedef struct asc_scsiq_1 {
 305         uchar status;
 306         uchar q_no;
 307         uchar cntl;
 308         uchar sg_queue_cnt;
 309         uchar target_id;
 310         uchar target_lun;
 311         ASC_PADDR data_addr;
 312         ASC_DCNT data_cnt;
 313         ASC_PADDR sense_addr;
 314         uchar sense_len;
 315         uchar extra_bytes;
 316 } ASC_SCSIQ_1;
 317
 318 typedef struct asc_scsiq_2 {
 319         ASC_VADDR srb_ptr;
 320         uchar target_ix;
 321         uchar flag;
 322         uchar cdb_len;
 323         uchar tag_code;
 324         ushort vm_id;
 325 } ASC_SCSIQ_2;
 326
 327 typedef struct asc_scsiq_3 {
 328         uchar done_stat;
 329         uchar host_stat;
 330         uchar scsi_stat;
 331         uchar scsi_msg;
 332 } ASC_SCSIQ_3;
 333
 334 typedef struct asc_scsiq_4 {
 335         uchar cdb[ASC_MAX_CDB_LEN];
 336         uchar y_first_sg_list_qp;
 337         uchar y_working_sg_qp;
 338         uchar y_working_sg_ix;
 339         uchar y_res;
 340         ushort x_req_count;
 341         ushort x_reconnect_rtn;
 342         ASC_PADDR x_saved_data_addr;
 343         ASC_DCNT x_saved_data_cnt;
 344 } ASC_SCSIQ_4;
 345
 346 typedef struct asc_q_done_info {
 347         ASC_SCSIQ_2 d2;
 348         ASC_SCSIQ_3 d3;
 349         uchar q_status;
 350         uchar q_no;
 351         uchar cntl;
 352         uchar sense_len;
 353         uchar extra_bytes;
 354         uchar res;
 355         ASC_DCNT remain_bytes;
 356 } ASC_QDONE_INFO;
 357
 358 typedef struct asc_sg_list {
 359         ASC_PADDR addr;
 360         ASC_DCNT bytes;
 361 } ASC_SG_LIST;
 362
 363 typedef struct asc_sg_head {
 364         ushort entry_cnt;
 365         ushort queue_cnt;
 366         ushort entry_to_copy;
 367         ushort res;
 368         ASC_SG_LIST sg_list[0];
 369 } ASC_SG_HEAD;
 370
 371 typedef struct asc_scsi_q {
 372         ASC_SCSIQ_1 q1;
 373         ASC_SCSIQ_2 q2;
 374         uchar *cdbptr;
 375         ASC_SG_HEAD *sg_head;
 376         ushort remain_sg_entry_cnt;
 377         ushort next_sg_index;
 378 } ASC_SCSI_Q;
 379
 380 typedef struct asc_scsi_req_q {
 381         ASC_SCSIQ_1 r1;
 382         ASC_SCSIQ_2 r2;
 383         uchar *cdbptr;
 384         ASC_SG_HEAD *sg_head;
 385         uchar *sense_ptr;
 386         ASC_SCSIQ_3 r3;
 387         uchar cdb[ASC_MAX_CDB_LEN];
 388         uchar sense[ASC_MIN_SENSE_LEN];
 389 } ASC_SCSI_REQ_Q;
 390
 391 typedef struct asc_scsi_bios_req_q {
 392         ASC_SCSIQ_1 r1;
 393         ASC_SCSIQ_2 r2;
 394         uchar *cdbptr;
 395         ASC_SG_HEAD *sg_head;
 396         uchar *sense_ptr;
 397         ASC_SCSIQ_3 r3;
 398         uchar cdb[ASC_MAX_CDB_LEN];
 399         uchar sense[ASC_MIN_SENSE_LEN];
 400 } ASC_SCSI_BIOS_REQ_Q;
 401
 402 typedef struct asc_risc_q {
 403         uchar fwd;
 404         uchar bwd;
 405         ASC_SCSIQ_1 i1;
 406         ASC_SCSIQ_2 i2;
 407         ASC_SCSIQ_3 i3;
 408         ASC_SCSIQ_4 i4;
 409 } ASC_RISC_Q;
 410
 411 typedef struct asc_sg_list_q {
 412         uchar seq_no;
 413         uchar q_no;
 414         uchar cntl;
 415         uchar sg_head_qp;
 416         uchar sg_list_cnt;
 417         uchar sg_cur_list_cnt;
 418 } ASC_SG_LIST_Q;
 419
 420 typedef struct asc_risc_sg_list_q {
 421         uchar fwd;
 422         uchar bwd;
 423         ASC_SG_LIST_Q sg;
 424         ASC_SG_LIST sg_list[7];
 425 } ASC_RISC_SG_LIST_Q;
 426
 427 #define ASCQ_ERR_Q_STATUS             0x0D
 428 #define ASCQ_ERR_CUR_QNG              0x17
 429 #define ASCQ_ERR_SG_Q_LINKS           0x18
 430 #define ASCQ_ERR_ISR_RE_ENTRY         0x1A
 431 #define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
 432 #define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
 433
 434 /*
 435  * Warning code values are set in ASC_DVC_VAR  'warn_code'.
 436  */
 437 #define ASC_WARN_NO_ERROR             0x0000
 438 #define ASC_WARN_IO_PORT_ROTATE       0x0001
 439 #define ASC_WARN_EEPROM_CHKSUM        0x0002
 440 #define ASC_WARN_IRQ_MODIFIED         0x0004
 441 #define ASC_WARN_AUTO_CONFIG          0x0008
 442 #define ASC_WARN_CMD_QNG_CONFLICT     0x0010
 443 #define ASC_WARN_EEPROM_RECOVER       0x0020
 444 #define ASC_WARN_CFG_MSW_RECOVER      0x0040
 445
 446 /*
 447  * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
 448  */
 449 #define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
 450 #define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
 451 #define ASC_IERR_SET_PC_ADDR            0x0004
 452 #define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
 453 #define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
 454 #define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
 455 #define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
 456 #define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
 457 #define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
 458 #define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
 459 #define ASC_IERR_NO_BUS_TYPE            0x0400
 460 #define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
 461 #define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
 462 #define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
 463
 464 #define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
 465 #define ASC_MIN_TAG_Q_PER_DVC   (0x04)
 466 #define ASC_MIN_FREE_Q        (0x02)
 467 #define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
 468 #define ASC_MAX_TOTAL_QNG 240
 469 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
 470 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
 471 #define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
 472 #define ASC_MAX_INRAM_TAG_QNG   16
 473 #define ASC_IOADR_GAP   0x10
 474 #define ASC_SYN_MAX_OFFSET         0x0F
 475 #define ASC_DEF_SDTR_OFFSET        0x0F
 476 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
 477 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
 478
 479 /* The narrow chip only supports a limited selection of transfer rates.
 480  * These are encoded in the range 0..7 or 0..15 depending whether the chip
 481  * is Ultra-capable or not.  These tables let us convert from one to the other.
 482  */
 483 static const unsigned char asc_syn_xfer_period[8] = {
 484         25, 30, 35, 40, 50, 60, 70, 85
 485 };
 486
 487 static const unsigned char asc_syn_ultra_xfer_period[16] = {
 488         12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
 489 };
 490
 491 typedef struct ext_msg {
 492         uchar msg_type;
 493         uchar msg_len;
 494         uchar msg_req;
 495         union {
 496                 struct {
 497                         uchar sdtr_xfer_period;
 498                         uchar sdtr_req_ack_offset;
 499                 } sdtr;
 500                 struct {
 501                         uchar wdtr_width;
 502                 } wdtr;
 503                 struct {
 504                         uchar mdp_b3;
 505                         uchar mdp_b2;
 506                         uchar mdp_b1;
 507                         uchar mdp_b0;
 508                 } mdp;
 509         } u_ext_msg;
 510         uchar res;
 511 } EXT_MSG;
 512
 513 #define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
 514 #define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
 515 #define wdtr_width      u_ext_msg.wdtr.wdtr_width
 516 #define mdp_b3          u_ext_msg.mdp_b3
 517 #define mdp_b2          u_ext_msg.mdp_b2
 518 #define mdp_b1          u_ext_msg.mdp_b1
 519 #define mdp_b0          u_ext_msg.mdp_b0
 520
 521 typedef struct asc_dvc_cfg {
 522         ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
 523         ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
 524         ASC_SCSI_BIT_ID_TYPE disc_enable;
 525         ASC_SCSI_BIT_ID_TYPE sdtr_enable;
 526         uchar chip_scsi_id;
 527         uchar isa_dma_speed;
 528         uchar isa_dma_channel;
 529         uchar chip_version;
 530         ushort mcode_date;
 531         ushort mcode_version;
 532         uchar max_tag_qng[ASC_MAX_TID + 1];
 533         uchar sdtr_period_offset[ASC_MAX_TID + 1];
 534         uchar adapter_info[6];
 535 } ASC_DVC_CFG;
 536
 537 #define ASC_DEF_DVC_CNTL       0xFFFF
 538 #define ASC_DEF_CHIP_SCSI_ID   7
 539 #define ASC_DEF_ISA_DMA_SPEED  4
 540 #define ASC_INIT_STATE_BEG_GET_CFG   0x0001
 541 #define ASC_INIT_STATE_END_GET_CFG   0x0002
 542 #define ASC_INIT_STATE_BEG_SET_CFG   0x0004
 543 #define ASC_INIT_STATE_END_SET_CFG   0x0008
 544 #define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
 545 #define ASC_INIT_STATE_END_LOAD_MC   0x0020
 546 #define ASC_INIT_STATE_BEG_INQUIRY   0x0040
 547 #define ASC_INIT_STATE_END_INQUIRY   0x0080
 548 #define ASC_INIT_RESET_SCSI_DONE     0x0100
 549 #define ASC_INIT_STATE_WITHOUT_EEP   0x8000
 550 #define ASC_BUG_FIX_IF_NOT_DWB       0x0001
 551 #define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
 552 #define ASC_MIN_TAGGED_CMD  7
 553 #define ASC_MAX_SCSI_RESET_WAIT      30
 554 #define ASC_OVERRUN_BSIZE               64
 555
 556 struct asc_dvc_var;             /* Forward Declaration. */
 557
 558 typedef struct asc_dvc_var {
 559         PortAddr iop_base;
 560         ushort err_code;
 561         ushort dvc_cntl;
 562         ushort bug_fix_cntl;
 563         ushort bus_type;
 564         ASC_SCSI_BIT_ID_TYPE init_sdtr;
 565         ASC_SCSI_BIT_ID_TYPE sdtr_done;
 566         ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
 567         ASC_SCSI_BIT_ID_TYPE unit_not_ready;
 568         ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
 569         ASC_SCSI_BIT_ID_TYPE start_motor;
 570         uchar *overrun_buf;
 571         dma_addr_t overrun_dma;
 572         uchar scsi_reset_wait;
 573         uchar chip_no;
 574         char is_in_int;
 575         uchar max_total_qng;
 576         uchar cur_total_qng;
 577         uchar in_critical_cnt;
 578         uchar last_q_shortage;
 579         ushort init_state;
 580         uchar cur_dvc_qng[ASC_MAX_TID + 1];
 581         uchar max_dvc_qng[ASC_MAX_TID + 1];
 582         ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
 583         ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
 584         const uchar *sdtr_period_tbl;
 585         ASC_DVC_CFG *cfg;
 586         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
 587         char redo_scam;
 588         ushort res2;
 589         uchar dos_int13_table[ASC_MAX_TID + 1];
 590         ASC_DCNT max_dma_count;
 591         ASC_SCSI_BIT_ID_TYPE no_scam;
 592         ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
 593         uchar min_sdtr_index;
 594         uchar max_sdtr_index;
 595         struct asc_board *drv_ptr;
 596         int ptr_map_count;
 597         void **ptr_map;
 598         ASC_DCNT uc_break;
 599 } ASC_DVC_VAR;
 600
 601 typedef struct asc_dvc_inq_info {
 602         uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 603 } ASC_DVC_INQ_INFO;
 604
 605 typedef struct asc_cap_info {
 606         ASC_DCNT lba;
 607         ASC_DCNT blk_size;
 608 } ASC_CAP_INFO;
 609
 610 typedef struct asc_cap_info_array {
 611         ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 612 } ASC_CAP_INFO_ARRAY;
 613
 614 #define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
 615 #define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
 616 #define ASC_CNTL_INITIATOR         (ushort)0x0001
 617 #define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
 618 #define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
 619 #define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
 620 #define ASC_CNTL_NO_SCAM           (ushort)0x0010
 621 #define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
 622 #define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
 623 #define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
 624 #define ASC_CNTL_RESET_SCSI        (ushort)0x0200
 625 #define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
 626 #define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
 627 #define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
 628 #define ASC_CNTL_BURST_MODE        (ushort)0x2000
 629 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
 630 #define ASC_EEP_DVC_CFG_BEG_VL    2
 631 #define ASC_EEP_MAX_DVC_ADDR_VL   15
 632 #define ASC_EEP_DVC_CFG_BEG      32
 633 #define ASC_EEP_MAX_DVC_ADDR     45
 634 #define ASC_EEP_MAX_RETRY        20
 635
 636 /*
 637  * These macros keep the chip SCSI id and ISA DMA speed
 638  * bitfields in board order. C bitfields aren't portable
 639  * between big and little-endian platforms so they are
 640  * not used.
 641  */
 642
 643 #define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
 644 #define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
 645 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
 646    ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
 647 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
 648    ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
 649
 650 typedef struct asceep_config {
 651         ushort cfg_lsw;
 652         ushort cfg_msw;
 653         uchar init_sdtr;
 654         uchar disc_enable;
 655         uchar use_cmd_qng;
 656         uchar start_motor;
 657         uchar max_total_qng;
 658         uchar max_tag_qng;
 659         uchar bios_scan;
 660         uchar power_up_wait;
 661         uchar no_scam;
 662         uchar id_speed;         /* low order 4 bits is chip scsi id */
 663         /* high order 4 bits is isa dma speed */
 664         uchar dos_int13_table[ASC_MAX_TID + 1];
 665         uchar adapter_info[6];
 666         ushort cntl;
 667         ushort chksum;
 668 } ASCEEP_CONFIG;
 669
 670 #define ASC_EEP_CMD_READ          0x80
 671 #define ASC_EEP_CMD_WRITE         0x40
 672 #define ASC_EEP_CMD_WRITE_ABLE    0x30
 673 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
 674 #define ASCV_MSGOUT_BEG         0x0000
 675 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
 676 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
 677 #define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
 678 #define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
 679 #define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
 680 #define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
 681 #define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
 682 #define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
 683 #define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
 684 #define ASCV_BREAK_ADDR           (ushort)0x0028
 685 #define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
 686 #define ASCV_BREAK_CONTROL        (ushort)0x002C
 687 #define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
 688
 689 #define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
 690 #define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
 691 #define ASCV_MCODE_SIZE_W     (ushort)0x0034
 692 #define ASCV_STOP_CODE_B      (ushort)0x0036
 693 #define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
 694 #define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
 695 #define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
 696 #define ASCV_HALTCODE_W       (ushort)0x0040
 697 #define ASCV_CHKSUM_W         (ushort)0x0042
 698 #define ASCV_MC_DATE_W        (ushort)0x0044
 699 #define ASCV_MC_VER_W         (ushort)0x0046
 700 #define ASCV_NEXTRDY_B        (ushort)0x0048
 701 #define ASCV_DONENEXT_B       (ushort)0x0049
 702 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
 703 #define ASCV_SCSIBUSY_B       (ushort)0x004B
 704 #define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
 705 #define ASCV_CURCDB_B         (ushort)0x004D
 706 #define ASCV_RCLUN_B          (ushort)0x004E
 707 #define ASCV_BUSY_QHEAD_B     (ushort)0x004F
 708 #define ASCV_DISC1_QHEAD_B    (ushort)0x0050
 709 #define ASCV_DISC_ENABLE_B    (ushort)0x0052
 710 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
 711 #define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
 712 #define ASCV_MCODE_CNTL_B     (ushort)0x0056
 713 #define ASCV_NULL_TARGET_B    (ushort)0x0057
 714 #define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
 715 #define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
 716 #define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
 717 #define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
 718 #define ASCV_HOST_FLAG_B      (ushort)0x005D
 719 #define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
 720 #define ASCV_VER_SERIAL_B     (ushort)0x0065
 721 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
 722 #define ASCV_WTM_FLAG_B       (ushort)0x0068
 723 #define ASCV_RISC_FLAG_B      (ushort)0x006A
 724 #define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
 725 #define ASC_HOST_FLAG_IN_ISR        0x01
 726 #define ASC_HOST_FLAG_ACK_INT       0x02
 727 #define ASC_RISC_FLAG_GEN_INT      0x01
 728 #define ASC_RISC_FLAG_REQ_SG_LIST  0x02
 729 #define IOP_CTRL         (0x0F)
 730 #define IOP_STATUS       (0x0E)
 731 #define IOP_INT_ACK      IOP_STATUS
 732 #define IOP_REG_IFC      (0x0D)
 733 #define IOP_SYN_OFFSET    (0x0B)
 734 #define IOP_EXTRA_CONTROL (0x0D)
 735 #define IOP_REG_PC        (0x0C)
 736 #define IOP_RAM_ADDR      (0x0A)
 737 #define IOP_RAM_DATA      (0x08)
 738 #define IOP_EEP_DATA      (0x06)
 739 #define IOP_EEP_CMD       (0x07)
 740 #define IOP_VERSION       (0x03)
 741 #define IOP_CONFIG_HIGH   (0x04)
 742 #define IOP_CONFIG_LOW    (0x02)
 743 #define IOP_SIG_BYTE      (0x01)
 744 #define IOP_SIG_WORD      (0x00)
 745 #define IOP_REG_DC1      (0x0E)
 746 #define IOP_REG_DC0      (0x0C)
 747 #define IOP_REG_SB       (0x0B)
 748 #define IOP_REG_DA1      (0x0A)
 749 #define IOP_REG_DA0      (0x08)
 750 #define IOP_REG_SC       (0x09)
 751 #define IOP_DMA_SPEED    (0x07)
 752 #define IOP_REG_FLAG     (0x07)
 753 #define IOP_FIFO_H       (0x06)
 754 #define IOP_FIFO_L       (0x04)
 755 #define IOP_REG_ID       (0x05)
 756 #define IOP_REG_QP       (0x03)
 757 #define IOP_REG_IH       (0x02)
 758 #define IOP_REG_IX       (0x01)
 759 #define IOP_REG_AX       (0x00)
 760 #define IFC_REG_LOCK      (0x00)
 761 #define IFC_REG_UNLOCK    (0x09)
 762 #define IFC_WR_EN_FILTER  (0x10)
 763 #define IFC_RD_NO_EEPROM  (0x10)
 764 #define IFC_SLEW_RATE     (0x20)
 765 #define IFC_ACT_NEG       (0x40)
 766 #define IFC_INP_FILTER    (0x80)
 767 #define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
 768 #define SC_SEL   (uchar)(0x80)
 769 #define SC_BSY   (uchar)(0x40)
 770 #define SC_ACK   (uchar)(0x20)
 771 #define SC_REQ   (uchar)(0x10)
 772 #define SC_ATN   (uchar)(0x08)
 773 #define SC_IO    (uchar)(0x04)
 774 #define SC_CD    (uchar)(0x02)
 775 #define SC_MSG   (uchar)(0x01)
 776 #define SEC_SCSI_CTL         (uchar)(0x80)
 777 #define SEC_ACTIVE_NEGATE    (uchar)(0x40)
 778 #define SEC_SLEW_RATE        (uchar)(0x20)
 779 #define SEC_ENABLE_FILTER    (uchar)(0x10)
 780 #define ASC_HALT_EXTMSG_IN     (ushort)0x8000
 781 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
 782 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
 783 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
 784 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
 785 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
 786 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
 787 #define ASC_MAX_QNO        0xF8
 788 #define ASC_DATA_SEC_BEG   (ushort)0x0080
 789 #define ASC_DATA_SEC_END   (ushort)0x0080
 790 #define ASC_CODE_SEC_BEG   (ushort)0x0080
 791 #define ASC_CODE_SEC_END   (ushort)0x0080
 792 #define ASC_QADR_BEG       (0x4000)
 793 #define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
 794 #define ASC_QADR_END       (ushort)0x7FFF
 795 #define ASC_QLAST_ADR      (ushort)0x7FC0
 796 #define ASC_QBLK_SIZE      0x40
 797 #define ASC_BIOS_DATA_QBEG 0xF8
 798 #define ASC_MIN_ACTIVE_QNO 0x01
 799 #define ASC_QLINK_END      0xFF
 800 #define ASC_EEPROM_WORDS   0x10
 801 #define ASC_MAX_MGS_LEN    0x10
 802 #define ASC_BIOS_ADDR_DEF  0xDC00
 803 #define ASC_BIOS_SIZE      0x3800
 804 #define ASC_BIOS_RAM_OFF   0x3800
 805 #define ASC_BIOS_RAM_SIZE  0x800
 806 #define ASC_BIOS_MIN_ADDR  0xC000
 807 #define ASC_BIOS_MAX_ADDR  0xEC00
 808 #define ASC_BIOS_BANK_SIZE 0x0400
 809 #define ASC_MCODE_START_ADDR  0x0080
 810 #define ASC_CFG0_HOST_INT_ON    0x0020
 811 #define ASC_CFG0_BIOS_ON        0x0040
 812 #define ASC_CFG0_VERA_BURST_ON  0x0080
 813 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
 814 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
 815 #define ASC_CFG1_LRAM_8BITS_ON  0x0800
 816 #define ASC_CFG_MSW_CLR_MASK    0x3080
 817 #define CSW_TEST1             (ASC_CS_TYPE)0x8000
 818 #define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
 819 #define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
 820 #define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
 821 #define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
 822 #define CSW_TEST2             (ASC_CS_TYPE)0x0400
 823 #define CSW_TEST3             (ASC_CS_TYPE)0x0200
 824 #define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
 825 #define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
 826 #define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
 827 #define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
 828 #define CSW_HALTED            (ASC_CS_TYPE)0x0010
 829 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
 830 #define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
 831 #define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
 832 #define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
 833 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
 834 #define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
 835 #define CIW_TEST1        (ASC_CS_TYPE)0x0200
 836 #define CIW_TEST2        (ASC_CS_TYPE)0x0400
 837 #define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
 838 #define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
 839 #define CC_CHIP_RESET   (uchar)0x80
 840 #define CC_SCSI_RESET   (uchar)0x40
 841 #define CC_HALT         (uchar)0x20
 842 #define CC_SINGLE_STEP  (uchar)0x10
 843 #define CC_DMA_ABLE     (uchar)0x08
 844 #define CC_TEST         (uchar)0x04
 845 #define CC_BANK_ONE     (uchar)0x02
 846 #define CC_DIAG         (uchar)0x01
 847 #define ASC_1000_ID0W      0x04C1
 848 #define ASC_1000_ID0W_FIX  0x00C1
 849 #define ASC_1000_ID1B      0x25
 850 #define ASC_EISA_REV_IOP_MASK  (0x0C83)
 851 #define ASC_EISA_CFG_IOP_MASK  (0x0C86)
 852 #define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
 853 #define INS_HALTINT        (ushort)0x6281
 854 #define INS_HALT           (ushort)0x6280
 855 #define INS_SINT           (ushort)0x6200
 856 #define INS_RFLAG_WTM      (ushort)0x7380
 857 #define ASC_MC_SAVE_CODE_WSIZE  0x500
 858 #define ASC_MC_SAVE_DATA_WSIZE  0x40
 859
 860 typedef struct asc_mc_saved {
 861         ushort data[ASC_MC_SAVE_DATA_WSIZE];
 862         ushort code[ASC_MC_SAVE_CODE_WSIZE];
 863 } ASC_MC_SAVED;
 864
 865 #define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
 866 #define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
 867 #define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
 868 #define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
 869 #define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
 870 #define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
 871 #define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
 872 #define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
 873 #define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
 874 #define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
 875 #define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
 876 #define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
 877 #define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
 878 #define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
 879 #define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
 880 #define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
 881 #define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
 882 #define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
 883 #define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
 884 #define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
 885 #define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
 886 #define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
 887 #define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
 888 #define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
 889 #define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
 890 #define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
 891 #define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
 892 #define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
 893 #define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
 894 #define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
 895 #define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
 896 #define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
 897 #define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
 898 #define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
 899 #define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
 900 #define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
 901 #define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
 902 #define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
 903 #define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
 904 #define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
 905 #define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
 906 #define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
 907 #define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
 908 #define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
 909 #define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
 910 #define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
 911 #define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
 912 #define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
 913 #define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
 914 #define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
 915 #define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
 916 #define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
 917 #define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
 918 #define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
 919 #define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
 920 #define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
 921 #define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
 922 #define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
 923 #define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
 924 #define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
 925 #define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
 926 #define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
 927 #define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
 928 #define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
 929 #define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
 930 #define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
 931 #define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
 932
 933 /*
 934  * Portable Data Types
 935  *
 936  * Any instance where a 32-bit long or pointer type is assumed
 937  * for precision or HW defined structures, the following define
 938  * types must be used. In Linux the char, short, and int types
 939  * are all consistent at 8, 16, and 32 bits respectively. Pointers
 940  * and long types are 64 bits on Alpha and UltraSPARC.
 941  */
 942 #define ADV_PADDR __u32         /* Physical address data type. */
 943 #define ADV_VADDR __u32         /* Virtual address data type. */
 944 #define ADV_DCNT  __u32         /* Unsigned Data count type. */
 945 #define ADV_SDCNT __s32         /* Signed Data count type. */
 946
 947 /*
 948  * These macros are used to convert a virtual address to a
 949  * 32-bit value. This currently can be used on Linux Alpha
 950  * which uses 64-bit virtual address but a 32-bit bus address.
 951  * This is likely to break in the future, but doing this now
 952  * will give us time to change the HW and FW to handle 64-bit
 953  * addresses.
 954  */
 955 #define ADV_VADDR_TO_U32   virt_to_bus
 956 #define ADV_U32_TO_VADDR   bus_to_virt
 957
 958 #define AdvPortAddr  void __iomem *     /* Virtual memory address size */
 959
 960 /*
 961  * Define Adv Library required memory access macros.
 962  */
 963 #define ADV_MEM_READB(addr) readb(addr)
 964 #define ADV_MEM_READW(addr) readw(addr)
 965 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
 966 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
 967 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
 968
 969 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
 970
 971 /*
 972  * Define total number of simultaneous maximum element scatter-gather
 973  * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
 974  * maximum number of outstanding commands per wide host adapter. Each
 975  * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
 976  * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
 977  * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
 978  * structures or 255 scatter-gather elements.
 979  */
 980 #define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
 981
 982 /*
 983  * Define maximum number of scatter-gather elements per request.
 984  */
 985 #define ADV_MAX_SG_LIST         255
 986 #define NO_OF_SG_PER_BLOCK              15
 987
 988 #define ADV_EEP_DVC_CFG_BEGIN           (0x00)
 989 #define ADV_EEP_DVC_CFG_END             (0x15)
 990 #define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
 991 #define ADV_EEP_MAX_WORD_ADDR           (0x1E)
 992
 993 #define ADV_EEP_DELAY_MS                100
 994
 995 #define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
 996 #define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
 997 /*
 998  * For the ASC3550 Bit 13 is Termination Polarity control bit.
 999  * For later ICs Bit 13 controls whether the CIS (Card Information
1000  * Service Section) is loaded from EEPROM.
1001  */
1002 #define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
1003 #define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
1004 /*
1005  * ASC38C1600 Bit 11
1006  *
1007  * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1008  * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1009  * Function 0 will specify INT B.
1010  *
1011  * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1012  * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1013  * Function 1 will specify INT A.
1014  */
1015 #define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
1016
1017 typedef struct adveep_3550_config {
1018         /* Word Offset, Description */
1019
1020         ushort cfg_lsw;         /* 00 power up initialization */
1021         /*  bit 13 set - Term Polarity Control */
1022         /*  bit 14 set - BIOS Enable */
1023         /*  bit 15 set - Big Endian Mode */
1024         ushort cfg_msw;         /* 01 unused      */
1025         ushort disc_enable;     /* 02 disconnect enable */
1026         ushort wdtr_able;       /* 03 Wide DTR able */
1027         ushort sdtr_able;       /* 04 Synchronous DTR able */
1028         ushort start_motor;     /* 05 send start up motor */
1029         ushort tagqng_able;     /* 06 tag queuing able */
1030         ushort bios_scan;       /* 07 BIOS device control */
1031         ushort scam_tolerant;   /* 08 no scam */
1032
1033         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1034         uchar bios_boot_delay;  /*    power up wait */
1035
1036         uchar scsi_reset_delay; /* 10 reset delay */
1037         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1038         /*    high nibble is lun */
1039         /*    low nibble is scsi id */
1040
1041         uchar termination;      /* 11 0 - automatic */
1042         /*    1 - low off / high off */
1043         /*    2 - low off / high on */
1044         /*    3 - low on  / high on */
1045         /*    There is no low on  / high off */
1046
1047         uchar reserved1;        /*    reserved byte (not used) */
1048
1049         ushort bios_ctrl;       /* 12 BIOS control bits */
1050         /*  bit 0  BIOS don't act as initiator. */
1051         /*  bit 1  BIOS > 1 GB support */
1052         /*  bit 2  BIOS > 2 Disk Support */
1053         /*  bit 3  BIOS don't support removables */
1054         /*  bit 4  BIOS support bootable CD */
1055         /*  bit 5  BIOS scan enabled */
1056         /*  bit 6  BIOS support multiple LUNs */
1057         /*  bit 7  BIOS display of message */
1058         /*  bit 8  SCAM disabled */
1059         /*  bit 9  Reset SCSI bus during init. */
1060         /*  bit 10 */
1061         /*  bit 11 No verbose initialization. */
1062         /*  bit 12 SCSI parity enabled */
1063         /*  bit 13 */
1064         /*  bit 14 */
1065         /*  bit 15 */
1066         ushort ultra_able;      /* 13 ULTRA speed able */
1067         ushort reserved2;       /* 14 reserved */
1068         uchar max_host_qng;     /* 15 maximum host queuing */
1069         uchar max_dvc_qng;      /*    maximum per device queuing */
1070         ushort dvc_cntl;        /* 16 control bit for driver */
1071         ushort bug_fix;         /* 17 control bit for bug fix */
1072         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1073         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1074         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1075         ushort check_sum;       /* 21 EEP check sum */
1076         uchar oem_name[16];     /* 22 OEM name */
1077         ushort dvc_err_code;    /* 30 last device driver error code */
1078         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1079         ushort adv_err_addr;    /* 32 last uc error address */
1080         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1081         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1082         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1083         ushort num_of_err;      /* 36 number of error */
1084 } ADVEEP_3550_CONFIG;
1085
1086 typedef struct adveep_38C0800_config {
1087         /* Word Offset, Description */
1088
1089         ushort cfg_lsw;         /* 00 power up initialization */
1090         /*  bit 13 set - Load CIS */
1091         /*  bit 14 set - BIOS Enable */
1092         /*  bit 15 set - Big Endian Mode */
1093         ushort cfg_msw;         /* 01 unused      */
1094         ushort disc_enable;     /* 02 disconnect enable */
1095         ushort wdtr_able;       /* 03 Wide DTR able */
1096         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1097         ushort start_motor;     /* 05 send start up motor */
1098         ushort tagqng_able;     /* 06 tag queuing able */
1099         ushort bios_scan;       /* 07 BIOS device control */
1100         ushort scam_tolerant;   /* 08 no scam */
1101
1102         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1103         uchar bios_boot_delay;  /*    power up wait */
1104
1105         uchar scsi_reset_delay; /* 10 reset delay */
1106         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1107         /*    high nibble is lun */
1108         /*    low nibble is scsi id */
1109
1110         uchar termination_se;   /* 11 0 - automatic */
1111         /*    1 - low off / high off */
1112         /*    2 - low off / high on */
1113         /*    3 - low on  / high on */
1114         /*    There is no low on  / high off */
1115
1116         uchar termination_lvd;  /* 11 0 - automatic */
1117         /*    1 - low off / high off */
1118         /*    2 - low off / high on */
1119         /*    3 - low on  / high on */
1120         /*    There is no low on  / high off */
1121
1122         ushort bios_ctrl;       /* 12 BIOS control bits */
1123         /*  bit 0  BIOS don't act as initiator. */
1124         /*  bit 1  BIOS > 1 GB support */
1125         /*  bit 2  BIOS > 2 Disk Support */
1126         /*  bit 3  BIOS don't support removables */
1127         /*  bit 4  BIOS support bootable CD */
1128         /*  bit 5  BIOS scan enabled */
1129         /*  bit 6  BIOS support multiple LUNs */
1130         /*  bit 7  BIOS display of message */
1131         /*  bit 8  SCAM disabled */
1132         /*  bit 9  Reset SCSI bus during init. */
1133         /*  bit 10 */
1134         /*  bit 11 No verbose initialization. */
1135         /*  bit 12 SCSI parity enabled */
1136         /*  bit 13 */
1137         /*  bit 14 */
1138         /*  bit 15 */
1139         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1140         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1141         uchar max_host_qng;     /* 15 maximum host queueing */
1142         uchar max_dvc_qng;      /*    maximum per device queuing */
1143         ushort dvc_cntl;        /* 16 control bit for driver */
1144         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1145         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1146         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1147         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1148         ushort check_sum;       /* 21 EEP check sum */
1149         uchar oem_name[16];     /* 22 OEM name */
1150         ushort dvc_err_code;    /* 30 last device driver error code */
1151         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1152         ushort adv_err_addr;    /* 32 last uc error address */
1153         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1154         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1155         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1156         ushort reserved36;      /* 36 reserved */
1157         ushort reserved37;      /* 37 reserved */
1158         ushort reserved38;      /* 38 reserved */
1159         ushort reserved39;      /* 39 reserved */
1160         ushort reserved40;      /* 40 reserved */
1161         ushort reserved41;      /* 41 reserved */
1162         ushort reserved42;      /* 42 reserved */
1163         ushort reserved43;      /* 43 reserved */
1164         ushort reserved44;      /* 44 reserved */
1165         ushort reserved45;      /* 45 reserved */
1166         ushort reserved46;      /* 46 reserved */
1167         ushort reserved47;      /* 47 reserved */
1168         ushort reserved48;      /* 48 reserved */
1169         ushort reserved49;      /* 49 reserved */
1170         ushort reserved50;      /* 50 reserved */
1171         ushort reserved51;      /* 51 reserved */
1172         ushort reserved52;      /* 52 reserved */
1173         ushort reserved53;      /* 53 reserved */
1174         ushort reserved54;      /* 54 reserved */
1175         ushort reserved55;      /* 55 reserved */
1176         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1177         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1178         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1179         ushort subsysid;        /* 59 SubSystem ID */
1180         ushort reserved60;      /* 60 reserved */
1181         ushort reserved61;      /* 61 reserved */
1182         ushort reserved62;      /* 62 reserved */
1183         ushort reserved63;      /* 63 reserved */
1184 } ADVEEP_38C0800_CONFIG;
1185
1186 typedef struct adveep_38C1600_config {
1187         /* Word Offset, Description */
1188
1189         ushort cfg_lsw;         /* 00 power up initialization */
1190         /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1191         /*       clear - Func. 0 INTA, Func. 1 INTB */
1192         /*  bit 13 set - Load CIS */
1193         /*  bit 14 set - BIOS Enable */
1194         /*  bit 15 set - Big Endian Mode */
1195         ushort cfg_msw;         /* 01 unused */
1196         ushort disc_enable;     /* 02 disconnect enable */
1197         ushort wdtr_able;       /* 03 Wide DTR able */
1198         ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1199         ushort start_motor;     /* 05 send start up motor */
1200         ushort tagqng_able;     /* 06 tag queuing able */
1201         ushort bios_scan;       /* 07 BIOS device control */
1202         ushort scam_tolerant;   /* 08 no scam */
1203
1204         uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1205         uchar bios_boot_delay;  /*    power up wait */
1206
1207         uchar scsi_reset_delay; /* 10 reset delay */
1208         uchar bios_id_lun;      /*    first boot device scsi id & lun */
1209         /*    high nibble is lun */
1210         /*    low nibble is scsi id */
1211
1212         uchar termination_se;   /* 11 0 - automatic */
1213         /*    1 - low off / high off */
1214         /*    2 - low off / high on */
1215         /*    3 - low on  / high on */
1216         /*    There is no low on  / high off */
1217
1218         uchar termination_lvd;  /* 11 0 - automatic */
1219         /*    1 - low off / high off */
1220         /*    2 - low off / high on */
1221         /*    3 - low on  / high on */
1222         /*    There is no low on  / high off */
1223
1224         ushort bios_ctrl;       /* 12 BIOS control bits */
1225         /*  bit 0  BIOS don't act as initiator. */
1226         /*  bit 1  BIOS > 1 GB support */
1227         /*  bit 2  BIOS > 2 Disk Support */
1228         /*  bit 3  BIOS don't support removables */
1229         /*  bit 4  BIOS support bootable CD */
1230         /*  bit 5  BIOS scan enabled */
1231         /*  bit 6  BIOS support multiple LUNs */
1232         /*  bit 7  BIOS display of message */
1233         /*  bit 8  SCAM disabled */
1234         /*  bit 9  Reset SCSI bus during init. */
1235         /*  bit 10 Basic Integrity Checking disabled */
1236         /*  bit 11 No verbose initialization. */
1237         /*  bit 12 SCSI parity enabled */
1238         /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1239         /*  bit 14 */
1240         /*  bit 15 */
1241         ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1242         ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1243         uchar max_host_qng;     /* 15 maximum host queueing */
1244         uchar max_dvc_qng;      /*    maximum per device queuing */
1245         ushort dvc_cntl;        /* 16 control bit for driver */
1246         ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1247         ushort serial_number_word1;     /* 18 Board serial number word 1 */
1248         ushort serial_number_word2;     /* 19 Board serial number word 2 */
1249         ushort serial_number_word3;     /* 20 Board serial number word 3 */
1250         ushort check_sum;       /* 21 EEP check sum */
1251         uchar oem_name[16];     /* 22 OEM name */
1252         ushort dvc_err_code;    /* 30 last device driver error code */
1253         ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1254         ushort adv_err_addr;    /* 32 last uc error address */
1255         ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1256         ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1257         ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1258         ushort reserved36;      /* 36 reserved */
1259         ushort reserved37;      /* 37 reserved */
1260         ushort reserved38;      /* 38 reserved */
1261         ushort reserved39;      /* 39 reserved */
1262         ushort reserved40;      /* 40 reserved */
1263         ushort reserved41;      /* 41 reserved */
1264         ushort reserved42;      /* 42 reserved */
1265         ushort reserved43;      /* 43 reserved */
1266         ushort reserved44;      /* 44 reserved */
1267         ushort reserved45;      /* 45 reserved */
1268         ushort reserved46;      /* 46 reserved */
1269         ushort reserved47;      /* 47 reserved */
1270         ushort reserved48;      /* 48 reserved */
1271         ushort reserved49;      /* 49 reserved */
1272         ushort reserved50;      /* 50 reserved */
1273         ushort reserved51;      /* 51 reserved */
1274         ushort reserved52;      /* 52 reserved */
1275         ushort reserved53;      /* 53 reserved */
1276         ushort reserved54;      /* 54 reserved */
1277         ushort reserved55;      /* 55 reserved */
1278         ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1279         ushort cisprt_msw;      /* 57 CIS PTR MSW */
1280         ushort subsysvid;       /* 58 SubSystem Vendor ID */
1281         ushort subsysid;        /* 59 SubSystem ID */
1282         ushort reserved60;      /* 60 reserved */
1283         ushort reserved61;      /* 61 reserved */
1284         ushort reserved62;      /* 62 reserved */
1285         ushort reserved63;      /* 63 reserved */
1286 } ADVEEP_38C1600_CONFIG;
1287
1288 /*
1289  * EEPROM Commands
1290  */
1291 #define ASC_EEP_CMD_DONE             0x0200
1292
1293 /* bios_ctrl */
1294 #define BIOS_CTRL_BIOS               0x0001
1295 #define BIOS_CTRL_EXTENDED_XLAT      0x0002
1296 #define BIOS_CTRL_GT_2_DISK          0x0004
1297 #define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1298 #define BIOS_CTRL_BOOTABLE_CD        0x0010
1299 #define BIOS_CTRL_MULTIPLE_LUN       0x0040
1300 #define BIOS_CTRL_DISPLAY_MSG        0x0080
1301 #define BIOS_CTRL_NO_SCAM            0x0100
1302 #define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1303 #define BIOS_CTRL_INIT_VERBOSE       0x0800
1304 #define BIOS_CTRL_SCSI_PARITY        0x1000
1305 #define BIOS_CTRL_AIPP_DIS           0x2000
1306
1307 #define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1308
1309 #define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1310
1311 /*
1312  * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1313  * a special 16K Adv Library and Microcode version. After the issue is
1314  * resolved, should restore 32K support.
1315  *
1316  * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1317  */
1318 #define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1319
1320 /*
1321  * Byte I/O register address from base of 'iop_base'.
1322  */
1323 #define IOPB_INTR_STATUS_REG    0x00
1324 #define IOPB_CHIP_ID_1          0x01
1325 #define IOPB_INTR_ENABLES       0x02
1326 #define IOPB_CHIP_TYPE_REV      0x03
1327 #define IOPB_RES_ADDR_4         0x04
1328 #define IOPB_RES_ADDR_5         0x05
1329 #define IOPB_RAM_DATA           0x06
1330 #define IOPB_RES_ADDR_7         0x07
1331 #define IOPB_FLAG_REG           0x08
1332 #define IOPB_RES_ADDR_9         0x09
1333 #define IOPB_RISC_CSR           0x0A
1334 #define IOPB_RES_ADDR_B         0x0B
1335 #define IOPB_RES_ADDR_C         0x0C
1336 #define IOPB_RES_ADDR_D         0x0D
1337 #define IOPB_SOFT_OVER_WR       0x0E
1338 #define IOPB_RES_ADDR_F         0x0F
1339 #define IOPB_MEM_CFG            0x10
1340 #define IOPB_RES_ADDR_11        0x11
1341 #define IOPB_GPIO_DATA          0x12
1342 #define IOPB_RES_ADDR_13        0x13
1343 #define IOPB_FLASH_PAGE         0x14
1344 #define IOPB_RES_ADDR_15        0x15
1345 #define IOPB_GPIO_CNTL          0x16
1346 #define IOPB_RES_ADDR_17        0x17
1347 #define IOPB_FLASH_DATA         0x18
1348 #define IOPB_RES_ADDR_19        0x19
1349 #define IOPB_RES_ADDR_1A        0x1A
1350 #define IOPB_RES_ADDR_1B        0x1B
1351 #define IOPB_RES_ADDR_1C        0x1C
1352 #define IOPB_RES_ADDR_1D        0x1D
1353 #define IOPB_RES_ADDR_1E        0x1E
1354 #define IOPB_RES_ADDR_1F        0x1F
1355 #define IOPB_DMA_CFG0           0x20
1356 #define IOPB_DMA_CFG1           0x21
1357 #define IOPB_TICKLE             0x22
1358 #define IOPB_DMA_REG_WR         0x23
1359 #define IOPB_SDMA_STATUS        0x24
1360 #define IOPB_SCSI_BYTE_CNT      0x25
1361 #define IOPB_HOST_BYTE_CNT      0x26
1362 #define IOPB_BYTE_LEFT_TO_XFER  0x27
1363 #define IOPB_BYTE_TO_XFER_0     0x28
1364 #define IOPB_BYTE_TO_XFER_1     0x29
1365 #define IOPB_BYTE_TO_XFER_2     0x2A
1366 #define IOPB_BYTE_TO_XFER_3     0x2B
1367 #define IOPB_ACC_GRP            0x2C
1368 #define IOPB_RES_ADDR_2D        0x2D
1369 #define IOPB_DEV_ID             0x2E
1370 #define IOPB_RES_ADDR_2F        0x2F
1371 #define IOPB_SCSI_DATA          0x30
1372 #define IOPB_RES_ADDR_31        0x31
1373 #define IOPB_RES_ADDR_32        0x32
1374 #define IOPB_SCSI_DATA_HSHK     0x33
1375 #define IOPB_SCSI_CTRL          0x34
1376 #define IOPB_RES_ADDR_35        0x35
1377 #define IOPB_RES_ADDR_36        0x36
1378 #define IOPB_RES_ADDR_37        0x37
1379 #define IOPB_RAM_BIST           0x38
1380 #define IOPB_PLL_TEST           0x39
1381 #define IOPB_PCI_INT_CFG        0x3A
1382 #define IOPB_RES_ADDR_3B        0x3B
1383 #define IOPB_RFIFO_CNT          0x3C
1384 #define IOPB_RES_ADDR_3D        0x3D
1385 #define IOPB_RES_ADDR_3E        0x3E
1386 #define IOPB_RES_ADDR_3F        0x3F
1387
1388 /*
1389  * Word I/O register address from base of 'iop_base'.
1390  */
1391 #define IOPW_CHIP_ID_0          0x00    /* CID0  */
1392 #define IOPW_CTRL_REG           0x02    /* CC    */
1393 #define IOPW_RAM_ADDR           0x04    /* LA    */
1394 #define IOPW_RAM_DATA           0x06    /* LD    */
1395 #define IOPW_RES_ADDR_08        0x08
1396 #define IOPW_RISC_CSR           0x0A    /* CSR   */
1397 #define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1398 #define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1399 #define IOPW_RES_ADDR_10        0x10
1400 #define IOPW_SEL_MASK           0x12    /* SM    */
1401 #define IOPW_RES_ADDR_14        0x14
1402 #define IOPW_FLASH_ADDR         0x16    /* FA    */
1403 #define IOPW_RES_ADDR_18        0x18
1404 #define IOPW_EE_CMD             0x1A    /* EC    */
1405 #define IOPW_EE_DATA            0x1C    /* ED    */
1406 #define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1407 #define IOPW_RES_ADDR_20        0x20
1408 #define IOPW_Q_BASE             0x22    /* QB    */
1409 #define IOPW_QP                 0x24    /* QP    */
1410 #define IOPW_IX                 0x26    /* IX    */
1411 #define IOPW_SP                 0x28    /* SP    */
1412 #define IOPW_PC                 0x2A    /* PC    */
1413 #define IOPW_RES_ADDR_2C        0x2C
1414 #define IOPW_RES_ADDR_2E        0x2E
1415 #define IOPW_SCSI_DATA          0x30    /* SD    */
1416 #define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1417 #define IOPW_SCSI_CTRL          0x34    /* SC    */
1418 #define IOPW_HSHK_CFG           0x36    /* HCFG  */
1419 #define IOPW_SXFR_STATUS        0x36    /* SXS   */
1420 #define IOPW_SXFR_CNTL          0x38    /* SXL   */
1421 #define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1422 #define IOPW_RES_ADDR_3C        0x3C
1423 #define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1424
1425 /*
1426  * Doubleword I/O register address from base of 'iop_base'.
1427  */
1428 #define IOPDW_RES_ADDR_0         0x00
1429 #define IOPDW_RAM_DATA           0x04
1430 #define IOPDW_RES_ADDR_8         0x08
1431 #define IOPDW_RES_ADDR_C         0x0C
1432 #define IOPDW_RES_ADDR_10        0x10
1433 #define IOPDW_COMMA              0x14
1434 #define IOPDW_COMMB              0x18
1435 #define IOPDW_RES_ADDR_1C        0x1C
1436 #define IOPDW_SDMA_ADDR0         0x20
1437 #define IOPDW_SDMA_ADDR1         0x24
1438 #define IOPDW_SDMA_COUNT         0x28
1439 #define IOPDW_SDMA_ERROR         0x2C
1440 #define IOPDW_RDMA_ADDR0         0x30
1441 #define IOPDW_RDMA_ADDR1         0x34
1442 #define IOPDW_RDMA_COUNT         0x38
1443 #define IOPDW_RDMA_ERROR         0x3C
1444
1445 #define ADV_CHIP_ID_BYTE         0x25
1446 #define ADV_CHIP_ID_WORD         0x04C1
1447
1448 #define ADV_INTR_ENABLE_HOST_INTR                   0x01
1449 #define ADV_INTR_ENABLE_SEL_INTR                    0x02
1450 #define ADV_INTR_ENABLE_DPR_INTR                    0x04
1451 #define ADV_INTR_ENABLE_RTA_INTR                    0x08
1452 #define ADV_INTR_ENABLE_RMA_INTR                    0x10
1453 #define ADV_INTR_ENABLE_RST_INTR                    0x20
1454 #define ADV_INTR_ENABLE_DPE_INTR                    0x40
1455 #define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1456
1457 #define ADV_INTR_STATUS_INTRA            0x01
1458 #define ADV_INTR_STATUS_INTRB            0x02
1459 #define ADV_INTR_STATUS_INTRC            0x04
1460
1461 #define ADV_RISC_CSR_STOP           (0x0000)
1462 #define ADV_RISC_TEST_COND          (0x2000)
1463 #define ADV_RISC_CSR_RUN            (0x4000)
1464 #define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1465
1466 #define ADV_CTRL_REG_HOST_INTR      0x0100
1467 #define ADV_CTRL_REG_SEL_INTR       0x0200
1468 #define ADV_CTRL_REG_DPR_INTR       0x0400
1469 #define ADV_CTRL_REG_RTA_INTR       0x0800
1470 #define ADV_CTRL_REG_RMA_INTR       0x1000
1471 #define ADV_CTRL_REG_RES_BIT14      0x2000
1472 #define ADV_CTRL_REG_DPE_INTR       0x4000
1473 #define ADV_CTRL_REG_POWER_DONE     0x8000
1474 #define ADV_CTRL_REG_ANY_INTR       0xFF00
1475
1476 #define ADV_CTRL_REG_CMD_RESET             0x00C6
1477 #define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1478 #define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1479 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1480 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1481
1482 #define ADV_TICKLE_NOP                      0x00
1483 #define ADV_TICKLE_A                        0x01
1484 #define ADV_TICKLE_B                        0x02
1485 #define ADV_TICKLE_C                        0x03
1486
1487 #define AdvIsIntPending(port) \
1488     (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1489
1490 /*
1491  * SCSI_CFG0 Register bit definitions
1492  */
1493 #define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1494 #define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1495 #define EVEN_PARITY     0x1000  /* Select Even Parity */
1496 #define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1497 #define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1498 #define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1499 #define SCAM_EN         0x0080  /* Enable SCAM selection */
1500 #define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1501 #define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1502 #define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1503 #define OUR_ID          0x000F  /* SCSI ID */
1504
1505 /*
1506  * SCSI_CFG1 Register bit definitions
1507  */
1508 #define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1509 #define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1510 #define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1511 #define FILTER_SEL      0x0C00  /* Filter Period Selection */
1512 #define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1513 #define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1514 #define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1515 #define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1516 #define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1517 #define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1518 #define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1519 #define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1520 #define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1521 #define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1522 #define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1523
1524 /*
1525  * Addendum for ASC-38C0800 Chip
1526  *
1527  * The ASC-38C1600 Chip uses the same definitions except that the
1528  * bus mode override bits [12:10] have been moved to byte register
1529  * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1530  * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1531  * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1532  * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1533  * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1534  */
1535 #define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1536 #define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1537 #define  HVD             0x1000 /* HVD Device Detect */
1538 #define  LVD             0x0800 /* LVD Device Detect */
1539 #define  SE              0x0400 /* SE Device Detect */
1540 #define TERM_LVD        0x00C0  /* LVD Termination Bits */
1541 #define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1542 #define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1543 #define TERM_SE         0x0030  /* SE Termination Bits */
1544 #define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1545 #define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1546 #define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1547 #define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1548 #define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1549 #define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1550 #define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1551 #define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1552
1553 #define CABLE_ILLEGAL_A 0x7
1554     /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1555
1556 #define CABLE_ILLEGAL_B 0xB
1557     /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1558
1559 /*
1560  * MEM_CFG Register bit definitions
1561  */
1562 #define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1563 #define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1564 #define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1565 #define  RAM_SZ_2KB      0x00   /* 2 KB */
1566 #define  RAM_SZ_4KB      0x04   /* 4 KB */
1567 #define  RAM_SZ_8KB      0x08   /* 8 KB */
1568 #define  RAM_SZ_16KB     0x0C   /* 16 KB */
1569 #define  RAM_SZ_32KB     0x10   /* 32 KB */
1570 #define  RAM_SZ_64KB     0x14   /* 64 KB */
1571
1572 /*
1573  * DMA_CFG0 Register bit definitions
1574  *
1575  * This register is only accessible to the host.
1576  */
1577 #define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1578 #define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1579 #define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1580 #define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1581 #define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1582 #define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1583 #define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1584 #define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1585 #define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1586 #define START_CTL       0x0C    /* DMA start conditions */
1587 #define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1588 #define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1589 #define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1590 #define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1591 #define READ_CMD        0x03    /* Memory Read Method */
1592 #define  READ_CMD_MR     0x00   /* Memory Read */
1593 #define  READ_CMD_MRL    0x02   /* Memory Read Long */
1594 #define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1595
1596 /*
1597  * ASC-38C0800 RAM BIST Register bit definitions
1598  */
1599 #define RAM_TEST_MODE         0x80
1600 #define PRE_TEST_MODE         0x40
1601 #define NORMAL_MODE           0x00
1602 #define RAM_TEST_DONE         0x10
1603 #define RAM_TEST_STATUS       0x0F
1604 #define  RAM_TEST_HOST_ERROR   0x08
1605 #define  RAM_TEST_INTRAM_ERROR 0x04
1606 #define  RAM_TEST_RISC_ERROR   0x02
1607 #define  RAM_TEST_SCSI_ERROR   0x01
1608 #define  RAM_TEST_SUCCESS      0x00
1609 #define PRE_TEST_VALUE        0x05
1610 #define NORMAL_VALUE          0x00
1611
1612 /*
1613  * ASC38C1600 Definitions
1614  *
1615  * IOPB_PCI_INT_CFG Bit Field Definitions
1616  */
1617
1618 #define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1619
1620 /*
1621  * Bit 1 can be set to change the interrupt for the Function to operate in
1622  * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1623  * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1624  * mode, otherwise the operating mode is undefined.
1625  */
1626 #define TOTEMPOLE       0x02
1627
1628 /*
1629  * Bit 0 can be used to change the Int Pin for the Function. The value is
1630  * 0 by default for both Functions with Function 0 using INT A and Function
1631  * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1632  * INT A is used.
1633  *
1634  * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1635  * value specified in the PCI Configuration Space.
1636  */
1637 #define INTAB           0x01
1638
1639 /*
1640  * Adv Library Status Definitions
1641  */
1642 #define ADV_TRUE        1
1643 #define ADV_FALSE       0
1644 #define ADV_SUCCESS     1
1645 #define ADV_BUSY        0
1646 #define ADV_ERROR       (-1)
1647
1648 /*
1649  * ADV_DVC_VAR 'warn_code' values
1650  */
1651 #define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1652 #define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1653 #define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1654 #define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1655
1656 #define ADV_MAX_TID                     15      /* max. target identifier */
1657 #define ADV_MAX_LUN                     7       /* max. logical unit number */
1658
1659 /*
1660  * Fixed locations of microcode operating variables.
1661  */
1662 #define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1663 #define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1664 #define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1665 #define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1666 #define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1667 #define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1668 #define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1669 #define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1670 #define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1671 #define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1672 #define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1673 #define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1674 #define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1675 #define ASC_MC_CHIP_TYPE                0x009A
1676 #define ASC_MC_INTRB_CODE               0x009B
1677 #define ASC_MC_WDTR_ABLE                0x009C
1678 #define ASC_MC_SDTR_ABLE                0x009E
1679 #define ASC_MC_TAGQNG_ABLE              0x00A0
1680 #define ASC_MC_DISC_ENABLE              0x00A2
1681 #define ASC_MC_IDLE_CMD_STATUS          0x00A4
1682 #define ASC_MC_IDLE_CMD                 0x00A6
1683 #define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1684 #define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1685 #define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1686 #define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1687 #define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1688 #define ASC_MC_SDTR_DONE                0x00B6
1689 #define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1690 #define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1691 #define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1692 #define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1693 #define ASC_MC_WDTR_DONE                0x0124
1694 #define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1695 #define ASC_MC_ICQ                      0x0160
1696 #define ASC_MC_IRQ                      0x0164
1697 #define ASC_MC_PPR_ABLE                 0x017A
1698
1699 /*
1700  * BIOS LRAM variable absolute offsets.
1701  */
1702 #define BIOS_CODESEG    0x54
1703 #define BIOS_CODELEN    0x56
1704 #define BIOS_SIGNATURE  0x58
1705 #define BIOS_VERSION    0x5A
1706
1707 /*
1708  * Microcode Control Flags
1709  *
1710  * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1711  * and handled by the microcode.
1712  */
1713 #define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1714 #define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1715
1716 /*
1717  * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1718  */
1719 #define HSHK_CFG_WIDE_XFR       0x8000
1720 #define HSHK_CFG_RATE           0x0F00
1721 #define HSHK_CFG_OFFSET         0x001F
1722
1723 #define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1724 #define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1725 #define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1726 #define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1727
1728 #define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1729 #define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1730 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1731 #define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1732 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1733
1734 #define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1735 #define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1736 #define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1737 #define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1738 #define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1739 /*
1740  * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1741  * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1742  */
1743 #define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1744 #define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1745
1746 /*
1747  * All fields here are accessed by the board microcode and need to be
1748  * little-endian.
1749  */
1750 typedef struct adv_carr_t {
1751         ADV_VADDR carr_va;      /* Carrier Virtual Address */
1752         ADV_PADDR carr_pa;      /* Carrier Physical Address */
1753         ADV_VADDR areq_vpa;     /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1754         /*
1755          * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1756          *
1757          * next_vpa [3:1]             Reserved Bits
1758          * next_vpa [0]               Done Flag set in Response Queue.
1759          */
1760         ADV_VADDR next_vpa;
1761 } ADV_CARR_T;
1762
1763 /*
1764  * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1765  */
1766 #define ASC_NEXT_VPA_MASK       0xFFFFFFF0
1767
1768 #define ASC_RQ_DONE             0x00000001
1769 #define ASC_RQ_GOOD             0x00000002
1770 #define ASC_CQ_STOPPER          0x00000000
1771
1772 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1773
1774 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1775     (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1776
1777 #define ADV_CARRIER_BUFSIZE \
1778     ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1779
1780 /*
1781  * ASC_SCSI_REQ_Q 'a_flag' definitions
1782  *
1783  * The Adv Library should limit use to the lower nibble (4 bits) of
1784  * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1785  */
1786 #define ADV_POLL_REQUEST                0x01    /* poll for request completion */
1787 #define ADV_SCSIQ_DONE                  0x02    /* request done */
1788 #define ADV_DONT_RETRY                  0x08    /* don't do retry */
1789
1790 #define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1791 #define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1792 #define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1793
1794 /*
1795  * Adapter temporary configuration structure
1796  *
1797  * This structure can be discarded after initialization. Don't add
1798  * fields here needed after initialization.
1799  *
1800  * Field naming convention:
1801  *
1802  *  *_enable indicates the field enables or disables a feature. The
1803  *  value of the field is never reset.
1804  */
1805 typedef struct adv_dvc_cfg {
1806         ushort disc_enable;     /* enable disconnection */
1807         uchar chip_version;     /* chip version */
1808         uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1809         ushort control_flag;    /* Microcode Control Flag */
1810         ushort mcode_date;      /* Microcode date */
1811         ushort mcode_version;   /* Microcode version */
1812         ushort serial1;         /* EEPROM serial number word 1 */
1813         ushort serial2;         /* EEPROM serial number word 2 */
1814         ushort serial3;         /* EEPROM serial number word 3 */
1815 } ADV_DVC_CFG;
1816
1817 struct adv_dvc_var;
1818 struct adv_scsi_req_q;
1819
1820 typedef struct asc_sg_block {
1821         uchar reserved1;
1822         uchar reserved2;
1823         uchar reserved3;
1824         uchar sg_cnt;           /* Valid entries in block. */
1825         ADV_PADDR sg_ptr;       /* Pointer to next sg block. */
1826         struct {
1827                 ADV_PADDR sg_addr;      /* SG element address. */
1828                 ADV_DCNT sg_count;      /* SG element count. */
1829         } sg_list[NO_OF_SG_PER_BLOCK];
1830 } ADV_SG_BLOCK;
1831
1832 /*
1833  * ADV_SCSI_REQ_Q - microcode request structure
1834  *
1835  * All fields in this structure up to byte 60 are used by the microcode.
1836  * The microcode makes assumptions about the size and ordering of fields
1837  * in this structure. Do not change the structure definition here without
1838  * coordinating the change with the microcode.
1839  *
1840  * All fields accessed by microcode must be maintained in little_endian
1841  * order.
1842  */
1843 typedef struct adv_scsi_req_q {
1844         uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1845         uchar target_cmd;
1846         uchar target_id;        /* Device target identifier. */
1847         uchar target_lun;       /* Device target logical unit number. */
1848         ADV_PADDR data_addr;    /* Data buffer physical address. */
1849         ADV_DCNT data_cnt;      /* Data count. Ucode sets to residual. */
1850         ADV_PADDR sense_addr;
1851         ADV_PADDR carr_pa;
1852         uchar mflag;
1853         uchar sense_len;
1854         uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1855         uchar scsi_cntl;
1856         uchar done_status;      /* Completion status. */
1857         uchar scsi_status;      /* SCSI status byte. */
1858         uchar host_status;      /* Ucode host status. */
1859         uchar sg_working_ix;
1860         uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1861         ADV_PADDR sg_real_addr; /* SG list physical address. */
1862         ADV_PADDR scsiq_rptr;
1863         uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1864         ADV_VADDR scsiq_ptr;
1865         ADV_VADDR carr_va;
1866         /*
1867          * End of microcode structure - 60 bytes. The rest of the structure
1868          * is used by the Adv Library and ignored by the microcode.
1869          */
1870         ADV_VADDR srb_ptr;
1871         ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1872         char *vdata_addr;       /* Data buffer virtual address. */
1873         uchar a_flag;
1874         uchar pad[2];           /* Pad out to a word boundary. */
1875 } ADV_SCSI_REQ_Q;
1876
1877 /*
1878  * The following two structures are used to process Wide Board requests.
1879  *
1880  * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1881  * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1882  * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1883  * Mid-Level SCSI request structure.
1884  *
1885  * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1886  * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1887  * up to 255 scatter-gather elements may be used per request or
1888  * ADV_SCSI_REQ_Q.
1889  *
1890  * Both structures must be 32 byte aligned.
1891  */
1892 typedef struct adv_sgblk {
1893         ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1894         uchar align[32];        /* Sgblock structure padding. */
1895         struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1896 } adv_sgblk_t;
1897
1898 typedef struct adv_req {
1899         ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1900         uchar align[32];        /* Request structure padding. */
1901         struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1902         adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1903         struct adv_req *next_reqp;      /* Next Request Structure. */
1904 } adv_req_t;
1905
1906 /*
1907  * Adapter operation variable structure.
1908  *
1909  * One structure is required per host adapter.
1910  *
1911  * Field naming convention:
1912  *
1913  *  *_able indicates both whether a feature should be enabled or disabled
1914  *  and whether a device isi capable of the feature. At initialization
1915  *  this field may be set, but later if a device is found to be incapable
1916  *  of the feature, the field is cleared.
1917  */
1918 typedef struct adv_dvc_var {
1919         AdvPortAddr iop_base;   /* I/O port address */
1920         ushort err_code;        /* fatal error code */
1921         ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1922         ushort wdtr_able;       /* try WDTR for a device */
1923         ushort sdtr_able;       /* try SDTR for a device */
1924         ushort ultra_able;      /* try SDTR Ultra speed for a device */
1925         ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1926         ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1927         ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1928         ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1929         ushort tagqng_able;     /* try tagged queuing with a device */
1930         ushort ppr_able;        /* PPR message capable per TID bitmask. */
1931         uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1932         ushort start_motor;     /* start motor command allowed */
1933         uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1934         uchar chip_no;          /* should be assigned by caller */
1935         uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1936         ushort no_scam;         /* scam_tolerant of EEPROM */
1937         struct asc_board *drv_ptr;      /* driver pointer to private structure */
1938         uchar chip_scsi_id;     /* chip SCSI target ID */
1939         uchar chip_type;
1940         uchar bist_err_code;
1941         ADV_CARR_T *carrier_buf;
1942         ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1943         ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1944         ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1945         ushort carr_pending_cnt;        /* Count of pending carriers. */
1946         struct adv_req *orig_reqp;      /* adv_req_t memory block. */
1947         /*
1948          * Note: The following fields will not be used after initialization. The
1949          * driver may discard the buffer after initialization is done.
1950          */
1951         ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1952 } ADV_DVC_VAR;
1953
1954 /*
1955  * Microcode idle loop commands
1956  */
1957 #define IDLE_CMD_COMPLETED           0
1958 #define IDLE_CMD_STOP_CHIP           0x0001
1959 #define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1960 #define IDLE_CMD_SEND_INT            0x0004
1961 #define IDLE_CMD_ABORT               0x0008
1962 #define IDLE_CMD_DEVICE_RESET        0x0010
1963 #define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1964 #define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1965 #define IDLE_CMD_SCSIREQ             0x0080
1966
1967 #define IDLE_CMD_STATUS_SUCCESS      0x0001
1968 #define IDLE_CMD_STATUS_FAILURE      0x0002
1969
1970 /*
1971  * AdvSendIdleCmd() flag definitions.
1972  */
1973 #define ADV_NOWAIT     0x01
1974
1975 /*
1976  * Wait loop time out values.
1977  */
1978 #define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1979 #define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1980 #define SCSI_MAX_RETRY               10 /* retry count */
1981
1982 #define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1983 #define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1984 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1985 #define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1986
1987 #define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1988
1989 /* Read byte from a register. */
1990 #define AdvReadByteRegister(iop_base, reg_off) \
1991      (ADV_MEM_READB((iop_base) + (reg_off)))
1992
1993 /* Write byte to a register. */
1994 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1995      (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1996
1997 /* Read word (2 bytes) from a register. */
1998 #define AdvReadWordRegister(iop_base, reg_off) \
1999      (ADV_MEM_READW((iop_base) + (reg_off)))
2000
2001 /* Write word (2 bytes) to a register. */
2002 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2003      (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2004
2005 /* Write dword (4 bytes) to a register. */
2006 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2007      (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2008
2009 /* Read byte from LRAM. */
2010 #define AdvReadByteLram(iop_base, addr, byte) \
2011 do { \
2012     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2013     (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2014 } while (0)
2015
2016 /* Write byte to LRAM. */
2017 #define AdvWriteByteLram(iop_base, addr, byte) \
2018     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2019      ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2020
2021 /* Read word (2 bytes) from LRAM. */
2022 #define AdvReadWordLram(iop_base, addr, word) \
2023 do { \
2024     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2025     (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2026 } while (0)
2027
2028 /* Write word (2 bytes) to LRAM. */
2029 #define AdvWriteWordLram(iop_base, addr, word) \
2030     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2031      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2032
2033 /* Write little-endian double word (4 bytes) to LRAM */
2034 /* Because of unspecified C language ordering don't use auto-increment. */
2035 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2036     ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2037       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2038                      cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2039      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2040       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2041                      cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2042
2043 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2044 #define AdvReadWordAutoIncLram(iop_base) \
2045      (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2046
2047 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2048 #define AdvWriteWordAutoIncLram(iop_base, word) \
2049      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2050
2051 /*
2052  * Define macro to check for Condor signature.
2053  *
2054  * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2055  * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2056  */
2057 #define AdvFindSignature(iop_base) \
2058     (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2059     ADV_CHIP_ID_BYTE) && \
2060      (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2061     ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
2062
2063 /*
2064  * Define macro to Return the version number of the chip at 'iop_base'.
2065  *
2066  * The second parameter 'bus_type' is currently unused.
2067  */
2068 #define AdvGetChipVersion(iop_base, bus_type) \
2069     AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2070
2071 /*
2072  * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2073  * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2074  *
2075  * If the request has not yet been sent to the device it will simply be
2076  * aborted from RISC memory. If the request is disconnected it will be
2077  * aborted on reselection by sending an Abort Message to the target ID.
2078  *
2079  * Return value:
2080  *      ADV_TRUE(1) - Queue was successfully aborted.
2081  *      ADV_FALSE(0) - Queue was not found on the active queue list.
2082  */
2083 #define AdvAbortQueue(asc_dvc, scsiq) \
2084         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2085                        (ADV_DCNT) (scsiq))
2086
2087 /*
2088  * Send a Bus Device Reset Message to the specified target ID.
2089  *
2090  * All outstanding commands will be purged if sending the
2091  * Bus Device Reset Message is successful.
2092  *
2093  * Return Value:
2094  *      ADV_TRUE(1) - All requests on the target are purged.
2095  *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2096  *                     are not purged.
2097  */
2098 #define AdvResetDevice(asc_dvc, target_id) \
2099         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2100                     (ADV_DCNT) (target_id))
2101
2102 /*
2103  * SCSI Wide Type definition.
2104  */
2105 #define ADV_SCSI_BIT_ID_TYPE   ushort
2106
2107 /*
2108  * AdvInitScsiTarget() 'cntl_flag' options.
2109  */
2110 #define ADV_SCAN_LUN           0x01
2111 #define ADV_CAPINFO_NOLUN      0x02
2112
2113 /*
2114  * Convert target id to target id bit mask.
2115  */
2116 #define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2117
2118 /*
2119  * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2120  */
2121
2122 #define QD_NO_STATUS         0x00       /* Request not completed yet. */
2123 #define QD_NO_ERROR          0x01
2124 #define QD_ABORTED_BY_HOST   0x02
2125 #define QD_WITH_ERROR        0x04
2126
2127 #define QHSTA_NO_ERROR              0x00
2128 #define QHSTA_M_SEL_TIMEOUT         0x11
2129 #define QHSTA_M_DATA_OVER_RUN       0x12
2130 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2131 #define QHSTA_M_QUEUE_ABORTED       0x15
2132 #define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2133 #define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2134 #define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2135 #define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2136 #define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2137 #define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2138 #define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2139 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2140 #define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2141 #define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2142 #define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2143 #define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2144 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2145 #define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2146 #define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2147 #define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2148 #define QHSTA_M_WTM_TIMEOUT         0x41
2149 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2150 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2151 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2152 #define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2153 #define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2154 #define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2155
2156 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2157 #define ADV_8BALIGN(addr)      (((ulong) (addr) + 0x7) & ~0x7)
2158 #define ADV_16BALIGN(addr)     (((ulong) (addr) + 0xF) & ~0xF)
2159 #define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2160
2161 /*
2162  * Total contiguous memory needed for driver SG blocks.
2163  *
2164  * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2165  * number of scatter-gather elements the driver supports in a
2166  * single request.
2167  */
2168
2169 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2170          (sizeof(ADV_SG_BLOCK) * \
2171           ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2172
2173 /* struct asc_board flags */
2174 #define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2175
2176 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2177
2178 #define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2179
2180 #define ASC_INFO_SIZE           128     /* advansys_info() line size */
2181
2182 #ifdef CONFIG_PROC_FS
2183 /* /proc/scsi/advansys/[0...] related definitions */
2184 #define ASC_PRTBUF_SIZE         2048
2185 #define ASC_PRTLINE_SIZE        160
2186
2187 #define ASC_PRT_NEXT() \
2188     if (cp) { \
2189         totlen += len; \
2190         leftlen -= len; \
2191         if (leftlen == 0) { \
2192             return totlen; \
2193         } \
2194         cp += len; \
2195     }
2196 #endif /* CONFIG_PROC_FS */
2197
2198 /* Asc Library return codes */
2199 #define ASC_TRUE        1
2200 #define ASC_FALSE       0
2201 #define ASC_NOERROR     1
2202 #define ASC_BUSY        0
2203 #define ASC_ERROR       (-1)
2204
2205 /* struct scsi_cmnd function return codes */
2206 #define STATUS_BYTE(byte)   (byte)
2207 #define MSG_BYTE(byte)      ((byte) << 8)
2208 #define HOST_BYTE(byte)     ((byte) << 16)
2209 #define DRIVER_BYTE(byte)   ((byte) << 24)
2210
2211 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2212 #ifndef ADVANSYS_STATS
2213 #define ASC_STATS_ADD(shost, counter, count)
2214 #else /* ADVANSYS_STATS */
2215 #define ASC_STATS_ADD(shost, counter, count) \
2216         (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2217 #endif /* ADVANSYS_STATS */
2218
2219 /* If the result wraps when calculating tenths, return 0. */
2220 #define ASC_TENTHS(num, den) \
2221     (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2222     0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2223
2224 /*
2225  * Display a message to the console.
2226  */
2227 #define ASC_PRINT(s) \
2228     { \
2229         printk("advansys: "); \
2230         printk(s); \
2231     }
2232
2233 #define ASC_PRINT1(s, a1) \
2234     { \
2235         printk("advansys: "); \
2236         printk((s), (a1)); \
2237     }
2238
2239 #define ASC_PRINT2(s, a1, a2) \
2240     { \
2241         printk("advansys: "); \
2242         printk((s), (a1), (a2)); \
2243     }
2244
2245 #define ASC_PRINT3(s, a1, a2, a3) \
2246     { \
2247         printk("advansys: "); \
2248         printk((s), (a1), (a2), (a3)); \
2249     }
2250
2251 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2252     { \
2253         printk("advansys: "); \
2254         printk((s), (a1), (a2), (a3), (a4)); \
2255     }
2256
2257 #ifndef ADVANSYS_DEBUG
2258
2259 #define ASC_DBG(lvl, s...)
2260 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2261 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2262 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2263 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2264 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2265 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2266 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2267 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2268 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2269
2270 #else /* ADVANSYS_DEBUG */
2271
2272 /*
2273  * Debugging Message Levels:
2274  * 0: Errors Only
2275  * 1: High-Level Tracing
2276  * 2-N: Verbose Tracing
2277  */
2278
2279 #define ASC_DBG(lvl, format, arg...) {                                  \
2280         if (asc_dbglvl >= (lvl))                                        \
2281                 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2282                         __func__ , ## arg);                             \
2283 }
2284
2285 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2286     { \
2287         if (asc_dbglvl >= (lvl)) { \
2288             asc_prt_scsi_host(s); \
2289         } \
2290     }
2291
2292 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2293     { \
2294         if (asc_dbglvl >= (lvl)) { \
2295             asc_prt_asc_scsi_q(scsiqp); \
2296         } \
2297     }
2298
2299 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2300     { \
2301         if (asc_dbglvl >= (lvl)) { \
2302             asc_prt_asc_qdone_info(qdone); \
2303         } \
2304     }
2305
2306 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2307     { \
2308         if (asc_dbglvl >= (lvl)) { \
2309             asc_prt_adv_scsi_req_q(scsiqp); \
2310         } \
2311     }
2312
2313 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2314     { \
2315         if (asc_dbglvl >= (lvl)) { \
2316             asc_prt_hex((name), (start), (length)); \
2317         } \
2318     }
2319
2320 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2321         ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2322
2323 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2324         ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2325
2326 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2327         ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2328 #endif /* ADVANSYS_DEBUG */
2329
2330 #ifdef ADVANSYS_STATS
2331
2332 /* Per board statistics structure */
2333 struct asc_stats {
2334         /* Driver Entrypoint Statistics */
2335         ADV_DCNT queuecommand;  /* # calls to advansys_queuecommand() */
2336         ADV_DCNT reset;         /* # calls to advansys_eh_bus_reset() */
2337         ADV_DCNT biosparam;     /* # calls to advansys_biosparam() */
2338         ADV_DCNT interrupt;     /* # advansys_interrupt() calls */
2339         ADV_DCNT callback;      /* # calls to asc/adv_isr_callback() */
2340         ADV_DCNT done;          /* # calls to request's scsi_done function */
2341         ADV_DCNT build_error;   /* # asc/adv_build_req() ASC_ERROR returns. */
2342         ADV_DCNT adv_build_noreq;       /* # adv_build_req() adv_req_t alloc. fail. */
2343         ADV_DCNT adv_build_nosg;        /* # adv_build_req() adv_sgblk_t alloc. fail. */
2344         /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2345         ADV_DCNT exe_noerror;   /* # ASC_NOERROR returns. */
2346         ADV_DCNT exe_busy;      /* # ASC_BUSY returns. */
2347         ADV_DCNT exe_error;     /* # ASC_ERROR returns. */
2348         ADV_DCNT exe_unknown;   /* # unknown returns. */
2349         /* Data Transfer Statistics */
2350         ADV_DCNT xfer_cnt;      /* # I/O requests received */
2351         ADV_DCNT xfer_elem;     /* # scatter-gather elements */
2352         ADV_DCNT xfer_sect;     /* # 512-byte blocks */
2353 };
2354 #endif /* ADVANSYS_STATS */
2355
2356 /*
2357  * Structure allocated for each board.
2358  *
2359  * This structure is allocated by scsi_host_alloc() at the end
2360  * of the 'Scsi_Host' structure starting at the 'hostdata'
2361  * field. It is guaranteed to be allocated from DMA-able memory.
2362  */
2363 struct asc_board {
2364         struct device *dev;
2365         uint flags;             /* Board flags */
2366         unsigned int irq;
2367         union {
2368                 ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2369                 ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2370         } dvc_var;
2371         union {
2372                 ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2373                 ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2374         } dvc_cfg;
2375         ushort asc_n_io_port;   /* Number I/O ports. */
2376         ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2377         ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2378         ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2379         ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2380         union {
2381                 ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2382                 ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2383                 ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2384                 ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2385         } eep_config;
2386         ulong last_reset;       /* Saved last reset time */
2387         /* /proc/scsi/advansys/[0...] */
2388         char *prtbuf;           /* /proc print buffer */
2389 #ifdef ADVANSYS_STATS
2390         struct asc_stats asc_stats;     /* Board statistics */
2391 #endif                          /* ADVANSYS_STATS */
2392         /*
2393          * The following fields are used only for Narrow Boards.
2394          */
2395         uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2396         /*
2397          * The following fields are used only for Wide Boards.
2398          */
2399         void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2400         ushort ioport;          /* I/O Port address. */
2401         adv_req_t *adv_reqp;    /* Request structures. */
2402         adv_sgblk_t *adv_sgblkp;        /* Scatter-gather structures. */
2403         ushort bios_signature;  /* BIOS Signature. */
2404         ushort bios_version;    /* BIOS Version. */
2405         ushort bios_codeseg;    /* BIOS Code Segment. */
2406         ushort bios_codelen;    /* BIOS Code Segment Length. */
2407 };
2408
2409 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2410                                                         dvc_var.asc_dvc_var)
2411 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2412                                                         dvc_var.adv_dvc_var)
2413 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2414
2415 #ifdef ADVANSYS_DEBUG
2416 static int asc_dbglvl = 3;
2417
2418 /*
2419  * asc_prt_asc_dvc_var()
2420  */
2421 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2422 {
2423         printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2424
2425         printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2426                "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2427
2428         printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2429                 (unsigned)h->init_sdtr);
2430
2431         printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2432                "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2433                (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2434                (unsigned)h->chip_no);
2435
2436         printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2437                "%u,\n", (unsigned)h->queue_full_or_busy,
2438                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2439
2440         printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2441                "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2442                (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2443                (unsigned)h->in_critical_cnt);
2444
2445         printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2446                "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2447                (unsigned)h->init_state, (unsigned)h->no_scam,
2448                (unsigned)h->pci_fix_asyn_xfer);
2449
2450         printk(" cfg 0x%lx\n", (ulong)h->cfg);
2451 }
2452
2453 /*
2454  * asc_prt_asc_dvc_cfg()
2455  */
2456 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2457 {
2458         printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2459
2460         printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2461                h->can_tagged_qng, h->cmd_qng_enabled);
2462         printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2463                h->disc_enable, h->sdtr_enable);
2464
2465         printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2466                 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2467                 h->isa_dma_channel, h->chip_version);
2468
2469         printk(" mcode_date 0x%x, mcode_version %d\n",
2470                 h->mcode_date, h->mcode_version);
2471 }
2472
2473 /*
2474  * asc_prt_adv_dvc_var()
2475  *
2476  * Display an ADV_DVC_VAR structure.
2477  */
2478 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2479 {
2480         printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2481
2482         printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2483                (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2484
2485         printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2486                (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2487
2488         printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2489                (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2490
2491         printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2492                (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2493                (ulong)h->carr_freelist);
2494
2495         printk("  icq_sp 0x%lx, irq_sp 0x%lx\n",
2496                (ulong)h->icq_sp, (ulong)h->irq_sp);
2497
2498         printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2499                (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2500
2501         printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2502                (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2503 }
2504
2505 /*
2506  * asc_prt_adv_dvc_cfg()
2507  *
2508  * Display an ADV_DVC_CFG structure.
2509  */
2510 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2511 {
2512         printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2513
2514         printk("  disc_enable 0x%x, termination 0x%x\n",
2515                h->disc_enable, h->termination);
2516
2517         printk("  chip_version 0x%x, mcode_date 0x%x\n",
2518                h->chip_version, h->mcode_date);
2519
2520         printk("  mcode_version 0x%x, control_flag 0x%x\n",
2521                h->mcode_version, h->control_flag);
2522 }
2523
2524 /*
2525  * asc_prt_scsi_host()
2526  */
2527 static void asc_prt_scsi_host(struct Scsi_Host *s)
2528 {
2529         struct asc_board *boardp = shost_priv(s);
2530
2531         printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2532         printk(" host_busy %u, host_no %d, last_reset %d,\n",
2533                s->host_busy, s->host_no, (unsigned)s->last_reset);
2534
2535         printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2536                (ulong)s->base, (ulong)s->io_port, boardp->irq);
2537
2538         printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2539                s->dma_channel, s->this_id, s->can_queue);
2540
2541         printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2542                s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2543
2544         if (ASC_NARROW_BOARD(boardp)) {
2545                 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2546                 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2547         } else {
2548                 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2549                 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2550         }
2551 }
2552
2553 /*
2554  * asc_prt_hex()
2555  *
2556  * Print hexadecimal output in 4 byte groupings 32 bytes
2557  * or 8 double-words per line.
2558  */
2559 static void asc_prt_hex(char *f, uchar *s, int l)
2560 {
2561         int i;
2562         int j;
2563         int k;
2564         int m;
2565
2566         printk("%s: (%d bytes)\n", f, l);
2567
2568         for (i = 0; i < l; i += 32) {
2569
2570                 /* Display a maximum of 8 double-words per line. */
2571                 if ((k = (l - i) / 4) >= 8) {
2572                         k = 8;
2573                         m = 0;
2574                 } else {
2575                         m = (l - i) % 4;
2576                 }
2577
2578                 for (j = 0; j < k; j++) {
2579                         printk(" %2.2X%2.2X%2.2X%2.2X",
2580                                (unsigned)s[i + (j * 4)],
2581                                (unsigned)s[i + (j * 4) + 1],
2582                                (unsigned)s[i + (j * 4) + 2],
2583                                (unsigned)s[i + (j * 4) + 3]);
2584                 }
2585
2586                 switch (m) {
2587                 case 0:
2588                 default:
2589                         break;
2590                 case 1:
2591                         printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2592                         break;
2593                 case 2:
2594                         printk(" %2.2X%2.2X",
2595                                (unsigned)s[i + (j * 4)],
2596                                (unsigned)s[i + (j * 4) + 1]);
2597                         break;
2598                 case 3:
2599                         printk(" %2.2X%2.2X%2.2X",
2600                                (unsigned)s[i + (j * 4) + 1],
2601                                (unsigned)s[i + (j * 4) + 2],
2602                                (unsigned)s[i + (j * 4) + 3]);
2603                         break;
2604                 }
2605
2606                 printk("\n");
2607         }
2608 }
2609
2610 /*
2611  * asc_prt_asc_scsi_q()
2612  */
2613 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2614 {
2615         ASC_SG_HEAD *sgp;
2616         int i;
2617
2618         printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2619
2620         printk
2621             (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2622              q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2623              q->q2.tag_code);
2624
2625         printk
2626             (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2627              (ulong)le32_to_cpu(q->q1.data_addr),
2628              (ulong)le32_to_cpu(q->q1.data_cnt),
2629              (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2630
2631         printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2632                (ulong)q->cdbptr, q->q2.cdb_len,
2633                (ulong)q->sg_head, q->q1.sg_queue_cnt);
2634
2635         if (q->sg_head) {
2636                 sgp = q->sg_head;
2637                 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2638                 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2639                        sgp->queue_cnt);
2640                 for (i = 0; i < sgp->entry_cnt; i++) {
2641                         printk(" [%u]: addr 0x%lx, bytes %lu\n",
2642                                i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2643                                (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2644                 }
2645
2646         }
2647 }
2648
2649 /*
2650  * asc_prt_asc_qdone_info()
2651  */
2652 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2653 {
2654         printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2655         printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2656                (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2657                q->d2.tag_code);
2658         printk
2659             (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2660              q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2661 }
2662
2663 /*
2664  * asc_prt_adv_sgblock()
2665  *
2666  * Display an ADV_SG_BLOCK structure.
2667  */
2668 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2669 {
2670         int i;
2671
2672         printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2673                (ulong)b, sgblockno);
2674         printk("  sg_cnt %u, sg_ptr 0x%lx\n",
2675                b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2676         BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2677         if (b->sg_ptr != 0)
2678                 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2679         for (i = 0; i < b->sg_cnt; i++) {
2680                 printk("  [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2681                        i, (ulong)b->sg_list[i].sg_addr,
2682                        (ulong)b->sg_list[i].sg_count);
2683         }
2684 }
2685
2686 /*
2687  * asc_prt_adv_scsi_req_q()
2688  *
2689  * Display an ADV_SCSI_REQ_Q structure.
2690  */
2691 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2692 {
2693         int sg_blk_cnt;
2694         struct asc_sg_block *sg_ptr;
2695
2696         printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2697
2698         printk("  target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2699                q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2700
2701         printk("  cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2702                q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2703
2704         printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2705                (ulong)le32_to_cpu(q->data_cnt),
2706                (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2707
2708         printk
2709             ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2710              q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2711
2712         printk("  sg_working_ix 0x%x, target_cmd %u\n",
2713                q->sg_working_ix, q->target_cmd);
2714
2715         printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2716                (ulong)le32_to_cpu(q->scsiq_rptr),
2717                (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2718
2719         /* Display the request's ADV_SG_BLOCK structures. */
2720         if (q->sg_list_ptr != NULL) {
2721                 sg_blk_cnt = 0;
2722                 while (1) {
2723                         /*
2724                          * 'sg_ptr' is a physical address. Convert it to a virtual
2725                          * address by indexing 'sg_blk_cnt' into the virtual address
2726                          * array 'sg_list_ptr'.
2727                          *
2728                          * XXX - Assumes all SG physical blocks are virtually contiguous.
2729                          */
2730                         sg_ptr =
2731                             &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2732                         asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2733                         if (sg_ptr->sg_ptr == 0) {
2734                                 break;
2735                         }
2736                         sg_blk_cnt++;
2737                 }
2738         }
2739 }
2740 #endif /* ADVANSYS_DEBUG */
2741
2742 /*
2743  * The advansys chip/microcode contains a 32-bit identifier for each command
2744  * known as the 'srb'.  I don't know what it stands for.  The driver used
2745  * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2746  * with bus_to_virt.  Now the driver keeps a per-host map of integers to
2747  * pointers.  It auto-expands when full, unless it can't allocate memory.
2748  * Note that an srb of 0 is treated specially by the chip/firmware, hence
2749  * the return of i+1 in this routine, and the corresponding subtraction in
2750  * the inverse routine.
2751  */
2752 #define BAD_SRB 0
2753 static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2754 {
2755         int i;
2756         void **new_ptr;
2757
2758         for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2759                 if (!asc_dvc->ptr_map[i])
2760                         goto out;
2761         }
2762
2763         if (asc_dvc->ptr_map_count == 0)
2764                 asc_dvc->ptr_map_count = 1;
2765         else
2766                 asc_dvc->ptr_map_count *= 2;
2767
2768         new_ptr = krealloc(asc_dvc->ptr_map,
2769                         asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2770         if (!new_ptr)
2771                 return BAD_SRB;
2772         asc_dvc->ptr_map = new_ptr;
2773  out:
2774         ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2775         asc_dvc->ptr_map[i] = ptr;
2776         return i + 1;
2777 }
2778
2779 static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2780 {
2781         void *ptr;
2782
2783         srb--;
2784         if (srb >= asc_dvc->ptr_map_count) {
2785                 printk("advansys: bad SRB %u, max %u\n", srb,
2786                                                         asc_dvc->ptr_map_count);
2787                 return NULL;
2788         }
2789         ptr = asc_dvc->ptr_map[srb];
2790         asc_dvc->ptr_map[srb] = NULL;
2791         ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2792         return ptr;
2793 }
2794
2795 /*
2796  * advansys_info()
2797  *
2798  * Return suitable for printing on the console with the argument
2799  * adapter's configuration information.
2800  *
2801  * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2802  * otherwise the static 'info' array will be overrun.
2803  */
2804 static const char *advansys_info(struct Scsi_Host *shost)
2805 {
2806         static char info[ASC_INFO_SIZE];
2807         struct asc_board *boardp = shost_priv(shost);
2808         ASC_DVC_VAR *asc_dvc_varp;
2809         ADV_DVC_VAR *adv_dvc_varp;
2810         char *busname;
2811         char *widename = NULL;
2812
2813         if (ASC_NARROW_BOARD(boardp)) {
2814                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2815                 ASC_DBG(1, "begin\n");
2816                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2817                         if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2818                             ASC_IS_ISAPNP) {
2819                                 busname = "ISA PnP";
2820                         } else {
2821                                 busname = "ISA";
2822                         }
2823                         sprintf(info,
2824                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2825                                 ASC_VERSION, busname,
2826                                 (ulong)shost->io_port,
2827                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2828                                 boardp->irq, shost->dma_channel);
2829                 } else {
2830                         if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2831                                 busname = "VL";
2832                         } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2833                                 busname = "EISA";
2834                         } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2835                                 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2836                                     == ASC_IS_PCI_ULTRA) {
2837                                         busname = "PCI Ultra";
2838                                 } else {
2839                                         busname = "PCI";
2840                                 }
2841                         } else {
2842                                 busname = "?";
2843                                 shost_printk(KERN_ERR, shost, "unknown bus "
2844                                         "type %d\n", asc_dvc_varp->bus_type);
2845                         }
2846                         sprintf(info,
2847                                 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2848                                 ASC_VERSION, busname, (ulong)shost->io_port,
2849                                 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2850                                 boardp->irq);
2851                 }
2852         } else {
2853                 /*
2854                  * Wide Adapter Information
2855                  *
2856                  * Memory-mapped I/O is used instead of I/O space to access
2857                  * the adapter, but display the I/O Port range. The Memory
2858                  * I/O address is displayed through the driver /proc file.
2859                  */
2860                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2861                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2862                         widename = "Ultra-Wide";
2863                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2864                         widename = "Ultra2-Wide";
2865                 } else {
2866                         widename = "Ultra3-Wide";
2867                 }
2868                 sprintf(info,
2869                         "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2870                         ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2871                         (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2872         }
2873         BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2874         ASC_DBG(1, "end\n");
2875         return info;
2876 }
2877
2878 #ifdef CONFIG_PROC_FS
2879 /*
2880  * asc_prt_line()
2881  *
2882  * If 'cp' is NULL print to the console, otherwise print to a buffer.
2883  *
2884  * Return 0 if printing to the console, otherwise return the number of
2885  * bytes written to the buffer.
2886  *
2887  * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
2888  * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
2889  */
2890 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
2891 {
2892         va_list args;
2893         int ret;
2894         char s[ASC_PRTLINE_SIZE];
2895
2896         va_start(args, fmt);
2897         ret = vsprintf(s, fmt, args);
2898         BUG_ON(ret >= ASC_PRTLINE_SIZE);
2899         if (buf == NULL) {
2900                 (void)printk(s);
2901                 ret = 0;
2902         } else {
2903                 ret = min(buflen, ret);
2904                 memcpy(buf, s, ret);
2905         }
2906         va_end(args);
2907         return ret;
2908 }
2909
2910 /*
2911  * asc_prt_board_devices()
2912  *
2913  * Print driver information for devices attached to the board.
2914  *
2915  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
2916  * cf. asc_prt_line().
2917  *
2918  * Return the number of characters copied into 'cp'. No more than
2919  * 'cplen' characters will be copied to 'cp'.
2920  */
2921 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
2922 {
2923         struct asc_board *boardp = shost_priv(shost);
2924         int leftlen;
2925         int totlen;
2926         int len;
2927         int chip_scsi_id;
2928         int i;
2929
2930         leftlen = cplen;
2931         totlen = len = 0;
2932
2933         len = asc_prt_line(cp, leftlen,
2934                            "\nDevice Information for AdvanSys SCSI Host %d:\n",
2935                            shost->host_no);
2936         ASC_PRT_NEXT();
2937
2938         if (ASC_NARROW_BOARD(boardp)) {
2939                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2940         } else {
2941                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2942         }
2943
2944         len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
2945         ASC_PRT_NEXT();
2946         for (i = 0; i <= ADV_MAX_TID; i++) {
2947                 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
2948                         len = asc_prt_line(cp, leftlen, " %X,", i);
2949                         ASC_PRT_NEXT();
2950                 }
2951         }
2952         len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
2953         ASC_PRT_NEXT();
2954
2955         return totlen;
2956 }
2957
2958 /*
2959  * Display Wide Board BIOS Information.
2960  */
2961 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
2962 {
2963         struct asc_board *boardp = shost_priv(shost);
2964         int leftlen;
2965         int totlen;
2966         int len;
2967         ushort major, minor, letter;
2968
2969         leftlen = cplen;
2970         totlen = len = 0;
2971
2972         len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
2973         ASC_PRT_NEXT();
2974
2975         /*
2976          * If the BIOS saved a valid signature, then fill in
2977          * the BIOS code segment base address.
2978          */
2979         if (boardp->bios_signature != 0x55AA) {
2980                 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
2981                 ASC_PRT_NEXT();
2982                 len = asc_prt_line(cp, leftlen,
2983                                    "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2984                 ASC_PRT_NEXT();
2985                 len = asc_prt_line(cp, leftlen,
2986                                    "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2987                 ASC_PRT_NEXT();
2988         } else {
2989                 major = (boardp->bios_version >> 12) & 0xF;
2990                 minor = (boardp->bios_version >> 8) & 0xF;
2991                 letter = (boardp->bios_version & 0xFF);
2992
2993                 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
2994                                    major, minor,
2995                                    letter >= 26 ? '?' : letter + 'A');
2996                 ASC_PRT_NEXT();
2997
2998                 /*
2999                  * Current available ROM BIOS release is 3.1I for UW
3000                  * and 3.2I for U2W. This code doesn't differentiate
3001                  * UW and U2W boards.
3002                  */
3003                 if (major < 3 || (major <= 3 && minor < 1) ||
3004                     (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3005                         len = asc_prt_line(cp, leftlen,
3006                                            "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3007                         ASC_PRT_NEXT();
3008                         len = asc_prt_line(cp, leftlen,
3009                                            "ftp://ftp.connectcom.net/pub\n");
3010                         ASC_PRT_NEXT();
3011                 }
3012         }
3013
3014         return totlen;
3015 }
3016
3017 /*
3018  * Add serial number to information bar if signature AAh
3019  * is found in at bit 15-9 (7 bits) of word 1.
3020  *
3021  * Serial Number consists fo 12 alpha-numeric digits.
3022  *
3023  *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
3024  *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
3025  *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
3026  *       5 - Product revision (A-J)    Word0:  "         "
3027  *
3028  *           Signature                 Word1: 15-9 (7 bits)
3029  *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3030  *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
3031  *
3032  *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3033  *
3034  * Note 1: Only production cards will have a serial number.
3035  *
3036  * Note 2: Signature is most significant 7 bits (0xFE).
3037  *
3038  * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3039  */
3040 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3041 {
3042         ushort w, num;
3043
3044         if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3045                 return ASC_FALSE;
3046         } else {
3047                 /*
3048                  * First word - 6 digits.
3049                  */
3050                 w = serialnum[0];
3051
3052                 /* Product type - 1st digit. */
3053                 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3054                         /* Product type is P=Prototype */
3055                         *cp += 0x8;
3056                 }
3057                 cp++;
3058
3059                 /* Manufacturing location - 2nd digit. */
3060                 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3061
3062                 /* Product ID - 3rd, 4th digits. */
3063                 num = w & 0x3FF;
3064                 *cp++ = '0' + (num / 100);
3065                 num %= 100;
3066                 *cp++ = '0' + (num / 10);
3067
3068                 /* Product revision - 5th digit. */
3069                 *cp++ = 'A' + (num % 10);
3070
3071                 /*
3072                  * Second word
3073                  */
3074                 w = serialnum[1];
3075
3076                 /*
3077                  * Year - 6th digit.
3078                  *
3079                  * If bit 15 of third word is set, then the
3080                  * last digit of the year is greater than 7.
3081                  */
3082                 if (serialnum[2] & 0x8000) {
3083                         *cp++ = '8' + ((w & 0x1C0) >> 6);
3084                 } else {
3085                         *cp++ = '0' + ((w & 0x1C0) >> 6);
3086                 }
3087
3088                 /* Week of year - 7th, 8th digits. */
3089                 num = w & 0x003F;
3090                 *cp++ = '0' + num / 10;
3091                 num %= 10;
3092                 *cp++ = '0' + num;
3093
3094                 /*
3095                  * Third word
3096                  */
3097                 w = serialnum[2] & 0x7FFF;
3098
3099                 /* Serial number - 9th digit. */
3100                 *cp++ = 'A' + (w / 1000);
3101
3102                 /* 10th, 11th, 12th digits. */
3103                 num = w % 1000;
3104                 *cp++ = '0' + num / 100;
3105                 num %= 100;
3106                 *cp++ = '0' + num / 10;
3107                 num %= 10;
3108                 *cp++ = '0' + num;
3109
3110                 *cp = '\0';     /* Null Terminate the string. */
3111                 return ASC_TRUE;
3112         }
3113 }
3114
3115 /*
3116  * asc_prt_asc_board_eeprom()
3117  *
3118  * Print board EEPROM configuration.
3119  *
3120  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3121  * cf. asc_prt_line().
3122  *
3123  * Return the number of characters copied into 'cp'. No more than
3124  * 'cplen' characters will be copied to 'cp'.
3125  */
3126 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3127 {
3128         struct asc_board *boardp = shost_priv(shost);
3129         ASC_DVC_VAR *asc_dvc_varp;
3130         int leftlen;
3131         int totlen;
3132         int len;
3133         ASCEEP_CONFIG *ep;
3134         int i;
3135 #ifdef CONFIG_ISA
3136         int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3137 #endif /* CONFIG_ISA */
3138         uchar serialstr[13];
3139
3140         asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3141         ep = &boardp->eep_config.asc_eep;
3142
3143         leftlen = cplen;
3144         totlen = len = 0;
3145
3146         len = asc_prt_line(cp, leftlen,
3147                            "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3148                            shost->host_no);
3149         ASC_PRT_NEXT();
3150
3151         if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3152             == ASC_TRUE) {
3153                 len =
3154                     asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3155                                  serialstr);
3156                 ASC_PRT_NEXT();
3157         } else {
3158                 if (ep->adapter_info[5] == 0xBB) {
3159                         len = asc_prt_line(cp, leftlen,
3160                                            " Default Settings Used for EEPROM-less Adapter.\n");
3161                         ASC_PRT_NEXT();
3162                 } else {
3163                         len = asc_prt_line(cp, leftlen,
3164                                            " Serial Number Signature Not Present.\n");
3165                         ASC_PRT_NEXT();
3166                 }
3167         }
3168
3169         len = asc_prt_line(cp, leftlen,
3170                            " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3171                            ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3172                            ep->max_tag_qng);
3173         ASC_PRT_NEXT();
3174
3175         len = asc_prt_line(cp, leftlen,
3176                            " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3177         ASC_PRT_NEXT();
3178
3179         len = asc_prt_line(cp, leftlen, " Target ID:           ");
3180         ASC_PRT_NEXT();
3181         for (i = 0; i <= ASC_MAX_TID; i++) {
3182                 len = asc_prt_line(cp, leftlen, " %d", i);
3183                 ASC_PRT_NEXT();
3184         }
3185         len = asc_prt_line(cp, leftlen, "\n");
3186         ASC_PRT_NEXT();
3187
3188         len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3189         ASC_PRT_NEXT();
3190         for (i = 0; i <= ASC_MAX_TID; i++) {
3191                 len = asc_prt_line(cp, leftlen, " %c",
3192                                    (ep->
3193                                     disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3194                                    'N');
3195                 ASC_PRT_NEXT();
3196         }
3197         len = asc_prt_line(cp, leftlen, "\n");
3198         ASC_PRT_NEXT();
3199
3200         len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3201         ASC_PRT_NEXT();
3202         for (i = 0; i <= ASC_MAX_TID; i++) {
3203                 len = asc_prt_line(cp, leftlen, " %c",
3204                                    (ep->
3205                                     use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3206                                    'N');
3207                 ASC_PRT_NEXT();
3208         }
3209         len = asc_prt_line(cp, leftlen, "\n");
3210         ASC_PRT_NEXT();
3211
3212         len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3213         ASC_PRT_NEXT();
3214         for (i = 0; i <= ASC_MAX_TID; i++) {
3215                 len = asc_prt_line(cp, leftlen, " %c",
3216                                    (ep->
3217                                     start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3218                                    'N');
3219                 ASC_PRT_NEXT();
3220         }
3221         len = asc_prt_line(cp, leftlen, "\n");
3222         ASC_PRT_NEXT();
3223
3224         len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3225         ASC_PRT_NEXT();
3226         for (i = 0; i <= ASC_MAX_TID; i++) {
3227                 len = asc_prt_line(cp, leftlen, " %c",
3228                                    (ep->
3229                                     init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3230                                    'N');
3231                 ASC_PRT_NEXT();
3232         }
3233         len = asc_prt_line(cp, leftlen, "\n");
3234         ASC_PRT_NEXT();
3235
3236 #ifdef CONFIG_ISA
3237         if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3238                 len = asc_prt_line(cp, leftlen,
3239                                    " Host ISA DMA speed:   %d MB/S\n",
3240                                    isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3241                 ASC_PRT_NEXT();
3242         }
3243 #endif /* CONFIG_ISA */
3244
3245         return totlen;
3246 }
3247
3248 /*
3249  * asc_prt_adv_board_eeprom()
3250  *
3251  * Print board EEPROM configuration.
3252  *
3253  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3254  * cf. asc_prt_line().
3255  *
3256  * Return the number of characters copied into 'cp'. No more than
3257  * 'cplen' characters will be copied to 'cp'.
3258  */
3259 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3260 {
3261         struct asc_board *boardp = shost_priv(shost);
3262         ADV_DVC_VAR *adv_dvc_varp;
3263         int leftlen;
3264         int totlen;
3265         int len;
3266         int i;
3267         char *termstr;
3268         uchar serialstr[13];
3269         ADVEEP_3550_CONFIG *ep_3550 = NULL;
3270         ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3271         ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3272         ushort word;
3273         ushort *wordp;
3274         ushort sdtr_speed = 0;
3275
3276         adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3277         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3278                 ep_3550 = &boardp->eep_config.adv_3550_eep;
3279         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3280                 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3281         } else {
3282                 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3283         }
3284
3285         leftlen = cplen;
3286         totlen = len = 0;
3287
3288         len = asc_prt_line(cp, leftlen,
3289                            "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3290                            shost->host_no);
3291         ASC_PRT_NEXT();
3292
3293         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3294                 wordp = &ep_3550->serial_number_word1;
3295         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3296                 wordp = &ep_38C0800->serial_number_word1;
3297         } else {
3298                 wordp = &ep_38C1600->serial_number_word1;
3299         }
3300
3301         if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3302                 len =
3303                     asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3304                                  serialstr);
3305                 ASC_PRT_NEXT();
3306         } else {
3307                 len = asc_prt_line(cp, leftlen,
3308                                    " Serial Number Signature Not Present.\n");
3309                 ASC_PRT_NEXT();
3310         }
3311
3312         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3313                 len = asc_prt_line(cp, leftlen,
3314                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3315                                    ep_3550->adapter_scsi_id,
3316                                    ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3317                 ASC_PRT_NEXT();
3318         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3319                 len = asc_prt_line(cp, leftlen,
3320                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3321                                    ep_38C0800->adapter_scsi_id,
3322                                    ep_38C0800->max_host_qng,
3323                                    ep_38C0800->max_dvc_qng);
3324                 ASC_PRT_NEXT();
3325         } else {
3326                 len = asc_prt_line(cp, leftlen,
3327                                    " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3328                                    ep_38C1600->adapter_scsi_id,
3329                                    ep_38C1600->max_host_qng,
3330                                    ep_38C1600->max_dvc_qng);
3331                 ASC_PRT_NEXT();
3332         }
3333         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3334                 word = ep_3550->termination;
3335         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3336                 word = ep_38C0800->termination_lvd;
3337         } else {
3338                 word = ep_38C1600->termination_lvd;
3339         }
3340         switch (word) {
3341         case 1:
3342                 termstr = "Low Off/High Off";
3343                 break;
3344         case 2:
3345                 termstr = "Low Off/High On";
3346                 break;
3347         case 3:
3348                 termstr = "Low On/High On";
3349                 break;
3350         default:
3351         case 0:
3352                 termstr = "Automatic";
3353                 break;
3354         }
3355
3356         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3357                 len = asc_prt_line(cp, leftlen,
3358                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3359                                    ep_3550->termination, termstr,
3360                                    ep_3550->bios_ctrl);
3361                 ASC_PRT_NEXT();
3362         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3363                 len = asc_prt_line(cp, leftlen,
3364                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3365                                    ep_38C0800->termination_lvd, termstr,
3366                                    ep_38C0800->bios_ctrl);
3367                 ASC_PRT_NEXT();
3368         } else {
3369                 len = asc_prt_line(cp, leftlen,
3370                                    " termination: %u (%s), bios_ctrl: 0x%x\n",
3371                                    ep_38C1600->termination_lvd, termstr,
3372                                    ep_38C1600->bios_ctrl);
3373                 ASC_PRT_NEXT();
3374         }
3375
3376         len = asc_prt_line(cp, leftlen, " Target ID:           ");
3377         ASC_PRT_NEXT();
3378         for (i = 0; i <= ADV_MAX_TID; i++) {
3379                 len = asc_prt_line(cp, leftlen, " %X", i);
3380                 ASC_PRT_NEXT();
3381         }
3382         len = asc_prt_line(cp, leftlen, "\n");
3383         ASC_PRT_NEXT();
3384
3385         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3386                 word = ep_3550->disc_enable;
3387         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3388                 word = ep_38C0800->disc_enable;
3389         } else {
3390                 word = ep_38C1600->disc_enable;
3391         }
3392         len = asc_prt_line(cp, leftlen, " Disconnects:         ");
3393         ASC_PRT_NEXT();
3394         for (i = 0; i <= ADV_MAX_TID; i++) {
3395                 len = asc_prt_line(cp, leftlen, " %c",
3396                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3397                 ASC_PRT_NEXT();
3398         }
3399         len = asc_prt_line(cp, leftlen, "\n");
3400         ASC_PRT_NEXT();
3401
3402         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3403                 word = ep_3550->tagqng_able;
3404         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3405                 word = ep_38C0800->tagqng_able;
3406         } else {
3407                 word = ep_38C1600->tagqng_able;
3408         }
3409         len = asc_prt_line(cp, leftlen, " Command Queuing:     ");
3410         ASC_PRT_NEXT();
3411         for (i = 0; i <= ADV_MAX_TID; i++) {
3412                 len = asc_prt_line(cp, leftlen, " %c",
3413                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3414                 ASC_PRT_NEXT();
3415         }
3416         len = asc_prt_line(cp, leftlen, "\n");
3417         ASC_PRT_NEXT();
3418
3419         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3420                 word = ep_3550->start_motor;
3421         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3422                 word = ep_38C0800->start_motor;
3423         } else {
3424                 word = ep_38C1600->start_motor;
3425         }
3426         len = asc_prt_line(cp, leftlen, " Start Motor:         ");
3427         ASC_PRT_NEXT();
3428         for (i = 0; i <= ADV_MAX_TID; i++) {
3429                 len = asc_prt_line(cp, leftlen, " %c",
3430                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3431                 ASC_PRT_NEXT();
3432         }
3433         len = asc_prt_line(cp, leftlen, "\n");
3434         ASC_PRT_NEXT();
3435
3436         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3437                 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3438                 ASC_PRT_NEXT();
3439                 for (i = 0; i <= ADV_MAX_TID; i++) {
3440                         len = asc_prt_line(cp, leftlen, " %c",
3441                                            (ep_3550->
3442                                             sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3443                                            'Y' : 'N');
3444                         ASC_PRT_NEXT();
3445                 }
3446                 len = asc_prt_line(cp, leftlen, "\n");
3447                 ASC_PRT_NEXT();
3448         }
3449
3450         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3451                 len = asc_prt_line(cp, leftlen, " Ultra Transfer:      ");
3452                 ASC_PRT_NEXT();
3453                 for (i = 0; i <= ADV_MAX_TID; i++) {
3454                         len = asc_prt_line(cp, leftlen, " %c",
3455                                            (ep_3550->
3456                                             ultra_able & ADV_TID_TO_TIDMASK(i))
3457                                            ? 'Y' : 'N');
3458                         ASC_PRT_NEXT();
3459                 }
3460                 len = asc_prt_line(cp, leftlen, "\n");
3461                 ASC_PRT_NEXT();
3462         }
3463
3464         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3465                 word = ep_3550->wdtr_able;
3466         } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3467                 word = ep_38C0800->wdtr_able;
3468         } else {
3469                 word = ep_38C1600->wdtr_able;
3470         }
3471         len = asc_prt_line(cp, leftlen, " Wide Transfer:       ");
3472         ASC_PRT_NEXT();
3473         for (i = 0; i <= ADV_MAX_TID; i++) {
3474                 len = asc_prt_line(cp, leftlen, " %c",
3475                                    (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3476                 ASC_PRT_NEXT();
3477         }
3478         len = asc_prt_line(cp, leftlen, "\n");
3479         ASC_PRT_NEXT();
3480
3481         if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3482             adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3483                 len = asc_prt_line(cp, leftlen,
3484                                    " Synchronous Transfer Speed (Mhz):\n  ");
3485                 ASC_PRT_NEXT();
3486                 for (i = 0; i <= ADV_MAX_TID; i++) {
3487                         char *speed_str;
3488
3489                         if (i == 0) {
3490                                 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3491                         } else if (i == 4) {
3492                                 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3493                         } else if (i == 8) {
3494                                 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3495                         } else if (i == 12) {
3496                                 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3497                         }
3498                         switch (sdtr_speed & ADV_MAX_TID) {
3499                         case 0:
3500                                 speed_str = "Off";
3501                                 break;
3502                         case 1:
3503                                 speed_str = "  5";
3504                                 break;
3505                         case 2:
3506                                 speed_str = " 10";
3507                                 break;
3508                         case 3:
3509                                 speed_str = " 20";
3510                                 break;
3511                         case 4:
3512                                 speed_str = " 40";
3513                                 break;
3514                         case 5:
3515                                 speed_str = " 80";
3516                                 break;
3517                         default:
3518                                 speed_str = "Unk";
3519                                 break;
3520                         }
3521                         len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3522                         ASC_PRT_NEXT();
3523                         if (i == 7) {
3524                                 len = asc_prt_line(cp, leftlen, "\n  ");
3525                                 ASC_PRT_NEXT();
3526                         }
3527                         sdtr_speed >>= 4;
3528                 }
3529                 len = asc_prt_line(cp, leftlen, "\n");
3530                 ASC_PRT_NEXT();
3531         }
3532
3533         return totlen;
3534 }
3535
3536 /*
3537  * asc_prt_driver_conf()
3538  *
3539  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3540  * cf. asc_prt_line().
3541  *
3542  * Return the number of characters copied into 'cp'. No more than
3543  * 'cplen' characters will be copied to 'cp'.
3544  */
3545 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3546 {
3547         struct asc_board *boardp = shost_priv(shost);
3548         int leftlen;
3549         int totlen;
3550         int len;
3551         int chip_scsi_id;
3552
3553         leftlen = cplen;
3554         totlen = len = 0;
3555
3556         len = asc_prt_line(cp, leftlen,
3557                            "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3558                            shost->host_no);
3559         ASC_PRT_NEXT();
3560
3561         len = asc_prt_line(cp, leftlen,
3562                            " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3563                            shost->host_busy, shost->last_reset, shost->max_id,
3564                            shost->max_lun, shost->max_channel);
3565         ASC_PRT_NEXT();
3566
3567         len = asc_prt_line(cp, leftlen,
3568                            " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3569                            shost->unique_id, shost->can_queue, shost->this_id,
3570                            shost->sg_tablesize, shost->cmd_per_lun);
3571         ASC_PRT_NEXT();
3572
3573         len = asc_prt_line(cp, leftlen,
3574                            " unchecked_isa_dma %d, use_clustering %d\n",
3575                            shost->unchecked_isa_dma, shost->use_clustering);
3576         ASC_PRT_NEXT();
3577
3578         len = asc_prt_line(cp, leftlen,
3579                            " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3580                            boardp->flags, boardp->last_reset, jiffies,
3581                            boardp->asc_n_io_port);
3582         ASC_PRT_NEXT();
3583
3584         len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3585         ASC_PRT_NEXT();
3586
3587         if (ASC_NARROW_BOARD(boardp)) {
3588                 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3589         } else {
3590                 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3591         }
3592
3593         return totlen;
3594 }
3595
3596 /*
3597  * asc_prt_asc_board_info()
3598  *
3599  * Print dynamic board configuration information.
3600  *
3601  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3602  * cf. asc_prt_line().
3603  *
3604  * Return the number of characters copied into 'cp'. No more than
3605  * 'cplen' characters will be copied to 'cp'.
3606  */
3607 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3608 {
3609         struct asc_board *boardp = shost_priv(shost);
3610         int chip_scsi_id;
3611         int leftlen;
3612         int totlen;
3613         int len;
3614         ASC_DVC_VAR *v;
3615         ASC_DVC_CFG *c;
3616         int i;
3617         int renegotiate = 0;
3618
3619         v = &boardp->dvc_var.asc_dvc_var;
3620         c = &boardp->dvc_cfg.asc_dvc_cfg;
3621         chip_scsi_id = c->chip_scsi_id;
3622
3623         leftlen = cplen;
3624         totlen = len = 0;
3625
3626         len = asc_prt_line(cp, leftlen,
3627                            "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3628                            shost->host_no);
3629         ASC_PRT_NEXT();
3630
3631         len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3632                            "mcode_version 0x%x, err_code %u\n",
3633                            c->chip_version, c->mcode_date, c->mcode_version,
3634                            v->err_code);
3635         ASC_PRT_NEXT();
3636
3637         /* Current number of commands waiting for the host. */
3638         len = asc_prt_line(cp, leftlen,
3639                            " Total Command Pending: %d\n", v->cur_total_qng);
3640         ASC_PRT_NEXT();
3641
3642         len = asc_prt_line(cp, leftlen, " Command Queuing:");
3643         ASC_PRT_NEXT();
3644         for (i = 0; i <= ASC_MAX_TID; i++) {
3645                 if ((chip_scsi_id == i) ||
3646                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3647                         continue;
3648                 }
3649                 len = asc_prt_line(cp, leftlen, " %X:%c",
3650                                    i,
3651                                    (v->
3652                                     use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3653                                    'Y' : 'N');
3654                 ASC_PRT_NEXT();
3655         }
3656         len = asc_prt_line(cp, leftlen, "\n");
3657         ASC_PRT_NEXT();
3658
3659         /* Current number of commands waiting for a device. */
3660         len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3661         ASC_PRT_NEXT();
3662         for (i = 0; i <= ASC_MAX_TID; i++) {
3663                 if ((chip_scsi_id == i) ||
3664                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3665                         continue;
3666                 }
3667                 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3668                 ASC_PRT_NEXT();
3669         }
3670         len = asc_prt_line(cp, leftlen, "\n");
3671         ASC_PRT_NEXT();
3672
3673         /* Current limit on number of commands that can be sent to a device. */
3674         len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3675         ASC_PRT_NEXT();
3676         for (i = 0; i <= ASC_MAX_TID; i++) {
3677                 if ((chip_scsi_id == i) ||
3678                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3679                         continue;
3680                 }
3681                 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3682                 ASC_PRT_NEXT();
3683         }
3684         len = asc_prt_line(cp, leftlen, "\n");
3685         ASC_PRT_NEXT();
3686
3687         /* Indicate whether the device has returned queue full status. */
3688         len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3689         ASC_PRT_NEXT();
3690         for (i = 0; i <= ASC_MAX_TID; i++) {
3691                 if ((chip_scsi_id == i) ||
3692                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3693                         continue;
3694                 }
3695                 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3696                         len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3697                                            i, boardp->queue_full_cnt[i]);
3698                 } else {
3699                         len = asc_prt_line(cp, leftlen, " %X:N", i);
3700                 }
3701                 ASC_PRT_NEXT();
3702         }
3703         len = asc_prt_line(cp, leftlen, "\n");
3704         ASC_PRT_NEXT();
3705
3706         len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3707         ASC_PRT_NEXT();
3708         for (i = 0; i <= ASC_MAX_TID; i++) {
3709                 if ((chip_scsi_id == i) ||
3710                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3711                         continue;
3712                 }
3713                 len = asc_prt_line(cp, leftlen, " %X:%c",
3714                                    i,
3715                                    (v->
3716                                     sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3717                                    'N');
3718                 ASC_PRT_NEXT();
3719         }
3720         len = asc_prt_line(cp, leftlen, "\n");
3721         ASC_PRT_NEXT();
3722
3723         for (i = 0; i <= ASC_MAX_TID; i++) {
3724                 uchar syn_period_ix;
3725
3726                 if ((chip_scsi_id == i) ||
3727                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3728                     ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3729                         continue;
3730                 }
3731
3732                 len = asc_prt_line(cp, leftlen, "  %X:", i);
3733                 ASC_PRT_NEXT();
3734
3735                 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3736                         len = asc_prt_line(cp, leftlen, " Asynchronous");
3737                         ASC_PRT_NEXT();
3738                 } else {
3739                         syn_period_ix =
3740                             (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3741                                                            1);
3742
3743                         len = asc_prt_line(cp, leftlen,
3744                                            " Transfer Period Factor: %d (%d.%d Mhz),",
3745                                            v->sdtr_period_tbl[syn_period_ix],
3746                                            250 /
3747                                            v->sdtr_period_tbl[syn_period_ix],
3748                                            ASC_TENTHS(250,
3749                                                       v->
3750                                                       sdtr_period_tbl
3751                                                       [syn_period_ix]));
3752                         ASC_PRT_NEXT();
3753
3754                         len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3755                                            boardp->
3756                                            sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3757                         ASC_PRT_NEXT();
3758                 }
3759
3760                 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3761                         len = asc_prt_line(cp, leftlen, "*\n");
3762                         renegotiate = 1;
3763                 } else {
3764                         len = asc_prt_line(cp, leftlen, "\n");
3765                 }
3766                 ASC_PRT_NEXT();
3767         }
3768
3769         if (renegotiate) {
3770                 len = asc_prt_line(cp, leftlen,
3771                                    " * = Re-negotiation pending before next command.\n");
3772                 ASC_PRT_NEXT();
3773         }
3774
3775         return totlen;
3776 }
3777
3778 /*
3779  * asc_prt_adv_board_info()
3780  *
3781  * Print dynamic board configuration information.
3782  *
3783  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3784  * cf. asc_prt_line().
3785  *
3786  * Return the number of characters copied into 'cp'. No more than
3787  * 'cplen' characters will be copied to 'cp'.
3788  */
3789 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3790 {
3791         struct asc_board *boardp = shost_priv(shost);
3792         int leftlen;
3793         int totlen;
3794         int len;
3795         int i;
3796         ADV_DVC_VAR *v;
3797         ADV_DVC_CFG *c;
3798         AdvPortAddr iop_base;
3799         ushort chip_scsi_id;
3800         ushort lramword;
3801         uchar lrambyte;
3802         ushort tagqng_able;
3803         ushort sdtr_able, wdtr_able;
3804         ushort wdtr_done, sdtr_done;
3805         ushort period = 0;
3806         int renegotiate = 0;
3807
3808         v = &boardp->dvc_var.adv_dvc_var;
3809         c = &boardp->dvc_cfg.adv_dvc_cfg;
3810         iop_base = v->iop_base;
3811         chip_scsi_id = v->chip_scsi_id;
3812
3813         leftlen = cplen;
3814         totlen = len = 0;
3815
3816         len = asc_prt_line(cp, leftlen,
3817                            "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3818                            shost->host_no);
3819         ASC_PRT_NEXT();
3820
3821         len = asc_prt_line(cp, leftlen,
3822                            " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3823                            v->iop_base,
3824                            AdvReadWordRegister(iop_base,
3825                                                IOPW_SCSI_CFG1) & CABLE_DETECT,
3826                            v->err_code);
3827         ASC_PRT_NEXT();
3828
3829         len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, "
3830                            "mcode_version 0x%x\n", c->chip_version,
3831                            c->mcode_date, c->mcode_version);
3832         ASC_PRT_NEXT();
3833
3834         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3835         len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3836         ASC_PRT_NEXT();
3837         for (i = 0; i <= ADV_MAX_TID; i++) {
3838                 if ((chip_scsi_id == i) ||
3839                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3840                         continue;
3841                 }
3842
3843                 len = asc_prt_line(cp, leftlen, " %X:%c",
3844                                    i,
3845                                    (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3846                                    'N');
3847                 ASC_PRT_NEXT();
3848         }
3849         len = asc_prt_line(cp, leftlen, "\n");
3850         ASC_PRT_NEXT();
3851
3852         len = asc_prt_line(cp, leftlen, " Queue Limit:");
3853         ASC_PRT_NEXT();
3854         for (i = 0; i <= ADV_MAX_TID; i++) {
3855                 if ((chip_scsi_id == i) ||
3856                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3857                         continue;
3858                 }
3859
3860                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3861                                 lrambyte);
3862
3863                 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3864                 ASC_PRT_NEXT();
3865         }
3866         len = asc_prt_line(cp, leftlen, "\n");
3867         ASC_PRT_NEXT();
3868
3869         len = asc_prt_line(cp, leftlen, " Command Pending:");
3870         ASC_PRT_NEXT();
3871         for (i = 0; i <= ADV_MAX_TID; i++) {
3872                 if ((chip_scsi_id == i) ||
3873                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3874                         continue;
3875                 }
3876
3877                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3878                                 lrambyte);
3879
3880                 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
3881                 ASC_PRT_NEXT();
3882         }
3883         len = asc_prt_line(cp, leftlen, "\n");
3884         ASC_PRT_NEXT();
3885
3886         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3887         len = asc_prt_line(cp, leftlen, " Wide Enabled:");
3888         ASC_PRT_NEXT();
3889         for (i = 0; i <= ADV_MAX_TID; i++) {
3890                 if ((chip_scsi_id == i) ||
3891                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3892                         continue;
3893                 }
3894
3895                 len = asc_prt_line(cp, leftlen, " %X:%c",
3896                                    i,
3897                                    (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3898                                    'N');
3899                 ASC_PRT_NEXT();
3900         }
3901         len = asc_prt_line(cp, leftlen, "\n");
3902         ASC_PRT_NEXT();
3903
3904         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3905         len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
3906         ASC_PRT_NEXT();
3907         for (i = 0; i <= ADV_MAX_TID; i++) {
3908                 if ((chip_scsi_id == i) ||
3909                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3910                         continue;
3911                 }
3912
3913                 AdvReadWordLram(iop_base,
3914                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3915                                 lramword);
3916
3917                 len = asc_prt_line(cp, leftlen, " %X:%d",
3918                                    i, (lramword & 0x8000) ? 16 : 8);
3919                 ASC_PRT_NEXT();
3920
3921                 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3922                     (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3923                         len = asc_prt_line(cp, leftlen, "*");
3924                         ASC_PRT_NEXT();
3925                         renegotiate = 1;
3926                 }
3927         }
3928         len = asc_prt_line(cp, leftlen, "\n");
3929         ASC_PRT_NEXT();
3930
3931         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3932         len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
3933         ASC_PRT_NEXT();
3934         for (i = 0; i <= ADV_MAX_TID; i++) {
3935                 if ((chip_scsi_id == i) ||
3936                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3937                         continue;
3938                 }
3939
3940                 len = asc_prt_line(cp, leftlen, " %X:%c",
3941                                    i,
3942                                    (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3943                                    'N');
3944                 ASC_PRT_NEXT();
3945         }
3946         len = asc_prt_line(cp, leftlen, "\n");
3947         ASC_PRT_NEXT();
3948
3949         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3950         for (i = 0; i <= ADV_MAX_TID; i++) {
3951
3952                 AdvReadWordLram(iop_base,
3953                                 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3954                                 lramword);
3955                 lramword &= ~0x8000;
3956
3957                 if ((chip_scsi_id == i) ||
3958                     ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3959                     ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3960                         continue;
3961                 }
3962
3963                 len = asc_prt_line(cp, leftlen, "  %X:", i);
3964                 ASC_PRT_NEXT();
3965
3966                 if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3967                         len = asc_prt_line(cp, leftlen, " Asynchronous");
3968                         ASC_PRT_NEXT();
3969                 } else {
3970                         len =
3971                             asc_prt_line(cp, leftlen,
3972                                          " Transfer Period Factor: ");
3973                         ASC_PRT_NEXT();
3974
3975                         if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3976                                 len =
3977                                     asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
3978                                 ASC_PRT_NEXT();
3979                         } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3980                                 len =
3981                                     asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
3982                                 ASC_PRT_NEXT();
3983                         } else {        /* 20 Mhz or below. */
3984
3985                                 period = (((lramword >> 8) * 25) + 50) / 4;
3986
3987                                 if (period == 0) {      /* Should never happen. */
3988                                         len =
3989                                             asc_prt_line(cp, leftlen,
3990                                                          "%d (? Mhz), ");
3991                                         ASC_PRT_NEXT();
3992                                 } else {
3993                                         len = asc_prt_line(cp, leftlen,
3994                                                            "%d (%d.%d Mhz),",
3995                                                            period, 250 / period,
3996                                                            ASC_TENTHS(250,
3997                                                                       period));
3998                                         ASC_PRT_NEXT();
3999                                 }
4000                         }
4001
4002                         len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4003                                            lramword & 0x1F);
4004                         ASC_PRT_NEXT();
4005                 }
4006
4007                 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4008                         len = asc_prt_line(cp, leftlen, "*\n");
4009                         renegotiate = 1;
4010                 } else {
4011                         len = asc_prt_line(cp, leftlen, "\n");
4012                 }
4013                 ASC_PRT_NEXT();
4014         }
4015
4016         if (renegotiate) {
4017                 len = asc_prt_line(cp, leftlen,
4018                                    " * = Re-negotiation pending before next command.\n");
4019                 ASC_PRT_NEXT();
4020         }
4021
4022         return totlen;
4023 }
4024
4025 /*
4026  * asc_proc_copy()
4027  *
4028  * Copy proc information to a read buffer taking into account the current
4029  * read offset in the file and the remaining space in the read buffer.
4030  */
4031 static int
4032 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4033               char *cp, int cplen)
4034 {
4035         int cnt = 0;
4036
4037         ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n",
4038                  (unsigned)offset, (unsigned)advoffset, cplen);
4039         if (offset <= advoffset) {
4040                 /* Read offset below current offset, copy everything. */
4041                 cnt = min(cplen, leftlen);
4042                 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4043                          (ulong)curbuf, (ulong)cp, cnt);
4044                 memcpy(curbuf, cp, cnt);
4045         } else if (offset < advoffset + cplen) {
4046                 /* Read offset within current range, partial copy. */
4047                 cnt = (advoffset + cplen) - offset;
4048                 cp = (cp + cplen) - cnt;
4049                 cnt = min(cnt, leftlen);
4050                 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4051                          (ulong)curbuf, (ulong)cp, cnt);
4052                 memcpy(curbuf, cp, cnt);
4053         }
4054         return cnt;
4055 }
4056
4057 #ifdef ADVANSYS_STATS
4058 /*
4059  * asc_prt_board_stats()
4060  *
4061  * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4062  * cf. asc_prt_line().
4063  *
4064  * Return the number of characters copied into 'cp'. No more than
4065  * 'cplen' characters will be copied to 'cp'.
4066  */
4067 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4068 {
4069         struct asc_board *boardp = shost_priv(shost);
4070         struct asc_stats *s = &boardp->asc_stats;
4071
4072         int leftlen = cplen;
4073         int len, totlen = 0;
4074
4075         len = asc_prt_line(cp, leftlen,
4076                            "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4077                            shost->host_no);
4078         ASC_PRT_NEXT();
4079
4080         len = asc_prt_line(cp, leftlen,
4081                            " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4082                            s->queuecommand, s->reset, s->biosparam,
4083                            s->interrupt);
4084         ASC_PRT_NEXT();
4085
4086         len = asc_prt_line(cp, leftlen,
4087                            " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4088                            s->callback, s->done, s->build_error,
4089                            s->adv_build_noreq, s->adv_build_nosg);
4090         ASC_PRT_NEXT();
4091
4092         len = asc_prt_line(cp, leftlen,
4093                            " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4094                            s->exe_noerror, s->exe_busy, s->exe_error,
4095                            s->exe_unknown);
4096         ASC_PRT_NEXT();
4097
4098         /*
4099          * Display data transfer statistics.
4100          */
4101         if (s->xfer_cnt > 0) {
4102                 len = asc_prt_line(cp, leftlen, " xfer_cnt %lu, xfer_elem %lu, ",
4103                                    s->xfer_cnt, s->xfer_elem);
4104                 ASC_PRT_NEXT();
4105
4106                 len = asc_prt_line(cp, leftlen, "xfer_bytes %lu.%01lu kb\n",
4107                                    s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
4108                 ASC_PRT_NEXT();
4109
4110                 /* Scatter gather transfer statistics */
4111                 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4112                                    s->xfer_elem / s->xfer_cnt,
4113                                    ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
4114                 ASC_PRT_NEXT();
4115
4116                 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4117                                    (s->xfer_sect / 2) / s->xfer_elem,
4118                                    ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
4119                 ASC_PRT_NEXT();
4120
4121                 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4122                                    (s->xfer_sect / 2) / s->xfer_cnt,
4123                                    ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
4124                 ASC_PRT_NEXT();
4125         }
4126
4127         return totlen;
4128 }
4129 #endif /* ADVANSYS_STATS */
4130
4131 /*
4132  * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4133  *
4134  * *buffer: I/O buffer
4135  * **start: if inout == FALSE pointer into buffer where user read should start
4136  * offset: current offset into a /proc/scsi/advansys/[0...] file
4137  * length: length of buffer
4138  * hostno: Scsi_Host host_no
4139  * inout: TRUE - user is writing; FALSE - user is reading
4140  *
4141  * Return the number of bytes read from or written to a
4142  * /proc/scsi/advansys/[0...] file.
4143  *
4144  * Note: This function uses the per board buffer 'prtbuf' which is
4145  * allocated when the board is initialized in advansys_detect(). The
4146  * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4147  * used to write to the buffer. The way asc_proc_copy() is written
4148  * if 'prtbuf' is too small it will not be overwritten. Instead the
4149  * user just won't get all the available statistics.
4150  */
4151 static int
4152 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4153                    off_t offset, int length, int inout)
4154 {
4155         struct asc_board *boardp = shost_priv(shost);
4156         char *cp;
4157         int cplen;
4158         int cnt;
4159         int totcnt;
4160         int leftlen;
4161         char *curbuf;
4162         off_t advoffset;
4163
4164         ASC_DBG(1, "begin\n");
4165
4166         /*
4167          * User write not supported.
4168          */
4169         if (inout == TRUE)
4170                 return -ENOSYS;
4171
4172         /*
4173          * User read of /proc/scsi/advansys/[0...] file.
4174          */
4175
4176         /* Copy read data starting at the beginning of the buffer. */
4177         *start = buffer;
4178         curbuf = buffer;
4179         advoffset = 0;
4180         totcnt = 0;
4181         leftlen = length;
4182
4183         /*
4184          * Get board configuration information.
4185          *
4186          * advansys_info() returns the board string from its own static buffer.
4187          */
4188         cp = (char *)advansys_info(shost);
4189         strcat(cp, "\n");
4190         cplen = strlen(cp);
4191         /* Copy board information. */
4192         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4193         totcnt += cnt;
4194         leftlen -= cnt;
4195         if (leftlen == 0) {
4196                 ASC_DBG(1, "totcnt %d\n", totcnt);
4197                 return totcnt;
4198         }
4199         advoffset += cplen;
4200         curbuf += cnt;
4201
4202         /*
4203          * Display Wide Board BIOS Information.
4204          */
4205         if (!ASC_NARROW_BOARD(boardp)) {
4206                 cp = boardp->prtbuf;
4207                 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4208                 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4209                 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4210                                   cplen);
4211                 totcnt += cnt;
4212                 leftlen -= cnt;
4213                 if (leftlen == 0) {
4214                         ASC_DBG(1, "totcnt %d\n", totcnt);
4215                         return totcnt;
4216                 }
4217                 advoffset += cplen;
4218                 curbuf += cnt;
4219         }
4220
4221         /*
4222          * Display driver information for each device attached to the board.
4223          */
4224         cp = boardp->prtbuf;
4225         cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4226         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4227         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4228         totcnt += cnt;
4229         leftlen -= cnt;
4230         if (leftlen == 0) {
4231                 ASC_DBG(1, "totcnt %d\n", totcnt);
4232                 return totcnt;
4233         }
4234         advoffset += cplen;
4235         curbuf += cnt;
4236
4237         /*
4238          * Display EEPROM configuration for the board.
4239          */
4240         cp = boardp->prtbuf;
4241         if (ASC_NARROW_BOARD(boardp)) {
4242                 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4243         } else {
4244                 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4245         }
4246         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4247         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4248         totcnt += cnt;
4249         leftlen -= cnt;
4250         if (leftlen == 0) {
4251                 ASC_DBG(1, "totcnt %d\n", totcnt);
4252                 return totcnt;
4253         }
4254         advoffset += cplen;
4255         curbuf += cnt;
4256
4257         /*
4258          * Display driver configuration and information for the board.
4259          */
4260         cp = boardp->prtbuf;
4261         cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4262         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4263         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4264         totcnt += cnt;
4265         leftlen -= cnt;
4266         if (leftlen == 0) {
4267                 ASC_DBG(1, "totcnt %d\n", totcnt);
4268                 return totcnt;
4269         }
4270         advoffset += cplen;
4271         curbuf += cnt;
4272
4273 #ifdef ADVANSYS_STATS
4274         /*
4275          * Display driver statistics for the board.
4276          */
4277         cp = boardp->prtbuf;
4278         cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4279         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4280         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4281         totcnt += cnt;
4282         leftlen -= cnt;
4283         if (leftlen == 0) {
4284                 ASC_DBG(1, "totcnt %d\n", totcnt);
4285                 return totcnt;
4286         }
4287         advoffset += cplen;
4288         curbuf += cnt;
4289 #endif /* ADVANSYS_STATS */
4290
4291         /*
4292          * Display Asc Library dynamic configuration information
4293          * for the board.
4294          */
4295         cp = boardp->prtbuf;
4296         if (ASC_NARROW_BOARD(boardp)) {
4297                 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4298         } else {
4299                 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4300         }
4301         BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4302         cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4303         totcnt += cnt;
4304         leftlen -= cnt;
4305         if (leftlen == 0) {
4306                 ASC_DBG(1, "totcnt %d\n", totcnt);
4307                 return totcnt;
4308         }
4309         advoffset += cplen;
4310         curbuf += cnt;
4311
4312         ASC_DBG(1, "totcnt %d\n", totcnt);
4313
4314         return totcnt;
4315 }
4316 #endif /* CONFIG_PROC_FS */
4317
4318 static void asc_scsi_done(struct scsi_cmnd *scp)
4319 {
4320         scsi_dma_unmap(scp);
4321         ASC_STATS(scp->device->host, done);
4322         scp->scsi_done(scp);
4323 }
4324
4325 static void AscSetBank(PortAddr iop_base, uchar bank)
4326 {
4327         uchar val;
4328
4329         val = AscGetChipControl(iop_base) &
4330             (~
4331              (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4332               CC_CHIP_RESET));
4333         if (bank == 1) {
4334                 val |= CC_BANK_ONE;
4335         } else if (bank == 2) {
4336                 val |= CC_DIAG | CC_BANK_ONE;
4337         } else {
4338                 val &= ~CC_BANK_ONE;
4339         }
4340         AscSetChipControl(iop_base, val);
4341 }
4342
4343 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4344 {
4345         AscSetBank(iop_base, 1);
4346         AscWriteChipIH(iop_base, ins_code);
4347         AscSetBank(iop_base, 0);
4348 }
4349
4350 static int AscStartChip(PortAddr iop_base)
4351 {
4352         AscSetChipControl(iop_base, 0);
4353         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4354                 return (0);
4355         }
4356         return (1);
4357 }
4358
4359 static int AscStopChip(PortAddr iop_base)
4360 {
4361         uchar cc_val;
4362
4363         cc_val =
4364             AscGetChipControl(iop_base) &
4365             (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4366         AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4367         AscSetChipIH(iop_base, INS_HALT);
4368         AscSetChipIH(iop_base, INS_RFLAG_WTM);
4369         if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4370                 return (0);
4371         }
4372         return (1);
4373 }
4374
4375 static int AscIsChipHalted(PortAddr iop_base)
4376 {
4377         if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4378                 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4379                         return (1);
4380                 }
4381         }
4382         return (0);
4383 }
4384
4385 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4386 {
4387         PortAddr iop_base;
4388         int i = 10;
4389
4390         iop_base = asc_dvc->iop_base;
4391         while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4392                && (i-- > 0)) {
4393                 mdelay(100);
4394         }
4395         AscStopChip(iop_base);
4396         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4397         udelay(60);
4398         AscSetChipIH(iop_base, INS_RFLAG_WTM);
4399         AscSetChipIH(iop_base, INS_HALT);
4400         AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4401         AscSetChipControl(iop_base, CC_HALT);
4402         mdelay(200);
4403         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4404         AscSetChipStatus(iop_base, 0);
4405         return (AscIsChipHalted(iop_base));
4406 }
4407
4408 static int AscFindSignature(PortAddr iop_base)
4409 {
4410         ushort sig_word;
4411
4412         ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
4413                  iop_base, AscGetChipSignatureByte(iop_base));
4414         if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4415                 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
4416                          iop_base, AscGetChipSignatureWord(iop_base));
4417                 sig_word = AscGetChipSignatureWord(iop_base);
4418                 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4419                     (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4420                         return (1);
4421                 }
4422         }
4423         return (0);
4424 }
4425
4426 static void AscEnableInterrupt(PortAddr iop_base)
4427 {
4428         ushort cfg;
4429
4430         cfg = AscGetChipCfgLsw(iop_base);
4431         AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4432 }
4433
4434 static void AscDisableInterrupt(PortAddr iop_base)
4435 {
4436         ushort cfg;
4437
4438         cfg = AscGetChipCfgLsw(iop_base);
4439         AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4440 }
4441
4442 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4443 {
4444         unsigned char byte_data;
4445         unsigned short word_data;
4446
4447         if (isodd_word(addr)) {
4448                 AscSetChipLramAddr(iop_base, addr - 1);
4449                 word_data = AscGetChipLramData(iop_base);
4450                 byte_data = (word_data >> 8) & 0xFF;
4451         } else {
4452                 AscSetChipLramAddr(iop_base, addr);
4453                 word_data = AscGetChipLramData(iop_base);
4454                 byte_data = word_data & 0xFF;
4455         }
4456         return byte_data;
4457 }
4458
4459 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4460 {
4461         ushort word_data;
4462
4463         AscSetChipLramAddr(iop_base, addr);
4464         word_data = AscGetChipLramData(iop_base);
4465         return (word_data);
4466 }
4467
4468 #if CC_VERY_LONG_SG_LIST
4469 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4470 {
4471         ushort val_low, val_high;
4472         ASC_DCNT dword_data;
4473
4474         AscSetChipLramAddr(iop_base, addr);
4475         val_low = AscGetChipLramData(iop_base);
4476         val_high = AscGetChipLramData(iop_base);
4477         dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4478         return (dword_data);
4479 }
4480 #endif /* CC_VERY_LONG_SG_LIST */
4481
4482 static void
4483 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4484 {
4485         int i;
4486
4487         AscSetChipLramAddr(iop_base, s_addr);
4488         for (i = 0; i < words; i++) {
4489                 AscSetChipLramData(iop_base, set_wval);
4490         }
4491 }
4492
4493 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4494 {
4495         AscSetChipLramAddr(iop_base, addr);
4496         AscSetChipLramData(iop_base, word_val);
4497 }
4498
4499 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4500 {
4501         ushort word_data;
4502
4503         if (isodd_word(addr)) {
4504                 addr--;
4505                 word_data = AscReadLramWord(iop_base, addr);
4506                 word_data &= 0x00FF;
4507                 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4508         } else {
4509                 word_data = AscReadLramWord(iop_base, addr);
4510                 word_data &= 0xFF00;
4511                 word_data |= ((ushort)byte_val & 0x00FF);
4512         }
4513         AscWriteLramWord(iop_base, addr, word_data);
4514 }
4515
4516 /*
4517  * Copy 2 bytes to LRAM.
4518  *
4519  * The source data is assumed to be in little-endian order in memory
4520  * and is maintained in little-endian order when written to LRAM.
4521  */
4522 static void
4523 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4524                         const uchar *s_buffer, int words)
4525 {
4526         int i;
4527
4528         AscSetChipLramAddr(iop_base, s_addr);
4529         for (i = 0; i < 2 * words; i += 2) {
4530                 /*
4531                  * On a little-endian system the second argument below
4532                  * produces a little-endian ushort which is written to
4533                  * LRAM in little-endian order. On a big-endian system
4534                  * the second argument produces a big-endian ushort which
4535                  * is "transparently" byte-swapped by outpw() and written
4536                  * in little-endian order to LRAM.
4537                  */
4538                 outpw(iop_base + IOP_RAM_DATA,
4539                       ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4540         }
4541 }
4542
4543 /*
4544  * Copy 4 bytes to LRAM.
4545  *
4546  * The source data is assumed to be in little-endian order in memory
4547  * and is maintained in little-endian order when written to LRAM.
4548  */
4549 static void
4550 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4551                          ushort s_addr, uchar *s_buffer, int dwords)
4552 {
4553         int i;
4554
4555         AscSetChipLramAddr(iop_base, s_addr);
4556         for (i = 0; i < 4 * dwords; i += 4) {
4557                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
4558                 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
4559         }
4560 }
4561
4562 /*
4563  * Copy 2 bytes from LRAM.
4564  *
4565  * The source data is assumed to be in little-endian order in LRAM
4566  * and is maintained in little-endian order when written to memory.
4567  */
4568 static void
4569 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4570                           ushort s_addr, uchar *d_buffer, int words)
4571 {
4572         int i;
4573         ushort word;
4574
4575         AscSetChipLramAddr(iop_base, s_addr);
4576         for (i = 0; i < 2 * words; i += 2) {
4577                 word = inpw(iop_base + IOP_RAM_DATA);
4578                 d_buffer[i] = word & 0xff;
4579                 d_buffer[i + 1] = (word >> 8) & 0xff;
4580         }
4581 }
4582
4583 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4584 {
4585         ASC_DCNT sum;
4586         int i;
4587
4588         sum = 0L;
4589         for (i = 0; i < words; i++, s_addr += 2) {
4590                 sum += AscReadLramWord(iop_base, s_addr);
4591         }
4592         return (sum);
4593 }
4594
4595 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4596 {
4597         uchar i;
4598         ushort s_addr;
4599         PortAddr iop_base;
4600         ushort warn_code;
4601
4602         iop_base = asc_dvc->iop_base;
4603         warn_code = 0;
4604         AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4605                           (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4606                                     64) >> 1));
4607         i = ASC_MIN_ACTIVE_QNO;
4608         s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4609         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4610                          (uchar)(i + 1));
4611         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4612                          (uchar)(asc_dvc->max_total_qng));
4613         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4614                          (uchar)i);
4615         i++;
4616         s_addr += ASC_QBLK_SIZE;
4617         for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4618                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4619                                  (uchar)(i + 1));
4620                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4621                                  (uchar)(i - 1));
4622                 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4623                                  (uchar)i);
4624         }
4625         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4626                          (uchar)ASC_QLINK_END);
4627         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4628                          (uchar)(asc_dvc->max_total_qng - 1));
4629         AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4630                          (uchar)asc_dvc->max_total_qng);
4631         i++;
4632         s_addr += ASC_QBLK_SIZE;
4633         for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4634              i++, s_addr += ASC_QBLK_SIZE) {
4635                 AscWriteLramByte(iop_base,
4636                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4637                 AscWriteLramByte(iop_base,
4638                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4639                 AscWriteLramByte(iop_base,
4640                                  (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4641         }
4642         return warn_code;
4643 }
4644
4645 static ASC_DCNT
4646 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4647                  const uchar *mcode_buf, ushort mcode_size)
4648 {
4649         ASC_DCNT chksum;
4650         ushort mcode_word_size;
4651         ushort mcode_chksum;
4652
4653         /* Write the microcode buffer starting at LRAM address 0. */
4654         mcode_word_size = (ushort)(mcode_size >> 1);
4655         AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4656         AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4657
4658         chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4659         ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4660         mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4661                                                  (ushort)ASC_CODE_SEC_BEG,
4662                                                  (ushort)((mcode_size -
4663                                                            s_addr - (ushort)
4664                                                            ASC_CODE_SEC_BEG) /
4665                                                           2));
4666         ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4667         AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4668         AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4669         return chksum;
4670 }
4671
4672 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4673 {
4674         PortAddr iop_base;
4675         int i;
4676         ushort lram_addr;
4677
4678         iop_base = asc_dvc->iop_base;
4679         AscPutRiscVarFreeQHead(iop_base, 1);
4680         AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4681         AscPutVarFreeQHead(iop_base, 1);
4682         AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4683         AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4684                          (uchar)((int)asc_dvc->max_total_qng + 1));
4685         AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4686                          (uchar)((int)asc_dvc->max_total_qng + 2));
4687         AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4688                          asc_dvc->max_total_qng);
4689         AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4690         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4691         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4692         AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4693         AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4694         AscPutQDoneInProgress(iop_base, 0);
4695         lram_addr = ASC_QADR_BEG;
4696         for (i = 0; i < 32; i++, lram_addr += 2) {
4697                 AscWriteLramWord(iop_base, lram_addr, 0);
4698         }
4699 }
4700
4701 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4702 {
4703         int i;
4704         ushort warn_code;
4705         PortAddr iop_base;
4706         ASC_PADDR phy_addr;
4707         ASC_DCNT phy_size;
4708         struct asc_board *board = asc_dvc_to_board(asc_dvc);
4709
4710         iop_base = asc_dvc->iop_base;
4711         warn_code = 0;
4712         for (i = 0; i <= ASC_MAX_TID; i++) {
4713                 AscPutMCodeInitSDTRAtID(iop_base, i,
4714                                         asc_dvc->cfg->sdtr_period_offset[i]);
4715         }
4716
4717         AscInitQLinkVar(asc_dvc);
4718         AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4719                          asc_dvc->cfg->disc_enable);
4720         AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4721                          ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4722
4723         /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4724         BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4725         asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4726                                         ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4727         if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4728                 warn_code = -ENOMEM;
4729                 goto err_dma_map;
4730         }
4731         phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4732         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4733                                  (uchar *)&phy_addr, 1);
4734         phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4735         AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4736                                  (uchar *)&phy_size, 1);
4737
4738         asc_dvc->cfg->mcode_date =
4739             AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4740         asc_dvc->cfg->mcode_version =
4741             AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4742
4743         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4744         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4745                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4746                 warn_code = UW_ERR;
4747                 goto err_mcode_start;
4748         }
4749         if (AscStartChip(iop_base) != 1) {
4750                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4751                 warn_code = UW_ERR;
4752                 goto err_mcode_start;
4753         }
4754
4755         return warn_code;
4756
4757 err_mcode_start:
4758         dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4759                          ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4760 err_dma_map:
4761         asc_dvc->overrun_dma = 0;
4762         return warn_code;
4763 }
4764
4765 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4766 {
4767         const struct firmware *fw;
4768         const char fwname[] = "advansys/mcode.bin";
4769         int err;
4770         unsigned long chksum;
4771         ushort warn_code;
4772         PortAddr iop_base;
4773
4774         iop_base = asc_dvc->iop_base;
4775         warn_code = 0;
4776         if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4777             !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4778                 AscResetChipAndScsiBus(asc_dvc);
4779                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4780         }
4781         asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4782         if (asc_dvc->err_code != 0)
4783                 return UW_ERR;
4784         if (!AscFindSignature(asc_dvc->iop_base)) {
4785                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4786                 return warn_code;
4787         }
4788         AscDisableInterrupt(iop_base);
4789         warn_code |= AscInitLram(asc_dvc);
4790         if (asc_dvc->err_code != 0)
4791                 return UW_ERR;
4792
4793         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4794         if (err) {
4795                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4796                        fwname, err);
4797                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4798                 return err;
4799         }
4800         if (fw->size < 4) {
4801                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4802                        fw->size, fwname);
4803                 release_firmware(fw);
4804                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4805                 return -EINVAL;
4806         }
4807         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4808                  (fw->data[1] << 8) | fw->data[0];
4809         ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4810         if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4811                              fw->size - 4) != chksum) {
4812                 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4813                 release_firmware(fw);
4814                 return warn_code;
4815         }
4816         release_firmware(fw);
4817         warn_code |= AscInitMicroCodeVar(asc_dvc);
4818         if (!asc_dvc->overrun_dma)
4819                 return warn_code;
4820         asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4821         AscEnableInterrupt(iop_base);
4822         return warn_code;
4823 }
4824
4825 /*
4826  * Load the Microcode
4827  *
4828  * Write the microcode image to RISC memory starting at address 0.
4829  *
4830  * The microcode is stored compressed in the following format:
4831  *
4832  *  254 word (508 byte) table indexed by byte code followed
4833  *  by the following byte codes:
4834  *
4835  *    1-Byte Code:
4836  *      00: Emit word 0 in table.
4837  *      01: Emit word 1 in table.
4838  *      .
4839  *      FD: Emit word 253 in table.
4840  *
4841  *    Multi-Byte Code:
4842  *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4843  *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4844  *
4845  * Returns 0 or an error if the checksum doesn't match
4846  */
4847 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4848                             int size, int memsize, int chksum)
4849 {
4850         int i, j, end, len = 0;
4851         ADV_DCNT sum;
4852
4853         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4854
4855         for (i = 253 * 2; i < size; i++) {
4856                 if (buf[i] == 0xff) {
4857                         unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4858                         for (j = 0; j < buf[i + 1]; j++) {
4859                                 AdvWriteWordAutoIncLram(iop_base, word);
4860                                 len += 2;
4861                         }
4862                         i += 3;
4863                 } else if (buf[i] == 0xfe) {
4864                         unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4865                         AdvWriteWordAutoIncLram(iop_base, word);
4866                         i += 2;
4867                         len += 2;
4868                 } else {
4869                         unsigned int off = buf[i] * 2;
4870                         unsigned short word = (buf[off + 1] << 8) | buf[off];
4871                         AdvWriteWordAutoIncLram(iop_base, word);
4872                         len += 2;
4873                 }
4874         }
4875
4876         end = len;
4877
4878         while (len < memsize) {
4879                 AdvWriteWordAutoIncLram(iop_base, 0);
4880                 len += 2;
4881         }
4882
4883         /* Verify the microcode checksum. */
4884         sum = 0;
4885         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4886
4887         for (len = 0; len < end; len += 2) {
4888                 sum += AdvReadWordAutoIncLram(iop_base);
4889         }
4890
4891         if (sum != chksum)
4892                 return ASC_IERR_MCODE_CHKSUM;
4893
4894         return 0;
4895 }
4896
4897 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4898 {
4899         ADV_CARR_T *carrp;
4900         ADV_SDCNT buf_size;
4901         ADV_PADDR carr_paddr;
4902
4903         carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4904         asc_dvc->carr_freelist = NULL;
4905         if (carrp == asc_dvc->carrier_buf) {
4906                 buf_size = ADV_CARRIER_BUFSIZE;
4907         } else {
4908                 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4909         }
4910
4911         do {
4912                 /* Get physical address of the carrier 'carrp'. */
4913                 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
4914
4915                 buf_size -= sizeof(ADV_CARR_T);
4916
4917                 carrp->carr_pa = carr_paddr;
4918                 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4919
4920                 /*
4921                  * Insert the carrier at the beginning of the freelist.
4922                  */
4923                 carrp->next_vpa =
4924                         cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4925                 asc_dvc->carr_freelist = carrp;
4926
4927                 carrp++;
4928         } while (buf_size > 0);
4929 }
4930
4931 /*
4932  * Send an idle command to the chip and wait for completion.
4933  *
4934  * Command completion is polled for once per microsecond.
4935  *
4936  * The function can be called from anywhere including an interrupt handler.
4937  * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4938  * functions to prevent reentrancy.
4939  *
4940  * Return Values:
4941  *   ADV_TRUE - command completed successfully
4942  *   ADV_FALSE - command failed
4943  *   ADV_ERROR - command timed out
4944  */
4945 static int
4946 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4947                ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4948 {
4949         int result;
4950         ADV_DCNT i, j;
4951         AdvPortAddr iop_base;
4952
4953         iop_base = asc_dvc->iop_base;
4954
4955         /*
4956          * Clear the idle command status which is set by the microcode
4957          * to a non-zero value to indicate when the command is completed.
4958          * The non-zero result is one of the IDLE_CMD_STATUS_* values
4959          */
4960         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4961
4962         /*
4963          * Write the idle command value after the idle command parameter
4964          * has been written to avoid a race condition. If the order is not
4965          * followed, the microcode may process the idle command before the
4966          * parameters have been written to LRAM.
4967          */
4968         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4969                                 cpu_to_le32(idle_cmd_parameter));
4970         AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4971
4972         /*
4973          * Tickle the RISC to tell it to process the idle command.
4974          */
4975         AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4976         if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4977                 /*
4978                  * Clear the tickle value. In the ASC-3550 the RISC flag
4979                  * command 'clr_tickle_b' does not work unless the host
4980                  * value is cleared.
4981                  */
4982                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4983         }
4984
4985         /* Wait for up to 100 millisecond for the idle command to timeout. */
4986         for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4987                 /* Poll once each microsecond for command completion. */
4988                 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4989                         AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4990                                         result);
4991                         if (result != 0)
4992                                 return result;
4993                         udelay(1);
4994                 }
4995         }
4996
4997         BUG();          /* The idle command should never timeout. */
4998         return ADV_ERROR;
4999 }
5000
5001 /*
5002  * Reset SCSI Bus and purge all outstanding requests.
5003  *
5004  * Return Value:
5005  *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
5006  *      ADV_FALSE(0) -  Microcode command failed.
5007  *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
5008  *                      may be hung which requires driver recovery.
5009  */
5010 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
5011 {
5012         int status;
5013
5014         /*
5015          * Send the SCSI Bus Reset idle start idle command which asserts
5016          * the SCSI Bus Reset signal.
5017          */
5018         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
5019         if (status != ADV_TRUE) {
5020                 return status;
5021         }
5022
5023         /*
5024          * Delay for the specified SCSI Bus Reset hold time.
5025          *
5026          * The hold time delay is done on the host because the RISC has no
5027          * microsecond accurate timer.
5028          */
5029         udelay(ASC_SCSI_RESET_HOLD_TIME_US);
5030
5031         /*
5032          * Send the SCSI Bus Reset end idle command which de-asserts
5033          * the SCSI Bus Reset signal and purges any pending requests.
5034          */
5035         status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
5036         if (status != ADV_TRUE) {
5037                 return status;
5038         }
5039
5040         mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
5041
5042         return status;
5043 }
5044
5045 /*
5046  * Initialize the ASC-3550.
5047  *
5048  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
5049  *
5050  * For a non-fatal error return a warning code. If there are no warnings
5051  * then 0 is returned.
5052  *
5053  * Needed after initialization for error recovery.
5054  */
5055 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
5056 {
5057         const struct firmware *fw;
5058         const char fwname[] = "advansys/3550.bin";
5059         AdvPortAddr iop_base;
5060         ushort warn_code;
5061         int begin_addr;
5062         int end_addr;
5063         ushort code_sum;
5064         int word;
5065         int i;
5066         int err;
5067         unsigned long chksum;
5068         ushort scsi_cfg1;
5069         uchar tid;
5070         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
5071         ushort wdtr_able = 0, sdtr_able, tagqng_able;
5072         uchar max_cmd[ADV_MAX_TID + 1];
5073
5074         /* If there is already an error, don't continue. */
5075         if (asc_dvc->err_code != 0)
5076                 return ADV_ERROR;
5077
5078         /*
5079          * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
5080          */
5081         if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
5082                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5083                 return ADV_ERROR;
5084         }
5085
5086         warn_code = 0;
5087         iop_base = asc_dvc->iop_base;
5088
5089         /*
5090          * Save the RISC memory BIOS region before writing the microcode.
5091          * The BIOS may already be loaded and using its RISC LRAM region
5092          * so its region must be saved and restored.
5093          *
5094          * Note: This code makes the assumption, which is currently true,
5095          * that a chip reset does not clear RISC LRAM.
5096          */
5097         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5098                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5099                                 bios_mem[i]);
5100         }
5101
5102         /*
5103          * Save current per TID negotiated values.
5104          */
5105         if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
5106                 ushort bios_version, major, minor;
5107
5108                 bios_version =
5109                     bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
5110                 major = (bios_version >> 12) & 0xF;
5111                 minor = (bios_version >> 8) & 0xF;
5112                 if (major < 3 || (major == 3 && minor == 1)) {
5113                         /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
5114                         AdvReadWordLram(iop_base, 0x120, wdtr_able);
5115                 } else {
5116                         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5117                 }
5118         }
5119         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5120         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5121         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5122                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5123                                 max_cmd[tid]);
5124         }
5125
5126         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5127         if (err) {
5128                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5129                        fwname, err);
5130                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5131                 return err;
5132         }
5133         if (fw->size < 4) {
5134                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5135                        fw->size, fwname);
5136                 release_firmware(fw);
5137                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5138                 return -EINVAL;
5139         }
5140         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5141                  (fw->data[1] << 8) | fw->data[0];
5142         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5143                                              fw->size - 4, ADV_3550_MEMSIZE,
5144                                              chksum);
5145         release_firmware(fw);
5146         if (asc_dvc->err_code)
5147                 return ADV_ERROR;
5148
5149         /*
5150          * Restore the RISC memory BIOS region.
5151          */
5152         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5153                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5154                                  bios_mem[i]);
5155         }
5156
5157         /*
5158          * Calculate and write the microcode code checksum to the microcode
5159          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5160          */
5161         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5162         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5163         code_sum = 0;
5164         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5165         for (word = begin_addr; word < end_addr; word += 2) {
5166                 code_sum += AdvReadWordAutoIncLram(iop_base);
5167         }
5168         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5169
5170         /*
5171          * Read and save microcode version and date.
5172          */
5173         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5174                         asc_dvc->cfg->mcode_date);
5175         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5176                         asc_dvc->cfg->mcode_version);
5177
5178         /*
5179          * Set the chip type to indicate the ASC3550.
5180          */
5181         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
5182
5183         /*
5184          * If the PCI Configuration Command Register "Parity Error Response
5185          * Control" Bit was clear (0), then set the microcode variable
5186          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5187          * to ignore DMA parity errors.
5188          */
5189         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5190                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5191                 word |= CONTROL_FLAG_IGNORE_PERR;
5192                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5193         }
5194
5195         /*
5196          * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
5197          * threshold of 128 bytes. This register is only accessible to the host.
5198          */
5199         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5200                              START_CTL_EMFU | READ_CMD_MRM);
5201
5202         /*
5203          * Microcode operating variables for WDTR, SDTR, and command tag
5204          * queuing will be set in slave_configure() based on what a
5205          * device reports it is capable of in Inquiry byte 7.
5206          *
5207          * If SCSI Bus Resets have been disabled, then directly set
5208          * SDTR and WDTR from the EEPROM configuration. This will allow
5209          * the BIOS and warm boot to work without a SCSI bus hang on
5210          * the Inquiry caused by host and target mismatched DTR values.
5211          * Without the SCSI Bus Reset, before an Inquiry a device can't
5212          * be assumed to be in Asynchronous, Narrow mode.
5213          */
5214         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5215                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5216                                  asc_dvc->wdtr_able);
5217                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5218                                  asc_dvc->sdtr_able);
5219         }
5220
5221         /*
5222          * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
5223          * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
5224          * bitmask. These values determine the maximum SDTR speed negotiated
5225          * with a device.
5226          *
5227          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5228          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5229          * without determining here whether the device supports SDTR.
5230          *
5231          * 4-bit speed  SDTR speed name
5232          * ===========  ===============
5233          * 0000b (0x0)  SDTR disabled
5234          * 0001b (0x1)  5 Mhz
5235          * 0010b (0x2)  10 Mhz
5236          * 0011b (0x3)  20 Mhz (Ultra)
5237          * 0100b (0x4)  40 Mhz (LVD/Ultra2)
5238          * 0101b (0x5)  80 Mhz (LVD2/Ultra3)
5239          * 0110b (0x6)  Undefined
5240          * .
5241          * 1111b (0xF)  Undefined
5242          */
5243         word = 0;
5244         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5245                 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
5246                         /* Set Ultra speed for TID 'tid'. */
5247                         word |= (0x3 << (4 * (tid % 4)));
5248                 } else {
5249                         /* Set Fast speed for TID 'tid'. */
5250                         word |= (0x2 << (4 * (tid % 4)));
5251                 }
5252                 if (tid == 3) { /* Check if done with sdtr_speed1. */
5253                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
5254                         word = 0;
5255                 } else if (tid == 7) {  /* Check if done with sdtr_speed2. */
5256                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
5257                         word = 0;
5258                 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
5259                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
5260                         word = 0;
5261                 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
5262                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
5263                         /* End of loop. */
5264                 }
5265         }
5266
5267         /*
5268          * Set microcode operating variable for the disconnect per TID bitmask.
5269          */
5270         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5271                          asc_dvc->cfg->disc_enable);
5272
5273         /*
5274          * Set SCSI_CFG0 Microcode Default Value.
5275          *
5276          * The microcode will set the SCSI_CFG0 register using this value
5277          * after it is started below.
5278          */
5279         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5280                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5281                          asc_dvc->chip_scsi_id);
5282
5283         /*
5284          * Determine SCSI_CFG1 Microcode Default Value.
5285          *
5286          * The microcode will set the SCSI_CFG1 register using this value
5287          * after it is started below.
5288          */
5289
5290         /* Read current SCSI_CFG1 Register value. */
5291         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5292
5293         /*
5294          * If all three connectors are in use, return an error.
5295          */
5296         if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
5297             (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
5298                 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
5299                 return ADV_ERROR;
5300         }
5301
5302         /*
5303          * If the internal narrow cable is reversed all of the SCSI_CTRL
5304          * register signals will be set. Check for and return an error if
5305          * this condition is found.
5306          */
5307         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5308                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5309                 return ADV_ERROR;
5310         }
5311
5312         /*
5313          * If this is a differential board and a single-ended device
5314          * is attached to one of the connectors, return an error.
5315          */
5316         if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
5317                 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
5318                 return ADV_ERROR;
5319         }
5320
5321         /*
5322          * If automatic termination control is enabled, then set the
5323          * termination value based on a table listed in a_condor.h.
5324          *
5325          * If manual termination was specified with an EEPROM setting
5326          * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
5327          * is ready to be 'ored' into SCSI_CFG1.
5328          */
5329         if (asc_dvc->cfg->termination == 0) {
5330                 /*
5331                  * The software always controls termination by setting TERM_CTL_SEL.
5332                  * If TERM_CTL_SEL were set to 0, the hardware would set termination.
5333                  */
5334                 asc_dvc->cfg->termination |= TERM_CTL_SEL;
5335
5336                 switch (scsi_cfg1 & CABLE_DETECT) {
5337                         /* TERM_CTL_H: on, TERM_CTL_L: on */
5338                 case 0x3:
5339                 case 0x7:
5340                 case 0xB:
5341                 case 0xD:
5342                 case 0xE:
5343                 case 0xF:
5344                         asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
5345                         break;
5346
5347                         /* TERM_CTL_H: on, TERM_CTL_L: off */
5348                 case 0x1:
5349                 case 0x5:
5350                 case 0x9:
5351                 case 0xA:
5352                 case 0xC:
5353                         asc_dvc->cfg->termination |= TERM_CTL_H;
5354                         break;
5355
5356                         /* TERM_CTL_H: off, TERM_CTL_L: off */
5357                 case 0x2:
5358                 case 0x6:
5359                         break;
5360                 }
5361         }
5362
5363         /*
5364          * Clear any set TERM_CTL_H and TERM_CTL_L bits.
5365          */
5366         scsi_cfg1 &= ~TERM_CTL;
5367
5368         /*
5369          * Invert the TERM_CTL_H and TERM_CTL_L bits and then
5370          * set 'scsi_cfg1'. The TERM_POL bit does not need to be
5371          * referenced, because the hardware internally inverts
5372          * the Termination High and Low bits if TERM_POL is set.
5373          */
5374         scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
5375
5376         /*
5377          * Set SCSI_CFG1 Microcode Default Value
5378          *
5379          * Set filter value and possibly modified termination control
5380          * bits in the Microcode SCSI_CFG1 Register Value.
5381          *
5382          * The microcode will set the SCSI_CFG1 register using this value
5383          * after it is started below.
5384          */
5385         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
5386                          FLTR_DISABLE | scsi_cfg1);
5387
5388         /*
5389          * Set MEM_CFG Microcode Default Value
5390          *
5391          * The microcode will set the MEM_CFG register using this value
5392          * after it is started below.
5393          *
5394          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5395          * are defined.
5396          *
5397          * ASC-3550 has 8KB internal memory.
5398          */
5399         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5400                          BIOS_EN | RAM_SZ_8KB);
5401
5402         /*
5403          * Set SEL_MASK Microcode Default Value
5404          *
5405          * The microcode will set the SEL_MASK register using this value
5406          * after it is started below.
5407          */
5408         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5409                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5410
5411         AdvBuildCarrierFreelist(asc_dvc);
5412
5413         /*
5414          * Set-up the Host->RISC Initiator Command Queue (ICQ).
5415          */
5416
5417         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5418                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5419                 return ADV_ERROR;
5420         }
5421         asc_dvc->carr_freelist = (ADV_CARR_T *)
5422             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5423
5424         /*
5425          * The first command issued will be placed in the stopper carrier.
5426          */
5427         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5428
5429         /*
5430          * Set RISC ICQ physical address start value.
5431          */
5432         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5433
5434         /*
5435          * Set-up the RISC->Host Initiator Response Queue (IRQ).
5436          */
5437         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5438                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5439                 return ADV_ERROR;
5440         }
5441         asc_dvc->carr_freelist = (ADV_CARR_T *)
5442             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5443
5444         /*
5445          * The first command completed by the RISC will be placed in
5446          * the stopper.
5447          *
5448          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5449          * completed the RISC will set the ASC_RQ_STOPPER bit.
5450          */
5451         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5452
5453         /*
5454          * Set RISC IRQ physical address start value.
5455          */
5456         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5457         asc_dvc->carr_pending_cnt = 0;
5458
5459         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5460                              (ADV_INTR_ENABLE_HOST_INTR |
5461                               ADV_INTR_ENABLE_GLOBAL_INTR));
5462
5463         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5464         AdvWriteWordRegister(iop_base, IOPW_PC, word);
5465
5466         /* finally, finally, gentlemen, start your engine */
5467         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5468
5469         /*
5470          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5471          * Resets should be performed. The RISC has to be running
5472          * to issue a SCSI Bus Reset.
5473          */
5474         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5475                 /*
5476                  * If the BIOS Signature is present in memory, restore the
5477                  * BIOS Handshake Configuration Table and do not perform
5478                  * a SCSI Bus Reset.
5479                  */
5480                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5481                     0x55AA) {
5482                         /*
5483                          * Restore per TID negotiated values.
5484                          */
5485                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5486                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5487                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5488                                          tagqng_able);
5489                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5490                                 AdvWriteByteLram(iop_base,
5491                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
5492                                                  max_cmd[tid]);
5493                         }
5494                 } else {
5495                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5496                                 warn_code = ASC_WARN_BUSRESET_ERROR;
5497                         }
5498                 }
5499         }
5500
5501         return warn_code;
5502 }
5503
5504 /*
5505  * Initialize the ASC-38C0800.
5506  *
5507  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
5508  *
5509  * For a non-fatal error return a warning code. If there are no warnings
5510  * then 0 is returned.
5511  *
5512  * Needed after initialization for error recovery.
5513  */
5514 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
5515 {
5516         const struct firmware *fw;
5517         const char fwname[] = "advansys/38C0800.bin";
5518         AdvPortAddr iop_base;
5519         ushort warn_code;
5520         int begin_addr;
5521         int end_addr;
5522         ushort code_sum;
5523         int word;
5524         int i;
5525         int err;
5526         unsigned long chksum;
5527         ushort scsi_cfg1;
5528         uchar byte;
5529         uchar tid;
5530         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
5531         ushort wdtr_able, sdtr_able, tagqng_able;
5532         uchar max_cmd[ADV_MAX_TID + 1];
5533
5534         /* If there is already an error, don't continue. */
5535         if (asc_dvc->err_code != 0)
5536                 return ADV_ERROR;
5537
5538         /*
5539          * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
5540          */
5541         if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
5542                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5543                 return ADV_ERROR;
5544         }
5545
5546         warn_code = 0;
5547         iop_base = asc_dvc->iop_base;
5548
5549         /*
5550          * Save the RISC memory BIOS region before writing the microcode.
5551          * The BIOS may already be loaded and using its RISC LRAM region
5552          * so its region must be saved and restored.
5553          *
5554          * Note: This code makes the assumption, which is currently true,
5555          * that a chip reset does not clear RISC LRAM.
5556          */
5557         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5558                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5559                                 bios_mem[i]);
5560         }
5561
5562         /*
5563          * Save current per TID negotiated values.
5564          */
5565         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5566         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5567         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5568         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5569                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5570                                 max_cmd[tid]);
5571         }
5572
5573         /*
5574          * RAM BIST (RAM Built-In Self Test)
5575          *
5576          * Address : I/O base + offset 0x38h register (byte).
5577          * Function: Bit 7-6(RW) : RAM mode
5578          *                          Normal Mode   : 0x00
5579          *                          Pre-test Mode : 0x40
5580          *                          RAM Test Mode : 0x80
5581          *           Bit 5       : unused
5582          *           Bit 4(RO)   : Done bit
5583          *           Bit 3-0(RO) : Status
5584          *                          Host Error    : 0x08
5585          *                          Int_RAM Error : 0x04
5586          *                          RISC Error    : 0x02
5587          *                          SCSI Error    : 0x01
5588          *                          No Error      : 0x00
5589          *
5590          * Note: RAM BIST code should be put right here, before loading the
5591          * microcode and after saving the RISC memory BIOS region.
5592          */
5593
5594         /*
5595          * LRAM Pre-test
5596          *
5597          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5598          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5599          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5600          * to NORMAL_MODE, return an error too.
5601          */
5602         for (i = 0; i < 2; i++) {
5603                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5604                 mdelay(10);     /* Wait for 10ms before reading back. */
5605                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5606                 if ((byte & RAM_TEST_DONE) == 0
5607                     || (byte & 0x0F) != PRE_TEST_VALUE) {
5608                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5609                         return ADV_ERROR;
5610                 }
5611
5612                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5613                 mdelay(10);     /* Wait for 10ms before reading back. */
5614                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5615                     != NORMAL_VALUE) {
5616                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5617                         return ADV_ERROR;
5618                 }
5619         }
5620
5621         /*
5622          * LRAM Test - It takes about 1.5 ms to run through the test.
5623          *
5624          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5625          * If Done bit not set or Status not 0, save register byte, set the
5626          * err_code, and return an error.
5627          */
5628         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5629         mdelay(10);     /* Wait for 10ms before checking status. */
5630
5631         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5632         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5633                 /* Get here if Done bit not set or Status not 0. */
5634                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
5635                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5636                 return ADV_ERROR;
5637         }
5638
5639         /* We need to reset back to normal mode after LRAM test passes. */
5640         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5641
5642         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5643         if (err) {
5644                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5645                        fwname, err);
5646                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5647                 return err;
5648         }
5649         if (fw->size < 4) {
5650                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5651                        fw->size, fwname);
5652                 release_firmware(fw);
5653                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5654                 return -EINVAL;
5655         }
5656         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5657                  (fw->data[1] << 8) | fw->data[0];
5658         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5659                                              fw->size - 4, ADV_38C0800_MEMSIZE,
5660                                              chksum);
5661         release_firmware(fw);
5662         if (asc_dvc->err_code)
5663                 return ADV_ERROR;
5664
5665         /*
5666          * Restore the RISC memory BIOS region.
5667          */
5668         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5669                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5670                                  bios_mem[i]);
5671         }
5672
5673         /*
5674          * Calculate and write the microcode code checksum to the microcode
5675          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5676          */
5677         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5678         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5679         code_sum = 0;
5680         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5681         for (word = begin_addr; word < end_addr; word += 2) {
5682                 code_sum += AdvReadWordAutoIncLram(iop_base);
5683         }
5684         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5685
5686         /*
5687          * Read microcode version and date.
5688          */
5689         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5690                         asc_dvc->cfg->mcode_date);
5691         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5692                         asc_dvc->cfg->mcode_version);
5693
5694         /*
5695          * Set the chip type to indicate the ASC38C0800.
5696          */
5697         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5698
5699         /*
5700          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5701          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5702          * cable detection and then we are able to read C_DET[3:0].
5703          *
5704          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5705          * Microcode Default Value' section below.
5706          */
5707         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5708         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5709                              scsi_cfg1 | DIS_TERM_DRV);
5710
5711         /*
5712          * If the PCI Configuration Command Register "Parity Error Response
5713          * Control" Bit was clear (0), then set the microcode variable
5714          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5715          * to ignore DMA parity errors.
5716          */
5717         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5718                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5719                 word |= CONTROL_FLAG_IGNORE_PERR;
5720                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5721         }
5722
5723         /*
5724          * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5725          * bits for the default FIFO threshold.
5726          *
5727          * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5728          *
5729          * For DMA Errata #4 set the BC_THRESH_ENB bit.
5730          */
5731         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5732                              BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5733                              READ_CMD_MRM);
5734
5735         /*
5736          * Microcode operating variables for WDTR, SDTR, and command tag
5737          * queuing will be set in slave_configure() based on what a
5738          * device reports it is capable of in Inquiry byte 7.
5739          *
5740          * If SCSI Bus Resets have been disabled, then directly set
5741          * SDTR and WDTR from the EEPROM configuration. This will allow
5742          * the BIOS and warm boot to work without a SCSI bus hang on
5743          * the Inquiry caused by host and target mismatched DTR values.
5744          * Without the SCSI Bus Reset, before an Inquiry a device can't
5745          * be assumed to be in Asynchronous, Narrow mode.
5746          */
5747         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5748                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5749                                  asc_dvc->wdtr_able);
5750                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5751                                  asc_dvc->sdtr_able);
5752         }
5753
5754         /*
5755          * Set microcode operating variables for DISC and SDTR_SPEED1,
5756          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5757          * configuration values.
5758          *
5759          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5760          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5761          * without determining here whether the device supports SDTR.
5762          */
5763         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5764                          asc_dvc->cfg->disc_enable);
5765         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5766         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5767         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5768         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5769
5770         /*
5771          * Set SCSI_CFG0 Microcode Default Value.
5772          *
5773          * The microcode will set the SCSI_CFG0 register using this value
5774          * after it is started below.
5775          */
5776         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5777                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5778                          asc_dvc->chip_scsi_id);
5779
5780         /*
5781          * Determine SCSI_CFG1 Microcode Default Value.
5782          *
5783          * The microcode will set the SCSI_CFG1 register using this value
5784          * after it is started below.
5785          */
5786
5787         /* Read current SCSI_CFG1 Register value. */
5788         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5789
5790         /*
5791          * If the internal narrow cable is reversed all of the SCSI_CTRL
5792          * register signals will be set. Check for and return an error if
5793          * this condition is found.
5794          */
5795         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5796                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5797                 return ADV_ERROR;
5798         }
5799
5800         /*
5801          * All kind of combinations of devices attached to one of four
5802          * connectors are acceptable except HVD device attached. For example,
5803          * LVD device can be attached to SE connector while SE device attached
5804          * to LVD connector.  If LVD device attached to SE connector, it only
5805          * runs up to Ultra speed.
5806          *
5807          * If an HVD device is attached to one of LVD connectors, return an
5808          * error.  However, there is no way to detect HVD device attached to
5809          * SE connectors.
5810          */
5811         if (scsi_cfg1 & HVD) {
5812                 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5813                 return ADV_ERROR;
5814         }
5815
5816         /*
5817          * If either SE or LVD automatic termination control is enabled, then
5818          * set the termination value based on a table listed in a_condor.h.
5819          *
5820          * If manual termination was specified with an EEPROM setting then
5821          * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5822          * to be 'ored' into SCSI_CFG1.
5823          */
5824         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5825                 /* SE automatic termination control is enabled. */
5826                 switch (scsi_cfg1 & C_DET_SE) {
5827                         /* TERM_SE_HI: on, TERM_SE_LO: on */
5828                 case 0x1:
5829                 case 0x2:
5830                 case 0x3:
5831                         asc_dvc->cfg->termination |= TERM_SE;
5832                         break;
5833
5834                         /* TERM_SE_HI: on, TERM_SE_LO: off */
5835                 case 0x0:
5836                         asc_dvc->cfg->termination |= TERM_SE_HI;
5837                         break;
5838                 }
5839         }
5840
5841         if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5842                 /* LVD automatic termination control is enabled. */
5843                 switch (scsi_cfg1 & C_DET_LVD) {
5844                         /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5845                 case 0x4:
5846                 case 0x8:
5847                 case 0xC:
5848                         asc_dvc->cfg->termination |= TERM_LVD;
5849                         break;
5850
5851                         /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5852                 case 0x0:
5853                         break;
5854                 }
5855         }
5856
5857         /*
5858          * Clear any set TERM_SE and TERM_LVD bits.
5859          */
5860         scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5861
5862         /*
5863          * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5864          */
5865         scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5866
5867         /*
5868          * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5869          * bits and set possibly modified termination control bits in the
5870          * Microcode SCSI_CFG1 Register Value.
5871          */
5872         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5873
5874         /*
5875          * Set SCSI_CFG1 Microcode Default Value
5876          *
5877          * Set possibly modified termination control and reset DIS_TERM_DRV
5878          * bits in the Microcode SCSI_CFG1 Register Value.
5879          *
5880          * The microcode will set the SCSI_CFG1 register using this value
5881          * after it is started below.
5882          */
5883         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5884
5885         /*
5886          * Set MEM_CFG Microcode Default Value
5887          *
5888          * The microcode will set the MEM_CFG register using this value
5889          * after it is started below.
5890          *
5891          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5892          * are defined.
5893          *
5894          * ASC-38C0800 has 16KB internal memory.
5895          */
5896         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5897                          BIOS_EN | RAM_SZ_16KB);
5898
5899         /*
5900          * Set SEL_MASK Microcode Default Value
5901          *
5902          * The microcode will set the SEL_MASK register using this value
5903          * after it is started below.
5904          */
5905         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5906                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5907
5908         AdvBuildCarrierFreelist(asc_dvc);
5909
5910         /*
5911          * Set-up the Host->RISC Initiator Command Queue (ICQ).
5912          */
5913
5914         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5915                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5916                 return ADV_ERROR;
5917         }
5918         asc_dvc->carr_freelist = (ADV_CARR_T *)
5919             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5920
5921         /*
5922          * The first command issued will be placed in the stopper carrier.
5923          */
5924         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5925
5926         /*
5927          * Set RISC ICQ physical address start value.
5928          * carr_pa is LE, must be native before write
5929          */
5930         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5931
5932         /*
5933          * Set-up the RISC->Host Initiator Response Queue (IRQ).
5934          */
5935         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5936                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5937                 return ADV_ERROR;
5938         }
5939         asc_dvc->carr_freelist = (ADV_CARR_T *)
5940             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5941
5942         /*
5943          * The first command completed by the RISC will be placed in
5944          * the stopper.
5945          *
5946          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5947          * completed the RISC will set the ASC_RQ_STOPPER bit.
5948          */
5949         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5950
5951         /*
5952          * Set RISC IRQ physical address start value.
5953          *
5954          * carr_pa is LE, must be native before write *
5955          */
5956         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5957         asc_dvc->carr_pending_cnt = 0;
5958
5959         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5960                              (ADV_INTR_ENABLE_HOST_INTR |
5961                               ADV_INTR_ENABLE_GLOBAL_INTR));
5962
5963         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5964         AdvWriteWordRegister(iop_base, IOPW_PC, word);
5965
5966         /* finally, finally, gentlemen, start your engine */
5967         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5968
5969         /*
5970          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5971          * Resets should be performed. The RISC has to be running
5972          * to issue a SCSI Bus Reset.
5973          */
5974         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5975                 /*
5976                  * If the BIOS Signature is present in memory, restore the
5977                  * BIOS Handshake Configuration Table and do not perform
5978                  * a SCSI Bus Reset.
5979                  */
5980                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5981                     0x55AA) {
5982                         /*
5983                          * Restore per TID negotiated values.
5984                          */
5985                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5986                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5987                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5988                                          tagqng_able);
5989                         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5990                                 AdvWriteByteLram(iop_base,
5991                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
5992                                                  max_cmd[tid]);
5993                         }
5994                 } else {
5995                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5996                                 warn_code = ASC_WARN_BUSRESET_ERROR;
5997                         }
5998                 }
5999         }
6000
6001         return warn_code;
6002 }
6003
6004 /*
6005  * Initialize the ASC-38C1600.
6006  *
6007  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
6008  *
6009  * For a non-fatal error return a warning code. If there are no warnings
6010  * then 0 is returned.
6011  *
6012  * Needed after initialization for error recovery.
6013  */
6014 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
6015 {
6016         const struct firmware *fw;
6017         const char fwname[] = "advansys/38C1600.bin";
6018         AdvPortAddr iop_base;
6019         ushort warn_code;
6020         int begin_addr;
6021         int end_addr;
6022         ushort code_sum;
6023         long word;
6024         int i;
6025         int err;
6026         unsigned long chksum;
6027         ushort scsi_cfg1;
6028         uchar byte;
6029         uchar tid;
6030         ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
6031         ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
6032         uchar max_cmd[ASC_MAX_TID + 1];
6033
6034         /* If there is already an error, don't continue. */
6035         if (asc_dvc->err_code != 0) {
6036                 return ADV_ERROR;
6037         }
6038
6039         /*
6040          * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
6041          */
6042         if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
6043                 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6044                 return ADV_ERROR;
6045         }
6046
6047         warn_code = 0;
6048         iop_base = asc_dvc->iop_base;
6049
6050         /*
6051          * Save the RISC memory BIOS region before writing the microcode.
6052          * The BIOS may already be loaded and using its RISC LRAM region
6053          * so its region must be saved and restored.
6054          *
6055          * Note: This code makes the assumption, which is currently true,
6056          * that a chip reset does not clear RISC LRAM.
6057          */
6058         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6059                 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6060                                 bios_mem[i]);
6061         }
6062
6063         /*
6064          * Save current per TID negotiated values.
6065          */
6066         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6067         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6068         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6069         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6070         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
6071                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6072                                 max_cmd[tid]);
6073         }
6074
6075         /*
6076          * RAM BIST (Built-In Self Test)
6077          *
6078          * Address : I/O base + offset 0x38h register (byte).
6079          * Function: Bit 7-6(RW) : RAM mode
6080          *                          Normal Mode   : 0x00
6081          *                          Pre-test Mode : 0x40
6082          *                          RAM Test Mode : 0x80
6083          *           Bit 5       : unused
6084          *           Bit 4(RO)   : Done bit
6085          *           Bit 3-0(RO) : Status
6086          *                          Host Error    : 0x08
6087          *                          Int_RAM Error : 0x04
6088          *                          RISC Error    : 0x02
6089          *                          SCSI Error    : 0x01
6090          *                          No Error      : 0x00
6091          *
6092          * Note: RAM BIST code should be put right here, before loading the
6093          * microcode and after saving the RISC memory BIOS region.
6094          */
6095
6096         /*
6097          * LRAM Pre-test
6098          *
6099          * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
6100          * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
6101          * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
6102          * to NORMAL_MODE, return an error too.
6103          */
6104         for (i = 0; i < 2; i++) {
6105                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
6106                 mdelay(10);     /* Wait for 10ms before reading back. */
6107                 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
6108                 if ((byte & RAM_TEST_DONE) == 0
6109                     || (byte & 0x0F) != PRE_TEST_VALUE) {
6110                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
6111                         return ADV_ERROR;
6112                 }
6113
6114                 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
6115                 mdelay(10);     /* Wait for 10ms before reading back. */
6116                 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
6117                     != NORMAL_VALUE) {
6118                         asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
6119                         return ADV_ERROR;
6120                 }
6121         }
6122
6123         /*
6124          * LRAM Test - It takes about 1.5 ms to run through the test.
6125          *
6126          * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
6127          * If Done bit not set or Status not 0, save register byte, set the
6128          * err_code, and return an error.
6129          */
6130         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
6131         mdelay(10);     /* Wait for 10ms before checking status. */
6132
6133         byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
6134         if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
6135                 /* Get here if Done bit not set or Status not 0. */
6136                 asc_dvc->bist_err_code = byte;  /* for BIOS display message */
6137                 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
6138                 return ADV_ERROR;
6139         }
6140
6141         /* We need to reset back to normal mode after LRAM test passes. */
6142         AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
6143
6144         err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
6145         if (err) {
6146                 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
6147                        fwname, err);
6148                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
6149                 return err;
6150         }
6151         if (fw->size < 4) {
6152                 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
6153                        fw->size, fwname);
6154                 release_firmware(fw);
6155                 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
6156                 return -EINVAL;
6157         }
6158         chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
6159                  (fw->data[1] << 8) | fw->data[0];
6160         asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
6161                                              fw->size - 4, ADV_38C1600_MEMSIZE,
6162                                              chksum);
6163         release_firmware(fw);
6164         if (asc_dvc->err_code)
6165                 return ADV_ERROR;
6166
6167         /*
6168          * Restore the RISC memory BIOS region.
6169          */
6170         for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6171                 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6172                                  bios_mem[i]);
6173         }
6174
6175         /*
6176          * Calculate and write the microcode code checksum to the microcode
6177          * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6178          */
6179         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6180         AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6181         code_sum = 0;
6182         AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6183         for (word = begin_addr; word < end_addr; word += 2) {
6184                 code_sum += AdvReadWordAutoIncLram(iop_base);
6185         }
6186         AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6187
6188         /*
6189          * Read microcode version and date.
6190          */
6191         AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6192                         asc_dvc->cfg->mcode_date);
6193         AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6194                         asc_dvc->cfg->mcode_version);
6195
6196         /*
6197          * Set the chip type to indicate the ASC38C1600.
6198          */
6199         AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
6200
6201         /*
6202          * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
6203          * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
6204          * cable detection and then we are able to read C_DET[3:0].
6205          *
6206          * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
6207          * Microcode Default Value' section below.
6208          */
6209         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
6210         AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
6211                              scsi_cfg1 | DIS_TERM_DRV);
6212
6213         /*
6214          * If the PCI Configuration Command Register "Parity Error Response
6215          * Control" Bit was clear (0), then set the microcode variable
6216          * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6217          * to ignore DMA parity errors.
6218          */
6219         if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6220                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6221                 word |= CONTROL_FLAG_IGNORE_PERR;
6222                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6223         }
6224
6225         /*
6226          * If the BIOS control flag AIPP (Asynchronous Information
6227          * Phase Protection) disable bit is not set, then set the firmware
6228          * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
6229          * AIPP checking and encoding.
6230          */
6231         if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
6232                 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6233                 word |= CONTROL_FLAG_ENABLE_AIPP;
6234                 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6235         }
6236
6237         /*
6238          * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
6239          * and START_CTL_TH [3:2].
6240          */
6241         AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6242                              FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
6243
6244         /*
6245          * Microcode operating variables for WDTR, SDTR, and command tag
6246          * queuing will be set in slave_configure() based on what a
6247          * device reports it is capable of in Inquiry byte 7.
6248          *
6249          * If SCSI Bus Resets have been disabled, then directly set
6250          * SDTR and WDTR from the EEPROM configuration. This will allow
6251          * the BIOS and warm boot to work without a SCSI bus hang on
6252          * the Inquiry caused by host and target mismatched DTR values.
6253          * Without the SCSI Bus Reset, before an Inquiry a device can't
6254          * be assumed to be in Asynchronous, Narrow mode.
6255          */
6256         if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
6257                 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
6258                                  asc_dvc->wdtr_able);
6259                 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
6260                                  asc_dvc->sdtr_able);
6261         }
6262
6263         /*
6264          * Set microcode operating variables for DISC and SDTR_SPEED1,
6265          * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
6266          * configuration values.
6267          *
6268          * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
6269          * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
6270          * without determining here whether the device supports SDTR.
6271          */
6272         AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
6273                          asc_dvc->cfg->disc_enable);
6274         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
6275         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
6276         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
6277         AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
6278
6279         /*
6280          * Set SCSI_CFG0 Microcode Default Value.
6281          *
6282          * The microcode will set the SCSI_CFG0 register using this value
6283          * after it is started below.
6284          */
6285         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
6286                          PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
6287                          asc_dvc->chip_scsi_id);
6288
6289         /*
6290          * Calculate SCSI_CFG1 Microcode Default Value.
6291          *
6292          * The microcode will set the SCSI_CFG1 register using this value
6293          * after it is started below.
6294          *
6295          * Each ASC-38C1600 function has only two cable detect bits.
6296          * The bus mode override bits are in IOPB_SOFT_OVER_WR.
6297          */
6298         scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
6299
6300         /*
6301          * If the cable is reversed all of the SCSI_CTRL register signals
6302          * will be set. Check for and return an error if this condition is
6303          * found.
6304          */
6305         if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
6306                 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
6307                 return ADV_ERROR;
6308         }
6309
6310         /*
6311          * Each ASC-38C1600 function has two connectors. Only an HVD device
6312          * can not be connected to either connector. An LVD device or SE device
6313          * may be connected to either connecor. If an SE device is connected,
6314          * then at most Ultra speed (20 Mhz) can be used on both connectors.
6315          *
6316          * If an HVD device is attached, return an error.
6317          */
6318         if (scsi_cfg1 & HVD) {
6319                 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
6320                 return ADV_ERROR;
6321         }
6322
6323         /*
6324          * Each function in the ASC-38C1600 uses only the SE cable detect and
6325          * termination because there are two connectors for each function. Each
6326          * function may use either LVD or SE mode. Corresponding the SE automatic
6327          * termination control EEPROM bits are used for each function. Each
6328          * function has its own EEPROM. If SE automatic control is enabled for
6329          * the function, then set the termination value based on a table listed
6330          * in a_condor.h.
6331          *
6332          * If manual termination is specified in the EEPROM for the function,
6333          * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
6334          * ready to be 'ored' into SCSI_CFG1.
6335          */
6336         if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
6337                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
6338                 /* SE automatic termination control is enabled. */
6339                 switch (scsi_cfg1 & C_DET_SE) {
6340                         /* TERM_SE_HI: on, TERM_SE_LO: on */
6341                 case 0x1:
6342                 case 0x2:
6343                 case 0x3:
6344                         asc_dvc->cfg->termination |= TERM_SE;
6345                         break;
6346
6347                 case 0x0:
6348                         if (PCI_FUNC(pdev->devfn) == 0) {
6349                                 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
6350                         } else {
6351                                 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
6352                                 asc_dvc->cfg->termination |= TERM_SE_HI;
6353                         }
6354                         break;
6355                 }
6356         }
6357
6358         /*
6359          * Clear any set TERM_SE bits.
6360          */
6361         scsi_cfg1 &= ~TERM_SE;
6362
6363         /*
6364          * Invert the TERM_SE bits and then set 'scsi_cfg1'.
6365          */
6366         scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
6367
6368         /*
6369          * Clear Big Endian and Terminator Polarity bits and set possibly
6370          * modified termination control bits in the Microcode SCSI_CFG1
6371          * Register Value.
6372          *
6373          * Big Endian bit is not used even on big endian machines.
6374          */
6375         scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
6376
6377         /*
6378          * Set SCSI_CFG1 Microcode Default Value
6379          *
6380          * Set possibly modified termination control bits in the Microcode
6381          * SCSI_CFG1 Register Value.
6382          *
6383          * The microcode will set the SCSI_CFG1 register using this value
6384          * after it is started below.
6385          */
6386         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
6387
6388         /*
6389          * Set MEM_CFG Microcode Default Value
6390          *
6391          * The microcode will set the MEM_CFG register using this value
6392          * after it is started below.
6393          *
6394          * MEM_CFG may be accessed as a word or byte, but only bits 0-7
6395          * are defined.
6396          *
6397          * ASC-38C1600 has 32KB internal memory.
6398          *
6399          * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
6400          * out a special 16K Adv Library and Microcode version. After the issue
6401          * resolved, we should turn back to the 32K support. Both a_condor.h and
6402          * mcode.sas files also need to be updated.
6403          *
6404          * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
6405          *  BIOS_EN | RAM_SZ_32KB);
6406          */
6407         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
6408                          BIOS_EN | RAM_SZ_16KB);
6409
6410         /*
6411          * Set SEL_MASK Microcode Default Value
6412          *
6413          * The microcode will set the SEL_MASK register using this value
6414          * after it is started below.
6415          */
6416         AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
6417                          ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
6418
6419         AdvBuildCarrierFreelist(asc_dvc);
6420
6421         /*
6422          * Set-up the Host->RISC Initiator Command Queue (ICQ).
6423          */
6424         if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
6425                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
6426                 return ADV_ERROR;
6427         }
6428         asc_dvc->carr_freelist = (ADV_CARR_T *)
6429             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
6430
6431         /*
6432          * The first command issued will be placed in the stopper carrier.
6433          */
6434         asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
6435
6436         /*
6437          * Set RISC ICQ physical address start value. Initialize the
6438          * COMMA register to the same value otherwise the RISC will
6439          * prematurely detect a command is available.
6440          */
6441         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
6442         AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
6443                               le32_to_cpu(asc_dvc->icq_sp->carr_pa));
6444
6445         /*
6446          * Set-up the RISC->Host Initiator Response Queue (IRQ).
6447          */
6448         if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
6449                 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
6450                 return ADV_ERROR;
6451         }
6452         asc_dvc->carr_freelist = (ADV_CARR_T *)
6453             ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
6454
6455         /*
6456          * The first command completed by the RISC will be placed in
6457          * the stopper.
6458          *
6459          * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
6460          * completed the RISC will set the ASC_RQ_STOPPER bit.
6461          */
6462         asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
6463
6464         /*
6465          * Set RISC IRQ physical address start value.
6466          */
6467         AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
6468         asc_dvc->carr_pending_cnt = 0;
6469
6470         AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
6471                              (ADV_INTR_ENABLE_HOST_INTR |
6472                               ADV_INTR_ENABLE_GLOBAL_INTR));
6473         AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
6474         AdvWriteWordRegister(iop_base, IOPW_PC, word);
6475
6476         /* finally, finally, gentlemen, start your engine */
6477         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
6478
6479         /*
6480          * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
6481          * Resets should be performed. The RISC has to be running
6482          * to issue a SCSI Bus Reset.
6483          */
6484         if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
6485                 /*
6486                  * If the BIOS Signature is present in memory, restore the
6487                  * per TID microcode operating variables.
6488                  */
6489                 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
6490                     0x55AA) {
6491                         /*
6492                          * Restore per TID negotiated values.
6493                          */
6494                         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6495                         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6496                         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6497                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
6498                                          tagqng_able);
6499                         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
6500                                 AdvWriteByteLram(iop_base,
6501                                                  ASC_MC_NUMBER_OF_MAX_CMD + tid,
6502                                                  max_cmd[tid]);
6503                         }
6504                 } else {
6505                         if (AdvResetSB(asc_dvc) != ADV_TRUE) {
6506                                 warn_code = ASC_WARN_BUSRESET_ERROR;
6507                         }
6508                 }
6509         }
6510
6511         return warn_code;
6512 }
6513
6514 /*
6515  * Reset chip and SCSI Bus.
6516  *
6517  * Return Value:
6518  *      ADV_TRUE(1) -   Chip re-initialization and SCSI Bus Reset successful.
6519  *      ADV_FALSE(0) -  Chip re-initialization and SCSI Bus Reset failure.
6520  */
6521 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
6522 {
6523         int status;
6524         ushort wdtr_able, sdtr_able, tagqng_able;
6525         ushort ppr_able = 0;
6526         uchar tid, max_cmd[ADV_MAX_TID + 1];
6527         AdvPortAddr iop_base;
6528         ushort bios_sig;
6529
6530         iop_base = asc_dvc->iop_base;
6531
6532         /*
6533          * Save current per TID negotiated values.
6534          */
6535         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6536         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6537         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6538                 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6539         }
6540         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6541         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6542                 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6543                                 max_cmd[tid]);
6544         }
6545
6546         /*
6547          * Force the AdvInitAsc3550/38C0800Driver() function to
6548          * perform a SCSI Bus Reset by clearing the BIOS signature word.
6549          * The initialization functions assumes a SCSI Bus Reset is not
6550          * needed if the BIOS signature word is present.
6551          */
6552         AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6553         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
6554
6555         /*
6556          * Stop chip and reset it.
6557          */
6558         AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
6559         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
6560         mdelay(100);
6561         AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
6562                              ADV_CTRL_REG_CMD_WR_IO_REG);
6563
6564         /*
6565          * Reset Adv Library error code, if any, and try
6566          * re-initializing the chip.
6567          */
6568         asc_dvc->err_code = 0;
6569         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6570                 status = AdvInitAsc38C1600Driver(asc_dvc);
6571         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6572                 status = AdvInitAsc38C0800Driver(asc_dvc);
6573         } else {
6574                 status = AdvInitAsc3550Driver(asc_dvc);
6575         }
6576
6577         /* Translate initialization return value to status value. */
6578         if (status == 0) {
6579                 status = ADV_TRUE;
6580         } else {
6581                 status = ADV_FALSE;
6582         }
6583
6584         /*
6585          * Restore the BIOS signature word.
6586          */
6587         AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6588
6589         /*
6590          * Restore per TID negotiated values.
6591          */
6592         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6593         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6594         if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6595                 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6596         }
6597         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6598         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6599                 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6600                                  max_cmd[tid]);
6601         }
6602
6603         return status;
6604 }
6605
6606 /*
6607  * adv_async_callback() - Adv Library asynchronous event callback function.
6608  */
6609 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6610 {
6611         switch (code) {
6612         case ADV_ASYNC_SCSI_BUS_RESET_DET:
6613                 /*
6614                  * The firmware detected a SCSI Bus reset.
6615                  */
6616                 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
6617                 break;
6618
6619         case ADV_ASYNC_RDMA_FAILURE:
6620                 /*
6621                  * Handle RDMA failure by resetting the SCSI Bus and
6622                  * possibly the chip if it is unresponsive. Log the error
6623                  * with a unique code.
6624                  */
6625                 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6626                 AdvResetChipAndSB(adv_dvc_varp);
6627                 break;
6628
6629         case ADV_HOST_SCSI_BUS_RESET:
6630                 /*
6631                  * Host generated SCSI bus reset occurred.
6632                  */
6633                 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6634                 break;
6635
6636         default:
6637                 ASC_DBG(0, "unknown code 0x%x\n", code);
6638                 break;
6639         }
6640 }
6641
6642 /*
6643  * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6644  *
6645  * Callback function for the Wide SCSI Adv Library.
6646  */
6647 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6648 {
6649         struct asc_board *boardp;
6650         adv_req_t *reqp;
6651         adv_sgblk_t *sgblkp;
6652         struct scsi_cmnd *scp;
6653         struct Scsi_Host *shost;
6654         ADV_DCNT resid_cnt;
6655
6656         ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
6657                  (ulong)adv_dvc_varp, (ulong)scsiqp);
6658         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6659
6660         /*
6661          * Get the adv_req_t structure for the command that has been
6662          * completed. The adv_req_t structure actually contains the
6663          * completed ADV_SCSI_REQ_Q structure.
6664          */
6665         reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
6666         ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6667         if (reqp == NULL) {
6668                 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6669                 return;
6670         }
6671
6672         /*
6673          * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6674          * command that has been completed.
6675          *
6676          * Note: The adv_req_t request structure and adv_sgblk_t structure,
6677          * if any, are dropped, because a board structure pointer can not be
6678          * determined.
6679          */
6680         scp = reqp->cmndp;
6681         ASC_DBG(1, "scp 0x%p\n", scp);
6682         if (scp == NULL) {
6683                 ASC_PRINT
6684                     ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6685                 return;
6686         }
6687         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6688
6689         shost = scp->device->host;
6690         ASC_STATS(shost, callback);
6691         ASC_DBG(1, "shost 0x%p\n", shost);
6692
6693         boardp = shost_priv(shost);
6694         BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
6695
6696         /*
6697          * 'done_status' contains the command's ending status.
6698          */
6699         switch (scsiqp->done_status) {
6700         case QD_NO_ERROR:
6701                 ASC_DBG(2, "QD_NO_ERROR\n");
6702                 scp->result = 0;
6703
6704                 /*
6705                  * Check for an underrun condition.
6706                  *
6707                  * If there was no error and an underrun condition, then
6708                  * then return the number of underrun bytes.
6709                  */
6710                 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6711                 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6712                     resid_cnt <= scsi_bufflen(scp)) {
6713                         ASC_DBG(1, "underrun condition %lu bytes\n",
6714                                  (ulong)resid_cnt);
6715                         scsi_set_resid(scp, resid_cnt);
6716                 }
6717                 break;
6718
6719         case QD_WITH_ERROR:
6720                 ASC_DBG(2, "QD_WITH_ERROR\n");
6721                 switch (scsiqp->host_status) {
6722                 case QHSTA_NO_ERROR:
6723                         if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6724                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6725                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6726                                                   SCSI_SENSE_BUFFERSIZE);
6727                                 /*
6728                                  * Note: The 'status_byte()' macro used by
6729                                  * target drivers defined in scsi.h shifts the
6730                                  * status byte returned by host drivers right
6731                                  * by 1 bit.  This is why target drivers also
6732                                  * use right shifted status byte definitions.
6733                                  * For instance target drivers use
6734                                  * CHECK_CONDITION, defined to 0x1, instead of
6735                                  * the SCSI defined check condition value of
6736                                  * 0x2. Host drivers are supposed to return
6737                                  * the status byte as it is defined by SCSI.
6738                                  */
6739                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6740                                     STATUS_BYTE(scsiqp->scsi_status);
6741                         } else {
6742                                 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6743                         }
6744                         break;
6745
6746                 default:
6747                         /* Some other QHSTA error occurred. */
6748                         ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6749                         scp->result = HOST_BYTE(DID_BAD_TARGET);
6750                         break;
6751                 }
6752                 break;
6753
6754         case QD_ABORTED_BY_HOST:
6755                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6756                 scp->result =
6757                     HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6758                 break;
6759
6760         default:
6761                 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6762                 scp->result =
6763                     HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6764                 break;
6765         }
6766
6767         /*
6768          * If the 'init_tidmask' bit isn't already set for the target and the
6769          * current request finished normally, then set the bit for the target
6770          * to indicate that a device is present.
6771          */
6772         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6773             scsiqp->done_status == QD_NO_ERROR &&
6774             scsiqp->host_status == QHSTA_NO_ERROR) {
6775                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6776         }
6777
6778         asc_scsi_done(scp);
6779
6780         /*
6781          * Free all 'adv_sgblk_t' structures allocated for the request.
6782          */
6783         while ((sgblkp = reqp->sgblkp) != NULL) {
6784                 /* Remove 'sgblkp' from the request list. */
6785                 reqp->sgblkp = sgblkp->next_sgblkp;
6786
6787                 /* Add 'sgblkp' to the board free list. */
6788                 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6789                 boardp->adv_sgblkp = sgblkp;
6790         }
6791
6792         /*
6793          * Free the adv_req_t structure used with the command by adding
6794          * it back to the board free list.
6795          */
6796         reqp->next_reqp = boardp->adv_reqp;
6797         boardp->adv_reqp = reqp;
6798
6799         ASC_DBG(1, "done\n");
6800 }
6801
6802 /*
6803  * Adv Library Interrupt Service Routine
6804  *
6805  *  This function is called by a driver's interrupt service routine.
6806  *  The function disables and re-enables interrupts.
6807  *
6808  *  When a microcode idle command is completed, the ADV_DVC_VAR
6809  *  'idle_cmd_done' field is set to ADV_TRUE.
6810  *
6811  *  Note: AdvISR() can be called when interrupts are disabled or even
6812  *  when there is no hardware interrupt condition present. It will
6813  *  always check for completed idle commands and microcode requests.
6814  *  This is an important feature that shouldn't be changed because it
6815  *  allows commands to be completed from polling mode loops.
6816  *
6817  * Return:
6818  *   ADV_TRUE(1) - interrupt was pending
6819  *   ADV_FALSE(0) - no interrupt was pending
6820  */
6821 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6822 {
6823         AdvPortAddr iop_base;
6824         uchar int_stat;
6825         ushort target_bit;
6826         ADV_CARR_T *free_carrp;
6827         ADV_VADDR irq_next_vpa;
6828         ADV_SCSI_REQ_Q *scsiq;
6829
6830         iop_base = asc_dvc->iop_base;
6831
6832         /* Reading the register clears the interrupt. */
6833         int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6834
6835         if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6836                          ADV_INTR_STATUS_INTRC)) == 0) {
6837                 return ADV_FALSE;
6838         }
6839
6840         /*
6841          * Notify the driver of an asynchronous microcode condition by
6842          * calling the adv_async_callback function. The function
6843          * is passed the microcode ASC_MC_INTRB_CODE byte value.
6844          */
6845         if (int_stat & ADV_INTR_STATUS_INTRB) {
6846                 uchar intrb_code;
6847
6848                 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6849
6850                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6851                     asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6852                         if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6853                             asc_dvc->carr_pending_cnt != 0) {
6854                                 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6855                                                      ADV_TICKLE_A);
6856                                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6857                                         AdvWriteByteRegister(iop_base,
6858                                                              IOPB_TICKLE,
6859                                                              ADV_TICKLE_NOP);
6860                                 }
6861                         }
6862                 }
6863
6864                 adv_async_callback(asc_dvc, intrb_code);
6865         }
6866
6867         /*
6868          * Check if the IRQ stopper carrier contains a completed request.
6869          */
6870         while (((irq_next_vpa =
6871                  le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6872                 /*
6873                  * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6874                  * The RISC will have set 'areq_vpa' to a virtual address.
6875                  *
6876                  * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6877                  * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6878                  * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6879                  * in AdvExeScsiQueue().
6880                  */
6881                 scsiq = (ADV_SCSI_REQ_Q *)
6882                     ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
6883
6884                 /*
6885                  * Request finished with good status and the queue was not
6886                  * DMAed to host memory by the firmware. Set all status fields
6887                  * to indicate good status.
6888                  */
6889                 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6890                         scsiq->done_status = QD_NO_ERROR;
6891                         scsiq->host_status = scsiq->scsi_status = 0;
6892                         scsiq->data_cnt = 0L;
6893                 }
6894
6895                 /*
6896                  * Advance the stopper pointer to the next carrier
6897                  * ignoring the lower four bits. Free the previous
6898                  * stopper carrier.
6899                  */
6900                 free_carrp = asc_dvc->irq_sp;
6901                 asc_dvc->irq_sp = (ADV_CARR_T *)
6902                     ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
6903
6904                 free_carrp->next_vpa =
6905                     cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6906                 asc_dvc->carr_freelist = free_carrp;
6907                 asc_dvc->carr_pending_cnt--;
6908
6909                 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6910
6911                 /*
6912                  * Clear request microcode control flag.
6913                  */
6914                 scsiq->cntl = 0;
6915
6916                 /*
6917                  * Notify the driver of the completed request by passing
6918                  * the ADV_SCSI_REQ_Q pointer to its callback function.
6919                  */
6920                 scsiq->a_flag |= ADV_SCSIQ_DONE;
6921                 adv_isr_callback(asc_dvc, scsiq);
6922                 /*
6923                  * Note: After the driver callback function is called, 'scsiq'
6924                  * can no longer be referenced.
6925                  *
6926                  * Fall through and continue processing other completed
6927                  * requests...
6928                  */
6929         }
6930         return ADV_TRUE;
6931 }
6932
6933 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6934 {
6935         if (asc_dvc->err_code == 0) {
6936                 asc_dvc->err_code = err_code;
6937                 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6938                                  err_code);
6939         }
6940         return err_code;
6941 }
6942
6943 static void AscAckInterrupt(PortAddr iop_base)
6944 {
6945         uchar host_flag;
6946         uchar risc_flag;
6947         ushort loop;
6948
6949         loop = 0;
6950         do {
6951                 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6952                 if (loop++ > 0x7FFF) {
6953                         break;
6954                 }
6955         } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6956         host_flag =
6957             AscReadLramByte(iop_base,
6958                             ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6959         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6960                          (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6961         AscSetChipStatus(iop_base, CIW_INT_ACK);
6962         loop = 0;
6963         while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6964                 AscSetChipStatus(iop_base, CIW_INT_ACK);
6965                 if (loop++ > 3) {
6966                         break;
6967                 }
6968         }
6969         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6970 }
6971
6972 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6973 {
6974         const uchar *period_table;
6975         int max_index;
6976         int min_index;
6977         int i;
6978
6979         period_table = asc_dvc->sdtr_period_tbl;
6980         max_index = (int)asc_dvc->max_sdtr_index;
6981         min_index = (int)asc_dvc->min_sdtr_index;
6982         if ((syn_time <= period_table[max_index])) {
6983                 for (i = min_index; i < (max_index - 1); i++) {
6984                         if (syn_time <= period_table[i]) {
6985                                 return (uchar)i;
6986                         }
6987                 }
6988                 return (uchar)max_index;
6989         } else {
6990                 return (uchar)(max_index + 1);
6991         }
6992 }
6993
6994 static uchar
6995 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6996 {
6997         EXT_MSG sdtr_buf;
6998         uchar sdtr_period_index;
6999         PortAddr iop_base;
7000
7001         iop_base = asc_dvc->iop_base;
7002         sdtr_buf.msg_type = EXTENDED_MESSAGE;
7003         sdtr_buf.msg_len = MS_SDTR_LEN;
7004         sdtr_buf.msg_req = EXTENDED_SDTR;
7005         sdtr_buf.xfer_period = sdtr_period;
7006         sdtr_offset &= ASC_SYN_MAX_OFFSET;
7007         sdtr_buf.req_ack_offset = sdtr_offset;
7008         sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
7009         if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
7010                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
7011                                         (uchar *)&sdtr_buf,
7012                                         sizeof(EXT_MSG) >> 1);
7013                 return ((sdtr_period_index << 4) | sdtr_offset);
7014         } else {
7015                 sdtr_buf.req_ack_offset = 0;
7016                 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
7017                                         (uchar *)&sdtr_buf,
7018                                         sizeof(EXT_MSG) >> 1);
7019                 return 0;
7020         }
7021 }
7022
7023 static uchar
7024 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
7025 {
7026         uchar byte;
7027         uchar sdtr_period_ix;
7028
7029         sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
7030         if (sdtr_period_ix > asc_dvc->max_sdtr_index)
7031                 return 0xFF;
7032         byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
7033         return byte;
7034 }
7035
7036 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
7037 {
7038         ASC_SCSI_BIT_ID_TYPE org_id;
7039         int i;
7040         int sta = TRUE;
7041
7042         AscSetBank(iop_base, 1);
7043         org_id = AscReadChipDvcID(iop_base);
7044         for (i = 0; i <= ASC_MAX_TID; i++) {
7045                 if (org_id == (0x01 << i))
7046                         break;
7047         }
7048         org_id = (ASC_SCSI_BIT_ID_TYPE) i;
7049         AscWriteChipDvcID(iop_base, id);
7050         if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
7051                 AscSetBank(iop_base, 0);
7052                 AscSetChipSyn(iop_base, sdtr_data);
7053                 if (AscGetChipSyn(iop_base) != sdtr_data) {
7054                         sta = FALSE;
7055                 }
7056         } else {
7057                 sta = FALSE;
7058         }
7059         AscSetBank(iop_base, 1);
7060         AscWriteChipDvcID(iop_base, org_id);
7061         AscSetBank(iop_base, 0);
7062         return (sta);
7063 }
7064
7065 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
7066 {
7067         AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7068         AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
7069 }
7070
7071 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
7072 {
7073         EXT_MSG ext_msg;
7074         EXT_MSG out_msg;
7075         ushort halt_q_addr;
7076         int sdtr_accept;
7077         ushort int_halt_code;
7078         ASC_SCSI_BIT_ID_TYPE scsi_busy;
7079         ASC_SCSI_BIT_ID_TYPE target_id;
7080         PortAddr iop_base;
7081         uchar tag_code;
7082         uchar q_status;
7083         uchar halt_qp;
7084         uchar sdtr_data;
7085         uchar target_ix;
7086         uchar q_cntl, tid_no;
7087         uchar cur_dvc_qng;
7088         uchar asyn_sdtr;
7089         uchar scsi_status;
7090         struct asc_board *boardp;
7091
7092         BUG_ON(!asc_dvc->drv_ptr);
7093         boardp = asc_dvc->drv_ptr;
7094
7095         iop_base = asc_dvc->iop_base;
7096         int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
7097
7098         halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
7099         halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
7100         target_ix = AscReadLramByte(iop_base,
7101                                     (ushort)(halt_q_addr +
7102                                              (ushort)ASC_SCSIQ_B_TARGET_IX));
7103         q_cntl = AscReadLramByte(iop_base,
7104                             (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
7105         tid_no = ASC_TIX_TO_TID(target_ix);
7106         target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
7107         if (asc_dvc->pci_fix_asyn_xfer & target_id) {
7108                 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
7109         } else {
7110                 asyn_sdtr = 0;
7111         }
7112         if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
7113                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
7114                         AscSetChipSDTR(iop_base, 0, tid_no);
7115                         boardp->sdtr_data[tid_no] = 0;
7116                 }
7117                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7118                 return (0);
7119         } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
7120                 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
7121                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
7122                         boardp->sdtr_data[tid_no] = asyn_sdtr;
7123                 }
7124                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7125                 return (0);
7126         } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
7127                 AscMemWordCopyPtrFromLram(iop_base,
7128                                           ASCV_MSGIN_BEG,
7129                                           (uchar *)&ext_msg,
7130                                           sizeof(EXT_MSG) >> 1);
7131
7132                 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
7133                     ext_msg.msg_req == EXTENDED_SDTR &&
7134                     ext_msg.msg_len == MS_SDTR_LEN) {
7135                         sdtr_accept = TRUE;
7136                         if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
7137
7138                                 sdtr_accept = FALSE;
7139                                 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
7140                         }
7141                         if ((ext_msg.xfer_period <
7142                              asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
7143                             || (ext_msg.xfer_period >
7144                                 asc_dvc->sdtr_period_tbl[asc_dvc->
7145                                                          max_sdtr_index])) {
7146                                 sdtr_accept = FALSE;
7147                                 ext_msg.xfer_period =
7148                                     asc_dvc->sdtr_period_tbl[asc_dvc->
7149                                                              min_sdtr_index];
7150                         }
7151                         if (sdtr_accept) {
7152                                 sdtr_data =
7153                                     AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
7154                                                    ext_msg.req_ack_offset);
7155                                 if ((sdtr_data == 0xFF)) {
7156
7157                                         q_cntl |= QC_MSG_OUT;
7158                                         asc_dvc->init_sdtr &= ~target_id;
7159                                         asc_dvc->sdtr_done &= ~target_id;
7160                                         AscSetChipSDTR(iop_base, asyn_sdtr,
7161                                                        tid_no);
7162                                         boardp->sdtr_data[tid_no] = asyn_sdtr;
7163                                 }
7164                         }
7165                         if (ext_msg.req_ack_offset == 0) {
7166
7167                                 q_cntl &= ~QC_MSG_OUT;
7168                                 asc_dvc->init_sdtr &= ~target_id;
7169                                 asc_dvc->sdtr_done &= ~target_id;
7170                                 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
7171                         } else {
7172                                 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
7173                                         q_cntl &= ~QC_MSG_OUT;
7174                                         asc_dvc->sdtr_done |= target_id;
7175                                         asc_dvc->init_sdtr |= target_id;
7176                                         asc_dvc->pci_fix_asyn_xfer &=
7177                                             ~target_id;
7178                                         sdtr_data =
7179                                             AscCalSDTRData(asc_dvc,
7180                                                            ext_msg.xfer_period,
7181                                                            ext_msg.
7182                                                            req_ack_offset);
7183                                         AscSetChipSDTR(iop_base, sdtr_data,
7184                                                        tid_no);
7185                                         boardp->sdtr_data[tid_no] = sdtr_data;
7186                                 } else {
7187                                         q_cntl |= QC_MSG_OUT;
7188                                         AscMsgOutSDTR(asc_dvc,
7189                                                       ext_msg.xfer_period,
7190                                                       ext_msg.req_ack_offset);
7191                                         asc_dvc->pci_fix_asyn_xfer &=
7192                                             ~target_id;
7193                                         sdtr_data =
7194                                             AscCalSDTRData(asc_dvc,
7195                                                            ext_msg.xfer_period,
7196                                                            ext_msg.
7197                                                            req_ack_offset);
7198                                         AscSetChipSDTR(iop_base, sdtr_data,
7199                                                        tid_no);
7200                                         boardp->sdtr_data[tid_no] = sdtr_data;
7201                                         asc_dvc->sdtr_done |= target_id;
7202                                         asc_dvc->init_sdtr |= target_id;
7203                                 }
7204                         }
7205
7206                         AscWriteLramByte(iop_base,
7207                                          (ushort)(halt_q_addr +
7208                                                   (ushort)ASC_SCSIQ_B_CNTL),
7209                                          q_cntl);
7210                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7211                         return (0);
7212                 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
7213                            ext_msg.msg_req == EXTENDED_WDTR &&
7214                            ext_msg.msg_len == MS_WDTR_LEN) {
7215
7216                         ext_msg.wdtr_width = 0;
7217                         AscMemWordCopyPtrToLram(iop_base,
7218                                                 ASCV_MSGOUT_BEG,
7219                                                 (uchar *)&ext_msg,
7220                                                 sizeof(EXT_MSG) >> 1);
7221                         q_cntl |= QC_MSG_OUT;
7222                         AscWriteLramByte(iop_base,
7223                                          (ushort)(halt_q_addr +
7224                                                   (ushort)ASC_SCSIQ_B_CNTL),
7225                                          q_cntl);
7226                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7227                         return (0);
7228                 } else {
7229
7230                         ext_msg.msg_type = MESSAGE_REJECT;
7231                         AscMemWordCopyPtrToLram(iop_base,
7232                                                 ASCV_MSGOUT_BEG,
7233                                                 (uchar *)&ext_msg,
7234                                                 sizeof(EXT_MSG) >> 1);
7235                         q_cntl |= QC_MSG_OUT;
7236                         AscWriteLramByte(iop_base,
7237                                          (ushort)(halt_q_addr +
7238                                                   (ushort)ASC_SCSIQ_B_CNTL),
7239                                          q_cntl);
7240                         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7241                         return (0);
7242                 }
7243         } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
7244
7245                 q_cntl |= QC_REQ_SENSE;
7246
7247                 if ((asc_dvc->init_sdtr & target_id) != 0) {
7248
7249                         asc_dvc->sdtr_done &= ~target_id;
7250
7251                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
7252                         q_cntl |= QC_MSG_OUT;
7253                         AscMsgOutSDTR(asc_dvc,
7254                                       asc_dvc->
7255                                       sdtr_period_tbl[(sdtr_data >> 4) &
7256                                                       (uchar)(asc_dvc->
7257                                                               max_sdtr_index -
7258                                                               1)],
7259                                       (uchar)(sdtr_data & (uchar)
7260                                               ASC_SYN_MAX_OFFSET));
7261                 }
7262
7263                 AscWriteLramByte(iop_base,
7264                                  (ushort)(halt_q_addr +
7265                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
7266
7267                 tag_code = AscReadLramByte(iop_base,
7268                                            (ushort)(halt_q_addr + (ushort)
7269                                                     ASC_SCSIQ_B_TAG_CODE));
7270                 tag_code &= 0xDC;
7271                 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
7272                     && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
7273                     ) {
7274
7275                         tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
7276                                      | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
7277
7278                 }
7279                 AscWriteLramByte(iop_base,
7280                                  (ushort)(halt_q_addr +
7281                                           (ushort)ASC_SCSIQ_B_TAG_CODE),
7282                                  tag_code);
7283
7284                 q_status = AscReadLramByte(iop_base,
7285                                            (ushort)(halt_q_addr + (ushort)
7286                                                     ASC_SCSIQ_B_STATUS));
7287                 q_status |= (QS_READY | QS_BUSY);
7288                 AscWriteLramByte(iop_base,
7289                                  (ushort)(halt_q_addr +
7290                                           (ushort)ASC_SCSIQ_B_STATUS),
7291                                  q_status);
7292
7293                 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
7294                 scsi_busy &= ~target_id;
7295                 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
7296
7297                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7298                 return (0);
7299         } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
7300
7301                 AscMemWordCopyPtrFromLram(iop_base,
7302                                           ASCV_MSGOUT_BEG,
7303                                           (uchar *)&out_msg,
7304                                           sizeof(EXT_MSG) >> 1);
7305
7306                 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
7307                     (out_msg.msg_len == MS_SDTR_LEN) &&
7308                     (out_msg.msg_req == EXTENDED_SDTR)) {
7309
7310                         asc_dvc->init_sdtr &= ~target_id;
7311                         asc_dvc->sdtr_done &= ~target_id;
7312                         AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
7313                         boardp->sdtr_data[tid_no] = asyn_sdtr;
7314                 }
7315                 q_cntl &= ~QC_MSG_OUT;
7316                 AscWriteLramByte(iop_base,
7317                                  (ushort)(halt_q_addr +
7318                                           (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
7319                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7320                 return (0);
7321         } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
7322
7323                 scsi_status = AscReadLramByte(iop_base,
7324                                               (ushort)((ushort)halt_q_addr +
7325                                                        (ushort)
7326                                                        ASC_SCSIQ_SCSI_STATUS));
7327                 cur_dvc_qng =
7328                     AscReadLramByte(iop_base,
7329                                     (ushort)((ushort)ASC_QADR_BEG +
7330                                              (ushort)target_ix));
7331                 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
7332
7333                         scsi_busy = AscReadLramByte(iop_base,
7334                                                     (ushort)ASCV_SCSIBUSY_B);
7335                         scsi_busy |= target_id;
7336                         AscWriteLramByte(iop_base,
7337                                          (ushort)ASCV_SCSIBUSY_B, scsi_busy);
7338                         asc_dvc->queue_full_or_busy |= target_id;
7339
7340                         if (scsi_status == SAM_STAT_TASK_SET_FULL) {
7341                                 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
7342                                         cur_dvc_qng -= 1;
7343                                         asc_dvc->max_dvc_qng[tid_no] =
7344                                             cur_dvc_qng;
7345
7346                                         AscWriteLramByte(iop_base,
7347                                                          (ushort)((ushort)
7348                                                                   ASCV_MAX_DVC_QNG_BEG
7349                                                                   + (ushort)
7350                                                                   tid_no),
7351                                                          cur_dvc_qng);
7352
7353                                         /*
7354                                          * Set the device queue depth to the
7355                                          * number of active requests when the
7356                                          * QUEUE FULL condition was encountered.
7357                                          */
7358                                         boardp->queue_full |= target_id;
7359                                         boardp->queue_full_cnt[tid_no] =
7360                                             cur_dvc_qng;
7361                                 }
7362                         }
7363                 }
7364                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7365                 return (0);
7366         }
7367 #if CC_VERY_LONG_SG_LIST
7368         else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
7369                 uchar q_no;
7370                 ushort q_addr;
7371                 uchar sg_wk_q_no;
7372                 uchar first_sg_wk_q_no;
7373                 ASC_SCSI_Q *scsiq;      /* Ptr to driver request. */
7374                 ASC_SG_HEAD *sg_head;   /* Ptr to driver SG request. */
7375                 ASC_SG_LIST_Q scsi_sg_q;        /* Structure written to queue. */
7376                 ushort sg_list_dwords;
7377                 ushort sg_entry_cnt;
7378                 uchar next_qp;
7379                 int i;
7380
7381                 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
7382                 if (q_no == ASC_QLINK_END)
7383                         return 0;
7384
7385                 q_addr = ASC_QNO_TO_QADDR(q_no);
7386
7387                 /*
7388                  * Convert the request's SRB pointer to a host ASC_SCSI_REQ
7389                  * structure pointer using a macro provided by the driver.
7390                  * The ASC_SCSI_REQ pointer provides a pointer to the
7391                  * host ASC_SG_HEAD structure.
7392                  */
7393                 /* Read request's SRB pointer. */
7394                 scsiq = (ASC_SCSI_Q *)
7395                     ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
7396                                                                     (ushort)
7397                                                                     (q_addr +
7398                                                                      ASC_SCSIQ_D_SRBPTR))));
7399
7400                 /*
7401                  * Get request's first and working SG queue.
7402                  */
7403                 sg_wk_q_no = AscReadLramByte(iop_base,
7404                                              (ushort)(q_addr +
7405                                                       ASC_SCSIQ_B_SG_WK_QP));
7406
7407                 first_sg_wk_q_no = AscReadLramByte(iop_base,
7408                                                    (ushort)(q_addr +
7409                                                             ASC_SCSIQ_B_FIRST_SG_WK_QP));
7410
7411                 /*
7412                  * Reset request's working SG queue back to the
7413                  * first SG queue.
7414                  */
7415                 AscWriteLramByte(iop_base,
7416                                  (ushort)(q_addr +
7417                                           (ushort)ASC_SCSIQ_B_SG_WK_QP),
7418                                  first_sg_wk_q_no);
7419
7420                 sg_head = scsiq->sg_head;
7421
7422                 /*
7423                  * Set sg_entry_cnt to the number of SG elements
7424                  * that will be completed on this interrupt.
7425                  *
7426                  * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
7427                  * SG elements. The data_cnt and data_addr fields which
7428                  * add 1 to the SG element capacity are not used when
7429                  * restarting SG handling after a halt.
7430                  */
7431                 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
7432                         sg_entry_cnt = ASC_MAX_SG_LIST - 1;
7433
7434                         /*
7435                          * Keep track of remaining number of SG elements that
7436                          * will need to be handled on the next interrupt.
7437                          */
7438                         scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
7439                 } else {
7440                         sg_entry_cnt = scsiq->remain_sg_entry_cnt;
7441                         scsiq->remain_sg_entry_cnt = 0;
7442                 }
7443
7444                 /*
7445                  * Copy SG elements into the list of allocated SG queues.
7446                  *
7447                  * Last index completed is saved in scsiq->next_sg_index.
7448                  */
7449                 next_qp = first_sg_wk_q_no;
7450                 q_addr = ASC_QNO_TO_QADDR(next_qp);
7451                 scsi_sg_q.sg_head_qp = q_no;
7452                 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
7453                 for (i = 0; i < sg_head->queue_cnt; i++) {
7454                         scsi_sg_q.seq_no = i + 1;
7455                         if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
7456                                 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
7457                                 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
7458                                 /*
7459                                  * After very first SG queue RISC FW uses next
7460                                  * SG queue first element then checks sg_list_cnt
7461                                  * against zero and then decrements, so set
7462                                  * sg_list_cnt 1 less than number of SG elements
7463                                  * in each SG queue.
7464                                  */
7465                                 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
7466                                 scsi_sg_q.sg_cur_list_cnt =
7467                                     ASC_SG_LIST_PER_Q - 1;
7468                         } else {
7469                                 /*
7470                                  * This is the last SG queue in the list of
7471                                  * allocated SG queues. If there are more
7472                                  * SG elements than will fit in the allocated
7473                                  * queues, then set the QCSG_SG_XFER_MORE flag.
7474                                  */
7475                                 if (scsiq->remain_sg_entry_cnt != 0) {
7476                                         scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
7477                                 } else {
7478                                         scsi_sg_q.cntl |= QCSG_SG_XFER_END;
7479                                 }
7480                                 /* equals sg_entry_cnt * 2 */
7481                                 sg_list_dwords = sg_entry_cnt << 1;
7482                                 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
7483                                 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
7484                                 sg_entry_cnt = 0;
7485                         }
7486
7487                         scsi_sg_q.q_no = next_qp;
7488                         AscMemWordCopyPtrToLram(iop_base,
7489                                                 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
7490                                                 (uchar *)&scsi_sg_q,
7491                                                 sizeof(ASC_SG_LIST_Q) >> 1);
7492
7493                         AscMemDWordCopyPtrToLram(iop_base,
7494                                                  q_addr + ASC_SGQ_LIST_BEG,
7495                                                  (uchar *)&sg_head->
7496                                                  sg_list[scsiq->next_sg_index],
7497                                                  sg_list_dwords);
7498
7499                         scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
7500
7501                         /*
7502                          * If the just completed SG queue contained the
7503                          * last SG element, then no more SG queues need
7504                          * to be written.
7505                          */
7506                         if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
7507                                 break;
7508                         }
7509
7510                         next_qp = AscReadLramByte(iop_base,
7511                                                   (ushort)(q_addr +
7512                                                            ASC_SCSIQ_B_FWD));
7513                         q_addr = ASC_QNO_TO_QADDR(next_qp);
7514                 }
7515
7516                 /*
7517                  * Clear the halt condition so the RISC will be restarted
7518                  * after the return.
7519                  */
7520                 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7521                 return (0);
7522         }
7523 #endif /* CC_VERY_LONG_SG_LIST */
7524         return (0);
7525 }
7526
7527 /*
7528  * void
7529  * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7530  *
7531  * Calling/Exit State:
7532  *    none
7533  *
7534  * Description:
7535  *     Input an ASC_QDONE_INFO structure from the chip
7536  */
7537 static void
7538 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7539 {
7540         int i;
7541         ushort word;
7542
7543         AscSetChipLramAddr(iop_base, s_addr);
7544         for (i = 0; i < 2 * words; i += 2) {
7545                 if (i == 10) {
7546                         continue;
7547                 }
7548                 word = inpw(iop_base + IOP_RAM_DATA);
7549                 inbuf[i] = word & 0xff;
7550                 inbuf[i + 1] = (word >> 8) & 0xff;
7551         }
7552         ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
7553 }
7554
7555 static uchar
7556 _AscCopyLramScsiDoneQ(PortAddr iop_base,
7557                       ushort q_addr,
7558                       ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
7559 {
7560         ushort _val;
7561         uchar sg_queue_cnt;
7562
7563         DvcGetQinfo(iop_base,
7564                     q_addr + ASC_SCSIQ_DONE_INFO_BEG,
7565                     (uchar *)scsiq,
7566                     (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
7567
7568         _val = AscReadLramWord(iop_base,
7569                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
7570         scsiq->q_status = (uchar)_val;
7571         scsiq->q_no = (uchar)(_val >> 8);
7572         _val = AscReadLramWord(iop_base,
7573                                (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
7574         scsiq->cntl = (uchar)_val;
7575         sg_queue_cnt = (uchar)(_val >> 8);
7576         _val = AscReadLramWord(iop_base,
7577                                (ushort)(q_addr +
7578                                         (ushort)ASC_SCSIQ_B_SENSE_LEN));
7579         scsiq->sense_len = (uchar)_val;
7580         scsiq->extra_bytes = (uchar)(_val >> 8);
7581
7582         /*
7583          * Read high word of remain bytes from alternate location.
7584          */
7585         scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7586                                                           (ushort)(q_addr +
7587                                                                    (ushort)
7588                                                                    ASC_SCSIQ_W_ALT_DC1)))
7589                                << 16);
7590         /*
7591          * Read low word of remain bytes from original location.
7592          */
7593         scsiq->remain_bytes += AscReadLramWord(iop_base,
7594                                                (ushort)(q_addr + (ushort)
7595                                                         ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7596
7597         scsiq->remain_bytes &= max_dma_count;
7598         return sg_queue_cnt;
7599 }
7600
7601 /*
7602  * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7603  *
7604  * Interrupt callback function for the Narrow SCSI Asc Library.
7605  */
7606 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7607 {
7608         struct asc_board *boardp;
7609         struct scsi_cmnd *scp;
7610         struct Scsi_Host *shost;
7611
7612         ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
7613         ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7614
7615         scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr);
7616         if (!scp)
7617                 return;
7618
7619         ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7620
7621         shost = scp->device->host;
7622         ASC_STATS(shost, callback);
7623         ASC_DBG(1, "shost 0x%p\n", shost);
7624
7625         boardp = shost_priv(shost);
7626         BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
7627
7628         dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7629                          SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7630         /*
7631          * 'qdonep' contains the command's ending status.
7632          */
7633         switch (qdonep->d3.done_stat) {
7634         case QD_NO_ERROR:
7635                 ASC_DBG(2, "QD_NO_ERROR\n");
7636                 scp->result = 0;
7637
7638                 /*
7639                  * Check for an underrun condition.
7640                  *
7641                  * If there was no error and an underrun condition, then
7642                  * return the number of underrun bytes.
7643                  */
7644                 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7645                     qdonep->remain_bytes <= scsi_bufflen(scp)) {
7646                         ASC_DBG(1, "underrun condition %u bytes\n",
7647                                  (unsigned)qdonep->remain_bytes);
7648                         scsi_set_resid(scp, qdonep->remain_bytes);
7649                 }
7650                 break;
7651
7652         case QD_WITH_ERROR:
7653                 ASC_DBG(2, "QD_WITH_ERROR\n");
7654                 switch (qdonep->d3.host_stat) {
7655                 case QHSTA_NO_ERROR:
7656                         if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7657                                 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7658                                 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7659                                                   SCSI_SENSE_BUFFERSIZE);
7660                                 /*
7661                                  * Note: The 'status_byte()' macro used by
7662                                  * target drivers defined in scsi.h shifts the
7663                                  * status byte returned by host drivers right
7664                                  * by 1 bit.  This is why target drivers also
7665                                  * use right shifted status byte definitions.
7666                                  * For instance target drivers use
7667                                  * CHECK_CONDITION, defined to 0x1, instead of
7668                                  * the SCSI defined check condition value of
7669                                  * 0x2. Host drivers are supposed to return
7670                                  * the status byte as it is defined by SCSI.
7671                                  */
7672                                 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7673                                     STATUS_BYTE(qdonep->d3.scsi_stat);
7674                         } else {
7675                                 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7676                         }
7677                         break;
7678
7679                 default:
7680                         /* QHSTA error occurred */
7681                         ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7682                         scp->result = HOST_BYTE(DID_BAD_TARGET);
7683                         break;
7684                 }
7685                 break;
7686
7687         case QD_ABORTED_BY_HOST:
7688                 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7689                 scp->result =
7690                     HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7691                                                     scsi_msg) |
7692                     STATUS_BYTE(qdonep->d3.scsi_stat);
7693                 break;
7694
7695         default:
7696                 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7697                 scp->result =
7698                     HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7699                                                     scsi_msg) |
7700                     STATUS_BYTE(qdonep->d3.scsi_stat);
7701                 break;
7702         }
7703
7704         /*
7705          * If the 'init_tidmask' bit isn't already set for the target and the
7706          * current request finished normally, then set the bit for the target
7707          * to indicate that a device is present.
7708          */
7709         if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7710             qdonep->d3.done_stat == QD_NO_ERROR &&
7711             qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7712                 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7713         }
7714
7715         asc_scsi_done(scp);
7716 }
7717
7718 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7719 {
7720         uchar next_qp;
7721         uchar n_q_used;
7722         uchar sg_list_qp;
7723         uchar sg_queue_cnt;
7724         uchar q_cnt;
7725         uchar done_q_tail;
7726         uchar tid_no;
7727         ASC_SCSI_BIT_ID_TYPE scsi_busy;
7728         ASC_SCSI_BIT_ID_TYPE target_id;
7729         PortAddr iop_base;
7730         ushort q_addr;
7731         ushort sg_q_addr;
7732         uchar cur_target_qng;
7733         ASC_QDONE_INFO scsiq_buf;
7734         ASC_QDONE_INFO *scsiq;
7735         int false_overrun;
7736
7737         iop_base = asc_dvc->iop_base;
7738         n_q_used = 1;
7739         scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7740         done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7741         q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7742         next_qp = AscReadLramByte(iop_base,
7743                                   (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7744         if (next_qp != ASC_QLINK_END) {
7745                 AscPutVarDoneQTail(iop_base, next_qp);
7746                 q_addr = ASC_QNO_TO_QADDR(next_qp);
7747                 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7748                                                      asc_dvc->max_dma_count);
7749                 AscWriteLramByte(iop_base,
7750                                  (ushort)(q_addr +
7751                                           (ushort)ASC_SCSIQ_B_STATUS),
7752                                  (uchar)(scsiq->
7753                                          q_status & (uchar)~(QS_READY |
7754                                                              QS_ABORTED)));
7755                 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7756                 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7757                 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7758                         sg_q_addr = q_addr;
7759                         sg_list_qp = next_qp;
7760                         for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7761                                 sg_list_qp = AscReadLramByte(iop_base,
7762                                                              (ushort)(sg_q_addr
7763                                                                       + (ushort)
7764                                                                       ASC_SCSIQ_B_FWD));
7765                                 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7766                                 if (sg_list_qp == ASC_QLINK_END) {
7767                                         AscSetLibErrorCode(asc_dvc,
7768                                                            ASCQ_ERR_SG_Q_LINKS);
7769                                         scsiq->d3.done_stat = QD_WITH_ERROR;
7770                                         scsiq->d3.host_stat =
7771                                             QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7772                                         goto FATAL_ERR_QDONE;
7773                                 }
7774                                 AscWriteLramByte(iop_base,
7775                                                  (ushort)(sg_q_addr + (ushort)
7776                                                           ASC_SCSIQ_B_STATUS),
7777                                                  QS_FREE);
7778                         }
7779                         n_q_used = sg_queue_cnt + 1;
7780                         AscPutVarDoneQTail(iop_base, sg_list_qp);
7781                 }
7782                 if (asc_dvc->queue_full_or_busy & target_id) {
7783                         cur_target_qng = AscReadLramByte(iop_base,
7784                                                          (ushort)((ushort)
7785                                                                   ASC_QADR_BEG
7786                                                                   + (ushort)
7787                                                                   scsiq->d2.
7788                                                                   target_ix));
7789                         if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7790                                 scsi_busy = AscReadLramByte(iop_base, (ushort)
7791                                                             ASCV_SCSIBUSY_B);
7792                                 scsi_busy &= ~target_id;
7793                                 AscWriteLramByte(iop_base,
7794                                                  (ushort)ASCV_SCSIBUSY_B,
7795                                                  scsi_busy);
7796                                 asc_dvc->queue_full_or_busy &= ~target_id;
7797                         }
7798                 }
7799                 if (asc_dvc->cur_total_qng >= n_q_used) {
7800                         asc_dvc->cur_total_qng -= n_q_used;
7801                         if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7802                                 asc_dvc->cur_dvc_qng[tid_no]--;
7803                         }
7804                 } else {
7805                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7806                         scsiq->d3.done_stat = QD_WITH_ERROR;
7807                         goto FATAL_ERR_QDONE;
7808                 }
7809                 if ((scsiq->d2.srb_ptr == 0UL) ||
7810                     ((scsiq->q_status & QS_ABORTED) != 0)) {
7811                         return (0x11);
7812                 } else if (scsiq->q_status == QS_DONE) {
7813                         false_overrun = FALSE;
7814                         if (scsiq->extra_bytes != 0) {
7815                                 scsiq->remain_bytes +=
7816                                     (ADV_DCNT)scsiq->extra_bytes;
7817                         }
7818                         if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7819                                 if (scsiq->d3.host_stat ==
7820                                     QHSTA_M_DATA_OVER_RUN) {
7821                                         if ((scsiq->
7822                                              cntl & (QC_DATA_IN | QC_DATA_OUT))
7823                                             == 0) {
7824                                                 scsiq->d3.done_stat =
7825                                                     QD_NO_ERROR;
7826                                                 scsiq->d3.host_stat =
7827                                                     QHSTA_NO_ERROR;
7828                                         } else if (false_overrun) {
7829                                                 scsiq->d3.done_stat =
7830                                                     QD_NO_ERROR;
7831                                                 scsiq->d3.host_stat =
7832                                                     QHSTA_NO_ERROR;
7833                                         }
7834                                 } else if (scsiq->d3.host_stat ==
7835                                            QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7836                                         AscStopChip(iop_base);
7837                                         AscSetChipControl(iop_base,
7838                                                           (uchar)(CC_SCSI_RESET
7839                                                                   | CC_HALT));
7840                                         udelay(60);
7841                                         AscSetChipControl(iop_base, CC_HALT);
7842                                         AscSetChipStatus(iop_base,
7843                                                          CIW_CLR_SCSI_RESET_INT);
7844                                         AscSetChipStatus(iop_base, 0);
7845                                         AscSetChipControl(iop_base, 0);
7846                                 }
7847                         }
7848                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7849                                 asc_isr_callback(asc_dvc, scsiq);
7850                         } else {
7851                                 if ((AscReadLramByte(iop_base,
7852                                                      (ushort)(q_addr + (ushort)
7853                                                               ASC_SCSIQ_CDB_BEG))
7854                                      == START_STOP)) {
7855                                         asc_dvc->unit_not_ready &= ~target_id;
7856                                         if (scsiq->d3.done_stat != QD_NO_ERROR) {
7857                                                 asc_dvc->start_motor &=
7858                                                     ~target_id;
7859                                         }
7860                                 }
7861                         }
7862                         return (1);
7863                 } else {
7864                         AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7865  FATAL_ERR_QDONE:
7866                         if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7867                                 asc_isr_callback(asc_dvc, scsiq);
7868                         }
7869                         return (0x80);
7870                 }
7871         }
7872         return (0);
7873 }
7874
7875 static int AscISR(ASC_DVC_VAR *asc_dvc)
7876 {
7877         ASC_CS_TYPE chipstat;
7878         PortAddr iop_base;
7879         ushort saved_ram_addr;
7880         uchar ctrl_reg;
7881         uchar saved_ctrl_reg;
7882         int int_pending;
7883         int status;
7884         uchar host_flag;
7885
7886         iop_base = asc_dvc->iop_base;
7887         int_pending = FALSE;
7888
7889         if (AscIsIntPending(iop_base) == 0)
7890                 return int_pending;
7891
7892         if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7893                 return ERR;
7894         }
7895         if (asc_dvc->in_critical_cnt != 0) {
7896                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7897                 return ERR;
7898         }
7899         if (asc_dvc->is_in_int) {
7900                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7901                 return ERR;
7902         }
7903         asc_dvc->is_in_int = TRUE;
7904         ctrl_reg = AscGetChipControl(iop_base);
7905         saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7906                                        CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7907         chipstat = AscGetChipStatus(iop_base);
7908         if (chipstat & CSW_SCSI_RESET_LATCH) {
7909                 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7910                         int i = 10;
7911                         int_pending = TRUE;
7912                         asc_dvc->sdtr_done = 0;
7913                         saved_ctrl_reg &= (uchar)(~CC_HALT);
7914                         while ((AscGetChipStatus(iop_base) &
7915                                 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7916                                 mdelay(100);
7917                         }
7918                         AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7919                         AscSetChipControl(iop_base, CC_HALT);
7920                         AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7921                         AscSetChipStatus(iop_base, 0);
7922                         chipstat = AscGetChipStatus(iop_base);
7923                 }
7924         }
7925         saved_ram_addr = AscGetChipLramAddr(iop_base);
7926         host_flag = AscReadLramByte(iop_base,
7927                                     ASCV_HOST_FLAG_B) &
7928             (uchar)(~ASC_HOST_FLAG_IN_ISR);
7929         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7930                          (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7931         if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7932                 AscAckInterrupt(iop_base);
7933                 int_pending = TRUE;
7934                 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7935                         if (AscIsrChipHalted(asc_dvc) == ERR) {
7936                                 goto ISR_REPORT_QDONE_FATAL_ERROR;
7937                         } else {
7938                                 saved_ctrl_reg &= (uchar)(~CC_HALT);
7939                         }
7940                 } else {
7941  ISR_REPORT_QDONE_FATAL_ERROR:
7942                         if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7943                                 while (((status =
7944                                          AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7945                                 }
7946                         } else {
7947                                 do {
7948                                         if ((status =
7949                                              AscIsrQDone(asc_dvc)) == 1) {
7950                                                 break;
7951                                         }
7952                                 } while (status == 0x11);
7953                         }
7954                         if ((status & 0x80) != 0)
7955                                 int_pending = ERR;
7956                 }
7957         }
7958         AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7959         AscSetChipLramAddr(iop_base, saved_ram_addr);
7960         AscSetChipControl(iop_base, saved_ctrl_reg);
7961         asc_dvc->is_in_int = FALSE;
7962         return int_pending;
7963 }
7964
7965 /*
7966  * advansys_reset()
7967  *
7968  * Reset the bus associated with the command 'scp'.
7969  *
7970  * This function runs its own thread. Interrupts must be blocked but
7971  * sleeping is allowed and no locking other than for host structures is
7972  * required. Returns SUCCESS or FAILED.
7973  */
7974 static int advansys_reset(struct scsi_cmnd *scp)
7975 {
7976         struct Scsi_Host *shost = scp->device->host;
7977         struct asc_board *boardp = shost_priv(shost);
7978         unsigned long flags;
7979         int status;
7980         int ret = SUCCESS;
7981
7982         ASC_DBG(1, "0x%p\n", scp);
7983
7984         ASC_STATS(shost, reset);
7985
7986         scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
7987
7988         if (ASC_NARROW_BOARD(boardp)) {
7989                 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7990
7991                 /* Reset the chip and SCSI bus. */
7992                 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7993                 status = AscInitAsc1000Driver(asc_dvc);
7994
7995                 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7996                 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7997                         scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
7998                                     "0x%x, status: 0x%x\n", asc_dvc->err_code,
7999                                     status);
8000                         ret = FAILED;
8001                 } else if (status) {
8002                         scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
8003                                     "0x%x\n", status);
8004                 } else {
8005                         scmd_printk(KERN_INFO, scp, "SCSI bus reset "
8006                                     "successful\n");
8007                 }
8008
8009                 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
8010                 spin_lock_irqsave(shost->host_lock, flags);
8011         } else {
8012                 /*
8013                  * If the suggest reset bus flags are set, then reset the bus.
8014                  * Otherwise only reset the device.
8015                  */
8016                 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8017
8018                 /*
8019                  * Reset the target's SCSI bus.
8020                  */
8021                 ASC_DBG(1, "before AdvResetChipAndSB()\n");
8022                 switch (AdvResetChipAndSB(adv_dvc)) {
8023                 case ASC_TRUE:
8024                         scmd_printk(KERN_INFO, scp, "SCSI bus reset "
8025                                     "successful\n");
8026                         break;
8027                 case ASC_FALSE:
8028                 default:
8029                         scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
8030                         ret = FAILED;
8031                         break;
8032                 }
8033                 spin_lock_irqsave(shost->host_lock, flags);
8034                 AdvISR(adv_dvc);
8035         }
8036
8037         /* Save the time of the most recently completed reset. */
8038         boardp->last_reset = jiffies;
8039         spin_unlock_irqrestore(shost->host_lock, flags);
8040
8041         ASC_DBG(1, "ret %d\n", ret);
8042
8043         return ret;
8044 }
8045
8046 /*
8047  * advansys_biosparam()
8048  *
8049  * Translate disk drive geometry if the "BIOS greater than 1 GB"
8050  * support is enabled for a drive.
8051  *
8052  * ip (information pointer) is an int array with the following definition:
8053  * ip[0]: heads
8054  * ip[1]: sectors
8055  * ip[2]: cylinders
8056  */
8057 static int
8058 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
8059                    sector_t capacity, int ip[])
8060 {
8061         struct asc_board *boardp = shost_priv(sdev->host);
8062
8063         ASC_DBG(1, "begin\n");
8064         ASC_STATS(sdev->host, biosparam);
8065         if (ASC_NARROW_BOARD(boardp)) {
8066                 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
8067                      ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
8068                         ip[0] = 255;
8069                         ip[1] = 63;
8070                 } else {
8071                         ip[0] = 64;
8072                         ip[1] = 32;
8073                 }
8074         } else {
8075                 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
8076                      BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
8077                         ip[0] = 255;
8078                         ip[1] = 63;
8079                 } else {
8080                         ip[0] = 64;
8081                         ip[1] = 32;
8082                 }
8083         }
8084         ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
8085         ASC_DBG(1, "end\n");
8086         return 0;
8087 }
8088
8089 /*
8090  * First-level interrupt handler.
8091  *
8092  * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
8093  */
8094 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
8095 {
8096         struct Scsi_Host *shost = dev_id;
8097         struct asc_board *boardp = shost_priv(shost);
8098         irqreturn_t result = IRQ_NONE;
8099
8100         ASC_DBG(2, "boardp 0x%p\n", boardp);
8101         spin_lock(shost->host_lock);
8102         if (ASC_NARROW_BOARD(boardp)) {
8103                 if (AscIsIntPending(shost->io_port)) {
8104                         result = IRQ_HANDLED;
8105                         ASC_STATS(shost, interrupt);
8106                         ASC_DBG(1, "before AscISR()\n");
8107                         AscISR(&boardp->dvc_var.asc_dvc_var);
8108                 }
8109         } else {
8110                 ASC_DBG(1, "before AdvISR()\n");
8111                 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
8112                         result = IRQ_HANDLED;
8113                         ASC_STATS(shost, interrupt);
8114                 }
8115         }
8116         spin_unlock(shost->host_lock);
8117
8118         ASC_DBG(1, "end\n");
8119         return result;
8120 }
8121
8122 static int AscHostReqRiscHalt(PortAddr iop_base)
8123 {
8124         int count = 0;
8125         int sta = 0;
8126         uchar saved_stop_code;
8127
8128         if (AscIsChipHalted(iop_base))
8129                 return (1);
8130         saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
8131         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8132                          ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
8133         do {
8134                 if (AscIsChipHalted(iop_base)) {
8135                         sta = 1;
8136                         break;
8137                 }
8138                 mdelay(100);
8139         } while (count++ < 20);
8140         AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
8141         return (sta);
8142 }
8143
8144 static int
8145 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
8146 {
8147         int sta = FALSE;
8148
8149         if (AscHostReqRiscHalt(iop_base)) {
8150                 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8151                 AscStartChip(iop_base);
8152         }
8153         return sta;
8154 }
8155
8156 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
8157 {
8158         char type = sdev->type;
8159         ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
8160
8161         if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
8162                 return;
8163         if (asc_dvc->init_sdtr & tid_bits)
8164                 return;
8165
8166         if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
8167                 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
8168
8169         asc_dvc->pci_fix_asyn_xfer |= tid_bits;
8170         if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
8171             (type == TYPE_ROM) || (type == TYPE_TAPE))
8172                 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
8173
8174         if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
8175                 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
8176                                         ASYN_SDTR_DATA_FIX_PCI_REV_AB);
8177 }
8178
8179 static void
8180 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
8181 {
8182         ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
8183         ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
8184
8185         if (sdev->lun == 0) {
8186                 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
8187                 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
8188                         asc_dvc->init_sdtr |= tid_bit;
8189                 } else {
8190                         asc_dvc->init_sdtr &= ~tid_bit;
8191                 }
8192
8193                 if (orig_init_sdtr != asc_dvc->init_sdtr)
8194                         AscAsyncFix(asc_dvc, sdev);
8195         }
8196
8197         if (sdev->tagged_supported) {
8198                 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
8199                         if (sdev->lun == 0) {
8200                                 asc_dvc->cfg->can_tagged_qng |= tid_bit;
8201                                 asc_dvc->use_tagged_qng |= tid_bit;
8202                         }
8203                         scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
8204                                                 asc_dvc->max_dvc_qng[sdev->id]);
8205                 }
8206         } else {
8207                 if (sdev->lun == 0) {
8208                         asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
8209                         asc_dvc->use_tagged_qng &= ~tid_bit;
8210                 }
8211                 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
8212         }
8213
8214         if ((sdev->lun == 0) &&
8215             (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
8216                 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
8217                                  asc_dvc->cfg->disc_enable);
8218                 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
8219                                  asc_dvc->use_tagged_qng);
8220                 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
8221                                  asc_dvc->cfg->can_tagged_qng);
8222
8223                 asc_dvc->max_dvc_qng[sdev->id] =
8224                                         asc_dvc->cfg->max_tag_qng[sdev->id];
8225                 AscWriteLramByte(asc_dvc->iop_base,
8226                                  (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
8227                                  asc_dvc->max_dvc_qng[sdev->id]);
8228         }
8229 }
8230
8231 /*
8232  * Wide Transfers
8233  *
8234  * If the EEPROM enabled WDTR for the device and the device supports wide
8235  * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
8236  * write the new value to the microcode.
8237  */
8238 static void
8239 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
8240 {
8241         unsigned short cfg_word;
8242         AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
8243         if ((cfg_word & tidmask) != 0)
8244                 return;
8245
8246         cfg_word |= tidmask;
8247         AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
8248
8249         /*
8250          * Clear the microcode SDTR and WDTR negotiation done indicators for
8251          * the target to cause it to negotiate with the new setting set above.
8252          * WDTR when accepted causes the target to enter asynchronous mode, so
8253          * SDTR must be negotiated.
8254          */
8255         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
8256         cfg_word &= ~tidmask;
8257         AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
8258         AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
8259         cfg_word &= ~tidmask;
8260         AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
8261 }
8262
8263 /*
8264  * Synchronous Transfers
8265  *
8266  * If the EEPROM enabled SDTR for the device and the device
8267  * supports synchronous transfers, then turn on the device's
8268  * 'sdtr_able' bit. Write the new value to the microcode.
8269  */
8270 static void
8271 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
8272 {
8273         unsigned short cfg_word;
8274         AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
8275         if ((cfg_word & tidmask) != 0)
8276                 return;
8277
8278         cfg_word |= tidmask;
8279         AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
8280
8281         /*
8282          * Clear the microcode "SDTR negotiation" done indicator for the
8283          * target to cause it to negotiate with the new setting set above.
8284          */
8285         AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
8286         cfg_word &= ~tidmask;
8287         AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
8288 }
8289
8290 /*
8291  * PPR (Parallel Protocol Request) Capable
8292  *
8293  * If the device supports DT mode, then it must be PPR capable.
8294  * The PPR message will be used in place of the SDTR and WDTR
8295  * messages to negotiate synchronous speed and offset, transfer
8296  * width, and protocol options.
8297  */
8298 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
8299                                 AdvPortAddr iop_base, unsigned short tidmask)
8300 {
8301         AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
8302         adv_dvc->ppr_able |= tidmask;
8303         AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
8304 }
8305
8306 static void
8307 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
8308 {
8309         AdvPortAddr iop_base = adv_dvc->iop_base;
8310         unsigned short tidmask = 1 << sdev->id;
8311
8312         if (sdev->lun == 0) {
8313                 /*
8314                  * Handle WDTR, SDTR, and Tag Queuing. If the feature
8315                  * is enabled in the EEPROM and the device supports the
8316                  * feature, then enable it in the microcode.
8317                  */
8318
8319                 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
8320                         advansys_wide_enable_wdtr(iop_base, tidmask);
8321                 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
8322                         advansys_wide_enable_sdtr(iop_base, tidmask);
8323                 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
8324                         advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
8325
8326                 /*
8327                  * Tag Queuing is disabled for the BIOS which runs in polled
8328                  * mode and would see no benefit from Tag Queuing. Also by
8329                  * disabling Tag Queuing in the BIOS devices with Tag Queuing
8330                  * bugs will at least work with the BIOS.
8331                  */
8332                 if ((adv_dvc->tagqng_able & tidmask) &&
8333                     sdev->tagged_supported) {
8334                         unsigned short cfg_word;
8335                         AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
8336                         cfg_word |= tidmask;
8337                         AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8338                                          cfg_word);
8339                         AdvWriteByteLram(iop_base,
8340                                          ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
8341                                          adv_dvc->max_dvc_qng);
8342                 }
8343         }
8344
8345         if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
8346                 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
8347                                         adv_dvc->max_dvc_qng);
8348         } else {
8349                 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
8350         }
8351 }
8352
8353 /*
8354  * Set the number of commands to queue per device for the
8355  * specified host adapter.
8356  */
8357 static int advansys_slave_configure(struct scsi_device *sdev)
8358 {
8359         struct asc_board *boardp = shost_priv(sdev->host);
8360
8361         if (ASC_NARROW_BOARD(boardp))
8362                 advansys_narrow_slave_configure(sdev,
8363                                                 &boardp->dvc_var.asc_dvc_var);
8364         else
8365                 advansys_wide_slave_configure(sdev,
8366                                                 &boardp->dvc_var.adv_dvc_var);
8367
8368         return 0;
8369 }
8370
8371 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
8372 {
8373         struct asc_board *board = shost_priv(scp->device->host);
8374         scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
8375                                              SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8376         dma_cache_sync(board->dev, scp->sense_buffer,
8377                        SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8378         return cpu_to_le32(scp->SCp.dma_handle);
8379 }
8380
8381 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
8382                         struct asc_scsi_q *asc_scsi_q)
8383 {
8384         struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8385         int use_sg;
8386
8387         memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
8388
8389         /*
8390          * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
8391          */
8392         asc_scsi_q->q2.srb_ptr = advansys_ptr_to_srb(asc_dvc, scp);
8393         if (asc_scsi_q->q2.srb_ptr == BAD_SRB) {
8394                 scp->result = HOST_BYTE(DID_SOFT_ERROR);
8395                 return ASC_ERROR;
8396         }
8397
8398         /*
8399          * Build the ASC_SCSI_Q request.
8400          */
8401         asc_scsi_q->cdbptr = &scp->cmnd[0];
8402         asc_scsi_q->q2.cdb_len = scp->cmd_len;
8403         asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
8404         asc_scsi_q->q1.target_lun = scp->device->lun;
8405         asc_scsi_q->q2.target_ix =
8406             ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
8407         asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
8408         asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
8409
8410         /*
8411          * If there are any outstanding requests for the current target,
8412          * then every 255th request send an ORDERED request. This heuristic
8413          * tries to retain the benefit of request sorting while preventing
8414          * request starvation. 255 is the max number of tags or pending commands
8415          * a device may have outstanding.
8416          *
8417          * The request count is incremented below for every successfully
8418          * started request.
8419          *
8420          */
8421         if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
8422             (boardp->reqcnt[scp->device->id] % 255) == 0) {
8423                 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
8424         } else {
8425                 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
8426         }
8427
8428         /* Build ASC_SCSI_Q */
8429         use_sg = scsi_dma_map(scp);
8430         if (use_sg != 0) {
8431                 int sgcnt;
8432                 struct scatterlist *slp;
8433                 struct asc_sg_head *asc_sg_head;
8434
8435                 if (use_sg > scp->device->host->sg_tablesize) {
8436                         scmd_printk(KERN_ERR, scp, "use_sg %d > "
8437                                 "sg_tablesize %d\n", use_sg,
8438                                 scp->device->host->sg_tablesize);
8439                         scsi_dma_unmap(scp);
8440                         scp->result = HOST_BYTE(DID_ERROR);
8441                         return ASC_ERROR;
8442                 }
8443
8444                 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
8445                         use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
8446                 if (!asc_sg_head) {
8447                         scsi_dma_unmap(scp);
8448                         scp->result = HOST_BYTE(DID_SOFT_ERROR);
8449                         return ASC_ERROR;
8450                 }
8451
8452                 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
8453                 asc_scsi_q->sg_head = asc_sg_head;
8454                 asc_scsi_q->q1.data_cnt = 0;
8455                 asc_scsi_q->q1.data_addr = 0;
8456                 /* This is a byte value, otherwise it would need to be swapped. */
8457                 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
8458                 ASC_STATS_ADD(scp->device->host, xfer_elem,
8459                               asc_sg_head->entry_cnt);
8460
8461                 /*
8462                  * Convert scatter-gather list into ASC_SG_HEAD list.
8463                  */
8464                 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
8465                         asc_sg_head->sg_list[sgcnt].addr =
8466                             cpu_to_le32(sg_dma_address(slp));
8467                         asc_sg_head->sg_list[sgcnt].bytes =
8468                             cpu_to_le32(sg_dma_len(slp));
8469                         ASC_STATS_ADD(scp->device->host, xfer_sect,
8470                                       DIV_ROUND_UP(sg_dma_len(slp), 512));
8471                 }
8472         }
8473
8474         ASC_STATS(scp->device->host, xfer_cnt);
8475
8476         ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
8477         ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8478
8479         return ASC_NOERROR;
8480 }
8481
8482 /*
8483  * Build scatter-gather list for Adv Library (Wide Board).
8484  *
8485  * Additional ADV_SG_BLOCK structures will need to be allocated
8486  * if the total number of scatter-gather elements exceeds
8487  * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
8488  * assumed to be physically contiguous.
8489  *
8490  * Return:
8491  *      ADV_SUCCESS(1) - SG List successfully created
8492  *      ADV_ERROR(-1) - SG List creation failed
8493  */
8494 static int
8495 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
8496                int use_sg)
8497 {
8498         adv_sgblk_t *sgblkp;
8499         ADV_SCSI_REQ_Q *scsiqp;
8500         struct scatterlist *slp;
8501         int sg_elem_cnt;
8502         ADV_SG_BLOCK *sg_block, *prev_sg_block;
8503         ADV_PADDR sg_block_paddr;
8504         int i;
8505
8506         scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
8507         slp = scsi_sglist(scp);
8508         sg_elem_cnt = use_sg;
8509         prev_sg_block = NULL;
8510         reqp->sgblkp = NULL;
8511
8512         for (;;) {
8513                 /*
8514                  * Allocate a 'adv_sgblk_t' structure from the board free
8515                  * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
8516                  * (15) scatter-gather elements.
8517                  */
8518                 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
8519                         ASC_DBG(1, "no free adv_sgblk_t\n");
8520                         ASC_STATS(scp->device->host, adv_build_nosg);
8521
8522                         /*
8523                          * Allocation failed. Free 'adv_sgblk_t' structures
8524                          * already allocated for the request.
8525                          */
8526                         while ((sgblkp = reqp->sgblkp) != NULL) {
8527                                 /* Remove 'sgblkp' from the request list. */
8528                                 reqp->sgblkp = sgblkp->next_sgblkp;
8529
8530                                 /* Add 'sgblkp' to the board free list. */
8531                                 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8532                                 boardp->adv_sgblkp = sgblkp;
8533                         }
8534                         return ASC_BUSY;
8535                 }
8536
8537                 /* Complete 'adv_sgblk_t' board allocation. */
8538                 boardp->adv_sgblkp = sgblkp->next_sgblkp;
8539                 sgblkp->next_sgblkp = NULL;
8540
8541                 /*
8542                  * Get 8 byte aligned virtual and physical addresses
8543                  * for the allocated ADV_SG_BLOCK structure.
8544                  */
8545                 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
8546                 sg_block_paddr = virt_to_bus(sg_block);
8547
8548                 /*
8549                  * Check if this is the first 'adv_sgblk_t' for the
8550                  * request.
8551                  */
8552                 if (reqp->sgblkp == NULL) {
8553                         /* Request's first scatter-gather block. */
8554                         reqp->sgblkp = sgblkp;
8555
8556                         /*
8557                          * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
8558                          * address pointers.
8559                          */
8560                         scsiqp->sg_list_ptr = sg_block;
8561                         scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
8562                 } else {
8563                         /* Request's second or later scatter-gather block. */
8564                         sgblkp->next_sgblkp = reqp->sgblkp;
8565                         reqp->sgblkp = sgblkp;
8566
8567                         /*
8568                          * Point the previous ADV_SG_BLOCK structure to
8569                          * the newly allocated ADV_SG_BLOCK structure.
8570                          */
8571                         prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
8572                 }
8573
8574                 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
8575                         sg_block->sg_list[i].sg_addr =
8576                                         cpu_to_le32(sg_dma_address(slp));
8577                         sg_block->sg_list[i].sg_count =
8578                                         cpu_to_le32(sg_dma_len(slp));
8579                         ASC_STATS_ADD(scp->device->host, xfer_sect,
8580                                       DIV_ROUND_UP(sg_dma_len(slp), 512));
8581
8582                         if (--sg_elem_cnt == 0) {       /* Last ADV_SG_BLOCK and scatter-gather entry. */
8583                                 sg_block->sg_cnt = i + 1;
8584                                 sg_block->sg_ptr = 0L;  /* Last ADV_SG_BLOCK in list. */
8585                                 return ADV_SUCCESS;
8586                         }
8587                         slp++;
8588                 }
8589                 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
8590                 prev_sg_block = sg_block;
8591         }
8592 }
8593
8594 /*
8595  * Build a request structure for the Adv Library (Wide Board).
8596  *
8597  * If an adv_req_t can not be allocated to issue the request,
8598  * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
8599  *
8600  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
8601  * microcode for DMA addresses or math operations are byte swapped
8602  * to little-endian order.
8603  */
8604 static int
8605 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
8606               ADV_SCSI_REQ_Q **adv_scsiqpp)
8607 {
8608         adv_req_t *reqp;
8609         ADV_SCSI_REQ_Q *scsiqp;
8610         int i;
8611         int ret;
8612         int use_sg;
8613
8614         /*
8615          * Allocate an adv_req_t structure from the board to execute
8616          * the command.
8617          */
8618         if (boardp->adv_reqp == NULL) {
8619                 ASC_DBG(1, "no free adv_req_t\n");
8620                 ASC_STATS(scp->device->host, adv_build_noreq);
8621                 return ASC_BUSY;
8622         } else {
8623                 reqp = boardp->adv_reqp;
8624                 boardp->adv_reqp = reqp->next_reqp;
8625                 reqp->next_reqp = NULL;
8626         }
8627
8628         /*
8629          * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
8630          */
8631         scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
8632
8633         /*
8634          * Initialize the structure.
8635          */
8636         scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
8637
8638         /*
8639          * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
8640          */
8641         scsiqp->srb_ptr = ADV_VADDR_TO_U32(reqp);
8642
8643         /*
8644          * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
8645          */
8646         reqp->cmndp = scp;
8647
8648         /*
8649          * Build the ADV_SCSI_REQ_Q request.
8650          */
8651
8652         /* Set CDB length and copy it to the request structure.  */
8653         scsiqp->cdb_len = scp->cmd_len;
8654         /* Copy first 12 CDB bytes to cdb[]. */
8655         for (i = 0; i < scp->cmd_len && i < 12; i++) {
8656                 scsiqp->cdb[i] = scp->cmnd[i];
8657         }
8658         /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8659         for (; i < scp->cmd_len; i++) {
8660                 scsiqp->cdb16[i - 12] = scp->cmnd[i];
8661         }
8662
8663         scsiqp->target_id = scp->device->id;
8664         scsiqp->target_lun = scp->device->lun;
8665
8666         scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
8667         scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
8668
8669         /* Build ADV_SCSI_REQ_Q */
8670
8671         use_sg = scsi_dma_map(scp);
8672         if (use_sg == 0) {
8673                 /* Zero-length transfer */
8674                 reqp->sgblkp = NULL;
8675                 scsiqp->data_cnt = 0;
8676                 scsiqp->vdata_addr = NULL;
8677
8678                 scsiqp->data_addr = 0;
8679                 scsiqp->sg_list_ptr = NULL;
8680                 scsiqp->sg_real_addr = 0;
8681         } else {
8682                 if (use_sg > ADV_MAX_SG_LIST) {
8683                         scmd_printk(KERN_ERR, scp, "use_sg %d > "
8684                                    "ADV_MAX_SG_LIST %d\n", use_sg,
8685                                    scp->device->host->sg_tablesize);
8686                         scsi_dma_unmap(scp);
8687                         scp->result = HOST_BYTE(DID_ERROR);
8688
8689                         /*
8690                          * Free the 'adv_req_t' structure by adding it back
8691                          * to the board free list.
8692                          */
8693                         reqp->next_reqp = boardp->adv_reqp;
8694                         boardp->adv_reqp = reqp;
8695
8696                         return ASC_ERROR;
8697                 }
8698
8699                 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8700
8701                 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
8702                 if (ret != ADV_SUCCESS) {
8703                         /*
8704                          * Free the adv_req_t structure by adding it back to
8705                          * the board free list.
8706                          */
8707                         reqp->next_reqp = boardp->adv_reqp;
8708                         boardp->adv_reqp = reqp;
8709
8710                         return ret;
8711                 }
8712
8713                 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8714         }
8715
8716         ASC_STATS(scp->device->host, xfer_cnt);
8717
8718         ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8719         ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8720
8721         *adv_scsiqpp = scsiqp;
8722
8723         return ASC_NOERROR;
8724 }
8725
8726 static int AscSgListToQueue(int sg_list)
8727 {
8728         int n_sg_list_qs;
8729
8730         n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8731         if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8732                 n_sg_list_qs++;
8733         return n_sg_list_qs + 1;
8734 }
8735
8736 static uint
8737 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8738 {
8739         uint cur_used_qs;
8740         uint cur_free_qs;
8741         ASC_SCSI_BIT_ID_TYPE target_id;
8742         uchar tid_no;
8743
8744         target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8745         tid_no = ASC_TIX_TO_TID(target_ix);
8746         if ((asc_dvc->unit_not_ready & target_id) ||
8747             (asc_dvc->queue_full_or_busy & target_id)) {
8748                 return 0;
8749         }
8750         if (n_qs == 1) {
8751                 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8752                     (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8753         } else {
8754                 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8755                     (uint) ASC_MIN_FREE_Q;
8756         }
8757         if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8758                 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8759                 if (asc_dvc->cur_dvc_qng[tid_no] >=
8760                     asc_dvc->max_dvc_qng[tid_no]) {
8761                         return 0;
8762                 }
8763                 return cur_free_qs;
8764         }
8765         if (n_qs > 1) {
8766                 if ((n_qs > asc_dvc->last_q_shortage)
8767                     && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8768                         asc_dvc->last_q_shortage = n_qs;
8769                 }
8770         }
8771         return 0;
8772 }
8773
8774 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8775 {
8776         ushort q_addr;
8777         uchar next_qp;
8778         uchar q_status;
8779
8780         q_addr = ASC_QNO_TO_QADDR(free_q_head);
8781         q_status = (uchar)AscReadLramByte(iop_base,
8782                                           (ushort)(q_addr +
8783                                                    ASC_SCSIQ_B_STATUS));
8784         next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8785         if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8786                 return next_qp;
8787         return ASC_QLINK_END;
8788 }
8789
8790 static uchar
8791 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8792 {
8793         uchar i;
8794
8795         for (i = 0; i < n_free_q; i++) {
8796                 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8797                 if (free_q_head == ASC_QLINK_END)
8798                         break;
8799         }
8800         return free_q_head;
8801 }
8802
8803 /*
8804  * void
8805  * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8806  *
8807  * Calling/Exit State:
8808  *    none
8809  *
8810  * Description:
8811  *     Output an ASC_SCSI_Q structure to the chip
8812  */
8813 static void
8814 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8815 {
8816         int i;
8817
8818         ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8819         AscSetChipLramAddr(iop_base, s_addr);
8820         for (i = 0; i < 2 * words; i += 2) {
8821                 if (i == 4 || i == 20) {
8822                         continue;
8823                 }
8824                 outpw(iop_base + IOP_RAM_DATA,
8825                       ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8826         }
8827 }
8828
8829 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8830 {
8831         ushort q_addr;
8832         uchar tid_no;
8833         uchar sdtr_data;
8834         uchar syn_period_ix;
8835         uchar syn_offset;
8836         PortAddr iop_base;
8837
8838         iop_base = asc_dvc->iop_base;
8839         if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8840             ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8841                 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8842                 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8843                 syn_period_ix =
8844                     (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8845                 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8846                 AscMsgOutSDTR(asc_dvc,
8847                               asc_dvc->sdtr_period_tbl[syn_period_ix],
8848                               syn_offset);
8849                 scsiq->q1.cntl |= QC_MSG_OUT;
8850         }
8851         q_addr = ASC_QNO_TO_QADDR(q_no);
8852         if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8853                 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
8854         }
8855         scsiq->q1.status = QS_FREE;
8856         AscMemWordCopyPtrToLram(iop_base,
8857                                 q_addr + ASC_SCSIQ_CDB_BEG,
8858                                 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8859
8860         DvcPutScsiQ(iop_base,
8861                     q_addr + ASC_SCSIQ_CPY_BEG,
8862                     (uchar *)&scsiq->q1.cntl,
8863                     ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8864         AscWriteLramWord(iop_base,
8865                          (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8866                          (ushort)(((ushort)scsiq->q1.
8867                                    q_no << 8) | (ushort)QS_READY));
8868         return 1;
8869 }
8870
8871 static int
8872 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8873 {
8874         int sta;
8875         int i;
8876         ASC_SG_HEAD *sg_head;
8877         ASC_SG_LIST_Q scsi_sg_q;
8878         ASC_DCNT saved_data_addr;
8879         ASC_DCNT saved_data_cnt;
8880         PortAddr iop_base;
8881         ushort sg_list_dwords;
8882         ushort sg_index;
8883         ushort sg_entry_cnt;
8884         ushort q_addr;
8885         uchar next_qp;
8886
8887         iop_base = asc_dvc->iop_base;
8888         sg_head = scsiq->sg_head;
8889         saved_data_addr = scsiq->q1.data_addr;
8890         saved_data_cnt = scsiq->q1.data_cnt;
8891         scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
8892         scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
8893 #if CC_VERY_LONG_SG_LIST
8894         /*
8895          * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8896          * then not all SG elements will fit in the allocated queues.
8897          * The rest of the SG elements will be copied when the RISC
8898          * completes the SG elements that fit and halts.
8899          */
8900         if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8901                 /*
8902                  * Set sg_entry_cnt to be the number of SG elements that
8903                  * will fit in the allocated SG queues. It is minus 1, because
8904                  * the first SG element is handled above. ASC_MAX_SG_LIST is
8905                  * already inflated by 1 to account for this. For example it
8906                  * may be 50 which is 1 + 7 queues * 7 SG elements.
8907                  */
8908                 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8909
8910                 /*
8911                  * Keep track of remaining number of SG elements that will
8912                  * need to be handled from a_isr.c.
8913                  */
8914                 scsiq->remain_sg_entry_cnt =
8915                     sg_head->entry_cnt - ASC_MAX_SG_LIST;
8916         } else {
8917 #endif /* CC_VERY_LONG_SG_LIST */
8918                 /*
8919                  * Set sg_entry_cnt to be the number of SG elements that
8920                  * will fit in the allocated SG queues. It is minus 1, because
8921                  * the first SG element is handled above.
8922                  */
8923                 sg_entry_cnt = sg_head->entry_cnt - 1;
8924 #if CC_VERY_LONG_SG_LIST
8925         }
8926 #endif /* CC_VERY_LONG_SG_LIST */
8927         if (sg_entry_cnt != 0) {
8928                 scsiq->q1.cntl |= QC_SG_HEAD;
8929                 q_addr = ASC_QNO_TO_QADDR(q_no);
8930                 sg_index = 1;
8931                 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8932                 scsi_sg_q.sg_head_qp = q_no;
8933                 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8934                 for (i = 0; i < sg_head->queue_cnt; i++) {
8935                         scsi_sg_q.seq_no = i + 1;
8936                         if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8937                                 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8938                                 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8939                                 if (i == 0) {
8940                                         scsi_sg_q.sg_list_cnt =
8941                                             ASC_SG_LIST_PER_Q;
8942                                         scsi_sg_q.sg_cur_list_cnt =
8943                                             ASC_SG_LIST_PER_Q;
8944                                 } else {
8945                                         scsi_sg_q.sg_list_cnt =
8946                                             ASC_SG_LIST_PER_Q - 1;
8947                                         scsi_sg_q.sg_cur_list_cnt =
8948                                             ASC_SG_LIST_PER_Q - 1;
8949                                 }
8950                         } else {
8951 #if CC_VERY_LONG_SG_LIST
8952                                 /*
8953                                  * This is the last SG queue in the list of
8954                                  * allocated SG queues. If there are more
8955                                  * SG elements than will fit in the allocated
8956                                  * queues, then set the QCSG_SG_XFER_MORE flag.
8957                                  */
8958                                 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8959                                         scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8960                                 } else {
8961 #endif /* CC_VERY_LONG_SG_LIST */
8962                                         scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8963 #if CC_VERY_LONG_SG_LIST
8964                                 }
8965 #endif /* CC_VERY_LONG_SG_LIST */
8966                                 sg_list_dwords = sg_entry_cnt << 1;
8967                                 if (i == 0) {
8968                                         scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8969                                         scsi_sg_q.sg_cur_list_cnt =
8970                                             sg_entry_cnt;
8971                                 } else {
8972                                         scsi_sg_q.sg_list_cnt =
8973                                             sg_entry_cnt - 1;
8974                                         scsi_sg_q.sg_cur_list_cnt =
8975                                             sg_entry_cnt - 1;
8976                                 }
8977                                 sg_entry_cnt = 0;
8978                         }
8979                         next_qp = AscReadLramByte(iop_base,
8980                                                   (ushort)(q_addr +
8981                                                            ASC_SCSIQ_B_FWD));
8982                         scsi_sg_q.q_no = next_qp;
8983                         q_addr = ASC_QNO_TO_QADDR(next_qp);
8984                         AscMemWordCopyPtrToLram(iop_base,
8985                                                 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8986                                                 (uchar *)&scsi_sg_q,
8987                                                 sizeof(ASC_SG_LIST_Q) >> 1);
8988                         AscMemDWordCopyPtrToLram(iop_base,
8989                                                  q_addr + ASC_SGQ_LIST_BEG,
8990                                                  (uchar *)&sg_head->
8991                                                  sg_list[sg_index],
8992                                                  sg_list_dwords);
8993                         sg_index += ASC_SG_LIST_PER_Q;
8994                         scsiq->next_sg_index = sg_index;
8995                 }
8996         } else {
8997                 scsiq->q1.cntl &= ~QC_SG_HEAD;
8998         }
8999         sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
9000         scsiq->q1.data_addr = saved_data_addr;
9001         scsiq->q1.data_cnt = saved_data_cnt;
9002         return (sta);
9003 }
9004
9005 static int
9006 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
9007 {
9008         PortAddr iop_base;
9009         uchar free_q_head;
9010         uchar next_qp;
9011         uchar tid_no;
9012         uchar target_ix;
9013         int sta;
9014
9015         iop_base = asc_dvc->iop_base;
9016         target_ix = scsiq->q2.target_ix;
9017         tid_no = ASC_TIX_TO_TID(target_ix);
9018         sta = 0;
9019         free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
9020         if (n_q_required > 1) {
9021                 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
9022                                                     (uchar)n_q_required);
9023                 if (next_qp != ASC_QLINK_END) {
9024                         asc_dvc->last_q_shortage = 0;
9025                         scsiq->sg_head->queue_cnt = n_q_required - 1;
9026                         scsiq->q1.q_no = free_q_head;
9027                         sta = AscPutReadySgListQueue(asc_dvc, scsiq,
9028                                                      free_q_head);
9029                 }
9030         } else if (n_q_required == 1) {
9031                 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
9032                 if (next_qp != ASC_QLINK_END) {
9033                         scsiq->q1.q_no = free_q_head;
9034                         sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
9035                 }
9036         }
9037         if (sta == 1) {
9038                 AscPutVarFreeQHead(iop_base, next_qp);
9039                 asc_dvc->cur_total_qng += n_q_required;
9040                 asc_dvc->cur_dvc_qng[tid_no]++;
9041         }
9042         return sta;
9043 }
9044
9045 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST  16
9046 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
9047         INQUIRY,
9048         REQUEST_SENSE,
9049         READ_CAPACITY,
9050         READ_TOC,
9051         MODE_SELECT,
9052         MODE_SENSE,
9053         MODE_SELECT_10,
9054         MODE_SENSE_10,
9055         0xFF,
9056         0xFF,
9057         0xFF,
9058         0xFF,
9059         0xFF,
9060         0xFF,
9061         0xFF,
9062         0xFF
9063 };
9064
9065 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
9066 {
9067         PortAddr iop_base;
9068         int sta;
9069         int n_q_required;
9070         int disable_syn_offset_one_fix;
9071         int i;
9072         ASC_PADDR addr;
9073         ushort sg_entry_cnt = 0;
9074         ushort sg_entry_cnt_minus_one = 0;
9075         uchar target_ix;
9076         uchar tid_no;
9077         uchar sdtr_data;
9078         uchar extra_bytes;
9079         uchar scsi_cmd;
9080         uchar disable_cmd;
9081         ASC_SG_HEAD *sg_head;
9082         ASC_DCNT data_cnt;
9083
9084         iop_base = asc_dvc->iop_base;
9085         sg_head = scsiq->sg_head;
9086         if (asc_dvc->err_code != 0)
9087                 return (ERR);
9088         scsiq->q1.q_no = 0;
9089         if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
9090                 scsiq->q1.extra_bytes = 0;
9091         }
9092         sta = 0;
9093         target_ix = scsiq->q2.target_ix;
9094         tid_no = ASC_TIX_TO_TID(target_ix);
9095         n_q_required = 1;
9096         if (scsiq->cdbptr[0] == REQUEST_SENSE) {
9097                 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
9098                         asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
9099                         sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
9100                         AscMsgOutSDTR(asc_dvc,
9101                                       asc_dvc->
9102                                       sdtr_period_tbl[(sdtr_data >> 4) &
9103                                                       (uchar)(asc_dvc->
9104                                                               max_sdtr_index -
9105                                                               1)],
9106                                       (uchar)(sdtr_data & (uchar)
9107                                               ASC_SYN_MAX_OFFSET));
9108                         scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
9109                 }
9110         }
9111         if (asc_dvc->in_critical_cnt != 0) {
9112                 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
9113                 return (ERR);
9114         }
9115         asc_dvc->in_critical_cnt++;
9116         if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
9117                 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
9118                         asc_dvc->in_critical_cnt--;
9119                         return (ERR);
9120                 }
9121 #if !CC_VERY_LONG_SG_LIST
9122                 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
9123                         asc_dvc->in_critical_cnt--;
9124                         return (ERR);
9125                 }
9126 #endif /* !CC_VERY_LONG_SG_LIST */
9127                 if (sg_entry_cnt == 1) {
9128                         scsiq->q1.data_addr =
9129                             (ADV_PADDR)sg_head->sg_list[0].addr;
9130                         scsiq->q1.data_cnt =
9131                             (ADV_DCNT)sg_head->sg_list[0].bytes;
9132                         scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
9133                 }
9134                 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
9135         }
9136         scsi_cmd = scsiq->cdbptr[0];
9137         disable_syn_offset_one_fix = FALSE;
9138         if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
9139             !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
9140                 if (scsiq->q1.cntl & QC_SG_HEAD) {
9141                         data_cnt = 0;
9142                         for (i = 0; i < sg_entry_cnt; i++) {
9143                                 data_cnt +=
9144                                     (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
9145                                                           bytes);
9146                         }
9147                 } else {
9148                         data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
9149                 }
9150                 if (data_cnt != 0UL) {
9151                         if (data_cnt < 512UL) {
9152                                 disable_syn_offset_one_fix = TRUE;
9153                         } else {
9154                                 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
9155                                      i++) {
9156                                         disable_cmd =
9157                                             _syn_offset_one_disable_cmd[i];
9158                                         if (disable_cmd == 0xFF) {
9159                                                 break;
9160                                         }
9161                                         if (scsi_cmd == disable_cmd) {
9162                                                 disable_syn_offset_one_fix =
9163                                                     TRUE;
9164                                                 break;
9165                                         }
9166                                 }
9167                         }
9168                 }
9169         }
9170         if (disable_syn_offset_one_fix) {
9171                 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
9172                 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
9173                                        ASC_TAG_FLAG_DISABLE_DISCONNECT);
9174         } else {
9175                 scsiq->q2.tag_code &= 0x27;
9176         }
9177         if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
9178                 if (asc_dvc->bug_fix_cntl) {
9179                         if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
9180                                 if ((scsi_cmd == READ_6) ||
9181                                     (scsi_cmd == READ_10)) {
9182                                         addr =
9183                                             (ADV_PADDR)le32_to_cpu(sg_head->
9184                                                                    sg_list
9185                                                                    [sg_entry_cnt_minus_one].
9186                                                                    addr) +
9187                                             (ADV_DCNT)le32_to_cpu(sg_head->
9188                                                                   sg_list
9189                                                                   [sg_entry_cnt_minus_one].
9190                                                                   bytes);
9191                                         extra_bytes =
9192                                             (uchar)((ushort)addr & 0x0003);
9193                                         if ((extra_bytes != 0)
9194                                             &&
9195                                             ((scsiq->q2.
9196                                               tag_code &
9197                                               ASC_TAG_FLAG_EXTRA_BYTES)
9198                                              == 0)) {
9199                                                 scsiq->q2.tag_code |=
9200                                                     ASC_TAG_FLAG_EXTRA_BYTES;
9201                                                 scsiq->q1.extra_bytes =
9202                                                     extra_bytes;
9203                                                 data_cnt =
9204                                                     le32_to_cpu(sg_head->
9205                                                                 sg_list
9206                                                                 [sg_entry_cnt_minus_one].
9207                                                                 bytes);
9208                                                 data_cnt -=
9209                                                     (ASC_DCNT) extra_bytes;
9210                                                 sg_head->
9211                                                     sg_list
9212                                                     [sg_entry_cnt_minus_one].
9213                                                     bytes =
9214                                                     cpu_to_le32(data_cnt);
9215                                         }
9216                                 }
9217                         }
9218                 }
9219                 sg_head->entry_to_copy = sg_head->entry_cnt;
9220 #if CC_VERY_LONG_SG_LIST
9221                 /*
9222                  * Set the sg_entry_cnt to the maximum possible. The rest of
9223                  * the SG elements will be copied when the RISC completes the
9224                  * SG elements that fit and halts.
9225                  */
9226                 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
9227                         sg_entry_cnt = ASC_MAX_SG_LIST;
9228                 }
9229 #endif /* CC_VERY_LONG_SG_LIST */
9230                 n_q_required = AscSgListToQueue(sg_entry_cnt);
9231                 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
9232                      (uint) n_q_required)
9233                     || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
9234                         if ((sta =
9235                              AscSendScsiQueue(asc_dvc, scsiq,
9236                                               n_q_required)) == 1) {
9237                                 asc_dvc->in_critical_cnt--;
9238                                 return (sta);
9239                         }
9240                 }
9241         } else {
9242                 if (asc_dvc->bug_fix_cntl) {
9243                         if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
9244                                 if ((scsi_cmd == READ_6) ||
9245                                     (scsi_cmd == READ_10)) {
9246                                         addr =
9247                                             le32_to_cpu(scsiq->q1.data_addr) +
9248                                             le32_to_cpu(scsiq->q1.data_cnt);
9249                                         extra_bytes =
9250                                             (uchar)((ushort)addr & 0x0003);
9251                                         if ((extra_bytes != 0)
9252                                             &&
9253                                             ((scsiq->q2.
9254                                               tag_code &
9255                                               ASC_TAG_FLAG_EXTRA_BYTES)
9256                                              == 0)) {
9257                                                 data_cnt =
9258                                                     le32_to_cpu(scsiq->q1.
9259                                                                 data_cnt);
9260                                                 if (((ushort)data_cnt & 0x01FF)
9261                                                     == 0) {
9262                                                         scsiq->q2.tag_code |=
9263                                                             ASC_TAG_FLAG_EXTRA_BYTES;
9264                                                         data_cnt -= (ASC_DCNT)
9265                                                             extra_bytes;
9266                                                         scsiq->q1.data_cnt =
9267                                                             cpu_to_le32
9268                                                             (data_cnt);
9269                                                         scsiq->q1.extra_bytes =
9270                                                             extra_bytes;
9271                                                 }
9272                                         }
9273                                 }
9274                         }
9275                 }
9276                 n_q_required = 1;
9277                 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
9278                     ((scsiq->q1.cntl & QC_URGENT) != 0)) {
9279                         if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
9280                                                     n_q_required)) == 1) {
9281                                 asc_dvc->in_critical_cnt--;
9282                                 return (sta);
9283                         }
9284                 }
9285         }
9286         asc_dvc->in_critical_cnt--;
9287         return (sta);
9288 }
9289
9290 /*
9291  * AdvExeScsiQueue() - Send a request to the RISC microcode program.
9292  *
9293  *   Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
9294  *   add the carrier to the ICQ (Initiator Command Queue), and tickle the
9295  *   RISC to notify it a new command is ready to be executed.
9296  *
9297  * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
9298  * set to SCSI_MAX_RETRY.
9299  *
9300  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
9301  * for DMA addresses or math operations are byte swapped to little-endian
9302  * order.
9303  *
9304  * Return:
9305  *      ADV_SUCCESS(1) - The request was successfully queued.
9306  *      ADV_BUSY(0) -    Resource unavailable; Retry again after pending
9307  *                       request completes.
9308  *      ADV_ERROR(-1) -  Invalid ADV_SCSI_REQ_Q request structure
9309  *                       host IC error.
9310  */
9311 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
9312 {
9313         AdvPortAddr iop_base;
9314         ADV_PADDR req_paddr;
9315         ADV_CARR_T *new_carrp;
9316
9317         /*
9318          * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
9319          */
9320         if (scsiq->target_id > ADV_MAX_TID) {
9321                 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
9322                 scsiq->done_status = QD_WITH_ERROR;
9323                 return ADV_ERROR;
9324         }
9325
9326         iop_base = asc_dvc->iop_base;
9327
9328         /*
9329          * Allocate a carrier ensuring at least one carrier always
9330          * remains on the freelist and initialize fields.
9331          */
9332         if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
9333                 return ADV_BUSY;
9334         }
9335         asc_dvc->carr_freelist = (ADV_CARR_T *)
9336             ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
9337         asc_dvc->carr_pending_cnt++;
9338
9339         /*
9340          * Set the carrier to be a stopper by setting 'next_vpa'
9341          * to the stopper value. The current stopper will be changed
9342          * below to point to the new stopper.
9343          */
9344         new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
9345
9346         /*
9347          * Clear the ADV_SCSI_REQ_Q done flag.
9348          */
9349         scsiq->a_flag &= ~ADV_SCSIQ_DONE;
9350
9351         req_paddr = virt_to_bus(scsiq);
9352         BUG_ON(req_paddr & 31);
9353         /* Wait for assertion before making little-endian */
9354         req_paddr = cpu_to_le32(req_paddr);
9355
9356         /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
9357         scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
9358         scsiq->scsiq_rptr = req_paddr;
9359
9360         scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
9361         /*
9362          * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
9363          * order during initialization.
9364          */
9365         scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
9366
9367         /*
9368          * Use the current stopper to send the ADV_SCSI_REQ_Q command to
9369          * the microcode. The newly allocated stopper will become the new
9370          * stopper.
9371          */
9372         asc_dvc->icq_sp->areq_vpa = req_paddr;
9373
9374         /*
9375          * Set the 'next_vpa' pointer for the old stopper to be the
9376          * physical address of the new stopper. The RISC can only
9377          * follow physical addresses.
9378          */
9379         asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
9380
9381         /*
9382          * Set the host adapter stopper pointer to point to the new carrier.
9383          */
9384         asc_dvc->icq_sp = new_carrp;
9385
9386         if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
9387             asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
9388                 /*
9389                  * Tickle the RISC to tell it to read its Command Queue Head pointer.
9390                  */
9391                 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
9392                 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
9393                         /*
9394                          * Clear the tickle value. In the ASC-3550 the RISC flag
9395                          * command 'clr_tickle_a' does not work unless the host
9396                          * value is cleared.
9397                          */
9398                         AdvWriteByteRegister(iop_base, IOPB_TICKLE,
9399                                              ADV_TICKLE_NOP);
9400                 }
9401         } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
9402                 /*
9403                  * Notify the RISC a carrier is ready by writing the physical
9404                  * address of the new carrier stopper to the COMMA register.
9405                  */
9406                 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
9407                                       le32_to_cpu(new_carrp->carr_pa));
9408         }
9409
9410         return ADV_SUCCESS;
9411 }
9412
9413 /*
9414  * Execute a single 'Scsi_Cmnd'.
9415  */
9416 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
9417 {
9418         int ret, err_code;
9419         struct asc_board *boardp = shost_priv(scp->device->host);
9420
9421         ASC_DBG(1, "scp 0x%p\n", scp);
9422
9423         if (ASC_NARROW_BOARD(boardp)) {
9424                 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9425                 struct asc_scsi_q asc_scsi_q;
9426
9427                 /* asc_build_req() can not return ASC_BUSY. */
9428                 ret = asc_build_req(boardp, scp, &asc_scsi_q);
9429                 if (ret == ASC_ERROR) {
9430                         ASC_STATS(scp->device->host, build_error);
9431                         return ASC_ERROR;
9432                 }
9433
9434                 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
9435                 kfree(asc_scsi_q.sg_head);
9436                 err_code = asc_dvc->err_code;
9437         } else {
9438                 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9439                 ADV_SCSI_REQ_Q *adv_scsiqp;
9440
9441                 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
9442                 case ASC_NOERROR:
9443                         ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
9444                         break;
9445                 case ASC_BUSY:
9446                         ASC_DBG(1, "adv_build_req ASC_BUSY\n");
9447                         /*
9448                          * The asc_stats fields 'adv_build_noreq' and
9449                          * 'adv_build_nosg' count wide board busy conditions.
9450                          * They are updated in adv_build_req and
9451                          * adv_get_sglist, respectively.
9452                          */
9453                         return ASC_BUSY;
9454                 case ASC_ERROR:
9455                 default:
9456                         ASC_DBG(1, "adv_build_req ASC_ERROR\n");
9457                         ASC_STATS(scp->device->host, build_error);
9458                         return ASC_ERROR;
9459                 }
9460
9461                 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
9462                 err_code = adv_dvc->err_code;
9463         }
9464
9465         switch (ret) {
9466         case ASC_NOERROR:
9467                 ASC_STATS(scp->device->host, exe_noerror);
9468                 /*
9469                  * Increment monotonically increasing per device
9470                  * successful request counter. Wrapping doesn't matter.
9471                  */
9472                 boardp->reqcnt[scp->device->id]++;
9473                 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
9474                 break;
9475         case ASC_BUSY:
9476                 ASC_STATS(scp->device->host, exe_busy);
9477                 break;
9478         case ASC_ERROR:
9479                 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
9480                         "err_code 0x%x\n", err_code);
9481                 ASC_STATS(scp->device->host, exe_error);
9482                 scp->result = HOST_BYTE(DID_ERROR);
9483                 break;
9484         default:
9485                 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
9486                         "err_code 0x%x\n", err_code);
9487                 ASC_STATS(scp->device->host, exe_unknown);
9488                 scp->result = HOST_BYTE(DID_ERROR);
9489                 break;
9490         }
9491
9492         ASC_DBG(1, "end\n");
9493         return ret;
9494 }
9495
9496 /*
9497  * advansys_queuecommand() - interrupt-driven I/O entrypoint.
9498  *
9499  * This function always returns 0. Command return status is saved
9500  * in the 'scp' result field.
9501  */
9502 static int
9503 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
9504 {
9505         struct Scsi_Host *shost = scp->device->host;
9506         int asc_res, result = 0;
9507
9508         ASC_STATS(shost, queuecommand);
9509         scp->scsi_done = done;
9510
9511         asc_res = asc_execute_scsi_cmnd(scp);
9512
9513         switch (asc_res) {
9514         case ASC_NOERROR:
9515                 break;
9516         case ASC_BUSY:
9517                 result = SCSI_MLQUEUE_HOST_BUSY;
9518                 break;
9519         case ASC_ERROR:
9520         default:
9521                 asc_scsi_done(scp);
9522                 break;
9523         }
9524
9525         return result;
9526 }
9527
9528 static DEF_SCSI_QCMD(advansys_queuecommand)
9529
9530 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
9531 {
9532         PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9533             (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9534         return inpw(eisa_cfg_iop);
9535 }
9536
9537 /*
9538  * Return the BIOS address of the adapter at the specified
9539  * I/O port and with the specified bus type.
9540  */
9541 static unsigned short __devinit
9542 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
9543 {
9544         unsigned short cfg_lsw;
9545         unsigned short bios_addr;
9546
9547         /*
9548          * The PCI BIOS is re-located by the motherboard BIOS. Because
9549          * of this the driver can not determine where a PCI BIOS is
9550          * loaded and executes.
9551          */
9552         if (bus_type & ASC_IS_PCI)
9553                 return 0;
9554
9555         if ((bus_type & ASC_IS_EISA) != 0) {
9556                 cfg_lsw = AscGetEisaChipCfg(iop_base);
9557                 cfg_lsw &= 0x000F;
9558                 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
9559                 return bios_addr;
9560         }
9561
9562         cfg_lsw = AscGetChipCfgLsw(iop_base);
9563
9564         /*
9565          *  ISA PnP uses the top bit as the 32K BIOS flag
9566          */
9567         if (bus_type == ASC_IS_ISAPNP)
9568                 cfg_lsw &= 0x7FFF;
9569         bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
9570         return bios_addr;
9571 }
9572
9573 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
9574 {
9575         ushort cfg_lsw;
9576
9577         if (AscGetChipScsiID(iop_base) == new_host_id) {
9578                 return (new_host_id);
9579         }
9580         cfg_lsw = AscGetChipCfgLsw(iop_base);
9581         cfg_lsw &= 0xF8FF;
9582         cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
9583         AscSetChipCfgLsw(iop_base, cfg_lsw);
9584         return (AscGetChipScsiID(iop_base));
9585 }
9586
9587 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
9588 {
9589         unsigned char sc;
9590
9591         AscSetBank(iop_base, 1);
9592         sc = inp(iop_base + IOP_REG_SC);
9593         AscSetBank(iop_base, 0);
9594         return sc;
9595 }
9596
9597 static unsigned char __devinit
9598 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
9599 {
9600         if (bus_type & ASC_IS_EISA) {
9601                 PortAddr eisa_iop;
9602                 unsigned char revision;
9603                 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9604                     (PortAddr) ASC_EISA_REV_IOP_MASK;
9605                 revision = inp(eisa_iop);
9606                 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
9607         }
9608         return AscGetChipVerNo(iop_base);
9609 }
9610
9611 #ifdef CONFIG_ISA
9612 static void __devinit AscEnableIsaDma(uchar dma_channel)
9613 {
9614         if (dma_channel < 4) {
9615                 outp(0x000B, (ushort)(0xC0 | dma_channel));
9616                 outp(0x000A, dma_channel);
9617         } else if (dma_channel < 8) {
9618                 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
9619                 outp(0x00D4, (ushort)(dma_channel - 4));
9620         }
9621 }
9622 #endif /* CONFIG_ISA */
9623
9624 static int AscStopQueueExe(PortAddr iop_base)
9625 {
9626         int count = 0;
9627
9628         if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
9629                 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9630                                  ASC_STOP_REQ_RISC_STOP);
9631                 do {
9632                         if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
9633                             ASC_STOP_ACK_RISC_STOP) {
9634                                 return (1);
9635                         }
9636                         mdelay(100);
9637                 } while (count++ < 20);
9638         }
9639         return (0);
9640 }
9641
9642 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
9643 {
9644         if (bus_type & ASC_IS_ISA)
9645                 return ASC_MAX_ISA_DMA_COUNT;
9646         else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
9647                 return ASC_MAX_VL_DMA_COUNT;
9648         return ASC_MAX_PCI_DMA_COUNT;
9649 }
9650
9651 #ifdef CONFIG_ISA
9652 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
9653 {
9654         ushort channel;
9655
9656         channel = AscGetChipCfgLsw(iop_base) & 0x0003;
9657         if (channel == 0x03)
9658                 return (0);
9659         else if (channel == 0x00)
9660                 return (7);
9661         return (channel + 4);
9662 }
9663
9664 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
9665 {
9666         ushort cfg_lsw;
9667         uchar value;
9668
9669         if ((dma_channel >= 5) && (dma_channel <= 7)) {
9670                 if (dma_channel == 7)
9671                         value = 0x00;
9672                 else
9673                         value = dma_channel - 4;
9674                 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9675                 cfg_lsw |= value;
9676                 AscSetChipCfgLsw(iop_base, cfg_lsw);
9677                 return (AscGetIsaDmaChannel(iop_base));
9678         }
9679         return 0;
9680 }
9681
9682 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
9683 {
9684         uchar speed_value;
9685
9686         AscSetBank(iop_base, 1);
9687         speed_value = AscReadChipDmaSpeed(iop_base);
9688         speed_value &= 0x07;
9689         AscSetBank(iop_base, 0);
9690         return speed_value;
9691 }
9692
9693 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9694 {
9695         speed_value &= 0x07;
9696         AscSetBank(iop_base, 1);
9697         AscWriteChipDmaSpeed(iop_base, speed_value);
9698         AscSetBank(iop_base, 0);
9699         return AscGetIsaDmaSpeed(iop_base);
9700 }
9701 #endif /* CONFIG_ISA */
9702
9703 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9704 {
9705         int i;
9706         PortAddr iop_base;
9707         ushort warn_code;
9708         uchar chip_version;
9709
9710         iop_base = asc_dvc->iop_base;
9711         warn_code = 0;
9712         asc_dvc->err_code = 0;
9713         if ((asc_dvc->bus_type &
9714              (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9715                 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9716         }
9717         AscSetChipControl(iop_base, CC_HALT);
9718         AscSetChipStatus(iop_base, 0);
9719         asc_dvc->bug_fix_cntl = 0;
9720         asc_dvc->pci_fix_asyn_xfer = 0;
9721         asc_dvc->pci_fix_asyn_xfer_always = 0;
9722         /* asc_dvc->init_state initialized in AscInitGetConfig(). */
9723         asc_dvc->sdtr_done = 0;
9724         asc_dvc->cur_total_qng = 0;
9725         asc_dvc->is_in_int = 0;
9726         asc_dvc->in_critical_cnt = 0;
9727         asc_dvc->last_q_shortage = 0;
9728         asc_dvc->use_tagged_qng = 0;
9729         asc_dvc->no_scam = 0;
9730         asc_dvc->unit_not_ready = 0;
9731         asc_dvc->queue_full_or_busy = 0;
9732         asc_dvc->redo_scam = 0;
9733         asc_dvc->res2 = 0;
9734         asc_dvc->min_sdtr_index = 0;
9735         asc_dvc->cfg->can_tagged_qng = 0;
9736         asc_dvc->cfg->cmd_qng_enabled = 0;
9737         asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9738         asc_dvc->init_sdtr = 0;
9739         asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9740         asc_dvc->scsi_reset_wait = 3;
9741         asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9742         asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9743         asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9744         asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9745         asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9746         chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9747         asc_dvc->cfg->chip_version = chip_version;
9748         asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9749         asc_dvc->max_sdtr_index = 7;
9750         if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9751             (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9752                 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9753                 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9754                 asc_dvc->max_sdtr_index = 15;
9755                 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9756                         AscSetExtraControl(iop_base,
9757                                            (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9758                 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9759                         AscSetExtraControl(iop_base,
9760                                            (SEC_ACTIVE_NEGATE |
9761                                             SEC_ENABLE_FILTER));
9762                 }
9763         }
9764         if (asc_dvc->bus_type == ASC_IS_PCI) {
9765                 AscSetExtraControl(iop_base,
9766                                    (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9767         }
9768
9769         asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9770 #ifdef CONFIG_ISA
9771         if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9772                 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9773                         AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9774                         asc_dvc->bus_type = ASC_IS_ISAPNP;
9775                 }
9776                 asc_dvc->cfg->isa_dma_channel =
9777                     (uchar)AscGetIsaDmaChannel(iop_base);
9778         }
9779 #endif /* CONFIG_ISA */
9780         for (i = 0; i <= ASC_MAX_TID; i++) {
9781                 asc_dvc->cur_dvc_qng[i] = 0;
9782                 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9783                 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9784                 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9785                 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9786         }
9787         return warn_code;
9788 }
9789
9790 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9791 {
9792         int retry;
9793
9794         for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9795                 unsigned char read_back;
9796                 AscSetChipEEPCmd(iop_base, cmd_reg);
9797                 mdelay(1);
9798                 read_back = AscGetChipEEPCmd(iop_base);
9799                 if (read_back == cmd_reg)
9800                         return 1;
9801         }
9802         return 0;
9803 }
9804
9805 static void __devinit AscWaitEEPRead(void)
9806 {
9807         mdelay(1);
9808 }
9809
9810 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
9811 {
9812         ushort read_wval;
9813         uchar cmd_reg;
9814
9815         AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9816         AscWaitEEPRead();
9817         cmd_reg = addr | ASC_EEP_CMD_READ;
9818         AscWriteEEPCmdReg(iop_base, cmd_reg);
9819         AscWaitEEPRead();
9820         read_wval = AscGetChipEEPData(iop_base);
9821         AscWaitEEPRead();
9822         return read_wval;
9823 }
9824
9825 static ushort __devinit
9826 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
9827 {
9828         ushort wval;
9829         ushort sum;
9830         ushort *wbuf;
9831         int cfg_beg;
9832         int cfg_end;
9833         int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9834         int s_addr;
9835
9836         wbuf = (ushort *)cfg_buf;
9837         sum = 0;
9838         /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9839         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9840                 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9841                 sum += *wbuf;
9842         }
9843         if (bus_type & ASC_IS_VL) {
9844                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9845                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9846         } else {
9847                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9848                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9849         }
9850         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9851                 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9852                 if (s_addr <= uchar_end_in_config) {
9853                         /*
9854                          * Swap all char fields - must unswap bytes already swapped
9855                          * by AscReadEEPWord().
9856                          */
9857                         *wbuf = le16_to_cpu(wval);
9858                 } else {
9859                         /* Don't swap word field at the end - cntl field. */
9860                         *wbuf = wval;
9861                 }
9862                 sum += wval;    /* Checksum treats all EEPROM data as words. */
9863         }
9864         /*
9865          * Read the checksum word which will be compared against 'sum'
9866          * by the caller. Word field already swapped.
9867          */
9868         *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9869         return sum;
9870 }
9871
9872 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9873 {
9874         PortAddr iop_base;
9875         ushort q_addr;
9876         ushort saved_word;
9877         int sta;
9878
9879         iop_base = asc_dvc->iop_base;
9880         sta = 0;
9881         q_addr = ASC_QNO_TO_QADDR(241);
9882         saved_word = AscReadLramWord(iop_base, q_addr);
9883         AscSetChipLramAddr(iop_base, q_addr);
9884         AscSetChipLramData(iop_base, 0x55AA);
9885         mdelay(10);
9886         AscSetChipLramAddr(iop_base, q_addr);
9887         if (AscGetChipLramData(iop_base) == 0x55AA) {
9888                 sta = 1;
9889                 AscWriteLramWord(iop_base, q_addr, saved_word);
9890         }
9891         return (sta);
9892 }
9893
9894 static void __devinit AscWaitEEPWrite(void)
9895 {
9896         mdelay(20);
9897 }
9898
9899 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9900 {
9901         ushort read_back;
9902         int retry;
9903
9904         retry = 0;
9905         while (TRUE) {
9906                 AscSetChipEEPData(iop_base, data_reg);
9907                 mdelay(1);
9908                 read_back = AscGetChipEEPData(iop_base);
9909                 if (read_back == data_reg) {
9910                         return (1);
9911                 }
9912                 if (retry++ > ASC_EEP_MAX_RETRY) {
9913                         return (0);
9914                 }
9915         }
9916 }
9917
9918 static ushort __devinit
9919 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9920 {
9921         ushort read_wval;
9922
9923         read_wval = AscReadEEPWord(iop_base, addr);
9924         if (read_wval != word_val) {
9925                 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9926                 AscWaitEEPRead();
9927                 AscWriteEEPDataReg(iop_base, word_val);
9928                 AscWaitEEPRead();
9929                 AscWriteEEPCmdReg(iop_base,
9930                                   (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9931                 AscWaitEEPWrite();
9932                 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9933                 AscWaitEEPRead();
9934                 return (AscReadEEPWord(iop_base, addr));
9935         }
9936         return (read_wval);
9937 }
9938
9939 static int __devinit
9940 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
9941 {
9942         int n_error;
9943         ushort *wbuf;
9944         ushort word;
9945         ushort sum;
9946         int s_addr;
9947         int cfg_beg;
9948         int cfg_end;
9949         int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9950
9951         wbuf = (ushort *)cfg_buf;
9952         n_error = 0;
9953         sum = 0;
9954         /* Write two config words; AscWriteEEPWord() will swap bytes. */
9955         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9956                 sum += *wbuf;
9957                 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9958                         n_error++;
9959                 }
9960         }
9961         if (bus_type & ASC_IS_VL) {
9962                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9963                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9964         } else {
9965                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9966                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9967         }
9968         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9969                 if (s_addr <= uchar_end_in_config) {
9970                         /*
9971                          * This is a char field. Swap char fields before they are
9972                          * swapped again by AscWriteEEPWord().
9973                          */
9974                         word = cpu_to_le16(*wbuf);
9975                         if (word !=
9976                             AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9977                                 n_error++;
9978                         }
9979                 } else {
9980                         /* Don't swap word field at the end - cntl field. */
9981                         if (*wbuf !=
9982                             AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9983                                 n_error++;
9984                         }
9985                 }
9986                 sum += *wbuf;   /* Checksum calculated from word values. */
9987         }
9988         /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9989         *wbuf = sum;
9990         if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9991                 n_error++;
9992         }
9993
9994         /* Read EEPROM back again. */
9995         wbuf = (ushort *)cfg_buf;
9996         /*
9997          * Read two config words; Byte-swapping done by AscReadEEPWord().
9998          */
9999         for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
10000                 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
10001                         n_error++;
10002                 }
10003         }
10004         if (bus_type & ASC_IS_VL) {
10005                 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
10006                 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
10007         } else {
10008                 cfg_beg = ASC_EEP_DVC_CFG_BEG;
10009                 cfg_end = ASC_EEP_MAX_DVC_ADDR;
10010         }
10011         for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
10012                 if (s_addr <= uchar_end_in_config) {
10013                         /*
10014                          * Swap all char fields. Must unswap bytes already swapped
10015                          * by AscReadEEPWord().
10016                          */
10017                         word =
10018                             le16_to_cpu(AscReadEEPWord
10019                                         (iop_base, (uchar)s_addr));
10020                 } else {
10021                         /* Don't swap word field at the end - cntl field. */
10022                         word = AscReadEEPWord(iop_base, (uchar)s_addr);
10023                 }
10024                 if (*wbuf != word) {
10025                         n_error++;
10026                 }
10027         }
10028         /* Read checksum; Byte swapping not needed. */
10029         if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
10030                 n_error++;
10031         }
10032         return n_error;
10033 }
10034
10035 static int __devinit
10036 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
10037 {
10038         int retry;
10039         int n_error;
10040
10041         retry = 0;
10042         while (TRUE) {
10043                 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
10044                                                    bus_type)) == 0) {
10045                         break;
10046                 }
10047                 if (++retry > ASC_EEP_MAX_RETRY) {
10048                         break;
10049                 }
10050         }
10051         return n_error;
10052 }
10053
10054 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
10055 {
10056         ASCEEP_CONFIG eep_config_buf;
10057         ASCEEP_CONFIG *eep_config;
10058         PortAddr iop_base;
10059         ushort chksum;
10060         ushort warn_code;
10061         ushort cfg_msw, cfg_lsw;
10062         int i;
10063         int write_eep = 0;
10064
10065         iop_base = asc_dvc->iop_base;
10066         warn_code = 0;
10067         AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
10068         AscStopQueueExe(iop_base);
10069         if ((AscStopChip(iop_base) == FALSE) ||
10070             (AscGetChipScsiCtrl(iop_base) != 0)) {
10071                 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
10072                 AscResetChipAndScsiBus(asc_dvc);
10073                 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
10074         }
10075         if (AscIsChipHalted(iop_base) == FALSE) {
10076                 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
10077                 return (warn_code);
10078         }
10079         AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
10080         if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
10081                 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
10082                 return (warn_code);
10083         }
10084         eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
10085         cfg_msw = AscGetChipCfgMsw(iop_base);
10086         cfg_lsw = AscGetChipCfgLsw(iop_base);
10087         if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
10088                 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
10089                 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
10090                 AscSetChipCfgMsw(iop_base, cfg_msw);
10091         }
10092         chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
10093         ASC_DBG(1, "chksum 0x%x\n", chksum);
10094         if (chksum == 0) {
10095                 chksum = 0xaa55;
10096         }
10097         if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
10098                 warn_code |= ASC_WARN_AUTO_CONFIG;
10099                 if (asc_dvc->cfg->chip_version == 3) {
10100                         if (eep_config->cfg_lsw != cfg_lsw) {
10101                                 warn_code |= ASC_WARN_EEPROM_RECOVER;
10102                                 eep_config->cfg_lsw =
10103                                     AscGetChipCfgLsw(iop_base);
10104                         }
10105                         if (eep_config->cfg_msw != cfg_msw) {
10106                                 warn_code |= ASC_WARN_EEPROM_RECOVER;
10107                                 eep_config->cfg_msw =
10108                                     AscGetChipCfgMsw(iop_base);
10109                         }
10110                 }
10111         }
10112         eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
10113         eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
10114         ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
10115         if (chksum != eep_config->chksum) {
10116                 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
10117                     ASC_CHIP_VER_PCI_ULTRA_3050) {
10118                         ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
10119                         eep_config->init_sdtr = 0xFF;
10120                         eep_config->disc_enable = 0xFF;
10121                         eep_config->start_motor = 0xFF;
10122                         eep_config->use_cmd_qng = 0;
10123                         eep_config->max_total_qng = 0xF0;
10124                         eep_config->max_tag_qng = 0x20;
10125                         eep_config->cntl = 0xBFFF;
10126                         ASC_EEP_SET_CHIP_ID(eep_config, 7);
10127                         eep_config->no_scam = 0;
10128                         eep_config->adapter_info[0] = 0;
10129                         eep_config->adapter_info[1] = 0;
10130                         eep_config->adapter_info[2] = 0;
10131                         eep_config->adapter_info[3] = 0;
10132                         eep_config->adapter_info[4] = 0;
10133                         /* Indicate EEPROM-less board. */
10134                         eep_config->adapter_info[5] = 0xBB;
10135                 } else {
10136                         ASC_PRINT
10137                             ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
10138                         write_eep = 1;
10139                         warn_code |= ASC_WARN_EEPROM_CHKSUM;
10140                 }
10141         }
10142         asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
10143         asc_dvc->cfg->disc_enable = eep_config->disc_enable;
10144         asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
10145         asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
10146         asc_dvc->start_motor = eep_config->start_motor;
10147         asc_dvc->dvc_cntl = eep_config->cntl;
10148         asc_dvc->no_scam = eep_config->no_scam;
10149         asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
10150         asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
10151         asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
10152         asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
10153         asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
10154         asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
10155         if (!AscTestExternalLram(asc_dvc)) {
10156                 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
10157                      ASC_IS_PCI_ULTRA)) {
10158                         eep_config->max_total_qng =
10159                             ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
10160                         eep_config->max_tag_qng =
10161                             ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
10162                 } else {
10163                         eep_config->cfg_msw |= 0x0800;
10164                         cfg_msw |= 0x0800;
10165                         AscSetChipCfgMsw(iop_base, cfg_msw);
10166                         eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
10167                         eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
10168                 }
10169         } else {
10170         }
10171         if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
10172                 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
10173         }
10174         if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
10175                 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
10176         }
10177         if (eep_config->max_tag_qng > eep_config->max_total_qng) {
10178                 eep_config->max_tag_qng = eep_config->max_total_qng;
10179         }
10180         if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
10181                 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
10182         }
10183         asc_dvc->max_total_qng = eep_config->max_total_qng;
10184         if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
10185             eep_config->use_cmd_qng) {
10186                 eep_config->disc_enable = eep_config->use_cmd_qng;
10187                 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
10188         }
10189         ASC_EEP_SET_CHIP_ID(eep_config,
10190                             ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
10191         asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
10192         if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
10193             !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
10194                 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
10195         }
10196
10197         for (i = 0; i <= ASC_MAX_TID; i++) {
10198                 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
10199                 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
10200                 asc_dvc->cfg->sdtr_period_offset[i] =
10201                     (uchar)(ASC_DEF_SDTR_OFFSET |
10202                             (asc_dvc->min_sdtr_index << 4));
10203         }
10204         eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
10205         if (write_eep) {
10206                 if ((i = AscSetEEPConfig(iop_base, eep_config,
10207                                      asc_dvc->bus_type)) != 0) {
10208                         ASC_PRINT1
10209                             ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
10210                              i);
10211                 } else {
10212                         ASC_PRINT
10213                             ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
10214                 }
10215         }
10216         return (warn_code);
10217 }
10218
10219 static int __devinit AscInitGetConfig(struct Scsi_Host *shost)
10220 {
10221         struct asc_board *board = shost_priv(shost);
10222         ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
10223         unsigned short warn_code = 0;
10224
10225         asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
10226         if (asc_dvc->err_code != 0)
10227                 return asc_dvc->err_code;
10228
10229         if (AscFindSignature(asc_dvc->iop_base)) {
10230                 warn_code |= AscInitAscDvcVar(asc_dvc);
10231                 warn_code |= AscInitFromEEP(asc_dvc);
10232                 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
10233                 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
10234                         asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
10235         } else {
10236                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10237         }
10238
10239         switch (warn_code) {
10240         case 0: /* No error */
10241                 break;
10242         case ASC_WARN_IO_PORT_ROTATE:
10243                 shost_printk(KERN_WARNING, shost, "I/O port address "
10244                                 "modified\n");
10245                 break;
10246         case ASC_WARN_AUTO_CONFIG:
10247                 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
10248                                 "enabled\n");
10249                 break;
10250         case ASC_WARN_EEPROM_CHKSUM:
10251                 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
10252                 break;
10253         case ASC_WARN_IRQ_MODIFIED:
10254                 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
10255                 break;
10256         case ASC_WARN_CMD_QNG_CONFLICT:
10257                 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
10258                                 "disconnects\n");
10259                 break;
10260         default:
10261                 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
10262                                 warn_code);
10263                 break;
10264         }
10265
10266         if (asc_dvc->err_code != 0)
10267                 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
10268                         "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
10269
10270         return asc_dvc->err_code;
10271 }
10272
10273 static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
10274 {
10275         struct asc_board *board = shost_priv(shost);
10276         ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
10277         PortAddr iop_base = asc_dvc->iop_base;
10278         unsigned short cfg_msw;
10279         unsigned short warn_code = 0;
10280
10281         asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
10282         if (asc_dvc->err_code != 0)
10283                 return asc_dvc->err_code;
10284         if (!AscFindSignature(asc_dvc->iop_base)) {
10285                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10286                 return asc_dvc->err_code;
10287         }
10288
10289         cfg_msw = AscGetChipCfgMsw(iop_base);
10290         if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
10291                 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
10292                 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
10293                 AscSetChipCfgMsw(iop_base, cfg_msw);
10294         }
10295         if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
10296             asc_dvc->cfg->cmd_qng_enabled) {
10297                 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
10298                 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
10299         }
10300         if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
10301                 warn_code |= ASC_WARN_AUTO_CONFIG;
10302         }
10303 #ifdef CONFIG_PCI
10304         if (asc_dvc->bus_type & ASC_IS_PCI) {
10305                 cfg_msw &= 0xFFC0;
10306                 AscSetChipCfgMsw(iop_base, cfg_msw);
10307                 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
10308                 } else {
10309                         if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
10310                             (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
10311                                 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
10312                                 asc_dvc->bug_fix_cntl |=
10313                                     ASC_BUG_FIX_ASYN_USE_SYN;
10314                         }
10315                 }
10316         } else
10317 #endif /* CONFIG_PCI */
10318         if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
10319                 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
10320                     == ASC_CHIP_VER_ASYN_BUG) {
10321                         asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
10322                 }
10323         }
10324         if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
10325             asc_dvc->cfg->chip_scsi_id) {
10326                 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
10327         }
10328 #ifdef CONFIG_ISA
10329         if (asc_dvc->bus_type & ASC_IS_ISA) {
10330                 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
10331                 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
10332         }
10333 #endif /* CONFIG_ISA */
10334
10335         asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
10336
10337         switch (warn_code) {
10338         case 0: /* No error. */
10339                 break;
10340         case ASC_WARN_IO_PORT_ROTATE:
10341                 shost_printk(KERN_WARNING, shost, "I/O port address "
10342                                 "modified\n");
10343                 break;
10344         case ASC_WARN_AUTO_CONFIG:
10345                 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
10346                                 "enabled\n");
10347                 break;
10348         case ASC_WARN_EEPROM_CHKSUM:
10349                 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
10350                 break;
10351         case ASC_WARN_IRQ_MODIFIED:
10352                 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
10353                 break;
10354         case ASC_WARN_CMD_QNG_CONFLICT:
10355                 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
10356                                 "disconnects\n");
10357                 break;
10358         default:
10359                 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
10360                                 warn_code);
10361                 break;
10362         }
10363
10364         if (asc_dvc->err_code != 0)
10365                 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
10366                         "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
10367
10368         return asc_dvc->err_code;
10369 }
10370
10371 /*
10372  * EEPROM Configuration.
10373  *
10374  * All drivers should use this structure to set the default EEPROM
10375  * configuration. The BIOS now uses this structure when it is built.
10376  * Additional structure information can be found in a_condor.h where
10377  * the structure is defined.
10378  *
10379  * The *_Field_IsChar structs are needed to correct for endianness.
10380  * These values are read from the board 16 bits at a time directly
10381  * into the structs. Because some fields are char, the values will be
10382  * in the wrong order. The *_Field_IsChar tells when to flip the
10383  * bytes. Data read and written to PCI memory is automatically swapped
10384  * on big-endian platforms so char fields read as words are actually being
10385  * unswapped on big-endian platforms.
10386  */
10387 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
10388         ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
10389         0x0000,                 /* cfg_msw */
10390         0xFFFF,                 /* disc_enable */
10391         0xFFFF,                 /* wdtr_able */
10392         0xFFFF,                 /* sdtr_able */
10393         0xFFFF,                 /* start_motor */
10394         0xFFFF,                 /* tagqng_able */
10395         0xFFFF,                 /* bios_scan */
10396         0,                      /* scam_tolerant */
10397         7,                      /* adapter_scsi_id */
10398         0,                      /* bios_boot_delay */
10399         3,                      /* scsi_reset_delay */
10400         0,                      /* bios_id_lun */
10401         0,                      /* termination */
10402         0,                      /* reserved1 */
10403         0xFFE7,                 /* bios_ctrl */
10404         0xFFFF,                 /* ultra_able */
10405         0,                      /* reserved2 */
10406         ASC_DEF_MAX_HOST_QNG,   /* max_host_qng */
10407         ASC_DEF_MAX_DVC_QNG,    /* max_dvc_qng */
10408         0,                      /* dvc_cntl */
10409         0,                      /* bug_fix */
10410         0,                      /* serial_number_word1 */
10411         0,                      /* serial_number_word2 */
10412         0,                      /* serial_number_word3 */
10413         0,                      /* check_sum */
10414         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10415         ,                       /* oem_name[16] */
10416         0,                      /* dvc_err_code */
10417         0,                      /* adv_err_code */
10418         0,                      /* adv_err_addr */
10419         0,                      /* saved_dvc_err_code */
10420         0,                      /* saved_adv_err_code */
10421         0,                      /* saved_adv_err_addr */
10422         0                       /* num_of_err */
10423 };
10424
10425 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
10426         0,                      /* cfg_lsw */
10427         0,                      /* cfg_msw */
10428         0,                      /* -disc_enable */
10429         0,                      /* wdtr_able */
10430         0,                      /* sdtr_able */
10431         0,                      /* start_motor */
10432         0,                      /* tagqng_able */
10433         0,                      /* bios_scan */
10434         0,                      /* scam_tolerant */
10435         1,                      /* adapter_scsi_id */
10436         1,                      /* bios_boot_delay */
10437         1,                      /* scsi_reset_delay */
10438         1,                      /* bios_id_lun */
10439         1,                      /* termination */
10440         1,                      /* reserved1 */
10441         0,                      /* bios_ctrl */
10442         0,                      /* ultra_able */
10443         0,                      /* reserved2 */
10444         1,                      /* max_host_qng */
10445         1,                      /* max_dvc_qng */
10446         0,                      /* dvc_cntl */
10447         0,                      /* bug_fix */
10448         0,                      /* serial_number_word1 */
10449         0,                      /* serial_number_word2 */
10450         0,                      /* serial_number_word3 */
10451         0,                      /* check_sum */
10452         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10453         ,                       /* oem_name[16] */
10454         0,                      /* dvc_err_code */
10455         0,                      /* adv_err_code */
10456         0,                      /* adv_err_addr */
10457         0,                      /* saved_dvc_err_code */
10458         0,                      /* saved_adv_err_code */
10459         0,                      /* saved_adv_err_addr */
10460         0                       /* num_of_err */
10461 };
10462
10463 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
10464         ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
10465         0x0000,                 /* 01 cfg_msw */
10466         0xFFFF,                 /* 02 disc_enable */
10467         0xFFFF,                 /* 03 wdtr_able */
10468         0x4444,                 /* 04 sdtr_speed1 */
10469         0xFFFF,                 /* 05 start_motor */
10470         0xFFFF,                 /* 06 tagqng_able */
10471         0xFFFF,                 /* 07 bios_scan */
10472         0,                      /* 08 scam_tolerant */
10473         7,                      /* 09 adapter_scsi_id */
10474         0,                      /*    bios_boot_delay */
10475         3,                      /* 10 scsi_reset_delay */
10476         0,                      /*    bios_id_lun */
10477         0,                      /* 11 termination_se */
10478         0,                      /*    termination_lvd */
10479         0xFFE7,                 /* 12 bios_ctrl */
10480         0x4444,                 /* 13 sdtr_speed2 */
10481         0x4444,                 /* 14 sdtr_speed3 */
10482         ASC_DEF_MAX_HOST_QNG,   /* 15 max_host_qng */
10483         ASC_DEF_MAX_DVC_QNG,    /*    max_dvc_qng */
10484         0,                      /* 16 dvc_cntl */
10485         0x4444,                 /* 17 sdtr_speed4 */
10486         0,                      /* 18 serial_number_word1 */
10487         0,                      /* 19 serial_number_word2 */
10488         0,                      /* 20 serial_number_word3 */
10489         0,                      /* 21 check_sum */
10490         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10491         ,                       /* 22-29 oem_name[16] */
10492         0,                      /* 30 dvc_err_code */
10493         0,                      /* 31 adv_err_code */
10494         0,                      /* 32 adv_err_addr */
10495         0,                      /* 33 saved_dvc_err_code */
10496         0,                      /* 34 saved_adv_err_code */
10497         0,                      /* 35 saved_adv_err_addr */
10498         0,                      /* 36 reserved */
10499         0,                      /* 37 reserved */
10500         0,                      /* 38 reserved */
10501         0,                      /* 39 reserved */
10502         0,                      /* 40 reserved */
10503         0,                      /* 41 reserved */
10504         0,                      /* 42 reserved */
10505         0,                      /* 43 reserved */
10506         0,                      /* 44 reserved */
10507         0,                      /* 45 reserved */
10508         0,                      /* 46 reserved */
10509         0,                      /* 47 reserved */
10510         0,                      /* 48 reserved */
10511         0,                      /* 49 reserved */
10512         0,                      /* 50 reserved */
10513         0,                      /* 51 reserved */
10514         0,                      /* 52 reserved */
10515         0,                      /* 53 reserved */
10516         0,                      /* 54 reserved */
10517         0,                      /* 55 reserved */
10518         0,                      /* 56 cisptr_lsw */
10519         0,                      /* 57 cisprt_msw */
10520         PCI_VENDOR_ID_ASP,      /* 58 subsysvid */
10521         PCI_DEVICE_ID_38C0800_REV1,     /* 59 subsysid */
10522         0,                      /* 60 reserved */
10523         0,                      /* 61 reserved */
10524         0,                      /* 62 reserved */
10525         0                       /* 63 reserved */
10526 };
10527
10528 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
10529         0,                      /* 00 cfg_lsw */
10530         0,                      /* 01 cfg_msw */
10531         0,                      /* 02 disc_enable */
10532         0,                      /* 03 wdtr_able */
10533         0,                      /* 04 sdtr_speed1 */
10534         0,                      /* 05 start_motor */
10535         0,                      /* 06 tagqng_able */
10536         0,                      /* 07 bios_scan */
10537         0,                      /* 08 scam_tolerant */
10538         1,                      /* 09 adapter_scsi_id */
10539         1,                      /*    bios_boot_delay */
10540         1,                      /* 10 scsi_reset_delay */
10541         1,                      /*    bios_id_lun */
10542         1,                      /* 11 termination_se */
10543         1,                      /*    termination_lvd */
10544         0,                      /* 12 bios_ctrl */
10545         0,                      /* 13 sdtr_speed2 */
10546         0,                      /* 14 sdtr_speed3 */
10547         1,                      /* 15 max_host_qng */
10548         1,                      /*    max_dvc_qng */
10549         0,                      /* 16 dvc_cntl */
10550         0,                      /* 17 sdtr_speed4 */
10551         0,                      /* 18 serial_number_word1 */
10552         0,                      /* 19 serial_number_word2 */
10553         0,                      /* 20 serial_number_word3 */
10554         0,                      /* 21 check_sum */
10555         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10556         ,                       /* 22-29 oem_name[16] */
10557         0,                      /* 30 dvc_err_code */
10558         0,                      /* 31 adv_err_code */
10559         0,                      /* 32 adv_err_addr */
10560         0,                      /* 33 saved_dvc_err_code */
10561         0,                      /* 34 saved_adv_err_code */
10562         0,                      /* 35 saved_adv_err_addr */
10563         0,                      /* 36 reserved */
10564         0,                      /* 37 reserved */
10565         0,                      /* 38 reserved */
10566         0,                      /* 39 reserved */
10567         0,                      /* 40 reserved */
10568         0,                      /* 41 reserved */
10569         0,                      /* 42 reserved */
10570         0,                      /* 43 reserved */
10571         0,                      /* 44 reserved */
10572         0,                      /* 45 reserved */
10573         0,                      /* 46 reserved */
10574         0,                      /* 47 reserved */
10575         0,                      /* 48 reserved */
10576         0,                      /* 49 reserved */
10577         0,                      /* 50 reserved */
10578         0,                      /* 51 reserved */
10579         0,                      /* 52 reserved */
10580         0,                      /* 53 reserved */
10581         0,                      /* 54 reserved */
10582         0,                      /* 55 reserved */
10583         0,                      /* 56 cisptr_lsw */
10584         0,                      /* 57 cisprt_msw */
10585         0,                      /* 58 subsysvid */
10586         0,                      /* 59 subsysid */
10587         0,                      /* 60 reserved */
10588         0,                      /* 61 reserved */
10589         0,                      /* 62 reserved */
10590         0                       /* 63 reserved */
10591 };
10592
10593 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
10594         ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
10595         0x0000,                 /* 01 cfg_msw */
10596         0xFFFF,                 /* 02 disc_enable */
10597         0xFFFF,                 /* 03 wdtr_able */
10598         0x5555,                 /* 04 sdtr_speed1 */
10599         0xFFFF,                 /* 05 start_motor */
10600         0xFFFF,                 /* 06 tagqng_able */
10601         0xFFFF,                 /* 07 bios_scan */
10602         0,                      /* 08 scam_tolerant */
10603         7,                      /* 09 adapter_scsi_id */
10604         0,                      /*    bios_boot_delay */
10605         3,                      /* 10 scsi_reset_delay */
10606         0,                      /*    bios_id_lun */
10607         0,                      /* 11 termination_se */
10608         0,                      /*    termination_lvd */
10609         0xFFE7,                 /* 12 bios_ctrl */
10610         0x5555,                 /* 13 sdtr_speed2 */
10611         0x5555,                 /* 14 sdtr_speed3 */
10612         ASC_DEF_MAX_HOST_QNG,   /* 15 max_host_qng */
10613         ASC_DEF_MAX_DVC_QNG,    /*    max_dvc_qng */
10614         0,                      /* 16 dvc_cntl */
10615         0x5555,                 /* 17 sdtr_speed4 */
10616         0,                      /* 18 serial_number_word1 */
10617         0,                      /* 19 serial_number_word2 */
10618         0,                      /* 20 serial_number_word3 */
10619         0,                      /* 21 check_sum */
10620         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10621         ,                       /* 22-29 oem_name[16] */
10622         0,                      /* 30 dvc_err_code */
10623         0,                      /* 31 adv_err_code */
10624         0,                      /* 32 adv_err_addr */
10625         0,                      /* 33 saved_dvc_err_code */
10626         0,                      /* 34 saved_adv_err_code */
10627         0,                      /* 35 saved_adv_err_addr */
10628         0,                      /* 36 reserved */
10629         0,                      /* 37 reserved */
10630         0,                      /* 38 reserved */
10631         0,                      /* 39 reserved */
10632         0,                      /* 40 reserved */
10633         0,                      /* 41 reserved */
10634         0,                      /* 42 reserved */
10635         0,                      /* 43 reserved */
10636         0,                      /* 44 reserved */
10637         0,                      /* 45 reserved */
10638         0,                      /* 46 reserved */
10639         0,                      /* 47 reserved */
10640         0,                      /* 48 reserved */
10641         0,                      /* 49 reserved */
10642         0,                      /* 50 reserved */
10643         0,                      /* 51 reserved */
10644         0,                      /* 52 reserved */
10645         0,                      /* 53 reserved */
10646         0,                      /* 54 reserved */
10647         0,                      /* 55 reserved */
10648         0,                      /* 56 cisptr_lsw */
10649         0,                      /* 57 cisprt_msw */
10650         PCI_VENDOR_ID_ASP,      /* 58 subsysvid */
10651         PCI_DEVICE_ID_38C1600_REV1,     /* 59 subsysid */
10652         0,                      /* 60 reserved */
10653         0,                      /* 61 reserved */
10654         0,                      /* 62 reserved */
10655         0                       /* 63 reserved */
10656 };
10657
10658 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
10659         0,                      /* 00 cfg_lsw */
10660         0,                      /* 01 cfg_msw */
10661         0,                      /* 02 disc_enable */
10662         0,                      /* 03 wdtr_able */
10663         0,                      /* 04 sdtr_speed1 */
10664         0,                      /* 05 start_motor */
10665         0,                      /* 06 tagqng_able */
10666         0,                      /* 07 bios_scan */
10667         0,                      /* 08 scam_tolerant */
10668         1,                      /* 09 adapter_scsi_id */
10669         1,                      /*    bios_boot_delay */
10670         1,                      /* 10 scsi_reset_delay */
10671         1,                      /*    bios_id_lun */
10672         1,                      /* 11 termination_se */
10673         1,                      /*    termination_lvd */
10674         0,                      /* 12 bios_ctrl */
10675         0,                      /* 13 sdtr_speed2 */
10676         0,                      /* 14 sdtr_speed3 */
10677         1,                      /* 15 max_host_qng */
10678         1,                      /*    max_dvc_qng */
10679         0,                      /* 16 dvc_cntl */
10680         0,                      /* 17 sdtr_speed4 */
10681         0,                      /* 18 serial_number_word1 */
10682         0,                      /* 19 serial_number_word2 */
10683         0,                      /* 20 serial_number_word3 */
10684         0,                      /* 21 check_sum */
10685         {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10686         ,                       /* 22-29 oem_name[16] */
10687         0,                      /* 30 dvc_err_code */
10688         0,                      /* 31 adv_err_code */
10689         0,                      /* 32 adv_err_addr */
10690         0,                      /* 33 saved_dvc_err_code */
10691         0,                      /* 34 saved_adv_err_code */
10692         0,                      /* 35 saved_adv_err_addr */
10693         0,                      /* 36 reserved */
10694         0,                      /* 37 reserved */
10695         0,                      /* 38 reserved */
10696         0,                      /* 39 reserved */
10697         0,                      /* 40 reserved */
10698         0,                      /* 41 reserved */
10699         0,                      /* 42 reserved */
10700         0,                      /* 43 reserved */
10701         0,                      /* 44 reserved */
10702         0,                      /* 45 reserved */
10703         0,                      /* 46 reserved */
10704         0,                      /* 47 reserved */
10705         0,                      /* 48 reserved */
10706         0,                      /* 49 reserved */
10707         0,                      /* 50 reserved */
10708         0,                      /* 51 reserved */
10709         0,                      /* 52 reserved */
10710         0,                      /* 53 reserved */
10711         0,                      /* 54 reserved */
10712         0,                      /* 55 reserved */
10713         0,                      /* 56 cisptr_lsw */
10714         0,                      /* 57 cisprt_msw */
10715         0,                      /* 58 subsysvid */
10716         0,                      /* 59 subsysid */
10717         0,                      /* 60 reserved */
10718         0,                      /* 61 reserved */
10719         0,                      /* 62 reserved */
10720         0                       /* 63 reserved */
10721 };
10722
10723 #ifdef CONFIG_PCI
10724 /*
10725  * Wait for EEPROM command to complete
10726  */
10727 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
10728 {
10729         int eep_delay_ms;
10730
10731         for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10732                 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10733                     ASC_EEP_CMD_DONE) {
10734                         break;
10735                 }
10736                 mdelay(1);
10737         }
10738         if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10739             0)
10740                 BUG();
10741 }
10742
10743 /*
10744  * Read the EEPROM from specified location
10745  */
10746 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10747 {
10748         AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10749                              ASC_EEP_CMD_READ | eep_word_addr);
10750         AdvWaitEEPCmd(iop_base);
10751         return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10752 }
10753
10754 /*
10755  * Write the EEPROM from 'cfg_buf'.
10756  */
10757 static void __devinit
10758 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
10759 {
10760         ushort *wbuf;
10761         ushort addr, chksum;
10762         ushort *charfields;
10763
10764         wbuf = (ushort *)cfg_buf;
10765         charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10766         chksum = 0;
10767
10768         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10769         AdvWaitEEPCmd(iop_base);
10770
10771         /*
10772          * Write EEPROM from word 0 to word 20.
10773          */
10774         for (addr = ADV_EEP_DVC_CFG_BEGIN;
10775              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10776                 ushort word;
10777
10778                 if (*charfields++) {
10779                         word = cpu_to_le16(*wbuf);
10780                 } else {
10781                         word = *wbuf;
10782                 }
10783                 chksum += *wbuf;        /* Checksum is calculated from word values. */
10784                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10785                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10786                                      ASC_EEP_CMD_WRITE | addr);
10787                 AdvWaitEEPCmd(iop_base);
10788                 mdelay(ADV_EEP_DELAY_MS);
10789         }
10790
10791         /*
10792          * Write EEPROM checksum at word 21.
10793          */
10794         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10795         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10796         AdvWaitEEPCmd(iop_base);
10797         wbuf++;
10798         charfields++;
10799
10800         /*
10801          * Write EEPROM OEM name at words 22 to 29.
10802          */
10803         for (addr = ADV_EEP_DVC_CTL_BEGIN;
10804              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10805                 ushort word;
10806
10807                 if (*charfields++) {
10808                         word = cpu_to_le16(*wbuf);
10809                 } else {
10810                         word = *wbuf;
10811                 }
10812                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10813                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10814                                      ASC_EEP_CMD_WRITE | addr);
10815                 AdvWaitEEPCmd(iop_base);
10816         }
10817         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10818         AdvWaitEEPCmd(iop_base);
10819 }
10820
10821 /*
10822  * Write the EEPROM from 'cfg_buf'.
10823  */
10824 static void __devinit
10825 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
10826 {
10827         ushort *wbuf;
10828         ushort *charfields;
10829         ushort addr, chksum;
10830
10831         wbuf = (ushort *)cfg_buf;
10832         charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10833         chksum = 0;
10834
10835         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10836         AdvWaitEEPCmd(iop_base);
10837
10838         /*
10839          * Write EEPROM from word 0 to word 20.
10840          */
10841         for (addr = ADV_EEP_DVC_CFG_BEGIN;
10842              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10843                 ushort word;
10844
10845                 if (*charfields++) {
10846                         word = cpu_to_le16(*wbuf);
10847                 } else {
10848                         word = *wbuf;
10849                 }
10850                 chksum += *wbuf;        /* Checksum is calculated from word values. */
10851                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10852                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10853                                      ASC_EEP_CMD_WRITE | addr);
10854                 AdvWaitEEPCmd(iop_base);
10855                 mdelay(ADV_EEP_DELAY_MS);
10856         }
10857
10858         /*
10859          * Write EEPROM checksum at word 21.
10860          */
10861         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10862         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10863         AdvWaitEEPCmd(iop_base);
10864         wbuf++;
10865         charfields++;
10866
10867         /*
10868          * Write EEPROM OEM name at words 22 to 29.
10869          */
10870         for (addr = ADV_EEP_DVC_CTL_BEGIN;
10871              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10872                 ushort word;
10873
10874                 if (*charfields++) {
10875                         word = cpu_to_le16(*wbuf);
10876                 } else {
10877                         word = *wbuf;
10878                 }
10879                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10880                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10881                                      ASC_EEP_CMD_WRITE | addr);
10882                 AdvWaitEEPCmd(iop_base);
10883         }
10884         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10885         AdvWaitEEPCmd(iop_base);
10886 }
10887
10888 /*
10889  * Write the EEPROM from 'cfg_buf'.
10890  */
10891 static void __devinit
10892 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
10893 {
10894         ushort *wbuf;
10895         ushort *charfields;
10896         ushort addr, chksum;
10897
10898         wbuf = (ushort *)cfg_buf;
10899         charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10900         chksum = 0;
10901
10902         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10903         AdvWaitEEPCmd(iop_base);
10904
10905         /*
10906          * Write EEPROM from word 0 to word 20.
10907          */
10908         for (addr = ADV_EEP_DVC_CFG_BEGIN;
10909              addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10910                 ushort word;
10911
10912                 if (*charfields++) {
10913                         word = cpu_to_le16(*wbuf);
10914                 } else {
10915                         word = *wbuf;
10916                 }
10917                 chksum += *wbuf;        /* Checksum is calculated from word values. */
10918                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10919                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10920                                      ASC_EEP_CMD_WRITE | addr);
10921                 AdvWaitEEPCmd(iop_base);
10922                 mdelay(ADV_EEP_DELAY_MS);
10923         }
10924
10925         /*
10926          * Write EEPROM checksum at word 21.
10927          */
10928         AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10929         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10930         AdvWaitEEPCmd(iop_base);
10931         wbuf++;
10932         charfields++;
10933
10934         /*
10935          * Write EEPROM OEM name at words 22 to 29.
10936          */
10937         for (addr = ADV_EEP_DVC_CTL_BEGIN;
10938              addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10939                 ushort word;
10940
10941                 if (*charfields++) {
10942                         word = cpu_to_le16(*wbuf);
10943                 } else {
10944                         word = *wbuf;
10945                 }
10946                 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10947                 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10948                                      ASC_EEP_CMD_WRITE | addr);
10949                 AdvWaitEEPCmd(iop_base);
10950         }
10951         AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10952         AdvWaitEEPCmd(iop_base);
10953 }
10954
10955 /*
10956  * Read EEPROM configuration into the specified buffer.
10957  *
10958  * Return a checksum based on the EEPROM configuration read.
10959  */
10960 static ushort __devinit
10961 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
10962 {
10963         ushort wval, chksum;
10964         ushort *wbuf;
10965         int eep_addr;
10966         ushort *charfields;
10967
10968         charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10969         wbuf = (ushort *)cfg_buf;
10970         chksum = 0;
10971
10972         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10973              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10974                 wval = AdvReadEEPWord(iop_base, eep_addr);
10975                 chksum += wval; /* Checksum is calculated from word values. */
10976                 if (*charfields++) {
10977                         *wbuf = le16_to_cpu(wval);
10978                 } else {
10979                         *wbuf = wval;
10980                 }
10981         }
10982         /* Read checksum word. */
10983         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10984         wbuf++;
10985         charfields++;
10986
10987         /* Read rest of EEPROM not covered by the checksum. */
10988         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10989              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10990                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10991                 if (*charfields++) {
10992                         *wbuf = le16_to_cpu(*wbuf);
10993                 }
10994         }
10995         return chksum;
10996 }
10997
10998 /*
10999  * Read EEPROM configuration into the specified buffer.
11000  *
11001  * Return a checksum based on the EEPROM configuration read.
11002  */
11003 static ushort __devinit
11004 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
11005 {
11006         ushort wval, chksum;
11007         ushort *wbuf;
11008         int eep_addr;
11009         ushort *charfields;
11010
11011         charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
11012         wbuf = (ushort *)cfg_buf;
11013         chksum = 0;
11014
11015         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
11016              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
11017                 wval = AdvReadEEPWord(iop_base, eep_addr);
11018                 chksum += wval; /* Checksum is calculated from word values. */
11019                 if (*charfields++) {
11020                         *wbuf = le16_to_cpu(wval);
11021                 } else {
11022                         *wbuf = wval;
11023                 }
11024         }
11025         /* Read checksum word. */
11026         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
11027         wbuf++;
11028         charfields++;
11029
11030         /* Read rest of EEPROM not covered by the checksum. */
11031         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
11032              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
11033                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
11034                 if (*charfields++) {
11035                         *wbuf = le16_to_cpu(*wbuf);
11036                 }
11037         }
11038         return chksum;
11039 }
11040
11041 /*
11042  * Read EEPROM configuration into the specified buffer.
11043  *
11044  * Return a checksum based on the EEPROM configuration read.
11045  */
11046 static ushort __devinit
11047 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
11048 {
11049         ushort wval, chksum;
11050         ushort *wbuf;
11051         int eep_addr;
11052         ushort *charfields;
11053
11054         charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
11055         wbuf = (ushort *)cfg_buf;
11056         chksum = 0;
11057
11058         for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
11059              eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
11060                 wval = AdvReadEEPWord(iop_base, eep_addr);
11061                 chksum += wval; /* Checksum is calculated from word values. */
11062                 if (*charfields++) {
11063                         *wbuf = le16_to_cpu(wval);
11064                 } else {
11065                         *wbuf = wval;
11066                 }
11067         }
11068         /* Read checksum word. */
11069         *wbuf = AdvReadEEPWord(iop_base, eep_addr);
11070         wbuf++;
11071         charfields++;
11072
11073         /* Read rest of EEPROM not covered by the checksum. */
11074         for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
11075              eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
11076                 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
11077                 if (*charfields++) {
11078                         *wbuf = le16_to_cpu(*wbuf);
11079                 }
11080         }
11081         return chksum;
11082 }
11083
11084 /*
11085  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
11086  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
11087  * all of this is done.
11088  *
11089  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11090  *
11091  * For a non-fatal error return a warning code. If there are no warnings
11092  * then 0 is returned.
11093  *
11094  * Note: Chip is stopped on entry.
11095  */
11096 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
11097 {
11098         AdvPortAddr iop_base;
11099         ushort warn_code;
11100         ADVEEP_3550_CONFIG eep_config;
11101
11102         iop_base = asc_dvc->iop_base;
11103
11104         warn_code = 0;
11105
11106         /*
11107          * Read the board's EEPROM configuration.
11108          *
11109          * Set default values if a bad checksum is found.
11110          */
11111         if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
11112                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
11113
11114                 /*
11115                  * Set EEPROM default values.
11116                  */
11117                 memcpy(&eep_config, &Default_3550_EEPROM_Config,
11118                         sizeof(ADVEEP_3550_CONFIG));
11119
11120                 /*
11121                  * Assume the 6 byte board serial number that was read from
11122                  * EEPROM is correct even if the EEPROM checksum failed.
11123                  */
11124                 eep_config.serial_number_word3 =
11125                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
11126
11127                 eep_config.serial_number_word2 =
11128                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
11129
11130                 eep_config.serial_number_word1 =
11131                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
11132
11133                 AdvSet3550EEPConfig(iop_base, &eep_config);
11134         }
11135         /*
11136          * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
11137          * EEPROM configuration that was read.
11138          *
11139          * This is the mapping of EEPROM fields to Adv Library fields.
11140          */
11141         asc_dvc->wdtr_able = eep_config.wdtr_able;
11142         asc_dvc->sdtr_able = eep_config.sdtr_able;
11143         asc_dvc->ultra_able = eep_config.ultra_able;
11144         asc_dvc->tagqng_able = eep_config.tagqng_able;
11145         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
11146         asc_dvc->max_host_qng = eep_config.max_host_qng;
11147         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11148         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
11149         asc_dvc->start_motor = eep_config.start_motor;
11150         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
11151         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
11152         asc_dvc->no_scam = eep_config.scam_tolerant;
11153         asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
11154         asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
11155         asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
11156
11157         /*
11158          * Set the host maximum queuing (max. 253, min. 16) and the per device
11159          * maximum queuing (max. 63, min. 4).
11160          */
11161         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
11162                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11163         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
11164                 /* If the value is zero, assume it is uninitialized. */
11165                 if (eep_config.max_host_qng == 0) {
11166                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11167                 } else {
11168                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
11169                 }
11170         }
11171
11172         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
11173                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11174         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
11175                 /* If the value is zero, assume it is uninitialized. */
11176                 if (eep_config.max_dvc_qng == 0) {
11177                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11178                 } else {
11179                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
11180                 }
11181         }
11182
11183         /*
11184          * If 'max_dvc_qng' is greater than 'max_host_qng', then
11185          * set 'max_dvc_qng' to 'max_host_qng'.
11186          */
11187         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
11188                 eep_config.max_dvc_qng = eep_config.max_host_qng;
11189         }
11190
11191         /*
11192          * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
11193          * values based on possibly adjusted EEPROM values.
11194          */
11195         asc_dvc->max_host_qng = eep_config.max_host_qng;
11196         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11197
11198         /*
11199          * If the EEPROM 'termination' field is set to automatic (0), then set
11200          * the ADV_DVC_CFG 'termination' field to automatic also.
11201          *
11202          * If the termination is specified with a non-zero 'termination'
11203          * value check that a legal value is set and set the ADV_DVC_CFG
11204          * 'termination' field appropriately.
11205          */
11206         if (eep_config.termination == 0) {
11207                 asc_dvc->cfg->termination = 0;  /* auto termination */
11208         } else {
11209                 /* Enable manual control with low off / high off. */
11210                 if (eep_config.termination == 1) {
11211                         asc_dvc->cfg->termination = TERM_CTL_SEL;
11212
11213                         /* Enable manual control with low off / high on. */
11214                 } else if (eep_config.termination == 2) {
11215                         asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
11216
11217                         /* Enable manual control with low on / high on. */
11218                 } else if (eep_config.termination == 3) {
11219                         asc_dvc->cfg->termination =
11220                             TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
11221                 } else {
11222                         /*
11223                          * The EEPROM 'termination' field contains a bad value. Use
11224                          * automatic termination instead.
11225                          */
11226                         asc_dvc->cfg->termination = 0;
11227                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
11228                 }
11229         }
11230
11231         return warn_code;
11232 }
11233
11234 /*
11235  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
11236  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
11237  * all of this is done.
11238  *
11239  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11240  *
11241  * For a non-fatal error return a warning code. If there are no warnings
11242  * then 0 is returned.
11243  *
11244  * Note: Chip is stopped on entry.
11245  */
11246 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
11247 {
11248         AdvPortAddr iop_base;
11249         ushort warn_code;
11250         ADVEEP_38C0800_CONFIG eep_config;
11251         uchar tid, termination;
11252         ushort sdtr_speed = 0;
11253
11254         iop_base = asc_dvc->iop_base;
11255
11256         warn_code = 0;
11257
11258         /*
11259          * Read the board's EEPROM configuration.
11260          *
11261          * Set default values if a bad checksum is found.
11262          */
11263         if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
11264             eep_config.check_sum) {
11265                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
11266
11267                 /*
11268                  * Set EEPROM default values.
11269                  */
11270                 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
11271                         sizeof(ADVEEP_38C0800_CONFIG));
11272
11273                 /*
11274                  * Assume the 6 byte board serial number that was read from
11275                  * EEPROM is correct even if the EEPROM checksum failed.
11276                  */
11277                 eep_config.serial_number_word3 =
11278                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
11279
11280                 eep_config.serial_number_word2 =
11281                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
11282
11283                 eep_config.serial_number_word1 =
11284                     AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
11285
11286                 AdvSet38C0800EEPConfig(iop_base, &eep_config);
11287         }
11288         /*
11289          * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
11290          * EEPROM configuration that was read.
11291          *
11292          * This is the mapping of EEPROM fields to Adv Library fields.
11293          */
11294         asc_dvc->wdtr_able = eep_config.wdtr_able;
11295         asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
11296         asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
11297         asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
11298         asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
11299         asc_dvc->tagqng_able = eep_config.tagqng_able;
11300         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
11301         asc_dvc->max_host_qng = eep_config.max_host_qng;
11302         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11303         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
11304         asc_dvc->start_motor = eep_config.start_motor;
11305         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
11306         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
11307         asc_dvc->no_scam = eep_config.scam_tolerant;
11308         asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
11309         asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
11310         asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
11311
11312         /*
11313          * For every Target ID if any of its 'sdtr_speed[1234]' bits
11314          * are set, then set an 'sdtr_able' bit for it.
11315          */
11316         asc_dvc->sdtr_able = 0;
11317         for (tid = 0; tid <= ADV_MAX_TID; tid++) {
11318                 if (tid == 0) {
11319                         sdtr_speed = asc_dvc->sdtr_speed1;
11320                 } else if (tid == 4) {
11321                         sdtr_speed = asc_dvc->sdtr_speed2;
11322                 } else if (tid == 8) {
11323                         sdtr_speed = asc_dvc->sdtr_speed3;
11324                 } else if (tid == 12) {
11325                         sdtr_speed = asc_dvc->sdtr_speed4;
11326                 }
11327                 if (sdtr_speed & ADV_MAX_TID) {
11328                         asc_dvc->sdtr_able |= (1 << tid);
11329                 }
11330                 sdtr_speed >>= 4;
11331         }
11332
11333         /*
11334          * Set the host maximum queuing (max. 253, min. 16) and the per device
11335          * maximum queuing (max. 63, min. 4).
11336          */
11337         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
11338                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11339         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
11340                 /* If the value is zero, assume it is uninitialized. */
11341                 if (eep_config.max_host_qng == 0) {
11342                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11343                 } else {
11344                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
11345                 }
11346         }
11347
11348         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
11349                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11350         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
11351                 /* If the value is zero, assume it is uninitialized. */
11352                 if (eep_config.max_dvc_qng == 0) {
11353                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11354                 } else {
11355                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
11356                 }
11357         }
11358
11359         /*
11360          * If 'max_dvc_qng' is greater than 'max_host_qng', then
11361          * set 'max_dvc_qng' to 'max_host_qng'.
11362          */
11363         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
11364                 eep_config.max_dvc_qng = eep_config.max_host_qng;
11365         }
11366
11367         /*
11368          * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
11369          * values based on possibly adjusted EEPROM values.
11370          */
11371         asc_dvc->max_host_qng = eep_config.max_host_qng;
11372         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11373
11374         /*
11375          * If the EEPROM 'termination' field is set to automatic (0), then set
11376          * the ADV_DVC_CFG 'termination' field to automatic also.
11377          *
11378          * If the termination is specified with a non-zero 'termination'
11379          * value check that a legal value is set and set the ADV_DVC_CFG
11380          * 'termination' field appropriately.
11381          */
11382         if (eep_config.termination_se == 0) {
11383                 termination = 0;        /* auto termination for SE */
11384         } else {
11385                 /* Enable manual control with low off / high off. */
11386                 if (eep_config.termination_se == 1) {
11387                         termination = 0;
11388
11389                         /* Enable manual control with low off / high on. */
11390                 } else if (eep_config.termination_se == 2) {
11391                         termination = TERM_SE_HI;
11392
11393                         /* Enable manual control with low on / high on. */
11394                 } else if (eep_config.termination_se == 3) {
11395                         termination = TERM_SE;
11396                 } else {
11397                         /*
11398                          * The EEPROM 'termination_se' field contains a bad value.
11399                          * Use automatic termination instead.
11400                          */
11401                         termination = 0;
11402                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
11403                 }
11404         }
11405
11406         if (eep_config.termination_lvd == 0) {
11407                 asc_dvc->cfg->termination = termination;        /* auto termination for LVD */
11408         } else {
11409                 /* Enable manual control with low off / high off. */
11410                 if (eep_config.termination_lvd == 1) {
11411                         asc_dvc->cfg->termination = termination;
11412
11413                         /* Enable manual control with low off / high on. */
11414                 } else if (eep_config.termination_lvd == 2) {
11415                         asc_dvc->cfg->termination = termination | TERM_LVD_HI;
11416
11417                         /* Enable manual control with low on / high on. */
11418                 } else if (eep_config.termination_lvd == 3) {
11419                         asc_dvc->cfg->termination = termination | TERM_LVD;
11420                 } else {
11421                         /*
11422                          * The EEPROM 'termination_lvd' field contains a bad value.
11423                          * Use automatic termination instead.
11424                          */
11425                         asc_dvc->cfg->termination = termination;
11426                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
11427                 }
11428         }
11429
11430         return warn_code;
11431 }
11432
11433 /*
11434  * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
11435  * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
11436  * all of this is done.
11437  *
11438  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
11439  *
11440  * For a non-fatal error return a warning code. If there are no warnings
11441  * then 0 is returned.
11442  *
11443  * Note: Chip is stopped on entry.
11444  */
11445 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
11446 {
11447         AdvPortAddr iop_base;
11448         ushort warn_code;
11449         ADVEEP_38C1600_CONFIG eep_config;
11450         uchar tid, termination;
11451         ushort sdtr_speed = 0;
11452
11453         iop_base = asc_dvc->iop_base;
11454
11455         warn_code = 0;
11456
11457         /*
11458          * Read the board's EEPROM configuration.
11459          *
11460          * Set default values if a bad checksum is found.
11461          */
11462         if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
11463             eep_config.check_sum) {
11464                 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
11465                 warn_code |= ASC_WARN_EEPROM_CHKSUM;
11466
11467                 /*
11468                  * Set EEPROM default values.
11469                  */
11470                 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
11471                         sizeof(ADVEEP_38C1600_CONFIG));
11472
11473                 if (PCI_FUNC(pdev->devfn) != 0) {
11474                         u8 ints;
11475                         /*
11476                          * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
11477                          * and old Mac system booting problem. The Expansion
11478                          * ROM must be disabled in Function 1 for these systems
11479                          */
11480                         eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
11481                         /*
11482                          * Clear the INTAB (bit 11) if the GPIO 0 input
11483                          * indicates the Function 1 interrupt line is wired
11484                          * to INTB.
11485                          *
11486                          * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
11487                          *   1 - Function 1 interrupt line wired to INT A.
11488                          *   0 - Function 1 interrupt line wired to INT B.
11489                          *
11490                          * Note: Function 0 is always wired to INTA.
11491                          * Put all 5 GPIO bits in input mode and then read
11492                          * their input values.
11493                          */
11494                         AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
11495                         ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
11496                         if ((ints & 0x01) == 0)
11497                                 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
11498                 }
11499
11500                 /*
11501                  * Assume the 6 byte board serial number that was read from
11502                  * EEPROM is correct even if the EEPROM checksum failed.
11503                  */
11504                 eep_config.serial_number_word3 =
11505                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
11506                 eep_config.serial_number_word2 =
11507                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
11508                 eep_config.serial_number_word1 =
11509                         AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
11510
11511                 AdvSet38C1600EEPConfig(iop_base, &eep_config);
11512         }
11513
11514         /*
11515          * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
11516          * EEPROM configuration that was read.
11517          *
11518          * This is the mapping of EEPROM fields to Adv Library fields.
11519          */
11520         asc_dvc->wdtr_able = eep_config.wdtr_able;
11521         asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
11522         asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
11523         asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
11524         asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
11525         asc_dvc->ppr_able = 0;
11526         asc_dvc->tagqng_able = eep_config.tagqng_able;
11527         asc_dvc->cfg->disc_enable = eep_config.disc_enable;
11528         asc_dvc->max_host_qng = eep_config.max_host_qng;
11529         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11530         asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
11531         asc_dvc->start_motor = eep_config.start_motor;
11532         asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
11533         asc_dvc->bios_ctrl = eep_config.bios_ctrl;
11534         asc_dvc->no_scam = eep_config.scam_tolerant;
11535
11536         /*
11537          * For every Target ID if any of its 'sdtr_speed[1234]' bits
11538          * are set, then set an 'sdtr_able' bit for it.
11539          */
11540         asc_dvc->sdtr_able = 0;
11541         for (tid = 0; tid <= ASC_MAX_TID; tid++) {
11542                 if (tid == 0) {
11543                         sdtr_speed = asc_dvc->sdtr_speed1;
11544                 } else if (tid == 4) {
11545                         sdtr_speed = asc_dvc->sdtr_speed2;
11546                 } else if (tid == 8) {
11547                         sdtr_speed = asc_dvc->sdtr_speed3;
11548                 } else if (tid == 12) {
11549                         sdtr_speed = asc_dvc->sdtr_speed4;
11550                 }
11551                 if (sdtr_speed & ASC_MAX_TID) {
11552                         asc_dvc->sdtr_able |= (1 << tid);
11553                 }
11554                 sdtr_speed >>= 4;
11555         }
11556
11557         /*
11558          * Set the host maximum queuing (max. 253, min. 16) and the per device
11559          * maximum queuing (max. 63, min. 4).
11560          */
11561         if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
11562                 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11563         } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
11564                 /* If the value is zero, assume it is uninitialized. */
11565                 if (eep_config.max_host_qng == 0) {
11566                         eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11567                 } else {
11568                         eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
11569                 }
11570         }
11571
11572         if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
11573                 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11574         } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
11575                 /* If the value is zero, assume it is uninitialized. */
11576                 if (eep_config.max_dvc_qng == 0) {
11577                         eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11578                 } else {
11579                         eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
11580                 }
11581         }
11582
11583         /*
11584          * If 'max_dvc_qng' is greater than 'max_host_qng', then
11585          * set 'max_dvc_qng' to 'max_host_qng'.
11586          */
11587         if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
11588                 eep_config.max_dvc_qng = eep_config.max_host_qng;
11589         }
11590
11591         /*
11592          * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
11593          * values based on possibly adjusted EEPROM values.
11594          */
11595         asc_dvc->max_host_qng = eep_config.max_host_qng;
11596         asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11597
11598         /*
11599          * If the EEPROM 'termination' field is set to automatic (0), then set
11600          * the ASC_DVC_CFG 'termination' field to automatic also.
11601          *
11602          * If the termination is specified with a non-zero 'termination'
11603          * value check that a legal value is set and set the ASC_DVC_CFG
11604          * 'termination' field appropriately.
11605          */
11606         if (eep_config.termination_se == 0) {
11607                 termination = 0;        /* auto termination for SE */
11608         } else {
11609                 /* Enable manual control with low off / high off. */
11610                 if (eep_config.termination_se == 1) {
11611                         termination = 0;
11612
11613                         /* Enable manual control with low off / high on. */
11614                 } else if (eep_config.termination_se == 2) {
11615                         termination = TERM_SE_HI;
11616
11617                         /* Enable manual control with low on / high on. */
11618                 } else if (eep_config.termination_se == 3) {
11619                         termination = TERM_SE;
11620                 } else {
11621                         /*
11622                          * The EEPROM 'termination_se' field contains a bad value.
11623                          * Use automatic termination instead.
11624                          */
11625                         termination = 0;
11626                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
11627                 }
11628         }
11629
11630         if (eep_config.termination_lvd == 0) {
11631                 asc_dvc->cfg->termination = termination;        /* auto termination for LVD */
11632         } else {
11633                 /* Enable manual control with low off / high off. */
11634                 if (eep_config.termination_lvd == 1) {
11635                         asc_dvc->cfg->termination = termination;
11636
11637                         /* Enable manual control with low off / high on. */
11638                 } else if (eep_config.termination_lvd == 2) {
11639                         asc_dvc->cfg->termination = termination | TERM_LVD_HI;
11640
11641                         /* Enable manual control with low on / high on. */
11642                 } else if (eep_config.termination_lvd == 3) {
11643                         asc_dvc->cfg->termination = termination | TERM_LVD;
11644                 } else {
11645                         /*
11646                          * The EEPROM 'termination_lvd' field contains a bad value.
11647                          * Use automatic termination instead.
11648                          */
11649                         asc_dvc->cfg->termination = termination;
11650                         warn_code |= ASC_WARN_EEPROM_TERMINATION;
11651                 }
11652         }
11653
11654         return warn_code;
11655 }
11656
11657 /*
11658  * Initialize the ADV_DVC_VAR structure.
11659  *
11660  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11661  *
11662  * For a non-fatal error return a warning code. If there are no warnings
11663  * then 0 is returned.
11664  */
11665 static int __devinit
11666 AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11667 {
11668         struct asc_board *board = shost_priv(shost);
11669         ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
11670         unsigned short warn_code = 0;
11671         AdvPortAddr iop_base = asc_dvc->iop_base;
11672         u16 cmd;
11673         int status;
11674
11675         asc_dvc->err_code = 0;
11676
11677         /*
11678          * Save the state of the PCI Configuration Command Register
11679          * "Parity Error Response Control" Bit. If the bit is clear (0),
11680          * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11681          * DMA parity errors.
11682          */
11683         asc_dvc->cfg->control_flag = 0;
11684         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11685         if ((cmd & PCI_COMMAND_PARITY) == 0)
11686                 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11687
11688         asc_dvc->cfg->chip_version =
11689             AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11690
11691         ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11692                  (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11693                  (ushort)ADV_CHIP_ID_BYTE);
11694
11695         ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11696                  (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11697                  (ushort)ADV_CHIP_ID_WORD);
11698
11699         /*
11700          * Reset the chip to start and allow register writes.
11701          */
11702         if (AdvFindSignature(iop_base) == 0) {
11703                 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11704                 return ADV_ERROR;
11705         } else {
11706                 /*
11707                  * The caller must set 'chip_type' to a valid setting.
11708                  */
11709                 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11710                     asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11711                     asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11712                         asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11713                         return ADV_ERROR;
11714                 }
11715
11716                 /*
11717                  * Reset Chip.
11718                  */
11719                 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11720                                      ADV_CTRL_REG_CMD_RESET);
11721                 mdelay(100);
11722                 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11723                                      ADV_CTRL_REG_CMD_WR_IO_REG);
11724
11725                 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11726                         status = AdvInitFrom38C1600EEP(asc_dvc);
11727                 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11728                         status = AdvInitFrom38C0800EEP(asc_dvc);
11729                 } else {
11730                         status = AdvInitFrom3550EEP(asc_dvc);
11731                 }
11732                 warn_code |= status;
11733         }
11734
11735         if (warn_code != 0)
11736                 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11737
11738         if (asc_dvc->err_code)
11739                 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11740                                 asc_dvc->err_code);
11741
11742         return asc_dvc->err_code;
11743 }
11744 #endif
11745
11746 static struct scsi_host_template advansys_template = {
11747         .proc_name = DRV_NAME,
11748 #ifdef CONFIG_PROC_FS
11749         .proc_info = advansys_proc_info,
11750 #endif
11751         .name = DRV_NAME,
11752         .info = advansys_info,
11753         .queuecommand = advansys_queuecommand,
11754         .eh_bus_reset_handler = advansys_reset,
11755         .bios_param = advansys_biosparam,
11756         .slave_configure = advansys_slave_configure,
11757         /*
11758          * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11759          * must be set. The flag will be cleared in advansys_board_found
11760          * for non-ISA adapters.
11761          */
11762         .unchecked_isa_dma = 1,
11763         /*
11764          * All adapters controlled by this driver are capable of large
11765          * scatter-gather lists. According to the mid-level SCSI documentation
11766          * this obviates any performance gain provided by setting
11767          * 'use_clustering'. But empirically while CPU utilization is increased
11768          * by enabling clustering, I/O throughput increases as well.
11769          */
11770         .use_clustering = ENABLE_CLUSTERING,
11771 };
11772
11773 static int __devinit advansys_wide_init_chip(struct Scsi_Host *shost)
11774 {
11775         struct asc_board *board = shost_priv(shost);
11776         struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11777         int req_cnt = 0;
11778         adv_req_t *reqp = NULL;
11779         int sg_cnt = 0;
11780         adv_sgblk_t *sgp;
11781         int warn_code, err_code;
11782
11783         /*
11784          * Allocate buffer carrier structures. The total size
11785          * is about 4 KB, so allocate all at once.
11786          */
11787         adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
11788         ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
11789
11790         if (!adv_dvc->carrier_buf)
11791                 goto kmalloc_failed;
11792
11793         /*
11794          * Allocate up to 'max_host_qng' request structures for the Wide
11795          * board. The total size is about 16 KB, so allocate all at once.
11796          * If the allocation fails decrement and try again.
11797          */
11798         for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
11799                 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
11800
11801                 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
11802                          (ulong)sizeof(adv_req_t) * req_cnt);
11803
11804                 if (reqp)
11805                         break;
11806         }
11807
11808         if (!reqp)
11809                 goto kmalloc_failed;
11810
11811         adv_dvc->orig_reqp = reqp;
11812
11813         /*
11814          * Allocate up to ADV_TOT_SG_BLOCK request structures for
11815          * the Wide board. Each structure is about 136 bytes.
11816          */
11817         board->adv_sgblkp = NULL;
11818         for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
11819                 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
11820
11821                 if (!sgp)
11822                         break;
11823
11824                 sgp->next_sgblkp = board->adv_sgblkp;
11825                 board->adv_sgblkp = sgp;
11826
11827         }
11828
11829         ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t),
11830                  sizeof(adv_sgblk_t) * sg_cnt);
11831
11832         if (!board->adv_sgblkp)
11833                 goto kmalloc_failed;
11834
11835         /*
11836          * Point 'adv_reqp' to the request structures and
11837          * link them together.
11838          */
11839         req_cnt--;
11840         reqp[req_cnt].next_reqp = NULL;
11841         for (; req_cnt > 0; req_cnt--) {
11842                 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
11843         }
11844         board->adv_reqp = &reqp[0];
11845
11846         if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11847                 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11848                 warn_code = AdvInitAsc3550Driver(adv_dvc);
11849         } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11850                 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11851                 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11852         } else {
11853                 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11854                 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11855         }
11856         err_code = adv_dvc->err_code;
11857
11858         if (warn_code || err_code) {
11859                 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11860                         "0x%x\n", warn_code, err_code);
11861         }
11862
11863         goto exit;
11864
11865  kmalloc_failed:
11866         shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11867         err_code = ADV_ERROR;
11868  exit:
11869         return err_code;
11870 }
11871
11872 static void advansys_wide_free_mem(struct asc_board *board)
11873 {
11874         struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11875         kfree(adv_dvc->carrier_buf);
11876         adv_dvc->carrier_buf = NULL;
11877         kfree(adv_dvc->orig_reqp);
11878         adv_dvc->orig_reqp = board->adv_reqp = NULL;
11879         while (board->adv_sgblkp) {
11880                 adv_sgblk_t *sgp = board->adv_sgblkp;
11881                 board->adv_sgblkp = sgp->next_sgblkp;
11882                 kfree(sgp);
11883         }
11884 }
11885
11886 static int __devinit advansys_board_found(struct Scsi_Host *shost,
11887                                           unsigned int iop, int bus_type)
11888 {
11889         struct pci_dev *pdev;
11890         struct asc_board *boardp = shost_priv(shost);
11891         ASC_DVC_VAR *asc_dvc_varp = NULL;
11892         ADV_DVC_VAR *adv_dvc_varp = NULL;
11893         int share_irq, warn_code, ret;
11894
11895         pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11896
11897         if (ASC_NARROW_BOARD(boardp)) {
11898                 ASC_DBG(1, "narrow board\n");
11899                 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11900                 asc_dvc_varp->bus_type = bus_type;
11901                 asc_dvc_varp->drv_ptr = boardp;
11902                 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11903                 asc_dvc_varp->iop_base = iop;
11904         } else {
11905 #ifdef CONFIG_PCI
11906                 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11907                 adv_dvc_varp->drv_ptr = boardp;
11908                 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11909                 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11910                         ASC_DBG(1, "wide board ASC-3550\n");
11911                         adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11912                 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11913                         ASC_DBG(1, "wide board ASC-38C0800\n");
11914                         adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11915                 } else {
11916                         ASC_DBG(1, "wide board ASC-38C1600\n");
11917                         adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11918                 }
11919
11920                 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11921                 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11922                 if (!boardp->ioremap_addr) {
11923                         shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11924                                         "returned NULL\n",
11925                                         (long)pci_resource_start(pdev, 1),
11926                                         boardp->asc_n_io_port);
11927                         ret = -ENODEV;
11928                         goto err_shost;
11929                 }
11930                 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11931                 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11932
11933                 /*
11934                  * Even though it isn't used to access wide boards, other
11935                  * than for the debug line below, save I/O Port address so
11936                  * that it can be reported.
11937                  */
11938                 boardp->ioport = iop;
11939
11940                 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11941                                 (ushort)inp(iop + 1), (ushort)inpw(iop));
11942 #endif /* CONFIG_PCI */
11943         }
11944
11945 #ifdef CONFIG_PROC_FS
11946         /*
11947          * Allocate buffer for printing information from
11948          * /proc/scsi/advansys/[0...].
11949          */
11950         boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
11951         if (!boardp->prtbuf) {
11952                 shost_printk(KERN_ERR, shost, "kmalloc(%d) returned NULL\n",
11953                                 ASC_PRTBUF_SIZE);
11954                 ret = -ENOMEM;
11955                 goto err_unmap;
11956         }
11957 #endif /* CONFIG_PROC_FS */
11958
11959         if (ASC_NARROW_BOARD(boardp)) {
11960                 /*
11961                  * Set the board bus type and PCI IRQ before
11962                  * calling AscInitGetConfig().
11963                  */
11964                 switch (asc_dvc_varp->bus_type) {
11965 #ifdef CONFIG_ISA
11966                 case ASC_IS_ISA:
11967                         shost->unchecked_isa_dma = TRUE;
11968                         share_irq = 0;
11969                         break;
11970                 case ASC_IS_VL:
11971                         shost->unchecked_isa_dma = FALSE;
11972                         share_irq = 0;
11973                         break;
11974                 case ASC_IS_EISA:
11975                         shost->unchecked_isa_dma = FALSE;
11976                         share_irq = IRQF_SHARED;
11977                         break;
11978 #endif /* CONFIG_ISA */
11979 #ifdef CONFIG_PCI
11980                 case ASC_IS_PCI:
11981                         shost->unchecked_isa_dma = FALSE;
11982                         share_irq = IRQF_SHARED;
11983                         break;
11984 #endif /* CONFIG_PCI */
11985                 default:
11986                         shost_printk(KERN_ERR, shost, "unknown adapter type: "
11987                                         "%d\n", asc_dvc_varp->bus_type);
11988                         shost->unchecked_isa_dma = TRUE;
11989                         share_irq = 0;
11990                         break;
11991                 }
11992
11993                 /*
11994                  * NOTE: AscInitGetConfig() may change the board's
11995                  * bus_type value. The bus_type value should no
11996                  * longer be used. If the bus_type field must be
11997                  * referenced only use the bit-wise AND operator "&".
11998                  */
11999                 ASC_DBG(2, "AscInitGetConfig()\n");
12000                 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
12001         } else {
12002 #ifdef CONFIG_PCI
12003                 /*
12004                  * For Wide boards set PCI information before calling
12005                  * AdvInitGetConfig().
12006                  */
12007                 shost->unchecked_isa_dma = FALSE;
12008                 share_irq = IRQF_SHARED;
12009                 ASC_DBG(2, "AdvInitGetConfig()\n");
12010
12011                 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
12012 #endif /* CONFIG_PCI */
12013         }
12014
12015         if (ret)
12016                 goto err_free_proc;
12017
12018         /*
12019          * Save the EEPROM configuration so that it can be displayed
12020          * from /proc/scsi/advansys/[0...].
12021          */
12022         if (ASC_NARROW_BOARD(boardp)) {
12023
12024                 ASCEEP_CONFIG *ep;
12025
12026                 /*
12027                  * Set the adapter's target id bit in the 'init_tidmask' field.
12028                  */
12029                 boardp->init_tidmask |=
12030                     ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
12031
12032                 /*
12033                  * Save EEPROM settings for the board.
12034                  */
12035                 ep = &boardp->eep_config.asc_eep;
12036
12037                 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
12038                 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
12039                 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
12040                 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
12041                 ep->start_motor = asc_dvc_varp->start_motor;
12042                 ep->cntl = asc_dvc_varp->dvc_cntl;
12043                 ep->no_scam = asc_dvc_varp->no_scam;
12044                 ep->max_total_qng = asc_dvc_varp->max_total_qng;
12045                 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
12046                 /* 'max_tag_qng' is set to the same value for every device. */
12047                 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
12048                 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
12049                 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
12050                 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
12051                 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
12052                 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
12053                 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
12054
12055                 /*
12056                  * Modify board configuration.
12057                  */
12058                 ASC_DBG(2, "AscInitSetConfig()\n");
12059                 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
12060                 if (ret)
12061                         goto err_free_proc;
12062         } else {
12063                 ADVEEP_3550_CONFIG *ep_3550;
12064                 ADVEEP_38C0800_CONFIG *ep_38C0800;
12065                 ADVEEP_38C1600_CONFIG *ep_38C1600;
12066
12067                 /*
12068                  * Save Wide EEP Configuration Information.
12069                  */
12070                 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
12071                         ep_3550 = &boardp->eep_config.adv_3550_eep;
12072
12073                         ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
12074                         ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
12075                         ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
12076                         ep_3550->termination = adv_dvc_varp->cfg->termination;
12077                         ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
12078                         ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
12079                         ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
12080                         ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
12081                         ep_3550->ultra_able = adv_dvc_varp->ultra_able;
12082                         ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
12083                         ep_3550->start_motor = adv_dvc_varp->start_motor;
12084                         ep_3550->scsi_reset_delay =
12085                             adv_dvc_varp->scsi_reset_wait;
12086                         ep_3550->serial_number_word1 =
12087                             adv_dvc_varp->cfg->serial1;
12088                         ep_3550->serial_number_word2 =
12089                             adv_dvc_varp->cfg->serial2;
12090                         ep_3550->serial_number_word3 =
12091                             adv_dvc_varp->cfg->serial3;
12092                 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
12093                         ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
12094
12095                         ep_38C0800->adapter_scsi_id =
12096                             adv_dvc_varp->chip_scsi_id;
12097                         ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
12098                         ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
12099                         ep_38C0800->termination_lvd =
12100                             adv_dvc_varp->cfg->termination;
12101                         ep_38C0800->disc_enable =
12102                             adv_dvc_varp->cfg->disc_enable;
12103                         ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
12104                         ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
12105                         ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
12106                         ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
12107                         ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
12108                         ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
12109                         ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
12110                         ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
12111                         ep_38C0800->start_motor = adv_dvc_varp->start_motor;
12112                         ep_38C0800->scsi_reset_delay =
12113                             adv_dvc_varp->scsi_reset_wait;
12114                         ep_38C0800->serial_number_word1 =
12115                             adv_dvc_varp->cfg->serial1;
12116                         ep_38C0800->serial_number_word2 =
12117                             adv_dvc_varp->cfg->serial2;
12118                         ep_38C0800->serial_number_word3 =
12119                             adv_dvc_varp->cfg->serial3;
12120                 } else {
12121                         ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
12122
12123                         ep_38C1600->adapter_scsi_id =
12124                             adv_dvc_varp->chip_scsi_id;
12125                         ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
12126                         ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
12127                         ep_38C1600->termination_lvd =
12128                             adv_dvc_varp->cfg->termination;
12129                         ep_38C1600->disc_enable =
12130                             adv_dvc_varp->cfg->disc_enable;
12131                         ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
12132                         ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
12133                         ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
12134                         ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
12135                         ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
12136                         ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
12137                         ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
12138                         ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
12139                         ep_38C1600->start_motor = adv_dvc_varp->start_motor;
12140                         ep_38C1600->scsi_reset_delay =
12141                             adv_dvc_varp->scsi_reset_wait;
12142                         ep_38C1600->serial_number_word1 =
12143                             adv_dvc_varp->cfg->serial1;
12144                         ep_38C1600->serial_number_word2 =
12145                             adv_dvc_varp->cfg->serial2;
12146                         ep_38C1600->serial_number_word3 =
12147                             adv_dvc_varp->cfg->serial3;
12148                 }
12149
12150                 /*
12151                  * Set the adapter's target id bit in the 'init_tidmask' field.
12152                  */
12153                 boardp->init_tidmask |=
12154                     ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
12155         }
12156
12157         /*
12158          * Channels are numbered beginning with 0. For AdvanSys one host
12159          * structure supports one channel. Multi-channel boards have a
12160          * separate host structure for each channel.
12161          */
12162         shost->max_channel = 0;
12163         if (ASC_NARROW_BOARD(boardp)) {
12164                 shost->max_id = ASC_MAX_TID + 1;
12165                 shost->max_lun = ASC_MAX_LUN + 1;
12166                 shost->max_cmd_len = ASC_MAX_CDB_LEN;
12167
12168                 shost->io_port = asc_dvc_varp->iop_base;
12169                 boardp->asc_n_io_port = ASC_IOADR_GAP;
12170                 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
12171
12172                 /* Set maximum number of queues the adapter can handle. */
12173                 shost->can_queue = asc_dvc_varp->max_total_qng;
12174         } else {
12175                 shost->max_id = ADV_MAX_TID + 1;
12176                 shost->max_lun = ADV_MAX_LUN + 1;
12177                 shost->max_cmd_len = ADV_MAX_CDB_LEN;
12178
12179                 /*
12180                  * Save the I/O Port address and length even though
12181                  * I/O ports are not used to access Wide boards.
12182                  * Instead the Wide boards are accessed with
12183                  * PCI Memory Mapped I/O.
12184                  */
12185                 shost->io_port = iop;
12186
12187                 shost->this_id = adv_dvc_varp->chip_scsi_id;
12188
12189                 /* Set maximum number of queues the adapter can handle. */
12190                 shost->can_queue = adv_dvc_varp->max_host_qng;
12191         }
12192
12193         /*
12194          * Following v1.3.89, 'cmd_per_lun' is no longer needed
12195          * and should be set to zero.
12196          *
12197          * But because of a bug introduced in v1.3.89 if the driver is
12198          * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
12199          * SCSI function 'allocate_device' will panic. To allow the driver
12200          * to work as a module in these kernels set 'cmd_per_lun' to 1.
12201          *
12202          * Note: This is wrong.  cmd_per_lun should be set to the depth
12203          * you want on untagged devices always.
12204          #ifdef MODULE
12205          */
12206         shost->cmd_per_lun = 1;
12207 /* #else
12208             shost->cmd_per_lun = 0;
12209 #endif */
12210
12211         /*
12212          * Set the maximum number of scatter-gather elements the
12213          * adapter can handle.
12214          */
12215         if (ASC_NARROW_BOARD(boardp)) {
12216                 /*
12217                  * Allow two commands with 'sg_tablesize' scatter-gather
12218                  * elements to be executed simultaneously. This value is
12219                  * the theoretical hardware limit. It may be decreased
12220                  * below.
12221                  */
12222                 shost->sg_tablesize =
12223                     (((asc_dvc_varp->max_total_qng - 2) / 2) *
12224                      ASC_SG_LIST_PER_Q) + 1;
12225         } else {
12226                 shost->sg_tablesize = ADV_MAX_SG_LIST;
12227         }
12228
12229         /*
12230          * The value of 'sg_tablesize' can not exceed the SCSI
12231          * mid-level driver definition of SG_ALL. SG_ALL also
12232          * must not be exceeded, because it is used to define the
12233          * size of the scatter-gather table in 'struct asc_sg_head'.
12234          */
12235         if (shost->sg_tablesize > SG_ALL) {
12236                 shost->sg_tablesize = SG_ALL;
12237         }
12238
12239         ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
12240
12241         /* BIOS start address. */
12242         if (ASC_NARROW_BOARD(boardp)) {
12243                 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
12244                                                     asc_dvc_varp->bus_type);
12245         } else {
12246                 /*
12247                  * Fill-in BIOS board variables. The Wide BIOS saves
12248                  * information in LRAM that is used by the driver.
12249                  */
12250                 AdvReadWordLram(adv_dvc_varp->iop_base,
12251                                 BIOS_SIGNATURE, boardp->bios_signature);
12252                 AdvReadWordLram(adv_dvc_varp->iop_base,
12253                                 BIOS_VERSION, boardp->bios_version);
12254                 AdvReadWordLram(adv_dvc_varp->iop_base,
12255                                 BIOS_CODESEG, boardp->bios_codeseg);
12256                 AdvReadWordLram(adv_dvc_varp->iop_base,
12257                                 BIOS_CODELEN, boardp->bios_codelen);
12258
12259                 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
12260                          boardp->bios_signature, boardp->bios_version);
12261
12262                 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
12263                          boardp->bios_codeseg, boardp->bios_codelen);
12264
12265                 /*
12266                  * If the BIOS saved a valid signature, then fill in
12267                  * the BIOS code segment base address.
12268                  */
12269                 if (boardp->bios_signature == 0x55AA) {
12270                         /*
12271                          * Convert x86 realmode code segment to a linear
12272                          * address by shifting left 4.
12273                          */
12274                         shost->base = ((ulong)boardp->bios_codeseg << 4);
12275                 } else {
12276                         shost->base = 0;
12277                 }
12278         }
12279
12280         /*
12281          * Register Board Resources - I/O Port, DMA, IRQ
12282          */
12283
12284         /* Register DMA Channel for Narrow boards. */
12285         shost->dma_channel = NO_ISA_DMA;        /* Default to no ISA DMA. */
12286 #ifdef CONFIG_ISA
12287         if (ASC_NARROW_BOARD(boardp)) {
12288                 /* Register DMA channel for ISA bus. */
12289                 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
12290                         shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
12291                         ret = request_dma(shost->dma_channel, DRV_NAME);
12292                         if (ret) {
12293                                 shost_printk(KERN_ERR, shost, "request_dma() "
12294                                                 "%d failed %d\n",
12295                                                 shost->dma_channel, ret);
12296                                 goto err_free_proc;
12297                         }
12298                         AscEnableIsaDma(shost->dma_channel);
12299                 }
12300         }
12301 #endif /* CONFIG_ISA */
12302
12303         /* Register IRQ Number. */
12304         ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
12305
12306         ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
12307                           DRV_NAME, shost);
12308
12309         if (ret) {
12310                 if (ret == -EBUSY) {
12311                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
12312                                         "already in use\n", boardp->irq);
12313                 } else if (ret == -EINVAL) {
12314                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
12315                                         "not valid\n", boardp->irq);
12316                 } else {
12317                         shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
12318                                         "failed with %d\n", boardp->irq, ret);
12319                 }
12320                 goto err_free_dma;
12321         }
12322
12323         /*
12324          * Initialize board RISC chip and enable interrupts.
12325          */
12326         if (ASC_NARROW_BOARD(boardp)) {
12327                 ASC_DBG(2, "AscInitAsc1000Driver()\n");
12328
12329                 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
12330                 if (!asc_dvc_varp->overrun_buf) {
12331                         ret = -ENOMEM;
12332                         goto err_free_irq;
12333                 }
12334                 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
12335
12336                 if (warn_code || asc_dvc_varp->err_code) {
12337                         shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
12338                                         "warn 0x%x, error 0x%x\n",
12339                                         asc_dvc_varp->init_state, warn_code,
12340                                         asc_dvc_varp->err_code);
12341                         if (!asc_dvc_varp->overrun_dma) {
12342                                 ret = -ENODEV;
12343                                 goto err_free_mem;
12344                         }
12345                 }
12346         } else {
12347                 if (advansys_wide_init_chip(shost)) {
12348                         ret = -ENODEV;
12349                         goto err_free_mem;
12350                 }
12351         }
12352
12353         ASC_DBG_PRT_SCSI_HOST(2, shost);
12354
12355         ret = scsi_add_host(shost, boardp->dev);
12356         if (ret)
12357                 goto err_free_mem;
12358
12359         scsi_scan_host(shost);
12360         return 0;
12361
12362  err_free_mem:
12363         if (ASC_NARROW_BOARD(boardp)) {
12364                 if (asc_dvc_varp->overrun_dma)
12365                         dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
12366                                          ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
12367                 kfree(asc_dvc_varp->overrun_buf);
12368         } else
12369                 advansys_wide_free_mem(boardp);
12370  err_free_irq:
12371         free_irq(boardp->irq, shost);
12372  err_free_dma:
12373 #ifdef CONFIG_ISA
12374         if (shost->dma_channel != NO_ISA_DMA)
12375                 free_dma(shost->dma_channel);
12376 #endif
12377  err_free_proc:
12378         kfree(boardp->prtbuf);
12379  err_unmap:
12380         if (boardp->ioremap_addr)
12381                 iounmap(boardp->ioremap_addr);
12382  err_shost:
12383         return ret;
12384 }
12385
12386 /*
12387  * advansys_release()
12388  *
12389  * Release resources allocated for a single AdvanSys adapter.
12390  */
12391 static int advansys_release(struct Scsi_Host *shost)
12392 {
12393         struct asc_board *board = shost_priv(shost);
12394         ASC_DBG(1, "begin\n");
12395         scsi_remove_host(shost);
12396         free_irq(board->irq, shost);
12397 #ifdef CONFIG_ISA
12398         if (shost->dma_channel != NO_ISA_DMA) {
12399                 ASC_DBG(1, "free_dma()\n");
12400                 free_dma(shost->dma_channel);
12401         }
12402 #endif
12403         if (ASC_NARROW_BOARD(board)) {
12404                 dma_unmap_single(board->dev,
12405                                         board->dvc_var.asc_dvc_var.overrun_dma,
12406                                         ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
12407                 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
12408         } else {
12409                 iounmap(board->ioremap_addr);
12410                 advansys_wide_free_mem(board);
12411         }
12412         kfree(board->prtbuf);
12413         scsi_host_put(shost);
12414         ASC_DBG(1, "end\n");
12415         return 0;
12416 }
12417
12418 #define ASC_IOADR_TABLE_MAX_IX  11
12419
12420 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
12421         0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
12422         0x0210, 0x0230, 0x0250, 0x0330
12423 };
12424
12425 /*
12426  * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw.  It decodes as:
12427  * 00: 10
12428  * 01: 11
12429  * 10: 12
12430  * 11: 15
12431  */
12432 static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base)
12433 {
12434         unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
12435         unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
12436         if (chip_irq == 13)
12437                 chip_irq = 15;
12438         return chip_irq;
12439 }
12440
12441 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
12442 {
12443         int err = -ENODEV;
12444         PortAddr iop_base = _asc_def_iop_base[id];
12445         struct Scsi_Host *shost;
12446         struct asc_board *board;
12447
12448         if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
12449                 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
12450                 return -ENODEV;
12451         }
12452         ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
12453         if (!AscFindSignature(iop_base))
12454                 goto release_region;
12455         if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
12456                 goto release_region;
12457
12458         err = -ENOMEM;
12459         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12460         if (!shost)
12461                 goto release_region;
12462
12463         board = shost_priv(shost);
12464         board->irq = advansys_isa_irq_no(iop_base);
12465         board->dev = dev;
12466
12467         err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
12468         if (err)
12469                 goto free_host;
12470
12471         dev_set_drvdata(dev, shost);
12472         return 0;
12473
12474  free_host:
12475         scsi_host_put(shost);
12476  release_region:
12477         release_region(iop_base, ASC_IOADR_GAP);
12478         return err;
12479 }
12480
12481 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
12482 {
12483         int ioport = _asc_def_iop_base[id];
12484         advansys_release(dev_get_drvdata(dev));
12485         release_region(ioport, ASC_IOADR_GAP);
12486         return 0;
12487 }
12488
12489 static struct isa_driver advansys_isa_driver = {
12490         .probe          = advansys_isa_probe,
12491         .remove         = __devexit_p(advansys_isa_remove),
12492         .driver = {
12493                 .owner  = THIS_MODULE,
12494                 .name   = DRV_NAME,
12495         },
12496 };
12497
12498 /*
12499  * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw.  It decodes as:
12500  * 000: invalid
12501  * 001: 10
12502  * 010: 11
12503  * 011: 12
12504  * 100: invalid
12505  * 101: 14
12506  * 110: 15
12507  * 111: invalid
12508  */
12509 static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base)
12510 {
12511         unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
12512         unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
12513         if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
12514                 return 0;
12515         return chip_irq;
12516 }
12517
12518 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
12519 {
12520         int err = -ENODEV;
12521         PortAddr iop_base = _asc_def_iop_base[id];
12522         struct Scsi_Host *shost;
12523         struct asc_board *board;
12524
12525         if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
12526                 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
12527                 return -ENODEV;
12528         }
12529         ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
12530         if (!AscFindSignature(iop_base))
12531                 goto release_region;
12532         /*
12533          * I don't think this condition can actually happen, but the old
12534          * driver did it, and the chances of finding a VLB setup in 2007
12535          * to do testing with is slight to none.
12536          */
12537         if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
12538                 goto release_region;
12539
12540         err = -ENOMEM;
12541         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12542         if (!shost)
12543                 goto release_region;
12544
12545         board = shost_priv(shost);
12546         board->irq = advansys_vlb_irq_no(iop_base);
12547         board->dev = dev;
12548
12549         err = advansys_board_found(shost, iop_base, ASC_IS_VL);
12550         if (err)
12551                 goto free_host;
12552
12553         dev_set_drvdata(dev, shost);
12554         return 0;
12555
12556  free_host:
12557         scsi_host_put(shost);
12558  release_region:
12559         release_region(iop_base, ASC_IOADR_GAP);
12560         return -ENODEV;
12561 }
12562
12563 static struct isa_driver advansys_vlb_driver = {
12564         .probe          = advansys_vlb_probe,
12565         .remove         = __devexit_p(advansys_isa_remove),
12566         .driver = {
12567                 .owner  = THIS_MODULE,
12568                 .name   = "advansys_vlb",
12569         },
12570 };
12571
12572 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
12573         { "ABP7401" },
12574         { "ABP7501" },
12575         { "" }
12576 };
12577
12578 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
12579
12580 /*
12581  * EISA is a little more tricky than PCI; each EISA device may have two
12582  * channels, and this driver is written to make each channel its own Scsi_Host
12583  */
12584 struct eisa_scsi_data {
12585         struct Scsi_Host *host[2];
12586 };
12587
12588 /*
12589  * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw.  It decodes as:
12590  * 000: 10
12591  * 001: 11
12592  * 010: 12
12593  * 011: invalid
12594  * 100: 14
12595  * 101: 15
12596  * 110: invalid
12597  * 111: invalid
12598  */
12599 static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev)
12600 {
12601         unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
12602         unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
12603         if ((chip_irq == 13) || (chip_irq > 15))
12604                 return 0;
12605         return chip_irq;
12606 }
12607
12608 static int __devinit advansys_eisa_probe(struct device *dev)
12609 {
12610         int i, ioport, irq = 0;
12611         int err;
12612         struct eisa_device *edev = to_eisa_device(dev);
12613         struct eisa_scsi_data *data;
12614
12615         err = -ENOMEM;
12616         data = kzalloc(sizeof(*data), GFP_KERNEL);
12617         if (!data)
12618                 goto fail;
12619         ioport = edev->base_addr + 0xc30;
12620
12621         err = -ENODEV;
12622         for (i = 0; i < 2; i++, ioport += 0x20) {
12623                 struct asc_board *board;
12624                 struct Scsi_Host *shost;
12625                 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
12626                         printk(KERN_WARNING "Region %x-%x busy\n", ioport,
12627                                ioport + ASC_IOADR_GAP - 1);
12628                         continue;
12629                 }
12630                 if (!AscFindSignature(ioport)) {
12631                         release_region(ioport, ASC_IOADR_GAP);
12632                         continue;
12633                 }
12634
12635                 /*
12636                  * I don't know why we need to do this for EISA chips, but
12637                  * not for any others.  It looks to be equivalent to
12638                  * AscGetChipCfgMsw, but I may have overlooked something,
12639                  * so I'm not converting it until I get an EISA board to
12640                  * test with.
12641                  */
12642                 inw(ioport + 4);
12643
12644                 if (!irq)
12645                         irq = advansys_eisa_irq_no(edev);
12646
12647                 err = -ENOMEM;
12648                 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12649                 if (!shost)
12650                         goto release_region;
12651
12652                 board = shost_priv(shost);
12653                 board->irq = irq;
12654                 board->dev = dev;
12655
12656                 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
12657                 if (!err) {
12658                         data->host[i] = shost;
12659                         continue;
12660                 }
12661
12662                 scsi_host_put(shost);
12663  release_region:
12664                 release_region(ioport, ASC_IOADR_GAP);
12665                 break;
12666         }
12667
12668         if (err)
12669                 goto free_data;
12670         dev_set_drvdata(dev, data);
12671         return 0;
12672
12673  free_data:
12674         kfree(data->host[0]);
12675         kfree(data->host[1]);
12676         kfree(data);
12677  fail:
12678         return err;
12679 }
12680
12681 static __devexit int advansys_eisa_remove(struct device *dev)
12682 {
12683         int i;
12684         struct eisa_scsi_data *data = dev_get_drvdata(dev);
12685
12686         for (i = 0; i < 2; i++) {
12687                 int ioport;
12688                 struct Scsi_Host *shost = data->host[i];
12689                 if (!shost)
12690                         continue;
12691                 ioport = shost->io_port;
12692                 advansys_release(shost);
12693                 release_region(ioport, ASC_IOADR_GAP);
12694         }
12695
12696         kfree(data);
12697         return 0;
12698 }
12699
12700 static struct eisa_driver advansys_eisa_driver = {
12701         .id_table =             advansys_eisa_table,
12702         .driver = {
12703                 .name =         DRV_NAME,
12704                 .probe =        advansys_eisa_probe,
12705                 .remove =       __devexit_p(advansys_eisa_remove),
12706         }
12707 };
12708
12709 /* PCI Devices supported by this driver */
12710 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
12711         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12712          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12713         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12714          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12715         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12716          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12717         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12718          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12719         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12720          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12721         {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12722          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12723         {}
12724 };
12725
12726 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12727
12728 static void __devinit advansys_set_latency(struct pci_dev *pdev)
12729 {
12730         if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12731             (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12732                 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12733         } else {
12734                 u8 latency;
12735                 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12736                 if (latency < 0x20)
12737                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12738         }
12739 }
12740
12741 static int __devinit
12742 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
12743 {
12744         int err, ioport;
12745         struct Scsi_Host *shost;
12746         struct asc_board *board;
12747
12748         err = pci_enable_device(pdev);
12749         if (err)
12750                 goto fail;
12751         err = pci_request_regions(pdev, DRV_NAME);
12752         if (err)
12753                 goto disable_device;
12754         pci_set_master(pdev);
12755         advansys_set_latency(pdev);
12756
12757         err = -ENODEV;
12758         if (pci_resource_len(pdev, 0) == 0)
12759                 goto release_region;
12760
12761         ioport = pci_resource_start(pdev, 0);
12762
12763         err = -ENOMEM;
12764         shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12765         if (!shost)
12766                 goto release_region;
12767
12768         board = shost_priv(shost);
12769         board->irq = pdev->irq;
12770         board->dev = &pdev->dev;
12771
12772         if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12773             pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12774             pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12775                 board->flags |= ASC_IS_WIDE_BOARD;
12776         }
12777
12778         err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12779         if (err)
12780                 goto free_host;
12781
12782         pci_set_drvdata(pdev, shost);
12783         return 0;
12784
12785  free_host:
12786         scsi_host_put(shost);
12787  release_region:
12788         pci_release_regions(pdev);
12789  disable_device:
12790         pci_disable_device(pdev);
12791  fail:
12792         return err;
12793 }
12794
12795 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
12796 {
12797         advansys_release(pci_get_drvdata(pdev));
12798         pci_release_regions(pdev);
12799         pci_disable_device(pdev);
12800 }
12801
12802 static struct pci_driver advansys_pci_driver = {
12803         .name =         DRV_NAME,
12804         .id_table =     advansys_pci_tbl,
12805         .probe =        advansys_pci_probe,
12806         .remove =       __devexit_p(advansys_pci_remove),
12807 };
12808
12809 static int __init advansys_init(void)
12810 {
12811         int error;
12812
12813         error = isa_register_driver(&advansys_isa_driver,
12814                                     ASC_IOADR_TABLE_MAX_IX);
12815         if (error)
12816                 goto fail;
12817
12818         error = isa_register_driver(&advansys_vlb_driver,
12819                                     ASC_IOADR_TABLE_MAX_IX);
12820         if (error)
12821                 goto unregister_isa;
12822
12823         error = eisa_driver_register(&advansys_eisa_driver);
12824         if (error)
12825                 goto unregister_vlb;
12826
12827         error = pci_register_driver(&advansys_pci_driver);
12828         if (error)
12829                 goto unregister_eisa;
12830
12831         return 0;
12832
12833  unregister_eisa:
12834         eisa_driver_unregister(&advansys_eisa_driver);
12835  unregister_vlb:
12836         isa_unregister_driver(&advansys_vlb_driver);
12837  unregister_isa:
12838         isa_unregister_driver(&advansys_isa_driver);
12839  fail:
12840         return error;
12841 }
12842
12843 static void __exit advansys_exit(void)
12844 {
12845         pci_unregister_driver(&advansys_pci_driver);
12846         eisa_driver_unregister(&advansys_eisa_driver);
12847         isa_unregister_driver(&advansys_vlb_driver);
12848         isa_unregister_driver(&advansys_isa_driver);
12849 }
12850
12851 module_init(advansys_init);
12852 module_exit(advansys_exit);
12853
12854 MODULE_LICENSE("GPL");
12855 MODULE_FIRMWARE("advansys/mcode.bin");
12856 MODULE_FIRMWARE("advansys/3550.bin");
12857 MODULE_FIRMWARE("advansys/38C0800.bin");
12858 MODULE_FIRMWARE("advansys/38C1600.bin");