| blob | e62be83796044876d6708a8f960ce554c0dfbecc |
1 /*
2 * Exception handling for Microblaze
3 *
4 * Rewriten interrupt handling
5 *
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
8 *
9 * uClinux customisation (C) 2005 John Williams
10 *
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
15 * Rewritten for PReP
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
30 *
31 * Original code
32 * Copyright (C) 2004 Xilinx, Inc.
33 *
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
37 */
39 /*
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
47 *
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
50 * - Unalignment
51 * - Instruction bus error
52 * - Data bus error
53 * - Illegal instruction opcode
54 * - Divide-by-zero
55 *
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
61 *
62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
64 * exceptions. JW
65 */
67 #include <asm/exceptions.h>
68 #include <asm/unistd.h>
69 #include <asm/page.h>
71 #include <asm/entry.h>
72 #include <asm/current.h>
73 #include <linux/linkage.h>
75 #include <asm/mmu.h>
76 #include <asm/pgtable.h>
77 #include <asm/signal.h>
78 #include <asm/asm-offsets.h>
80 #undef DEBUG
82 /* Helpful Macros */
83 #define NUM_TO_REG(num) r ## num
85 #ifdef CONFIG_MMU
86 #define RESTORE_STATE \
87 lwi r5, r1, 0; \
88 mts rmsr, r5; \
89 nop; \
90 lwi r3, r1, PT_R3; \
91 lwi r4, r1, PT_R4; \
92 lwi r5, r1, PT_R5; \
93 lwi r6, r1, PT_R6; \
94 lwi r11, r1, PT_R11; \
95 lwi r31, r1, PT_R31; \
96 lwi r1, r1, PT_R1;
97 #endif /* CONFIG_MMU */
99 #define LWREG_NOP \
100 bri ex_handler_unhandled; \
101 nop;
103 #define SWREG_NOP \
104 bri ex_handler_unhandled; \
105 nop;
107 /* FIXME this is weird - for noMMU kernel is not possible to use brid
108 * instruction which can shorten executed time
109 */
111 /* r3 is the source */
112 #define R3_TO_LWREG_V(regnum) \
113 swi r3, r1, 4 * regnum; \
114 bri ex_handler_done;
116 /* r3 is the source */
117 #define R3_TO_LWREG(regnum) \
118 or NUM_TO_REG (regnum), r0, r3; \
119 bri ex_handler_done;
121 /* r3 is the target */
122 #define SWREG_TO_R3_V(regnum) \
123 lwi r3, r1, 4 * regnum; \
124 bri ex_sw_tail;
126 /* r3 is the target */
127 #define SWREG_TO_R3(regnum) \
128 or r3, r0, NUM_TO_REG (regnum); \
129 bri ex_sw_tail;
131 #ifdef CONFIG_MMU
132 #define R3_TO_LWREG_VM_V(regnum) \
133 brid ex_lw_end_vm; \
134 swi r3, r7, 4 * regnum;
136 #define R3_TO_LWREG_VM(regnum) \
137 brid ex_lw_end_vm; \
138 or NUM_TO_REG (regnum), r0, r3;
140 #define SWREG_TO_R3_VM_V(regnum) \
141 brid ex_sw_tail_vm; \
142 lwi r3, r7, 4 * regnum;
144 #define SWREG_TO_R3_VM(regnum) \
145 brid ex_sw_tail_vm; \
146 or r3, r0, NUM_TO_REG (regnum);
148 /* Shift right instruction depending on available configuration */
149 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
150 #define BSRLI(rD, rA, imm) \
151 bsrli rD, rA, imm
152 #else
153 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
154 /* Only the used shift constants defined here - add more if needed */
155 #define BSRLI2(rD, rA) \
156 srl rD, rA; /* << 1 */ \
157 srl rD, rD; /* << 2 */
158 #define BSRLI10(rD, rA) \
159 srl rD, rA; /* << 1 */ \
160 srl rD, rD; /* << 2 */ \
161 srl rD, rD; /* << 3 */ \
162 srl rD, rD; /* << 4 */ \
163 srl rD, rD; /* << 5 */ \
164 srl rD, rD; /* << 6 */ \
165 srl rD, rD; /* << 7 */ \
166 srl rD, rD; /* << 8 */ \
167 srl rD, rD; /* << 9 */ \
168 srl rD, rD /* << 10 */
169 #define BSRLI20(rD, rA) \
170 BSRLI10(rD, rA); \
171 BSRLI10(rD, rD)
172 #endif
173 #endif /* CONFIG_MMU */
175 .extern other_exception_handler /* Defined in exception.c */
177 /*
178 * hw_exception_handler - Handler for exceptions
179 *
180 * Exception handler notes:
181 * - Handles all exceptions
182 * - Does not handle unaligned exceptions during load into r17, r1, r0.
183 * - Does not handle unaligned exceptions during store from r17 (cannot be
184 * done) and r1 (slows down common case)
185 *
186 * Relevant register structures
187 *
188 * EAR - |----|----|----|----|----|----|----|----|
189 * - < ## 32 bit faulting address ## >
190 *
191 * ESR - |----|----|----|----|----| - | - |-----|-----|
192 * - W S REG EXC
193 *
194 *
195 * STACK FRAME STRUCTURE (for NO_MMU)
196 * ---------------------------------
197 *
198 * +-------------+ + 0
199 * | MSR |
200 * +-------------+ + 4
201 * | r1 |
202 * | . |
203 * | . |
204 * | . |
205 * | . |
206 * | r18 |
207 * +-------------+ + 76
208 * | . |
209 * | . |
210 *
211 * MMU kernel uses the same 'pt_pool_space' pointed space
212 * which is used for storing register values - noMMu style was, that values were
213 * stored in stack but in case of failure you lost information about register.
214 * Currently you can see register value in memory in specific place.
215 * In compare to with previous solution the speed should be the same.
216 *
217 * MMU exception handler has different handling compare to no MMU kernel.
218 * Exception handler use jump table for directing of what happen. For MMU kernel
219 * is this approach better because MMU relate exception are handled by asm code
220 * in this file. In compare to with MMU expect of unaligned exception
221 * is everything handled by C code.
222 */
224 /*
225 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
226 * and clobbered so care should be taken to restore them if someone is going to
227 * return from exception
228 */
230 /* wrappers to restore state before coming to entry.S */
231 #ifdef CONFIG_MMU
232 .section .data
233 .align 4
234 pt_pool_space:
235 .space PT_SIZE
237 #ifdef DEBUG
238 /* Create space for exception counting. */
239 .section .data
240 .global exception_debug_table
241 .align 4
242 exception_debug_table:
243 /* Look at exception vector table. There is 32 exceptions * word size */
244 .space (32 * 4)
245 #endif /* DEBUG */
247 .section .rodata
248 .align 4
249 _MB_HW_ExceptionVectorTable:
250 /* 0 - Undefined */
251 .long TOPHYS(ex_handler_unhandled)
252 /* 1 - Unaligned data access exception */
253 .long TOPHYS(handle_unaligned_ex)
254 /* 2 - Illegal op-code exception */
255 .long TOPHYS(full_exception_trapw)
256 /* 3 - Instruction bus error exception */
257 .long TOPHYS(full_exception_trapw)
258 /* 4 - Data bus error exception */
259 .long TOPHYS(full_exception_trapw)
260 /* 5 - Divide by zero exception */
261 .long TOPHYS(full_exception_trapw)
262 /* 6 - Floating point unit exception */
263 .long TOPHYS(full_exception_trapw)
264 /* 7 - Privileged instruction exception */
265 .long TOPHYS(full_exception_trapw)
266 /* 8 - 15 - Undefined */
267 .long TOPHYS(ex_handler_unhandled)
268 .long TOPHYS(ex_handler_unhandled)
269 .long TOPHYS(ex_handler_unhandled)
270 .long TOPHYS(ex_handler_unhandled)
271 .long TOPHYS(ex_handler_unhandled)
272 .long TOPHYS(ex_handler_unhandled)
273 .long TOPHYS(ex_handler_unhandled)
274 .long TOPHYS(ex_handler_unhandled)
275 /* 16 - Data storage exception */
276 .long TOPHYS(handle_data_storage_exception)
277 /* 17 - Instruction storage exception */
278 .long TOPHYS(handle_instruction_storage_exception)
279 /* 18 - Data TLB miss exception */
280 .long TOPHYS(handle_data_tlb_miss_exception)
281 /* 19 - Instruction TLB miss exception */
282 .long TOPHYS(handle_instruction_tlb_miss_exception)
283 /* 20 - 31 - Undefined */
284 .long TOPHYS(ex_handler_unhandled)
285 .long TOPHYS(ex_handler_unhandled)
286 .long TOPHYS(ex_handler_unhandled)
287 .long TOPHYS(ex_handler_unhandled)
288 .long TOPHYS(ex_handler_unhandled)
289 .long TOPHYS(ex_handler_unhandled)
290 .long TOPHYS(ex_handler_unhandled)
291 .long TOPHYS(ex_handler_unhandled)
292 .long TOPHYS(ex_handler_unhandled)
293 .long TOPHYS(ex_handler_unhandled)
294 .long TOPHYS(ex_handler_unhandled)
295 .long TOPHYS(ex_handler_unhandled)
296 #endif
298 .global _hw_exception_handler
299 .section .text
300 .align 4
301 .ent _hw_exception_handler
302 _hw_exception_handler:
303 #ifndef CONFIG_MMU
304 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
305 #else
306 swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */
307 /* Save date to kernel memory. Here is the problem
308 * when you came from user space */
309 ori r1, r0, TOPHYS(pt_pool_space);
310 #endif
311 swi r3, r1, PT_R3
312 swi r4, r1, PT_R4
313 swi r5, r1, PT_R5
314 swi r6, r1, PT_R6
316 #ifdef CONFIG_MMU
317 swi r11, r1, PT_R11
318 swi r31, r1, PT_R31
319 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
320 #endif
322 mfs r5, rmsr;
323 nop
324 swi r5, r1, 0;
325 mfs r4, resr
326 nop
327 mfs r3, rear;
328 nop
330 #ifndef CONFIG_MMU
331 andi r5, r4, 0x1000; /* Check ESR[DS] */
332 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
333 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
334 nop
335 not_in_delay_slot:
336 swi r17, r1, PT_R17
337 #endif
339 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
341 #ifdef CONFIG_MMU
342 /* Calculate exception vector offset = r5 << 2 */
343 addk r6, r5, r5; /* << 1 */
344 addk r6, r6, r6; /* << 2 */
346 #ifdef DEBUG
347 /* counting which exception happen */
348 lwi r5, r0, TOPHYS(exception_debug_table)
349 addi r5, r5, 1
350 swi r5, r0, TOPHYS(exception_debug_table)
351 lwi r5, r6, TOPHYS(exception_debug_table)
352 addi r5, r5, 1
353 swi r5, r6, TOPHYS(exception_debug_table)
354 #endif
355 /* end */
356 /* Load the HW Exception vector */
357 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
358 bra r6
360 full_exception_trapw:
361 RESTORE_STATE
362 bri full_exception_trap
363 #else
364 /* Exceptions enabled here. This will allow nested exceptions */
365 mfs r6, rmsr;
366 nop
367 swi r6, r1, 0; /* RMSR_OFFSET */
368 ori r6, r6, 0x100; /* Turn ON the EE bit */
369 andi r6, r6, ~2; /* Disable interrupts */
370 mts rmsr, r6;
371 nop
373 xori r6, r5, 1; /* 00001 = Unaligned Exception */
374 /* Jump to unalignment exception handler */
375 beqi r6, handle_unaligned_ex;
377 handle_other_ex: /* Handle Other exceptions here */
378 /* Save other volatiles before we make procedure calls below */
379 swi r7, r1, PT_R7
380 swi r8, r1, PT_R8
381 swi r9, r1, PT_R9
382 swi r10, r1, PT_R10
383 swi r11, r1, PT_R11
384 swi r12, r1, PT_R12
385 swi r14, r1, PT_R14
386 swi r15, r1, PT_R15
387 swi r18, r1, PT_R18
389 or r5, r1, r0
390 andi r6, r4, 0x1F; /* Load ESR[EC] */
391 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
392 swi r7, r1, PT_MODE
393 mfs r7, rfsr
394 nop
395 addk r8, r17, r0; /* Load exception address */
396 bralid r15, full_exception; /* Branch to the handler */
397 nop;
398 mts rfsr, r0; /* Clear sticky fsr */
399 nop
401 /*
402 * Trigger execution of the signal handler by enabling
403 * interrupts and calling an invalid syscall.
404 */
405 mfs r5, rmsr;
406 nop
407 ori r5, r5, 2;
408 mts rmsr, r5; /* enable interrupt */
409 nop
410 addi r12, r0, __NR_syscalls;
411 brki r14, 0x08;
412 mfs r5, rmsr; /* disable interrupt */
413 nop
414 andi r5, r5, ~2;
415 mts rmsr, r5;
416 nop
418 lwi r7, r1, PT_R7
419 lwi r8, r1, PT_R8
420 lwi r9, r1, PT_R9
421 lwi r10, r1, PT_R10
422 lwi r11, r1, PT_R11
423 lwi r12, r1, PT_R12
424 lwi r14, r1, PT_R14
425 lwi r15, r1, PT_R15
426 lwi r18, r1, PT_R18
428 bri ex_handler_done; /* Complete exception handling */
429 #endif
431 /* 0x01 - Unaligned data access exception
432 * This occurs when a word access is not aligned on a word boundary,
433 * or when a 16-bit access is not aligned on a 16-bit boundary.
434 * This handler perform the access, and returns, except for MMU when
435 * the unaligned address is last on a 4k page or the physical address is
436 * not found in the page table, in which case unaligned_data_trap is called.
437 */
438 handle_unaligned_ex:
439 /* Working registers already saved: R3, R4, R5, R6
440 * R4 = ESR
441 * R3 = EAR
442 */
443 #ifdef CONFIG_MMU
444 andi r6, r4, 0x1000 /* Check ESR[DS] */
445 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
446 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
447 nop
448 _no_delayslot:
449 /* jump to high level unaligned handler */
450 RESTORE_STATE;
451 bri unaligned_data_trap
452 #endif
453 andi r6, r4, 0x3E0; /* Mask and extract the register operand */
454 srl r6, r6; /* r6 >> 5 */
455 srl r6, r6;
456 srl r6, r6;
457 srl r6, r6;
458 srl r6, r6;
459 /* Store the register operand in a temporary location */
460 sbi r6, r0, TOPHYS(ex_reg_op);
462 andi r6, r4, 0x400; /* Extract ESR[S] */
463 bnei r6, ex_sw;
464 ex_lw:
465 andi r6, r4, 0x800; /* Extract ESR[W] */
466 beqi r6, ex_lhw;
467 lbui r5, r3, 0; /* Exception address in r3 */
468 /* Load a word, byte-by-byte from destination address
469 and save it in tmp space */
470 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
471 lbui r5, r3, 1;
472 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
473 lbui r5, r3, 2;
474 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
475 lbui r5, r3, 3;
476 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
477 /* Get the destination register value into r4 */
478 lwi r4, r0, TOPHYS(ex_tmp_data_loc_0);
479 bri ex_lw_tail;
480 ex_lhw:
481 lbui r5, r3, 0; /* Exception address in r3 */
482 /* Load a half-word, byte-by-byte from destination
483 address and save it in tmp space */
484 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
485 lbui r5, r3, 1;
486 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
487 /* Get the destination register value into r4 */
488 lhui r4, r0, TOPHYS(ex_tmp_data_loc_0);
489 ex_lw_tail:
490 /* Get the destination register number into r5 */
491 lbui r5, r0, TOPHYS(ex_reg_op);
492 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
493 addik r6, r0, TOPHYS(lw_table);
494 addk r5, r5, r5;
495 addk r5, r5, r5;
496 addk r5, r5, r5;
497 addk r5, r5, r6;
498 bra r5;
499 ex_lw_end: /* Exception handling of load word, ends */
500 ex_sw:
501 /* Get the destination register number into r5 */
502 lbui r5, r0, TOPHYS(ex_reg_op);
503 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
504 addik r6, r0, TOPHYS(sw_table);
505 add r5, r5, r5;
506 add r5, r5, r5;
507 add r5, r5, r5;
508 add r5, r5, r6;
509 bra r5;
510 ex_sw_tail:
511 mfs r6, resr;
512 nop
513 andi r6, r6, 0x800; /* Extract ESR[W] */
514 beqi r6, ex_shw;
515 /* Get the word - delay slot */
516 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
517 /* Store the word, byte-by-byte into destination address */
518 lbui r4, r0, TOPHYS(ex_tmp_data_loc_0);
519 sbi r4, r3, 0;
520 lbui r4, r0, TOPHYS(ex_tmp_data_loc_1);
521 sbi r4, r3, 1;
522 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
523 sbi r4, r3, 2;
524 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
525 sbi r4, r3, 3;
526 bri ex_handler_done;
528 ex_shw:
529 /* Store the lower half-word, byte-by-byte into destination address */
530 swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
531 lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
532 sbi r4, r3, 0;
533 lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
534 sbi r4, r3, 1;
535 ex_sw_end: /* Exception handling of store word, ends. */
537 ex_handler_done:
538 #ifndef CONFIG_MMU
539 lwi r5, r1, 0 /* RMSR */
540 mts rmsr, r5
541 nop
542 lwi r3, r1, PT_R3
543 lwi r4, r1, PT_R4
544 lwi r5, r1, PT_R5
545 lwi r6, r1, PT_R6
546 lwi r17, r1, PT_R17
548 rted r17, 0
549 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
550 #else
551 RESTORE_STATE;
552 rted r17, 0
553 nop
554 #endif
556 #ifdef CONFIG_MMU
557 /* Exception vector entry code. This code runs with address translation
558 * turned off (i.e. using physical addresses). */
560 /* Exception vectors. */
562 /* 0x10 - Data Storage Exception
563 * This happens for just a few reasons. U0 set (but we don't do that),
564 * or zone protection fault (user violation, write to protected page).
565 * If this is just an update of modified status, we do that quickly
566 * and exit. Otherwise, we call heavyweight functions to do the work.
567 */
568 handle_data_storage_exception:
569 /* Working registers already saved: R3, R4, R5, R6
570 * R3 = ESR
571 */
572 mfs r11, rpid
573 nop
574 /* If we are faulting a kernel address, we have to use the
575 * kernel page tables.
576 */
577 ori r5, r0, CONFIG_KERNEL_START
578 cmpu r5, r3, r5
579 bgti r5, ex3
580 /* First, check if it was a zone fault (which means a user
581 * tried to access a kernel or read-protected page - always
582 * a SEGV). All other faults here must be stores, so no
583 * need to check ESR_S as well. */
584 andi r4, r4, 0x800 /* ESR_Z - zone protection */
585 bnei r4, ex2
587 ori r4, r0, swapper_pg_dir
588 mts rpid, r0 /* TLB will have 0 TID */
589 nop
590 bri ex4
592 /* Get the PGD for the current thread. */
593 ex3:
594 /* First, check if it was a zone fault (which means a user
595 * tried to access a kernel or read-protected page - always
596 * a SEGV). All other faults here must be stores, so no
597 * need to check ESR_S as well. */
598 andi r4, r4, 0x800 /* ESR_Z */
599 bnei r4, ex2
600 /* get current task address */
601 addi r4 ,CURRENT_TASK, TOPHYS(0);
602 lwi r4, r4, TASK_THREAD+PGDIR
603 ex4:
604 tophys(r4,r4)
605 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
606 andi r5, r5, 0xffc
607 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
608 or r4, r4, r5
609 lwi r4, r4, 0 /* Get L1 entry */
610 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
611 beqi r5, ex2 /* Bail if no table */
613 tophys(r5,r5)
614 BSRLI(r6,r3,10) /* Compute PTE address */
615 andi r6, r6, 0xffc
616 andi r5, r5, 0xfffff003
617 or r5, r5, r6
618 lwi r4, r5, 0 /* Get Linux PTE */
620 andi r6, r4, _PAGE_RW /* Is it writeable? */
621 beqi r6, ex2 /* Bail if not */
623 /* Update 'changed' */
624 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
625 swi r4, r5, 0 /* Update Linux page table */
627 /* Most of the Linux PTE is ready to load into the TLB LO.
628 * We set ZSEL, where only the LS-bit determines user access.
629 * We set execute, because we don't have the granularity to
630 * properly set this at the page level (Linux problem).
631 * If shared is set, we cause a zero PID->TID load.
632 * Many of these bits are software only. Bits we don't set
633 * here we (properly should) assume have the appropriate value.
634 */
635 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
636 ori r4, r4, _PAGE_HWEXEC /* make it executable */
638 /* find the TLB index that caused the fault. It has to be here*/
639 mts rtlbsx, r3
640 nop
641 mfs r5, rtlbx /* DEBUG: TBD */
642 nop
643 mts rtlblo, r4 /* Load TLB LO */
644 nop
645 /* Will sync shadow TLBs */
647 /* Done...restore registers and get out of here. */
648 mts rpid, r11
649 nop
650 bri 4
652 RESTORE_STATE;
653 rted r17, 0
654 nop
655 ex2:
656 /* The bailout. Restore registers to pre-exception conditions
657 * and call the heavyweights to help us out. */
658 mts rpid, r11
659 nop
660 bri 4
661 RESTORE_STATE;
662 bri page_fault_data_trap
665 /* 0x11 - Instruction Storage Exception
666 * This is caused by a fetch from non-execute or guarded pages. */
667 handle_instruction_storage_exception:
668 /* Working registers already saved: R3, R4, R5, R6
669 * R3 = ESR
670 */
672 RESTORE_STATE;
673 bri page_fault_instr_trap
675 /* 0x12 - Data TLB Miss Exception
676 * As the name implies, translation is not in the MMU, so search the
677 * page tables and fix it. The only purpose of this function is to
678 * load TLB entries from the page table if they exist.
679 */
680 handle_data_tlb_miss_exception:
681 /* Working registers already saved: R3, R4, R5, R6
682 * R3 = EAR, R4 = ESR
683 */
684 mfs r11, rpid
685 nop
687 /* If we are faulting a kernel address, we have to use the
688 * kernel page tables. */
689 ori r6, r0, CONFIG_KERNEL_START
690 cmpu r4, r3, r6
691 bgti r4, ex5
692 ori r4, r0, swapper_pg_dir
693 mts rpid, r0 /* TLB will have 0 TID */
694 nop
695 bri ex6
697 /* Get the PGD for the current thread. */
698 ex5:
699 /* get current task address */
700 addi r4 ,CURRENT_TASK, TOPHYS(0);
701 lwi r4, r4, TASK_THREAD+PGDIR
702 ex6:
703 tophys(r4,r4)
704 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
705 andi r5, r5, 0xffc
706 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
707 or r4, r4, r5
708 lwi r4, r4, 0 /* Get L1 entry */
709 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
710 beqi r5, ex7 /* Bail if no table */
712 tophys(r5,r5)
713 BSRLI(r6,r3,10) /* Compute PTE address */
714 andi r6, r6, 0xffc
715 andi r5, r5, 0xfffff003
716 or r5, r5, r6
717 lwi r4, r5, 0 /* Get Linux PTE */
719 andi r6, r4, _PAGE_PRESENT
720 beqi r6, ex7
722 ori r4, r4, _PAGE_ACCESSED
723 swi r4, r5, 0
725 /* Most of the Linux PTE is ready to load into the TLB LO.
726 * We set ZSEL, where only the LS-bit determines user access.
727 * We set execute, because we don't have the granularity to
728 * properly set this at the page level (Linux problem).
729 * If shared is set, we cause a zero PID->TID load.
730 * Many of these bits are software only. Bits we don't set
731 * here we (properly should) assume have the appropriate value.
732 */
733 brid finish_tlb_load
734 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
735 ex7:
736 /* The bailout. Restore registers to pre-exception conditions
737 * and call the heavyweights to help us out.
738 */
739 mts rpid, r11
740 nop
741 bri 4
742 RESTORE_STATE;
743 bri page_fault_data_trap
745 /* 0x13 - Instruction TLB Miss Exception
746 * Nearly the same as above, except we get our information from
747 * different registers and bailout to a different point.
748 */
749 handle_instruction_tlb_miss_exception:
750 /* Working registers already saved: R3, R4, R5, R6
751 * R3 = ESR
752 */
753 mfs r11, rpid
754 nop
756 /* If we are faulting a kernel address, we have to use the
757 * kernel page tables.
758 */
759 ori r4, r0, CONFIG_KERNEL_START
760 cmpu r4, r3, r4
761 bgti r4, ex8
762 ori r4, r0, swapper_pg_dir
763 mts rpid, r0 /* TLB will have 0 TID */
764 nop
765 bri ex9
767 /* Get the PGD for the current thread. */
768 ex8:
769 /* get current task address */
770 addi r4 ,CURRENT_TASK, TOPHYS(0);
771 lwi r4, r4, TASK_THREAD+PGDIR
772 ex9:
773 tophys(r4,r4)
774 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
775 andi r5, r5, 0xffc
776 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
777 or r4, r4, r5
778 lwi r4, r4, 0 /* Get L1 entry */
779 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
780 beqi r5, ex10 /* Bail if no table */
782 tophys(r5,r5)
783 BSRLI(r6,r3,10) /* Compute PTE address */
784 andi r6, r6, 0xffc
785 andi r5, r5, 0xfffff003
786 or r5, r5, r6
787 lwi r4, r5, 0 /* Get Linux PTE */
789 andi r6, r4, _PAGE_PRESENT
790 beqi r6, ex10
792 ori r4, r4, _PAGE_ACCESSED
793 swi r4, r5, 0
795 /* Most of the Linux PTE is ready to load into the TLB LO.
796 * We set ZSEL, where only the LS-bit determines user access.
797 * We set execute, because we don't have the granularity to
798 * properly set this at the page level (Linux problem).
799 * If shared is set, we cause a zero PID->TID load.
800 * Many of these bits are software only. Bits we don't set
801 * here we (properly should) assume have the appropriate value.
802 */
803 brid finish_tlb_load
804 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
805 ex10:
806 /* The bailout. Restore registers to pre-exception conditions
807 * and call the heavyweights to help us out.
808 */
809 mts rpid, r11
810 nop
811 bri 4
812 RESTORE_STATE;
813 bri page_fault_instr_trap
815 /* Both the instruction and data TLB miss get to this point to load the TLB.
816 * r3 - EA of fault
817 * r4 - TLB LO (info from Linux PTE)
818 * r5, r6 - available to use
819 * PID - loaded with proper value when we get here
820 * Upon exit, we reload everything and RFI.
821 * A common place to load the TLB.
822 */
823 tlb_index:
824 .long 1 /* MS: storing last used tlb index */
825 finish_tlb_load:
826 /* MS: load the last used TLB index. */
827 lwi r5, r0, TOPHYS(tlb_index)
828 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
830 /* MS: FIXME this is potential fault, because this is mask not count */
831 andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
832 ori r6, r0, 1
833 cmp r31, r5, r6
834 blti r31, ex12
835 addik r5, r6, 1
836 ex12:
837 /* MS: save back current TLB index */
838 swi r5, r0, TOPHYS(tlb_index)
840 ori r4, r4, _PAGE_HWEXEC /* make it executable */
841 mts rtlbx, r5 /* MS: save current TLB */
842 nop
843 mts rtlblo, r4 /* MS: save to TLB LO */
844 nop
846 /* Create EPN. This is the faulting address plus a static
847 * set of bits. These are size, valid, E, U0, and ensure
848 * bits 20 and 21 are zero.
849 */
850 andi r3, r3, 0xfffff000
851 ori r3, r3, 0x0c0
852 mts rtlbhi, r3 /* Load TLB HI */
853 nop
855 /* Done...restore registers and get out of here. */
856 mts rpid, r11
857 nop
858 bri 4
859 RESTORE_STATE;
860 rted r17, 0
861 nop
863 /* extern void giveup_fpu(struct task_struct *prev)
864 *
865 * The MicroBlaze processor may have an FPU, so this should not just
866 * return: TBD.
867 */
868 .globl giveup_fpu;
869 .align 4;
870 giveup_fpu:
871 bralid r15,0 /* TBD */
872 nop
874 /* At present, this routine just hangs. - extern void abort(void) */
875 .globl abort;
876 .align 4;
877 abort:
878 br r0
880 .globl set_context;
881 .align 4;
882 set_context:
883 mts rpid, r5 /* Shadow TLBs are automatically */
884 nop
885 bri 4 /* flushed by changing PID */
886 rtsd r15,8
887 nop
889 #endif
890 .end _hw_exception_handler
892 #ifdef CONFIG_MMU
893 /* Unaligned data access exception last on a 4k page for MMU.
894 * When this is called, we are in virtual mode with exceptions enabled
895 * and registers 1-13,15,17,18 saved.
896 *
897 * R3 = ESR
898 * R4 = EAR
899 * R7 = pointer to saved registers (struct pt_regs *regs)
900 *
901 * This handler perform the access, and returns via ret_from_exc.
902 */
903 .global _unaligned_data_exception
904 .ent _unaligned_data_exception
905 _unaligned_data_exception:
906 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
907 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
908 andi r6, r3, 0x400; /* Extract ESR[S] */
909 bneid r6, ex_sw_vm;
910 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
911 ex_lw_vm:
912 beqid r6, ex_lhw_vm;
913 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
914 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
915 addik r6, r0, ex_tmp_data_loc_0;
916 sbi r5, r6, 0;
917 load2: lbui r5, r4, 1;
918 sbi r5, r6, 1;
919 load3: lbui r5, r4, 2;
920 sbi r5, r6, 2;
921 load4: lbui r5, r4, 3;
922 sbi r5, r6, 3;
923 brid ex_lw_tail_vm;
924 /* Get the destination register value into r3 - delay slot */
925 lwi r3, r6, 0;
926 ex_lhw_vm:
927 /* Load a half-word, byte-by-byte from destination address and
928 * save it in tmp space */
929 addik r6, r0, ex_tmp_data_loc_0;
930 sbi r5, r6, 0;
931 load5: lbui r5, r4, 1;
932 sbi r5, r6, 1;
933 lhui r3, r6, 0; /* Get the destination register value into r3 */
934 ex_lw_tail_vm:
935 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
936 addik r5, r8, lw_table_vm;
937 bra r5;
938 ex_lw_end_vm: /* Exception handling of load word, ends */
939 brai ret_from_exc;
940 ex_sw_vm:
941 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
942 addik r5, r8, sw_table_vm;
943 bra r5;
944 ex_sw_tail_vm:
945 addik r5, r0, ex_tmp_data_loc_0;
946 beqid r6, ex_shw_vm;
947 swi r3, r5, 0; /* Get the word - delay slot */
948 /* Store the word, byte-by-byte into destination address */
949 lbui r3, r5, 0;
950 store1: sbi r3, r4, 0;
951 lbui r3, r5, 1;
952 store2: sbi r3, r4, 1;
953 lbui r3, r5, 2;
954 store3: sbi r3, r4, 2;
955 lbui r3, r5, 3;
956 brid ret_from_exc;
957 store4: sbi r3, r4, 3; /* Delay slot */
958 ex_shw_vm:
959 /* Store the lower half-word, byte-by-byte into destination address */
960 #ifdef __MICROBLAZEEL__
961 lbui r3, r5, 0;
962 store5: sbi r3, r4, 0;
963 lbui r3, r5, 1;
964 brid ret_from_exc;
965 store6: sbi r3, r4, 1; /* Delay slot */
966 #else
967 lbui r3, r5, 2;
968 store5: sbi r3, r4, 0;
969 lbui r3, r5, 3;
970 brid ret_from_exc;
971 store6: sbi r3, r4, 1; /* Delay slot */
972 #endif
974 ex_sw_end_vm: /* Exception handling of store word, ends. */
976 /* We have to prevent cases that get/put_user macros get unaligned pointer
977 * to bad page area. We have to find out which origin instruction caused it
978 * and called fixup for that origin instruction not instruction in unaligned
979 * handler */
980 ex_unaligned_fixup:
981 ori r5, r7, 0 /* setup pointer to pt_regs */
982 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
983 addik r6, r6, -4 /* for finding proper fixup */
984 swi r6, r7, PT_PC; /* a save back it to PT_PC */
985 addik r7, r0, SIGSEGV
986 /* call bad_page_fault for finding aligned fixup, fixup address is saved
987 * in PT_PC which is used as return address from exception */
988 addik r15, r0, ret_from_exc-8 /* setup return address */
989 brid bad_page_fault
990 nop
992 /* We prevent all load/store because it could failed any attempt to access */
993 .section __ex_table,"a";
994 .word load1,ex_unaligned_fixup;
995 .word load2,ex_unaligned_fixup;
996 .word load3,ex_unaligned_fixup;
997 .word load4,ex_unaligned_fixup;
998 .word load5,ex_unaligned_fixup;
999 .word store1,ex_unaligned_fixup;
1000 .word store2,ex_unaligned_fixup;
1001 .word store3,ex_unaligned_fixup;
1002 .word store4,ex_unaligned_fixup;
1003 .word store5,ex_unaligned_fixup;
1004 .word store6,ex_unaligned_fixup;
1005 .previous;
1006 .end _unaligned_data_exception
1007 #endif /* CONFIG_MMU */
1009 .global ex_handler_unhandled
1010 ex_handler_unhandled:
1011 /* FIXME add handle function for unhandled exception - dump register */
1012 bri 0
1014 /*
1015 * hw_exception_handler Jump Table
1016 * - Contains code snippets for each register that caused the unalign exception
1017 * - Hence exception handler is NOT self-modifying
1018 * - Separate table for load exceptions and store exceptions.
1019 * - Each table is of size: (8 * 32) = 256 bytes
1020 */
1022 .section .text
1023 .align 4
1024 lw_table:
1025 lw_r0: R3_TO_LWREG (0);
1026 lw_r1: LWREG_NOP;
1027 lw_r2: R3_TO_LWREG (2);
1028 lw_r3: R3_TO_LWREG_V (3);
1029 lw_r4: R3_TO_LWREG_V (4);
1030 lw_r5: R3_TO_LWREG_V (5);
1031 lw_r6: R3_TO_LWREG_V (6);
1032 lw_r7: R3_TO_LWREG (7);
1033 lw_r8: R3_TO_LWREG (8);
1034 lw_r9: R3_TO_LWREG (9);
1035 lw_r10: R3_TO_LWREG (10);
1036 lw_r11: R3_TO_LWREG (11);
1037 lw_r12: R3_TO_LWREG (12);
1038 lw_r13: R3_TO_LWREG (13);
1039 lw_r14: R3_TO_LWREG (14);
1040 lw_r15: R3_TO_LWREG (15);
1041 lw_r16: R3_TO_LWREG (16);
1042 lw_r17: LWREG_NOP;
1043 lw_r18: R3_TO_LWREG (18);
1044 lw_r19: R3_TO_LWREG (19);
1045 lw_r20: R3_TO_LWREG (20);
1046 lw_r21: R3_TO_LWREG (21);
1047 lw_r22: R3_TO_LWREG (22);
1048 lw_r23: R3_TO_LWREG (23);
1049 lw_r24: R3_TO_LWREG (24);
1050 lw_r25: R3_TO_LWREG (25);
1051 lw_r26: R3_TO_LWREG (26);
1052 lw_r27: R3_TO_LWREG (27);
1053 lw_r28: R3_TO_LWREG (28);
1054 lw_r29: R3_TO_LWREG (29);
1055 lw_r30: R3_TO_LWREG (30);
1056 #ifdef CONFIG_MMU
1057 lw_r31: R3_TO_LWREG_V (31);
1058 #else
1059 lw_r31: R3_TO_LWREG (31);
1060 #endif
1062 sw_table:
1063 sw_r0: SWREG_TO_R3 (0);
1064 sw_r1: SWREG_NOP;
1065 sw_r2: SWREG_TO_R3 (2);
1066 sw_r3: SWREG_TO_R3_V (3);
1067 sw_r4: SWREG_TO_R3_V (4);
1068 sw_r5: SWREG_TO_R3_V (5);
1069 sw_r6: SWREG_TO_R3_V (6);
1070 sw_r7: SWREG_TO_R3 (7);
1071 sw_r8: SWREG_TO_R3 (8);
1072 sw_r9: SWREG_TO_R3 (9);
1073 sw_r10: SWREG_TO_R3 (10);
1074 sw_r11: SWREG_TO_R3 (11);
1075 sw_r12: SWREG_TO_R3 (12);
1076 sw_r13: SWREG_TO_R3 (13);
1077 sw_r14: SWREG_TO_R3 (14);
1078 sw_r15: SWREG_TO_R3 (15);
1079 sw_r16: SWREG_TO_R3 (16);
1080 sw_r17: SWREG_NOP;
1081 sw_r18: SWREG_TO_R3 (18);
1082 sw_r19: SWREG_TO_R3 (19);
1083 sw_r20: SWREG_TO_R3 (20);
1084 sw_r21: SWREG_TO_R3 (21);
1085 sw_r22: SWREG_TO_R3 (22);
1086 sw_r23: SWREG_TO_R3 (23);
1087 sw_r24: SWREG_TO_R3 (24);
1088 sw_r25: SWREG_TO_R3 (25);
1089 sw_r26: SWREG_TO_R3 (26);
1090 sw_r27: SWREG_TO_R3 (27);
1091 sw_r28: SWREG_TO_R3 (28);
1092 sw_r29: SWREG_TO_R3 (29);
1093 sw_r30: SWREG_TO_R3 (30);
1094 #ifdef CONFIG_MMU
1095 sw_r31: SWREG_TO_R3_V (31);
1096 #else
1097 sw_r31: SWREG_TO_R3 (31);
1098 #endif
1100 #ifdef CONFIG_MMU
1101 lw_table_vm:
1102 lw_r0_vm: R3_TO_LWREG_VM (0);
1103 lw_r1_vm: R3_TO_LWREG_VM_V (1);
1104 lw_r2_vm: R3_TO_LWREG_VM_V (2);
1105 lw_r3_vm: R3_TO_LWREG_VM_V (3);
1106 lw_r4_vm: R3_TO_LWREG_VM_V (4);
1107 lw_r5_vm: R3_TO_LWREG_VM_V (5);
1108 lw_r6_vm: R3_TO_LWREG_VM_V (6);
1109 lw_r7_vm: R3_TO_LWREG_VM_V (7);
1110 lw_r8_vm: R3_TO_LWREG_VM_V (8);
1111 lw_r9_vm: R3_TO_LWREG_VM_V (9);
1112 lw_r10_vm: R3_TO_LWREG_VM_V (10);
1113 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1114 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1115 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1116 lw_r14_vm: R3_TO_LWREG_VM_V (14);
1117 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1118 lw_r16_vm: R3_TO_LWREG_VM_V (16);
1119 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1120 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1121 lw_r19_vm: R3_TO_LWREG_VM_V (19);
1122 lw_r20_vm: R3_TO_LWREG_VM_V (20);
1123 lw_r21_vm: R3_TO_LWREG_VM_V (21);
1124 lw_r22_vm: R3_TO_LWREG_VM_V (22);
1125 lw_r23_vm: R3_TO_LWREG_VM_V (23);
1126 lw_r24_vm: R3_TO_LWREG_VM_V (24);
1127 lw_r25_vm: R3_TO_LWREG_VM_V (25);
1128 lw_r26_vm: R3_TO_LWREG_VM_V (26);
1129 lw_r27_vm: R3_TO_LWREG_VM_V (27);
1130 lw_r28_vm: R3_TO_LWREG_VM_V (28);
1131 lw_r29_vm: R3_TO_LWREG_VM_V (29);
1132 lw_r30_vm: R3_TO_LWREG_VM_V (30);
1133 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1135 sw_table_vm:
1136 sw_r0_vm: SWREG_TO_R3_VM (0);
1137 sw_r1_vm: SWREG_TO_R3_VM_V (1);
1138 sw_r2_vm: SWREG_TO_R3_VM_V (2);
1139 sw_r3_vm: SWREG_TO_R3_VM_V (3);
1140 sw_r4_vm: SWREG_TO_R3_VM_V (4);
1141 sw_r5_vm: SWREG_TO_R3_VM_V (5);
1142 sw_r6_vm: SWREG_TO_R3_VM_V (6);
1143 sw_r7_vm: SWREG_TO_R3_VM_V (7);
1144 sw_r8_vm: SWREG_TO_R3_VM_V (8);
1145 sw_r9_vm: SWREG_TO_R3_VM_V (9);
1146 sw_r10_vm: SWREG_TO_R3_VM_V (10);
1147 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1148 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1149 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1150 sw_r14_vm: SWREG_TO_R3_VM_V (14);
1151 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1152 sw_r16_vm: SWREG_TO_R3_VM_V (16);
1153 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1154 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1155 sw_r19_vm: SWREG_TO_R3_VM_V (19);
1156 sw_r20_vm: SWREG_TO_R3_VM_V (20);
1157 sw_r21_vm: SWREG_TO_R3_VM_V (21);
1158 sw_r22_vm: SWREG_TO_R3_VM_V (22);
1159 sw_r23_vm: SWREG_TO_R3_VM_V (23);
1160 sw_r24_vm: SWREG_TO_R3_VM_V (24);
1161 sw_r25_vm: SWREG_TO_R3_VM_V (25);
1162 sw_r26_vm: SWREG_TO_R3_VM_V (26);
1163 sw_r27_vm: SWREG_TO_R3_VM_V (27);
1164 sw_r28_vm: SWREG_TO_R3_VM_V (28);
1165 sw_r29_vm: SWREG_TO_R3_VM_V (29);
1166 sw_r30_vm: SWREG_TO_R3_VM_V (30);
1167 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1168 #endif /* CONFIG_MMU */
1170 /* Temporary data structures used in the handler */
1171 .section .data
1172 .align 4
1173 ex_tmp_data_loc_0:
1174 .byte 0
1175 ex_tmp_data_loc_1:
1176 .byte 0
1177 ex_tmp_data_loc_2:
1178 .byte 0
1179 ex_tmp_data_loc_3:
1180 .byte 0
1181 ex_reg_op:
1182 .byte 0