drivers/net/bnx2x/bnx2x.h

   1 /* bnx2x.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  */
  13
  14 #ifndef BNX2X_H
  15 #define BNX2X_H
  16 #include <linux/netdevice.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/types.h>
  19
  20 /* compilation time flags */
  21
  22 /* define this to make the driver freeze on error to allow getting debug info
  23  * (you will need to reboot afterwards) */
  24 /* #define BNX2X_STOP_ON_ERROR */
  25
  26 #define DRV_MODULE_VERSION      "1.70.00-0"
  27 #define DRV_MODULE_RELDATE      "2011/06/13"
  28 #define BNX2X_BC_VER            0x040200
  29
  30 #if defined(CONFIG_DCB)
  31 #define BCM_DCBNL
  32 #endif
  33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
  34 #define BCM_CNIC 1
  35 #include "../cnic_if.h"
  36 #endif
  37
  38 #ifdef BCM_CNIC
  39 #define BNX2X_MIN_MSIX_VEC_CNT 3
  40 #define BNX2X_MSIX_VEC_FP_START 2
  41 #else
  42 #define BNX2X_MIN_MSIX_VEC_CNT 2
  43 #define BNX2X_MSIX_VEC_FP_START 1
  44 #endif
  45
  46 #include <linux/mdio.h>
  47
  48 #include "bnx2x_reg.h"
  49 #include "bnx2x_fw_defs.h"
  50 #include "bnx2x_hsi.h"
  51 #include "bnx2x_link.h"
  52 #include "bnx2x_sp.h"
  53 #include "bnx2x_dcb.h"
  54 #include "bnx2x_stats.h"
  55
  56 /* error/debug prints */
  57
  58 #define DRV_MODULE_NAME         "bnx2x"
  59
  60 /* for messages that are currently off */
  61 #define BNX2X_MSG_OFF                   0
  62 #define BNX2X_MSG_MCP                   0x010000 /* was: NETIF_MSG_HW */
  63 #define BNX2X_MSG_STATS                 0x020000 /* was: NETIF_MSG_TIMER */
  64 #define BNX2X_MSG_NVM                   0x040000 /* was: NETIF_MSG_HW */
  65 #define BNX2X_MSG_DMAE                  0x080000 /* was: NETIF_MSG_HW */
  66 #define BNX2X_MSG_SP                    0x100000 /* was: NETIF_MSG_INTR */
  67 #define BNX2X_MSG_FP                    0x200000 /* was: NETIF_MSG_INTR */
  68
  69 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
  70
  71 /* regular debug print */
  72 #define DP(__mask, __fmt, __args...)                            \
  73 do {                                                            \
  74         if (bp->msg_enable & (__mask))                          \
  75                 printk(DP_LEVEL "[%s:%d(%s)]" __fmt,            \
  76                        __func__, __LINE__,                      \
  77                        bp->dev ? (bp->dev->name) : "?",         \
  78                        ##__args);                               \
  79 } while (0)
  80
  81 #define DP_CONT(__mask, __fmt, __args...)                       \
  82 do {                                                            \
  83         if (bp->msg_enable & (__mask))                          \
  84                 pr_cont(__fmt, ##__args);                       \
  85 } while (0)
  86
  87 /* errors debug print */
  88 #define BNX2X_DBG_ERR(__fmt, __args...)                         \
  89 do {                                                            \
  90         if (netif_msg_probe(bp))                                \
  91                 pr_err("[%s:%d(%s)]" __fmt,                     \
  92                        __func__, __LINE__,                      \
  93                        bp->dev ? (bp->dev->name) : "?",         \
  94                        ##__args);                               \
  95 } while (0)
  96
  97 /* for errors (never masked) */
  98 #define BNX2X_ERR(__fmt, __args...)                             \
  99 do {                                                            \
 100         pr_err("[%s:%d(%s)]" __fmt,                             \
 101                __func__, __LINE__,                              \
 102                bp->dev ? (bp->dev->name) : "?",                 \
 103                ##__args);                                       \
 104         } while (0)
 105
 106 #define BNX2X_ERROR(__fmt, __args...) do { \
 107         pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
 108         } while (0)
 109
 110
 111 /* before we have a dev->name use dev_info() */
 112 #define BNX2X_DEV_INFO(__fmt, __args...)                         \
 113 do {                                                             \
 114         if (netif_msg_probe(bp))                                 \
 115                 dev_info(&bp->pdev->dev, __fmt, ##__args);       \
 116 } while (0)
 117
 118 #define BNX2X_MAC_FMT           "%pM"
 119 #define BNX2X_MAC_PRN_LIST(mac) (mac)
 120
 121
 122 #ifdef BNX2X_STOP_ON_ERROR
 123 void bnx2x_int_disable(struct bnx2x *bp);
 124 #define bnx2x_panic() do { \
 125                 bp->panic = 1; \
 126                 BNX2X_ERR("driver assert\n"); \
 127                 bnx2x_int_disable(bp); \
 128                 bnx2x_panic_dump(bp); \
 129         } while (0)
 130 #else
 131 #define bnx2x_panic() do { \
 132                 bp->panic = 1; \
 133                 BNX2X_ERR("driver assert\n"); \
 134                 bnx2x_panic_dump(bp); \
 135         } while (0)
 136 #endif
 137
 138 #define bnx2x_mc_addr(ha)      ((ha)->addr)
 139 #define bnx2x_uc_addr(ha)      ((ha)->addr)
 140
 141 #define U64_LO(x)                       (u32)(((u64)(x)) & 0xffffffff)
 142 #define U64_HI(x)                       (u32)(((u64)(x)) >> 32)
 143 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 144
 145
 146 #define REG_ADDR(bp, offset)            ((bp->regview) + (offset))
 147
 148 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
 149 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
 150 #define REG_RD16(bp, offset)            readw(REG_ADDR(bp, offset))
 151
 152 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
 153 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
 154 #define REG_WR16(bp, offset, val)       writew((u16)val, REG_ADDR(bp, offset))
 155
 156 #define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
 157 #define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
 158
 159 #define REG_RD_DMAE(bp, offset, valp, len32) \
 160         do { \
 161                 bnx2x_read_dmae(bp, offset, len32);\
 162                 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
 163         } while (0)
 164
 165 #define REG_WR_DMAE(bp, offset, valp, len32) \
 166         do { \
 167                 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
 168                 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
 169                                  offset, len32); \
 170         } while (0)
 171
 172 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
 173         REG_WR_DMAE(bp, offset, valp, len32)
 174
 175 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
 176         do { \
 177                 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
 178                 bnx2x_write_big_buf_wb(bp, addr, len32); \
 179         } while (0)
 180
 181 #define SHMEM_ADDR(bp, field)           (bp->common.shmem_base + \
 182                                          offsetof(struct shmem_region, field))
 183 #define SHMEM_RD(bp, field)             REG_RD(bp, SHMEM_ADDR(bp, field))
 184 #define SHMEM_WR(bp, field, val)        REG_WR(bp, SHMEM_ADDR(bp, field), val)
 185
 186 #define SHMEM2_ADDR(bp, field)          (bp->common.shmem2_base + \
 187                                          offsetof(struct shmem2_region, field))
 188 #define SHMEM2_RD(bp, field)            REG_RD(bp, SHMEM2_ADDR(bp, field))
 189 #define SHMEM2_WR(bp, field, val)       REG_WR(bp, SHMEM2_ADDR(bp, field), val)
 190 #define MF_CFG_ADDR(bp, field)          (bp->common.mf_cfg_base + \
 191                                          offsetof(struct mf_cfg, field))
 192 #define MF2_CFG_ADDR(bp, field)         (bp->common.mf2_cfg_base + \
 193                                          offsetof(struct mf2_cfg, field))
 194
 195 #define MF_CFG_RD(bp, field)            REG_RD(bp, MF_CFG_ADDR(bp, field))
 196 #define MF_CFG_WR(bp, field, val)       REG_WR(bp,\
 197                                                MF_CFG_ADDR(bp, field), (val))
 198 #define MF2_CFG_RD(bp, field)           REG_RD(bp, MF2_CFG_ADDR(bp, field))
 199
 200 #define SHMEM2_HAS(bp, field)           ((bp)->common.shmem2_base &&    \
 201                                          (SHMEM2_RD((bp), size) >       \
 202                                          offsetof(struct shmem2_region, field)))
 203
 204 #define EMAC_RD(bp, reg)                REG_RD(bp, emac_base + reg)
 205 #define EMAC_WR(bp, reg, val)           REG_WR(bp, emac_base + reg, val)
 206
 207 /* SP SB indices */
 208
 209 /* General SP events - stats query, cfc delete, etc  */
 210 #define HC_SP_INDEX_ETH_DEF_CONS                3
 211
 212 /* EQ completions */
 213 #define HC_SP_INDEX_EQ_CONS                     7
 214
 215 /* FCoE L2 connection completions */
 216 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS         6
 217 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS         4
 218 /* iSCSI L2 */
 219 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS           5
 220 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS        1
 221
 222 /* Special clients parameters */
 223
 224 /* SB indices */
 225 /* FCoE L2 */
 226 #define BNX2X_FCOE_L2_RX_INDEX \
 227         (&bp->def_status_blk->sp_sb.\
 228         index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
 229
 230 #define BNX2X_FCOE_L2_TX_INDEX \
 231         (&bp->def_status_blk->sp_sb.\
 232         index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
 233
 234 /**
 235  *  CIDs and CLIDs:
 236  *  CLIDs below is a CLID for func 0, then the CLID for other
 237  *  functions will be calculated by the formula:
 238  *
 239  *  FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
 240  *
 241  */
 242 /* iSCSI L2 */
 243 #define BNX2X_ISCSI_ETH_CL_ID_IDX       1
 244 #define BNX2X_ISCSI_ETH_CID             49
 245
 246 /* FCoE L2 */
 247 #define BNX2X_FCOE_ETH_CL_ID_IDX        2
 248 #define BNX2X_FCOE_ETH_CID              50
 249
 250 /** Additional rings budgeting */
 251 #ifdef BCM_CNIC
 252 #define CNIC_PRESENT                    1
 253 #define FCOE_PRESENT                    1
 254 #else
 255 #define CNIC_PRESENT                    0
 256 #define FCOE_PRESENT                    0
 257 #endif /* BCM_CNIC */
 258 #define NON_ETH_CONTEXT_USE     (FCOE_PRESENT)
 259
 260 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
 261         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
 262
 263 #define SM_RX_ID                        0
 264 #define SM_TX_ID                        1
 265
 266 /* defines for multiple tx priority indices */
 267 #define FIRST_TX_ONLY_COS_INDEX         1
 268 #define FIRST_TX_COS_INDEX              0
 269
 270 /* defines for decodeing the fastpath index and the cos index out of the
 271  * transmission queue index
 272  */
 273 #define MAX_TXQS_PER_COS        FP_SB_MAX_E1x
 274
 275 #define TXQ_TO_FP(txq_index)    ((txq_index) % MAX_TXQS_PER_COS)
 276 #define TXQ_TO_COS(txq_index)   ((txq_index) / MAX_TXQS_PER_COS)
 277
 278 /* rules for calculating the cids of tx-only connections */
 279 #define CID_TO_FP(cid)          ((cid) % MAX_TXQS_PER_COS)
 280 #define CID_COS_TO_TX_ONLY_CID(cid, cos)        (cid + cos * MAX_TXQS_PER_COS)
 281
 282 /* fp index inside class of service range */
 283 #define FP_COS_TO_TXQ(fp, cos)    ((fp)->index + cos * MAX_TXQS_PER_COS)
 284
 285 /*
 286  * 0..15 eth cos0
 287  * 16..31 eth cos1 if applicable
 288  * 32..47 eth cos2 If applicable
 289  * fcoe queue follows eth queues (16, 32, 48 depending on cos)
 290  */
 291 #define MAX_ETH_TXQ_IDX(bp)     (MAX_TXQS_PER_COS * (bp)->max_cos)
 292 #define FCOE_TXQ_IDX(bp)        (MAX_ETH_TXQ_IDX(bp))
 293
 294 /* fast path */
 295 struct sw_rx_bd {
 296         struct sk_buff  *skb;
 297         DEFINE_DMA_UNMAP_ADDR(mapping);
 298 };
 299
 300 struct sw_tx_bd {
 301         struct sk_buff  *skb;
 302         u16             first_bd;
 303         u8              flags;
 304 /* Set on the first BD descriptor when there is a split BD */
 305 #define BNX2X_TSO_SPLIT_BD              (1<<0)
 306 };
 307
 308 struct sw_rx_page {
 309         struct page     *page;
 310         DEFINE_DMA_UNMAP_ADDR(mapping);
 311 };
 312
 313 union db_prod {
 314         struct doorbell_set_prod data;
 315         u32             raw;
 316 };
 317
 318 /* dropless fc FW/HW related params */
 319 #define BRB_SIZE(bp)            (CHIP_IS_E3(bp) ? 1024 : 512)
 320 #define MAX_AGG_QS(bp)          (CHIP_IS_E1(bp) ? \
 321                                         ETH_MAX_AGGREGATION_QUEUES_E1 :\
 322                                         ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
 323 #define FW_DROP_LEVEL(bp)       (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
 324 #define FW_PREFETCH_CNT         16
 325 #define DROPLESS_FC_HEADROOM    100
 326
 327 /* MC hsi */
 328 #define BCM_PAGE_SHIFT          12
 329 #define BCM_PAGE_SIZE           (1 << BCM_PAGE_SHIFT)
 330 #define BCM_PAGE_MASK           (~(BCM_PAGE_SIZE - 1))
 331 #define BCM_PAGE_ALIGN(addr)    (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
 332
 333 #define PAGES_PER_SGE_SHIFT     0
 334 #define PAGES_PER_SGE           (1 << PAGES_PER_SGE_SHIFT)
 335 #define SGE_PAGE_SIZE           PAGE_SIZE
 336 #define SGE_PAGE_SHIFT          PAGE_SHIFT
 337 #define SGE_PAGE_ALIGN(addr)    PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
 338
 339 /* SGE ring related macros */
 340 #define NUM_RX_SGE_PAGES        2
 341 #define RX_SGE_CNT              (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
 342 #define NEXT_PAGE_SGE_DESC_CNT  2
 343 #define MAX_RX_SGE_CNT          (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
 344 /* RX_SGE_CNT is promised to be a power of 2 */
 345 #define RX_SGE_MASK             (RX_SGE_CNT - 1)
 346 #define NUM_RX_SGE              (RX_SGE_CNT * NUM_RX_SGE_PAGES)
 347 #define MAX_RX_SGE              (NUM_RX_SGE - 1)
 348 #define NEXT_SGE_IDX(x)         ((((x) & RX_SGE_MASK) == \
 349                                   (MAX_RX_SGE_CNT - 1)) ? \
 350                                         (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
 351                                         (x) + 1)
 352 #define RX_SGE(x)               ((x) & MAX_RX_SGE)
 353
 354 /*
 355  * Number of required  SGEs is the sum of two:
 356  * 1. Number of possible opened aggregations (next packet for
 357  *    these aggregations will probably consume SGE immidiatelly)
 358  * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
 359  *    after placement on BD for new TPA aggregation)
 360  *
 361  * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
 362  */
 363 #define NUM_SGE_REQ             (MAX_AGG_QS(bp) + \
 364                                         (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
 365 #define NUM_SGE_PG_REQ          ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
 366                                                 MAX_RX_SGE_CNT)
 367 #define SGE_TH_LO(bp)           (NUM_SGE_REQ + \
 368                                  NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
 369 #define SGE_TH_HI(bp)           (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
 370
 371 /* Manipulate a bit vector defined as an array of u64 */
 372
 373 /* Number of bits in one sge_mask array element */
 374 #define BIT_VEC64_ELEM_SZ               64
 375 #define BIT_VEC64_ELEM_SHIFT            6
 376 #define BIT_VEC64_ELEM_MASK             ((u64)BIT_VEC64_ELEM_SZ - 1)
 377
 378
 379 #define __BIT_VEC64_SET_BIT(el, bit) \
 380         do { \
 381                 el = ((el) | ((u64)0x1 << (bit))); \
 382         } while (0)
 383
 384 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
 385         do { \
 386                 el = ((el) & (~((u64)0x1 << (bit)))); \
 387         } while (0)
 388
 389
 390 #define BIT_VEC64_SET_BIT(vec64, idx) \
 391         __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
 392                            (idx) & BIT_VEC64_ELEM_MASK)
 393
 394 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
 395         __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
 396                              (idx) & BIT_VEC64_ELEM_MASK)
 397
 398 #define BIT_VEC64_TEST_BIT(vec64, idx) \
 399         (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
 400         ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
 401
 402 /* Creates a bitmask of all ones in less significant bits.
 403    idx - index of the most significant bit in the created mask */
 404 #define BIT_VEC64_ONES_MASK(idx) \
 405                 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
 406 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
 407
 408 /*******************************************************/
 409
 410
 411
 412 /* Number of u64 elements in SGE mask array */
 413 #define RX_SGE_MASK_LEN                 ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
 414                                          BIT_VEC64_ELEM_SZ)
 415 #define RX_SGE_MASK_LEN_MASK            (RX_SGE_MASK_LEN - 1)
 416 #define NEXT_SGE_MASK_ELEM(el)          (((el) + 1) & RX_SGE_MASK_LEN_MASK)
 417
 418 union host_hc_status_block {
 419         /* pointer to fp status block e1x */
 420         struct host_hc_status_block_e1x *e1x_sb;
 421         /* pointer to fp status block e2 */
 422         struct host_hc_status_block_e2  *e2_sb;
 423 };
 424
 425 struct bnx2x_agg_info {
 426         /*
 427          * First aggregation buffer is an skb, the following - are pages.
 428          * We will preallocate the skbs for each aggregation when
 429          * we open the interface and will replace the BD at the consumer
 430          * with this one when we receive the TPA_START CQE in order to
 431          * keep the Rx BD ring consistent.
 432          */
 433         struct sw_rx_bd         first_buf;
 434         u8                      tpa_state;
 435 #define BNX2X_TPA_START                 1
 436 #define BNX2X_TPA_STOP                  2
 437 #define BNX2X_TPA_ERROR                 3
 438         u8                      placement_offset;
 439         u16                     parsing_flags;
 440         u16                     vlan_tag;
 441         u16                     len_on_bd;
 442 };
 443
 444 #define Q_STATS_OFFSET32(stat_name) \
 445                         (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
 446
 447 struct bnx2x_fp_txdata {
 448
 449         struct sw_tx_bd         *tx_buf_ring;
 450
 451         union eth_tx_bd_types   *tx_desc_ring;
 452         dma_addr_t              tx_desc_mapping;
 453
 454         u32                     cid;
 455
 456         union db_prod           tx_db;
 457
 458         u16                     tx_pkt_prod;
 459         u16                     tx_pkt_cons;
 460         u16                     tx_bd_prod;
 461         u16                     tx_bd_cons;
 462
 463         unsigned long           tx_pkt;
 464
 465         __le16                  *tx_cons_sb;
 466
 467         int                     txq_index;
 468 };
 469
 470 struct bnx2x_fastpath {
 471         struct bnx2x            *bp; /* parent */
 472
 473 #define BNX2X_NAPI_WEIGHT       128
 474         struct napi_struct      napi;
 475         union host_hc_status_block      status_blk;
 476         /* chip independed shortcuts into sb structure */
 477         __le16                  *sb_index_values;
 478         __le16                  *sb_running_index;
 479         /* chip independed shortcut into rx_prods_offset memory */
 480         u32                     ustorm_rx_prods_offset;
 481
 482         u32                     rx_buf_size;
 483
 484         dma_addr_t              status_blk_mapping;
 485
 486         u8                      max_cos; /* actual number of active tx coses */
 487         struct bnx2x_fp_txdata  txdata[BNX2X_MULTI_TX_COS];
 488
 489         struct sw_rx_bd         *rx_buf_ring;   /* BDs mappings ring */
 490         struct sw_rx_page       *rx_page_ring;  /* SGE pages mappings ring */
 491
 492         struct eth_rx_bd        *rx_desc_ring;
 493         dma_addr_t              rx_desc_mapping;
 494
 495         union eth_rx_cqe        *rx_comp_ring;
 496         dma_addr_t              rx_comp_mapping;
 497
 498         /* SGE ring */
 499         struct eth_rx_sge       *rx_sge_ring;
 500         dma_addr_t              rx_sge_mapping;
 501
 502         u64                     sge_mask[RX_SGE_MASK_LEN];
 503
 504         u32                     cid;
 505
 506         __le16                  fp_hc_idx;
 507
 508         u8                      index;          /* number in fp array */
 509         u8                      cl_id;          /* eth client id */
 510         u8                      cl_qzone_id;
 511         u8                      fw_sb_id;       /* status block number in FW */
 512         u8                      igu_sb_id;      /* status block number in HW */
 513
 514         u16                     rx_bd_prod;
 515         u16                     rx_bd_cons;
 516         u16                     rx_comp_prod;
 517         u16                     rx_comp_cons;
 518         u16                     rx_sge_prod;
 519         /* The last maximal completed SGE */
 520         u16                     last_max_sge;
 521         __le16                  *rx_cons_sb;
 522         unsigned long           rx_pkt,
 523                                 rx_calls;
 524
 525         /* TPA related */
 526         struct bnx2x_agg_info   tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
 527         u8                      disable_tpa;
 528 #ifdef BNX2X_STOP_ON_ERROR
 529         u64                     tpa_queue_used;
 530 #endif
 531
 532         struct tstorm_per_queue_stats old_tclient;
 533         struct ustorm_per_queue_stats old_uclient;
 534         struct xstorm_per_queue_stats old_xclient;
 535         struct bnx2x_eth_q_stats eth_q_stats;
 536
 537         /* The size is calculated using the following:
 538              sizeof name field from netdev structure +
 539              4 ('-Xx-' string) +
 540              4 (for the digits and to make it DWORD aligned) */
 541 #define FP_NAME_SIZE            (sizeof(((struct net_device *)0)->name) + 8)
 542         char                    name[FP_NAME_SIZE];
 543
 544         /* MACs object */
 545         struct bnx2x_vlan_mac_obj mac_obj;
 546
 547         /* Queue State object */
 548         struct bnx2x_queue_sp_obj q_obj;
 549
 550 };
 551
 552 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
 553
 554 /* Use 2500 as a mini-jumbo MTU for FCoE */
 555 #define BNX2X_FCOE_MINI_JUMBO_MTU       2500
 556
 557 /* FCoE L2 `fastpath' entry is right after the eth entries */
 558 #define FCOE_IDX                        BNX2X_NUM_ETH_QUEUES(bp)
 559 #define bnx2x_fcoe_fp(bp)               (&bp->fp[FCOE_IDX])
 560 #define bnx2x_fcoe(bp, var)             (bnx2x_fcoe_fp(bp)->var)
 561 #define bnx2x_fcoe_tx(bp, var)          (bnx2x_fcoe_fp(bp)-> \
 562                                                 txdata[FIRST_TX_COS_INDEX].var)
 563
 564
 565 #define IS_ETH_FP(fp)                   (fp->index < \
 566                                          BNX2X_NUM_ETH_QUEUES(fp->bp))
 567 #ifdef BCM_CNIC
 568 #define IS_FCOE_FP(fp)                  (fp->index == FCOE_IDX)
 569 #define IS_FCOE_IDX(idx)                ((idx) == FCOE_IDX)
 570 #else
 571 #define IS_FCOE_FP(fp)          false
 572 #define IS_FCOE_IDX(idx)        false
 573 #endif
 574
 575
 576 /* MC hsi */
 577 #define MAX_FETCH_BD            13      /* HW max BDs per packet */
 578 #define RX_COPY_THRESH          92
 579
 580 #define NUM_TX_RINGS            16
 581 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
 582 #define NEXT_PAGE_TX_DESC_CNT   1
 583 #define MAX_TX_DESC_CNT         (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
 584 #define NUM_TX_BD               (TX_DESC_CNT * NUM_TX_RINGS)
 585 #define MAX_TX_BD               (NUM_TX_BD - 1)
 586 #define MAX_TX_AVAIL            (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
 587 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
 588                                   (MAX_TX_DESC_CNT - 1)) ? \
 589                                         (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
 590                                         (x) + 1)
 591 #define TX_BD(x)                ((x) & MAX_TX_BD)
 592 #define TX_BD_POFF(x)           ((x) & MAX_TX_DESC_CNT)
 593
 594 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
 595 #define NUM_RX_RINGS            8
 596 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
 597 #define NEXT_PAGE_RX_DESC_CNT   2
 598 #define MAX_RX_DESC_CNT         (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
 599 #define RX_DESC_MASK            (RX_DESC_CNT - 1)
 600 #define NUM_RX_BD               (RX_DESC_CNT * NUM_RX_RINGS)
 601 #define MAX_RX_BD               (NUM_RX_BD - 1)
 602 #define MAX_RX_AVAIL            (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
 603
 604 /* dropless fc calculations for BDs
 605  *
 606  * Number of BDs should as number of buffers in BRB:
 607  * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
 608  * "next" elements on each page
 609  */
 610 #define NUM_BD_REQ              BRB_SIZE(bp)
 611 #define NUM_BD_PG_REQ           ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
 612                                               MAX_RX_DESC_CNT)
 613 #define BD_TH_LO(bp)            (NUM_BD_REQ + \
 614                                  NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
 615                                  FW_DROP_LEVEL(bp))
 616 #define BD_TH_HI(bp)            (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
 617
 618 #define MIN_RX_AVAIL            ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
 619
 620 #define MIN_RX_SIZE_TPA_HW      (CHIP_IS_E1(bp) ? \
 621                                         ETH_MIN_RX_CQES_WITH_TPA_E1 : \
 622                                         ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
 623 #define MIN_RX_SIZE_NONTPA_HW   ETH_MIN_RX_CQES_WITHOUT_TPA
 624 #define MIN_RX_SIZE_TPA         (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
 625 #define MIN_RX_SIZE_NONTPA      (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
 626                                                                 MIN_RX_AVAIL))
 627
 628 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
 629                                   (MAX_RX_DESC_CNT - 1)) ? \
 630                                         (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
 631                                         (x) + 1)
 632 #define RX_BD(x)                ((x) & MAX_RX_BD)
 633
 634 /*
 635  * As long as CQE is X times bigger than BD entry we have to allocate X times
 636  * more pages for CQ ring in order to keep it balanced with BD ring
 637  */
 638 #define CQE_BD_REL      (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
 639 #define NUM_RCQ_RINGS           (NUM_RX_RINGS * CQE_BD_REL)
 640 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
 641 #define NEXT_PAGE_RCQ_DESC_CNT  1
 642 #define MAX_RCQ_DESC_CNT        (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
 643 #define NUM_RCQ_BD              (RCQ_DESC_CNT * NUM_RCQ_RINGS)
 644 #define MAX_RCQ_BD              (NUM_RCQ_BD - 1)
 645 #define MAX_RCQ_AVAIL           (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
 646 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
 647                                   (MAX_RCQ_DESC_CNT - 1)) ? \
 648                                         (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
 649                                         (x) + 1)
 650 #define RCQ_BD(x)               ((x) & MAX_RCQ_BD)
 651
 652 /* dropless fc calculations for RCQs
 653  *
 654  * Number of RCQs should be as number of buffers in BRB:
 655  * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
 656  * "next" elements on each page
 657  */
 658 #define NUM_RCQ_REQ             BRB_SIZE(bp)
 659 #define NUM_RCQ_PG_REQ          ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
 660                                               MAX_RCQ_DESC_CNT)
 661 #define RCQ_TH_LO(bp)           (NUM_RCQ_REQ + \
 662                                  NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
 663                                  FW_DROP_LEVEL(bp))
 664 #define RCQ_TH_HI(bp)           (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
 665
 666
 667 /* This is needed for determining of last_max */
 668 #define SUB_S16(a, b)           (s16)((s16)(a) - (s16)(b))
 669 #define SUB_S32(a, b)           (s32)((s32)(a) - (s32)(b))
 670
 671
 672 #define BNX2X_SWCID_SHIFT       17
 673 #define BNX2X_SWCID_MASK        ((0x1 << BNX2X_SWCID_SHIFT) - 1)
 674
 675 /* used on a CID received from the HW */
 676 #define SW_CID(x)                       (le32_to_cpu(x) & BNX2X_SWCID_MASK)
 677 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
 678                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
 679
 680 #define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
 681                                                  le32_to_cpu((bd)->addr_lo))
 682 #define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
 683
 684 #define BNX2X_DB_MIN_SHIFT              3       /* 8 bytes */
 685 #define BNX2X_DB_SHIFT                  7       /* 128 bytes*/
 686 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
 687 #error "Min DB doorbell stride is 8"
 688 #endif
 689 #define DPM_TRIGER_TYPE                 0x40
 690 #define DOORBELL(bp, cid, val) \
 691         do { \
 692                 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
 693                        DPM_TRIGER_TYPE); \
 694         } while (0)
 695
 696
 697 /* TX CSUM helpers */
 698 #define SKB_CS_OFF(skb)         (offsetof(struct tcphdr, check) - \
 699                                  skb->csum_offset)
 700 #define SKB_CS(skb)             (*(u16 *)(skb_transport_header(skb) + \
 701                                           skb->csum_offset))
 702
 703 #define pbd_tcp_flags(skb)      (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
 704
 705 #define XMIT_PLAIN                      0
 706 #define XMIT_CSUM_V4                    0x1
 707 #define XMIT_CSUM_V6                    0x2
 708 #define XMIT_CSUM_TCP                   0x4
 709 #define XMIT_GSO_V4                     0x8
 710 #define XMIT_GSO_V6                     0x10
 711
 712 #define XMIT_CSUM                       (XMIT_CSUM_V4 | XMIT_CSUM_V6)
 713 #define XMIT_GSO                        (XMIT_GSO_V4 | XMIT_GSO_V6)
 714
 715
 716 /* stuff added to make the code fit 80Col */
 717 #define CQE_TYPE(cqe_fp_flags)   ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
 718 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
 719 #define CQE_TYPE_STOP(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
 720 #define CQE_TYPE_SLOW(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
 721 #define CQE_TYPE_FAST(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
 722
 723 #define ETH_RX_ERROR_FALGS              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
 724
 725 #define BNX2X_IP_CSUM_ERR(cqe) \
 726                         (!((cqe)->fast_path_cqe.status_flags & \
 727                            ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
 728                          ((cqe)->fast_path_cqe.type_error_flags & \
 729                           ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
 730
 731 #define BNX2X_L4_CSUM_ERR(cqe) \
 732                         (!((cqe)->fast_path_cqe.status_flags & \
 733                            ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
 734                          ((cqe)->fast_path_cqe.type_error_flags & \
 735                           ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
 736
 737 #define BNX2X_RX_CSUM_OK(cqe) \
 738                         (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
 739
 740 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
 741                                 (((le16_to_cpu(flags) & \
 742                                    PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
 743                                   PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
 744                                  == PRS_FLAG_OVERETH_IPV4)
 745 #define BNX2X_RX_SUM_FIX(cqe) \
 746         BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
 747
 748
 749 #define FP_USB_FUNC_OFF \
 750                         offsetof(struct cstorm_status_block_u, func)
 751 #define FP_CSB_FUNC_OFF \
 752                         offsetof(struct cstorm_status_block_c, func)
 753
 754 #define HC_INDEX_ETH_RX_CQ_CONS         1
 755
 756 #define HC_INDEX_OOO_TX_CQ_CONS         4
 757
 758 #define HC_INDEX_ETH_TX_CQ_CONS_COS0    5
 759
 760 #define HC_INDEX_ETH_TX_CQ_CONS_COS1    6
 761
 762 #define HC_INDEX_ETH_TX_CQ_CONS_COS2    7
 763
 764 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS   HC_INDEX_ETH_TX_CQ_CONS_COS0
 765
 766 #define BNX2X_RX_SB_INDEX \
 767         (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
 768
 769 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
 770
 771 #define BNX2X_TX_SB_INDEX_COS0 \
 772         (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
 773
 774 /* end of fast path */
 775
 776 /* common */
 777
 778 struct bnx2x_common {
 779
 780         u32                     chip_id;
 781 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 782 #define CHIP_ID(bp)                     (bp->common.chip_id & 0xfffffff0)
 783
 784 #define CHIP_NUM(bp)                    (bp->common.chip_id >> 16)
 785 #define CHIP_NUM_57710                  0x164e
 786 #define CHIP_NUM_57711                  0x164f
 787 #define CHIP_NUM_57711E                 0x1650
 788 #define CHIP_NUM_57712                  0x1662
 789 #define CHIP_NUM_57712_MF               0x1663
 790 #define CHIP_NUM_57713                  0x1651
 791 #define CHIP_NUM_57713E                 0x1652
 792 #define CHIP_NUM_57800                  0x168a
 793 #define CHIP_NUM_57800_MF               0x16a5
 794 #define CHIP_NUM_57810                  0x168e
 795 #define CHIP_NUM_57810_MF               0x16ae
 796 #define CHIP_NUM_57840                  0x168d
 797 #define CHIP_NUM_57840_MF               0x16ab
 798 #define CHIP_IS_E1(bp)                  (CHIP_NUM(bp) == CHIP_NUM_57710)
 799 #define CHIP_IS_57711(bp)               (CHIP_NUM(bp) == CHIP_NUM_57711)
 800 #define CHIP_IS_57711E(bp)              (CHIP_NUM(bp) == CHIP_NUM_57711E)
 801 #define CHIP_IS_57712(bp)               (CHIP_NUM(bp) == CHIP_NUM_57712)
 802 #define CHIP_IS_57712_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
 803 #define CHIP_IS_57800(bp)               (CHIP_NUM(bp) == CHIP_NUM_57800)
 804 #define CHIP_IS_57800_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
 805 #define CHIP_IS_57810(bp)               (CHIP_NUM(bp) == CHIP_NUM_57810)
 806 #define CHIP_IS_57810_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
 807 #define CHIP_IS_57840(bp)               (CHIP_NUM(bp) == CHIP_NUM_57840)
 808 #define CHIP_IS_57840_MF(bp)            (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
 809 #define CHIP_IS_E1H(bp)                 (CHIP_IS_57711(bp) || \
 810                                          CHIP_IS_57711E(bp))
 811 #define CHIP_IS_E2(bp)                  (CHIP_IS_57712(bp) || \
 812                                          CHIP_IS_57712_MF(bp))
 813 #define CHIP_IS_E3(bp)                  (CHIP_IS_57800(bp) || \
 814                                          CHIP_IS_57800_MF(bp) || \
 815                                          CHIP_IS_57810(bp) || \
 816                                          CHIP_IS_57810_MF(bp) || \
 817                                          CHIP_IS_57840(bp) || \
 818                                          CHIP_IS_57840_MF(bp))
 819 #define CHIP_IS_E1x(bp)                 (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
 820 #define USES_WARPCORE(bp)               (CHIP_IS_E3(bp))
 821 #define IS_E1H_OFFSET                   (!CHIP_IS_E1(bp))
 822
 823 #define CHIP_REV_SHIFT                  12
 824 #define CHIP_REV_MASK                   (0xF << CHIP_REV_SHIFT)
 825 #define CHIP_REV_VAL(bp)                (bp->common.chip_id & CHIP_REV_MASK)
 826 #define CHIP_REV_Ax                     (0x0 << CHIP_REV_SHIFT)
 827 #define CHIP_REV_Bx                     (0x1 << CHIP_REV_SHIFT)
 828 /* assume maximum 5 revisions */
 829 #define CHIP_REV_IS_SLOW(bp)            (CHIP_REV_VAL(bp) > 0x00005000)
 830 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
 831 #define CHIP_REV_IS_EMUL(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 832                                          !(CHIP_REV_VAL(bp) & 0x00001000))
 833 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
 834 #define CHIP_REV_IS_FPGA(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 835                                          (CHIP_REV_VAL(bp) & 0x00001000))
 836
 837 #define CHIP_TIME(bp)                   ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
 838                                         ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
 839
 840 #define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
 841 #define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
 842 #define CHIP_REV_SIM(bp)                (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
 843                                            (CHIP_REV_SHIFT + 1)) \
 844                                                 << CHIP_REV_SHIFT)
 845 #define CHIP_REV(bp)                    (CHIP_REV_IS_SLOW(bp) ? \
 846                                                 CHIP_REV_SIM(bp) :\
 847                                                 CHIP_REV_VAL(bp))
 848 #define CHIP_IS_E3B0(bp)                (CHIP_IS_E3(bp) && \
 849                                          (CHIP_REV(bp) == CHIP_REV_Bx))
 850 #define CHIP_IS_E3A0(bp)                (CHIP_IS_E3(bp) && \
 851                                          (CHIP_REV(bp) == CHIP_REV_Ax))
 852
 853         int                     flash_size;
 854 #define BNX2X_NVRAM_1MB_SIZE                    0x20000 /* 1M bit in bytes */
 855 #define BNX2X_NVRAM_TIMEOUT_COUNT               30000
 856 #define BNX2X_NVRAM_PAGE_SIZE                   256
 857
 858         u32                     shmem_base;
 859         u32                     shmem2_base;
 860         u32                     mf_cfg_base;
 861         u32                     mf2_cfg_base;
 862
 863         u32                     hw_config;
 864
 865         u32                     bc_ver;
 866
 867         u8                      int_block;
 868 #define INT_BLOCK_HC                    0
 869 #define INT_BLOCK_IGU                   1
 870 #define INT_BLOCK_MODE_NORMAL           0
 871 #define INT_BLOCK_MODE_BW_COMP          2
 872 #define CHIP_INT_MODE_IS_NBC(bp)                \
 873                         (!CHIP_IS_E1x(bp) &&    \
 874                         !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
 875 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
 876
 877         u8                      chip_port_mode;
 878 #define CHIP_4_PORT_MODE                        0x0
 879 #define CHIP_2_PORT_MODE                        0x1
 880 #define CHIP_PORT_MODE_NONE                     0x2
 881 #define CHIP_MODE(bp)                   (bp->common.chip_port_mode)
 882 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
 883 };
 884
 885 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
 886 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
 887 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
 888
 889 /* end of common */
 890
 891 /* port */
 892
 893 struct bnx2x_port {
 894         u32                     pmf;
 895
 896         u32                     link_config[LINK_CONFIG_SIZE];
 897
 898         u32                     supported[LINK_CONFIG_SIZE];
 899 /* link settings - missing defines */
 900 #define SUPPORTED_2500baseX_Full        (1 << 15)
 901
 902         u32                     advertising[LINK_CONFIG_SIZE];
 903 /* link settings - missing defines */
 904 #define ADVERTISED_2500baseX_Full       (1 << 15)
 905
 906         u32                     phy_addr;
 907
 908         /* used to synchronize phy accesses */
 909         struct mutex            phy_mutex;
 910         int                     need_hw_lock;
 911
 912         u32                     port_stx;
 913
 914         struct nig_stats        old_nig_stats;
 915 };
 916
 917 /* end of port */
 918
 919 #define STATS_OFFSET32(stat_name) \
 920                         (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
 921
 922 /* slow path */
 923
 924 /* slow path work-queue */
 925 extern struct workqueue_struct *bnx2x_wq;
 926
 927 #define BNX2X_MAX_NUM_OF_VFS    64
 928 #define BNX2X_VF_ID_INVALID     0xFF
 929
 930 /*
 931  * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
 932  * control by the number of fast-path status blocks supported by the
 933  * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
 934  * status block represents an independent interrupts context that can
 935  * serve a regular L2 networking queue. However special L2 queues such
 936  * as the FCoE queue do not require a FP-SB and other components like
 937  * the CNIC may consume FP-SB reducing the number of possible L2 queues
 938  *
 939  * If the maximum number of FP-SB available is X then:
 940  * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
 941  *    regular L2 queues is Y=X-1
 942  * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
 943  * c. If the FCoE L2 queue is supported the actual number of L2 queues
 944  *    is Y+1
 945  * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
 946  *    slow-path interrupts) or Y+2 if CNIC is supported (one additional
 947  *    FP interrupt context for the CNIC).
 948  * e. The number of HW context (CID count) is always X or X+1 if FCoE
 949  *    L2 queue is supported. the cid for the FCoE L2 queue is always X.
 950  */
 951
 952 /* fast-path interrupt contexts E1x */
 953 #define FP_SB_MAX_E1x           16
 954 /* fast-path interrupt contexts E2 */
 955 #define FP_SB_MAX_E2            HC_SB_MAX_SB_E2
 956
 957 union cdu_context {
 958         struct eth_context eth;
 959         char pad[1024];
 960 };
 961
 962 /* CDU host DB constants */
 963 #define CDU_ILT_PAGE_SZ_HW      3
 964 #define CDU_ILT_PAGE_SZ         (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
 965 #define ILT_PAGE_CIDS           (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
 966
 967 #ifdef BCM_CNIC
 968 #define CNIC_ISCSI_CID_MAX      256
 969 #define CNIC_FCOE_CID_MAX       2048
 970 #define CNIC_CID_MAX            (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
 971 #define CNIC_ILT_LINES          DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
 972 #endif
 973
 974 #define QM_ILT_PAGE_SZ_HW       0
 975 #define QM_ILT_PAGE_SZ          (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
 976 #define QM_CID_ROUND            1024
 977
 978 #ifdef BCM_CNIC
 979 /* TM (timers) host DB constants */
 980 #define TM_ILT_PAGE_SZ_HW       0
 981 #define TM_ILT_PAGE_SZ          (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
 982 /* #define TM_CONN_NUM          (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
 983 #define TM_CONN_NUM             1024
 984 #define TM_ILT_SZ               (8 * TM_CONN_NUM)
 985 #define TM_ILT_LINES            DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
 986
 987 /* SRC (Searcher) host DB constants */
 988 #define SRC_ILT_PAGE_SZ_HW      0
 989 #define SRC_ILT_PAGE_SZ         (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
 990 #define SRC_HASH_BITS           10
 991 #define SRC_CONN_NUM            (1 << SRC_HASH_BITS) /* 1024 */
 992 #define SRC_ILT_SZ              (sizeof(struct src_ent) * SRC_CONN_NUM)
 993 #define SRC_T2_SZ               SRC_ILT_SZ
 994 #define SRC_ILT_LINES           DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
 995
 996 #endif
 997
 998 #define MAX_DMAE_C              8
 999
1000 /* DMA memory not used in fastpath */
1001 struct bnx2x_slowpath {
1002         union {
1003                 struct mac_configuration_cmd            e1x;
1004                 struct eth_classify_rules_ramrod_data   e2;
1005         } mac_rdata;
1006
1007
1008         union {
1009                 struct tstorm_eth_mac_filter_config     e1x;
1010                 struct eth_filter_rules_ramrod_data     e2;
1011         } rx_mode_rdata;
1012
1013         union {
1014                 struct mac_configuration_cmd            e1;
1015                 struct eth_multicast_rules_ramrod_data  e2;
1016         } mcast_rdata;
1017
1018         struct eth_rss_update_ramrod_data       rss_rdata;
1019
1020         /* Queue State related ramrods are always sent under rtnl_lock */
1021         union {
1022                 struct client_init_ramrod_data  init_data;
1023                 struct client_update_ramrod_data update_data;
1024         } q_rdata;
1025
1026         union {
1027                 struct function_start_data      func_start;
1028                 /* pfc configuration for DCBX ramrod */
1029                 struct flow_control_configuration pfc_config;
1030         } func_rdata;
1031
1032         /* used by dmae command executer */
1033         struct dmae_command             dmae[MAX_DMAE_C];
1034
1035         u32                             stats_comp;
1036         union mac_stats                 mac_stats;
1037         struct nig_stats                nig_stats;
1038         struct host_port_stats          port_stats;
1039         struct host_func_stats          func_stats;
1040         struct host_func_stats          func_stats_base;
1041
1042         u32                             wb_comp;
1043         u32                             wb_data[4];
1044 };
1045
1046 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
1047 #define bnx2x_sp_mapping(bp, var) \
1048                 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1049
1050
1051 /* attn group wiring */
1052 #define MAX_DYNAMIC_ATTN_GRPS           8
1053
1054 struct attn_route {
1055         u32 sig[5];
1056 };
1057
1058 struct iro {
1059         u32 base;
1060         u16 m1;
1061         u16 m2;
1062         u16 m3;
1063         u16 size;
1064 };
1065
1066 struct hw_context {
1067         union cdu_context *vcxt;
1068         dma_addr_t cxt_mapping;
1069         size_t size;
1070 };
1071
1072 /* forward */
1073 struct bnx2x_ilt;
1074
1075
1076 enum bnx2x_recovery_state {
1077         BNX2X_RECOVERY_DONE,
1078         BNX2X_RECOVERY_INIT,
1079         BNX2X_RECOVERY_WAIT,
1080         BNX2X_RECOVERY_FAILED
1081 };
1082
1083 /*
1084  * Event queue (EQ or event ring) MC hsi
1085  * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1086  */
1087 #define NUM_EQ_PAGES            1
1088 #define EQ_DESC_CNT_PAGE        (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1089 #define EQ_DESC_MAX_PAGE        (EQ_DESC_CNT_PAGE - 1)
1090 #define NUM_EQ_DESC             (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1091 #define EQ_DESC_MASK            (NUM_EQ_DESC - 1)
1092 #define MAX_EQ_AVAIL            (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1093
1094 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1095 #define NEXT_EQ_IDX(x)          ((((x) & EQ_DESC_MAX_PAGE) == \
1096                                   (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1097
1098 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1099 #define EQ_DESC(x)              ((x) & EQ_DESC_MASK)
1100
1101 #define BNX2X_EQ_INDEX \
1102         (&bp->def_status_blk->sp_sb.\
1103         index_values[HC_SP_INDEX_EQ_CONS])
1104
1105 /* This is a data that will be used to create a link report message.
1106  * We will keep the data used for the last link report in order
1107  * to prevent reporting the same link parameters twice.
1108  */
1109 struct bnx2x_link_report_data {
1110         u16 line_speed;                 /* Effective line speed */
1111         unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1112 };
1113
1114 enum {
1115         BNX2X_LINK_REPORT_FD,           /* Full DUPLEX */
1116         BNX2X_LINK_REPORT_LINK_DOWN,
1117         BNX2X_LINK_REPORT_RX_FC_ON,
1118         BNX2X_LINK_REPORT_TX_FC_ON,
1119 };
1120
1121 enum {
1122         BNX2X_PORT_QUERY_IDX,
1123         BNX2X_PF_QUERY_IDX,
1124         BNX2X_FIRST_QUEUE_QUERY_IDX,
1125 };
1126
1127 struct bnx2x_fw_stats_req {
1128         struct stats_query_header hdr;
1129         struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
1130 };
1131
1132 struct bnx2x_fw_stats_data {
1133         struct stats_counter    storm_counters;
1134         struct per_port_stats   port;
1135         struct per_pf_stats     pf;
1136         struct per_queue_stats  queue_stats[1];
1137 };
1138
1139 /* Public slow path states */
1140 enum {
1141         BNX2X_SP_RTNL_SETUP_TC,
1142         BNX2X_SP_RTNL_TX_TIMEOUT,
1143 };
1144
1145
1146 struct bnx2x {
1147         /* Fields used in the tx and intr/napi performance paths
1148          * are grouped together in the beginning of the structure
1149          */
1150         struct bnx2x_fastpath   *fp;
1151         void __iomem            *regview;
1152         void __iomem            *doorbells;
1153         u16                     db_size;
1154
1155         u8                      pf_num; /* absolute PF number */
1156         u8                      pfid;   /* per-path PF number */
1157         int                     base_fw_ndsb; /**/
1158 #define BP_PATH(bp)                     (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1159 #define BP_PORT(bp)                     (bp->pfid & 1)
1160 #define BP_FUNC(bp)                     (bp->pfid)
1161 #define BP_ABS_FUNC(bp)                 (bp->pf_num)
1162 #define BP_VN(bp)                       ((bp)->pfid >> 1)
1163 #define BP_MAX_VN_NUM(bp)               (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1164 #define BP_L_ID(bp)                     (BP_VN(bp) << 2)
1165 #define BP_FW_MB_IDX_VN(bp, vn)         (BP_PORT(bp) +\
1166           (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2  : 1))
1167 #define BP_FW_MB_IDX(bp)                BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1168
1169         struct net_device       *dev;
1170         struct pci_dev          *pdev;
1171
1172         const struct iro        *iro_arr;
1173 #define IRO (bp->iro_arr)
1174
1175         enum bnx2x_recovery_state recovery_state;
1176         int                     is_leader;
1177         struct msix_entry       *msix_table;
1178
1179         int                     tx_ring_size;
1180
1181 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1182 #define ETH_OVREHEAD            (ETH_HLEN + 8 + 8)
1183 #define ETH_MIN_PACKET_SIZE             60
1184 #define ETH_MAX_PACKET_SIZE             1500
1185 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
1186
1187         /* Max supported alignment is 256 (8 shift) */
1188 #define BNX2X_RX_ALIGN_SHIFT            ((L1_CACHE_SHIFT < 8) ? \
1189                                          L1_CACHE_SHIFT : 8)
1190         /* FW use 2 Cache lines Alignment for start packet and size  */
1191 #define BNX2X_FW_RX_ALIGN               (2 << BNX2X_RX_ALIGN_SHIFT)
1192 #define BNX2X_PXP_DRAM_ALIGN            (BNX2X_RX_ALIGN_SHIFT - 5)
1193
1194         struct host_sp_status_block *def_status_blk;
1195 #define DEF_SB_IGU_ID                   16
1196 #define DEF_SB_ID                       HC_SP_SB_ID
1197         __le16                  def_idx;
1198         __le16                  def_att_idx;
1199         u32                     attn_state;
1200         struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
1201
1202         /* slow path ring */
1203         struct eth_spe          *spq;
1204         dma_addr_t              spq_mapping;
1205         u16                     spq_prod_idx;
1206         struct eth_spe          *spq_prod_bd;
1207         struct eth_spe          *spq_last_bd;
1208         __le16                  *dsb_sp_prod;
1209         atomic_t                cq_spq_left; /* ETH_XXX ramrods credit */
1210         /* used to synchronize spq accesses */
1211         spinlock_t              spq_lock;
1212
1213         /* event queue */
1214         union event_ring_elem   *eq_ring;
1215         dma_addr_t              eq_mapping;
1216         u16                     eq_prod;
1217         u16                     eq_cons;
1218         __le16                  *eq_cons_sb;
1219         atomic_t                eq_spq_left; /* COMMON_XXX ramrods credit */
1220
1221
1222
1223         /* Counter for marking that there is a STAT_QUERY ramrod pending */
1224         u16                     stats_pending;
1225         /*  Counter for completed statistics ramrods */
1226         u16                     stats_comp;
1227
1228         /* End of fields used in the performance code paths */
1229
1230         int                     panic;
1231         int                     msg_enable;
1232
1233         u32                     flags;
1234 #define PCIX_FLAG                       (1 << 0)
1235 #define PCI_32BIT_FLAG                  (1 << 1)
1236 #define ONE_PORT_FLAG                   (1 << 2)
1237 #define NO_WOL_FLAG                     (1 << 3)
1238 #define USING_DAC_FLAG                  (1 << 4)
1239 #define USING_MSIX_FLAG                 (1 << 5)
1240 #define USING_MSI_FLAG                  (1 << 6)
1241 #define DISABLE_MSI_FLAG                (1 << 7)
1242 #define TPA_ENABLE_FLAG                 (1 << 8)
1243 #define NO_MCP_FLAG                     (1 << 9)
1244
1245 #define BP_NOMCP(bp)                    (bp->flags & NO_MCP_FLAG)
1246 #define MF_FUNC_DIS                     (1 << 11)
1247 #define OWN_CNIC_IRQ                    (1 << 12)
1248 #define NO_ISCSI_OOO_FLAG               (1 << 13)
1249 #define NO_ISCSI_FLAG                   (1 << 14)
1250 #define NO_FCOE_FLAG                    (1 << 15)
1251
1252 #define NO_ISCSI(bp)            ((bp)->flags & NO_ISCSI_FLAG)
1253 #define NO_ISCSI_OOO(bp)        ((bp)->flags & NO_ISCSI_OOO_FLAG)
1254 #define NO_FCOE(bp)             ((bp)->flags & NO_FCOE_FLAG)
1255
1256         int                     pm_cap;
1257         int                     mrrs;
1258
1259         struct delayed_work     sp_task;
1260         struct delayed_work     sp_rtnl_task;
1261
1262         struct delayed_work     period_task;
1263         struct timer_list       timer;
1264         int                     current_interval;
1265
1266         u16                     fw_seq;
1267         u16                     fw_drv_pulse_wr_seq;
1268         u32                     func_stx;
1269
1270         struct link_params      link_params;
1271         struct link_vars        link_vars;
1272         u32                     link_cnt;
1273         struct bnx2x_link_report_data last_reported_link;
1274
1275         struct mdio_if_info     mdio;
1276
1277         struct bnx2x_common     common;
1278         struct bnx2x_port       port;
1279
1280         struct cmng_struct_per_port cmng;
1281         u32                     vn_weight_sum;
1282         u32                     mf_config[E1HVN_MAX];
1283         u32                     mf2_config[E2_FUNC_MAX];
1284         u32                     path_has_ovlan; /* E3 */
1285         u16                     mf_ov;
1286         u8                      mf_mode;
1287 #define IS_MF(bp)               (bp->mf_mode != 0)
1288 #define IS_MF_SI(bp)            (bp->mf_mode == MULTI_FUNCTION_SI)
1289 #define IS_MF_SD(bp)            (bp->mf_mode == MULTI_FUNCTION_SD)
1290
1291         u8                      wol;
1292
1293         int                     rx_ring_size;
1294
1295         u16                     tx_quick_cons_trip_int;
1296         u16                     tx_quick_cons_trip;
1297         u16                     tx_ticks_int;
1298         u16                     tx_ticks;
1299
1300         u16                     rx_quick_cons_trip_int;
1301         u16                     rx_quick_cons_trip;
1302         u16                     rx_ticks_int;
1303         u16                     rx_ticks;
1304 /* Maximal coalescing timeout in us */
1305 #define BNX2X_MAX_COALESCE_TOUT         (0xf0*12)
1306
1307         u32                     lin_cnt;
1308
1309         u16                     state;
1310 #define BNX2X_STATE_CLOSED              0
1311 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
1312 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
1313 #define BNX2X_STATE_OPEN                0x3000
1314 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
1315 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1316
1317 #define BNX2X_STATE_DIAG                0xe000
1318 #define BNX2X_STATE_ERROR               0xf000
1319
1320         int                     multi_mode;
1321 #define BNX2X_MAX_PRIORITY              8
1322 #define BNX2X_MAX_ENTRIES_PER_PRI       16
1323 #define BNX2X_MAX_COS                   3
1324 #define BNX2X_MAX_TX_COS                2
1325         int                     num_queues;
1326         int                     disable_tpa;
1327
1328         u32                     rx_mode;
1329 #define BNX2X_RX_MODE_NONE              0
1330 #define BNX2X_RX_MODE_NORMAL            1
1331 #define BNX2X_RX_MODE_ALLMULTI          2
1332 #define BNX2X_RX_MODE_PROMISC           3
1333 #define BNX2X_MAX_MULTICAST             64
1334
1335         u8                      igu_dsb_id;
1336         u8                      igu_base_sb;
1337         u8                      igu_sb_cnt;
1338         dma_addr_t              def_status_blk_mapping;
1339
1340         struct bnx2x_slowpath   *slowpath;
1341         dma_addr_t              slowpath_mapping;
1342
1343         /* Total number of FW statistics requests */
1344         u8                      fw_stats_num;
1345
1346         /*
1347          * This is a memory buffer that will contain both statistics
1348          * ramrod request and data.
1349          */
1350         void                    *fw_stats;
1351         dma_addr_t              fw_stats_mapping;
1352
1353         /*
1354          * FW statistics request shortcut (points at the
1355          * beginning of fw_stats buffer).
1356          */
1357         struct bnx2x_fw_stats_req       *fw_stats_req;
1358         dma_addr_t                      fw_stats_req_mapping;
1359         int                             fw_stats_req_sz;
1360
1361         /*
1362          * FW statistics data shortcut (points at the begining of
1363          * fw_stats buffer + fw_stats_req_sz).
1364          */
1365         struct bnx2x_fw_stats_data      *fw_stats_data;
1366         dma_addr_t                      fw_stats_data_mapping;
1367         int                             fw_stats_data_sz;
1368
1369         struct hw_context       context;
1370
1371         struct bnx2x_ilt        *ilt;
1372 #define BP_ILT(bp)              ((bp)->ilt)
1373 #define ILT_MAX_LINES           256
1374 /*
1375  * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1376  * to CNIC.
1377  */
1378 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1379
1380 /*
1381  * Maximum CID count that might be required by the bnx2x:
1382  * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1383  */
1384 #define BNX2X_L2_CID_COUNT(bp)  (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1385                                         NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1386 #define L2_ILT_LINES(bp)        (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1387                                         ILT_PAGE_CIDS))
1388 #define BNX2X_DB_SIZE(bp)       (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1389
1390         int                     qm_cid_count;
1391
1392         int                     dropless_fc;
1393
1394 #ifdef BCM_CNIC
1395         u32                     cnic_flags;
1396 #define BNX2X_CNIC_FLAG_MAC_SET         1
1397         void                    *t2;
1398         dma_addr_t              t2_mapping;
1399         struct cnic_ops __rcu   *cnic_ops;
1400         void                    *cnic_data;
1401         u32                     cnic_tag;
1402         struct cnic_eth_dev     cnic_eth_dev;
1403         union host_hc_status_block cnic_sb;
1404         dma_addr_t              cnic_sb_mapping;
1405         struct eth_spe          *cnic_kwq;
1406         struct eth_spe          *cnic_kwq_prod;
1407         struct eth_spe          *cnic_kwq_cons;
1408         struct eth_spe          *cnic_kwq_last;
1409         u16                     cnic_kwq_pending;
1410         u16                     cnic_spq_pending;
1411         u8                      fip_mac[ETH_ALEN];
1412         struct mutex            cnic_mutex;
1413         struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1414
1415         /* Start index of the "special" (CNIC related) L2 cleints */
1416         u8                              cnic_base_cl_id;
1417 #endif
1418
1419         int                     dmae_ready;
1420         /* used to synchronize dmae accesses */
1421         spinlock_t              dmae_lock;
1422
1423         /* used to protect the FW mail box */
1424         struct mutex            fw_mb_mutex;
1425
1426         /* used to synchronize stats collecting */
1427         int                     stats_state;
1428
1429         /* used for synchronization of concurrent threads statistics handling */
1430         spinlock_t              stats_lock;
1431
1432         /* used by dmae command loader */
1433         struct dmae_command     stats_dmae;
1434         int                     executer_idx;
1435
1436         u16                     stats_counter;
1437         struct bnx2x_eth_stats  eth_stats;
1438
1439         struct z_stream_s       *strm;
1440         void                    *gunzip_buf;
1441         dma_addr_t              gunzip_mapping;
1442         int                     gunzip_outlen;
1443 #define FW_BUF_SIZE                     0x8000
1444 #define GUNZIP_BUF(bp)                  (bp->gunzip_buf)
1445 #define GUNZIP_PHYS(bp)                 (bp->gunzip_mapping)
1446 #define GUNZIP_OUTLEN(bp)               (bp->gunzip_outlen)
1447
1448         struct raw_op           *init_ops;
1449         /* Init blocks offsets inside init_ops */
1450         u16                     *init_ops_offsets;
1451         /* Data blob - has 32 bit granularity */
1452         u32                     *init_data;
1453         u32                     init_mode_flags;
1454 #define INIT_MODE_FLAGS(bp)     (bp->init_mode_flags)
1455         /* Zipped PRAM blobs - raw data */
1456         const u8                *tsem_int_table_data;
1457         const u8                *tsem_pram_data;
1458         const u8                *usem_int_table_data;
1459         const u8                *usem_pram_data;
1460         const u8                *xsem_int_table_data;
1461         const u8                *xsem_pram_data;
1462         const u8                *csem_int_table_data;
1463         const u8                *csem_pram_data;
1464 #define INIT_OPS(bp)                    (bp->init_ops)
1465 #define INIT_OPS_OFFSETS(bp)            (bp->init_ops_offsets)
1466 #define INIT_DATA(bp)                   (bp->init_data)
1467 #define INIT_TSEM_INT_TABLE_DATA(bp)    (bp->tsem_int_table_data)
1468 #define INIT_TSEM_PRAM_DATA(bp)         (bp->tsem_pram_data)
1469 #define INIT_USEM_INT_TABLE_DATA(bp)    (bp->usem_int_table_data)
1470 #define INIT_USEM_PRAM_DATA(bp)         (bp->usem_pram_data)
1471 #define INIT_XSEM_INT_TABLE_DATA(bp)    (bp->xsem_int_table_data)
1472 #define INIT_XSEM_PRAM_DATA(bp)         (bp->xsem_pram_data)
1473 #define INIT_CSEM_INT_TABLE_DATA(bp)    (bp->csem_int_table_data)
1474 #define INIT_CSEM_PRAM_DATA(bp)         (bp->csem_pram_data)
1475
1476 #define PHY_FW_VER_LEN                  20
1477         char                    fw_ver[32];
1478         const struct firmware   *firmware;
1479
1480         /* DCB support on/off */
1481         u16 dcb_state;
1482 #define BNX2X_DCB_STATE_OFF                     0
1483 #define BNX2X_DCB_STATE_ON                      1
1484
1485         /* DCBX engine mode */
1486         int dcbx_enabled;
1487 #define BNX2X_DCBX_ENABLED_OFF                  0
1488 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF           1
1489 #define BNX2X_DCBX_ENABLED_ON_NEG_ON            2
1490 #define BNX2X_DCBX_ENABLED_INVALID              (-1)
1491
1492         bool dcbx_mode_uset;
1493
1494         struct bnx2x_config_dcbx_params         dcbx_config_params;
1495         struct bnx2x_dcbx_port_params           dcbx_port_params;
1496         int                                     dcb_version;
1497
1498         /* CAM credit pools */
1499         struct bnx2x_credit_pool_obj            macs_pool;
1500
1501         /* RX_MODE object */
1502         struct bnx2x_rx_mode_obj                rx_mode_obj;
1503
1504         /* MCAST object */
1505         struct bnx2x_mcast_obj                  mcast_obj;
1506
1507         /* RSS configuration object */
1508         struct bnx2x_rss_config_obj             rss_conf_obj;
1509
1510         /* Function State controlling object */
1511         struct bnx2x_func_sp_obj                func_obj;
1512
1513         unsigned long                           sp_state;
1514
1515         /* operation indication for the sp_rtnl task */
1516         unsigned long                           sp_rtnl_state;
1517
1518         /* DCBX Negotation results */
1519         struct dcbx_features                    dcbx_local_feat;
1520         u32                                     dcbx_error;
1521
1522 #ifdef BCM_DCBNL
1523         struct dcbx_features                    dcbx_remote_feat;
1524         u32                                     dcbx_remote_flags;
1525 #endif
1526         u32                                     pending_max;
1527
1528         /* multiple tx classes of service */
1529         u8                                      max_cos;
1530
1531         /* priority to cos mapping */
1532         u8                                      prio_to_cos[8];
1533 };
1534
1535 /* Tx queues may be less or equal to Rx queues */
1536 extern int num_queues;
1537 #define BNX2X_NUM_QUEUES(bp)    (bp->num_queues)
1538 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1539 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1540
1541 #define is_multi(bp)            (BNX2X_NUM_QUEUES(bp) > 1)
1542
1543 #define BNX2X_MAX_QUEUES(bp)    BNX2X_MAX_RSS_COUNT(bp)
1544 /* #define is_eth_multi(bp)     (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1545
1546 #define RSS_IPV4_CAP_MASK                                               \
1547         TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1548
1549 #define RSS_IPV4_TCP_CAP_MASK                                           \
1550         TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1551
1552 #define RSS_IPV6_CAP_MASK                                               \
1553         TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1554
1555 #define RSS_IPV6_TCP_CAP_MASK                                           \
1556         TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1557
1558 /* func init flags */
1559 #define FUNC_FLG_RSS            0x0001
1560 #define FUNC_FLG_STATS          0x0002
1561 /* removed  FUNC_FLG_UNMATCHED  0x0004 */
1562 #define FUNC_FLG_TPA            0x0008
1563 #define FUNC_FLG_SPQ            0x0010
1564 #define FUNC_FLG_LEADING        0x0020  /* PF only */
1565
1566
1567 struct bnx2x_func_init_params {
1568         /* dma */
1569         dma_addr_t      fw_stat_map;    /* valid iff FUNC_FLG_STATS */
1570         dma_addr_t      spq_map;        /* valid iff FUNC_FLG_SPQ */
1571
1572         u16             func_flgs;
1573         u16             func_id;        /* abs fid */
1574         u16             pf_id;
1575         u16             spq_prod;       /* valid iff FUNC_FLG_SPQ */
1576 };
1577
1578 #define for_each_eth_queue(bp, var) \
1579         for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1580
1581 #define for_each_nondefault_eth_queue(bp, var) \
1582         for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1583
1584 #define for_each_queue(bp, var) \
1585         for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1586                 if (skip_queue(bp, var))        \
1587                         continue;               \
1588                 else
1589
1590 /* Skip forwarding FP */
1591 #define for_each_rx_queue(bp, var) \
1592         for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1593                 if (skip_rx_queue(bp, var))     \
1594                         continue;               \
1595                 else
1596
1597 /* Skip OOO FP */
1598 #define for_each_tx_queue(bp, var) \
1599         for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1600                 if (skip_tx_queue(bp, var))     \
1601                         continue;               \
1602                 else
1603
1604 #define for_each_nondefault_queue(bp, var) \
1605         for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1606                 if (skip_queue(bp, var))        \
1607                         continue;               \
1608                 else
1609
1610 #define for_each_cos_in_tx_queue(fp, var) \
1611         for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1612
1613 /* skip rx queue
1614  * if FCOE l2 support is disabled and this is the fcoe L2 queue
1615  */
1616 #define skip_rx_queue(bp, idx)  (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1617
1618 /* skip tx queue
1619  * if FCOE l2 support is disabled and this is the fcoe L2 queue
1620  */
1621 #define skip_tx_queue(bp, idx)  (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1622
1623 #define skip_queue(bp, idx)     (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1624
1625
1626
1627
1628 /**
1629  * bnx2x_set_mac_one - configure a single MAC address
1630  *
1631  * @bp:                 driver handle
1632  * @mac:                MAC to configure
1633  * @obj:                MAC object handle
1634  * @set:                if 'true' add a new MAC, otherwise - delete
1635  * @mac_type:           the type of the MAC to configure (e.g. ETH, UC list)
1636  * @ramrod_flags:       RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1637  *
1638  * Configures one MAC according to provided parameters or continues the
1639  * execution of previously scheduled commands if RAMROD_CONT is set in
1640  * ramrod_flags.
1641  *
1642  * Returns zero if operation has successfully completed, a positive value if the
1643  * operation has been successfully scheduled and a negative - if a requested
1644  * operations has failed.
1645  */
1646 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1647                       struct bnx2x_vlan_mac_obj *obj, bool set,
1648                       int mac_type, unsigned long *ramrod_flags);
1649 /**
1650  * Deletes all MACs configured for the specific MAC object.
1651  *
1652  * @param bp Function driver instance
1653  * @param mac_obj MAC object to cleanup
1654  *
1655  * @return zero if all MACs were cleaned
1656  */
1657
1658 /**
1659  * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1660  *
1661  * @bp:                 driver handle
1662  * @mac_obj:            MAC object handle
1663  * @mac_type:           type of the MACs to clear (BNX2X_XXX_MAC)
1664  * @wait_for_comp:      if 'true' block until completion
1665  *
1666  * Deletes all MACs of the specific type (e.g. ETH, UC list).
1667  *
1668  * Returns zero if operation has successfully completed, a positive value if the
1669  * operation has been successfully scheduled and a negative - if a requested
1670  * operations has failed.
1671  */
1672 int bnx2x_del_all_macs(struct bnx2x *bp,
1673                        struct bnx2x_vlan_mac_obj *mac_obj,
1674                        int mac_type, bool wait_for_comp);
1675
1676 /* Init Function API  */
1677 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1678 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1679 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1680 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1681 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1682 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1683
1684
1685 /* dmae */
1686 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1687 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1688                       u32 len32);
1689 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1690 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1691 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1692 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1693                       bool with_comp, u8 comp_type);
1694
1695
1696 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1697 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1698                   u32 data_hi, u32 data_lo, int cmd_type);
1699 void bnx2x_update_coalesce(struct bnx2x *bp);
1700 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1701
1702 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1703                            int wait)
1704 {
1705         u32 val;
1706
1707         do {
1708                 val = REG_RD(bp, reg);
1709                 if (val == expected)
1710                         break;
1711                 ms -= wait;
1712                 msleep(wait);
1713
1714         } while (ms > 0);
1715
1716         return val;
1717 }
1718
1719 #define BNX2X_ILT_ZALLOC(x, y, size) \
1720         do { \
1721                 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1722                 if (x) \
1723                         memset(x, 0, size); \
1724         } while (0)
1725
1726 #define BNX2X_ILT_FREE(x, y, size) \
1727         do { \
1728                 if (x) { \
1729                         dma_free_coherent(&bp->pdev->dev, size, x, y); \
1730                         x = NULL; \
1731                         y = 0; \
1732                 } \
1733         } while (0)
1734
1735 #define ILOG2(x)        (ilog2((x)))
1736
1737 #define ILT_NUM_PAGE_ENTRIES    (3072)
1738 /* In 57710/11 we use whole table since we have 8 func
1739  * In 57712 we have only 4 func, but use same size per func, then only half of
1740  * the table in use
1741  */
1742 #define ILT_PER_FUNC            (ILT_NUM_PAGE_ENTRIES/8)
1743
1744 #define FUNC_ILT_BASE(func)     (func * ILT_PER_FUNC)
1745 /*
1746  * the phys address is shifted right 12 bits and has an added
1747  * 1=valid bit added to the 53rd bit
1748  * then since this is a wide register(TM)
1749  * we split it into two 32 bit writes
1750  */
1751 #define ONCHIP_ADDR1(x)         ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1752 #define ONCHIP_ADDR2(x)         ((u32)((1 << 20) | ((u64)x >> 44)))
1753
1754 /* load/unload mode */
1755 #define LOAD_NORMAL                     0
1756 #define LOAD_OPEN                       1
1757 #define LOAD_DIAG                       2
1758 #define UNLOAD_NORMAL                   0
1759 #define UNLOAD_CLOSE                    1
1760 #define UNLOAD_RECOVERY                 2
1761
1762
1763 /* DMAE command defines */
1764 #define DMAE_TIMEOUT                    -1
1765 #define DMAE_PCI_ERROR                  -2      /* E2 and onward */
1766 #define DMAE_NOT_RDY                    -3
1767 #define DMAE_PCI_ERR_FLAG               0x80000000
1768
1769 #define DMAE_SRC_PCI                    0
1770 #define DMAE_SRC_GRC                    1
1771
1772 #define DMAE_DST_NONE                   0
1773 #define DMAE_DST_PCI                    1
1774 #define DMAE_DST_GRC                    2
1775
1776 #define DMAE_COMP_PCI                   0
1777 #define DMAE_COMP_GRC                   1
1778
1779 /* E2 and onward - PCI error handling in the completion */
1780
1781 #define DMAE_COMP_REGULAR               0
1782 #define DMAE_COM_SET_ERR                1
1783
1784 #define DMAE_CMD_SRC_PCI                (DMAE_SRC_PCI << \
1785                                                 DMAE_COMMAND_SRC_SHIFT)
1786 #define DMAE_CMD_SRC_GRC                (DMAE_SRC_GRC << \
1787                                                 DMAE_COMMAND_SRC_SHIFT)
1788
1789 #define DMAE_CMD_DST_PCI                (DMAE_DST_PCI << \
1790                                                 DMAE_COMMAND_DST_SHIFT)
1791 #define DMAE_CMD_DST_GRC                (DMAE_DST_GRC << \
1792                                                 DMAE_COMMAND_DST_SHIFT)
1793
1794 #define DMAE_CMD_C_DST_PCI              (DMAE_COMP_PCI << \
1795                                                 DMAE_COMMAND_C_DST_SHIFT)
1796 #define DMAE_CMD_C_DST_GRC              (DMAE_COMP_GRC << \
1797                                                 DMAE_COMMAND_C_DST_SHIFT)
1798
1799 #define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
1800
1801 #define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1802 #define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1803 #define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1804 #define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1805
1806 #define DMAE_CMD_PORT_0                 0
1807 #define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
1808
1809 #define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
1810 #define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
1811 #define DMAE_CMD_E1HVN_SHIFT            DMAE_COMMAND_E1HVN_SHIFT
1812
1813 #define DMAE_SRC_PF                     0
1814 #define DMAE_SRC_VF                     1
1815
1816 #define DMAE_DST_PF                     0
1817 #define DMAE_DST_VF                     1
1818
1819 #define DMAE_C_SRC                      0
1820 #define DMAE_C_DST                      1
1821
1822 #define DMAE_LEN32_RD_MAX               0x80
1823 #define DMAE_LEN32_WR_MAX(bp)           (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1824
1825 #define DMAE_COMP_VAL                   0x60d0d0ae /* E2 and on - upper bit
1826                                                         indicates eror */
1827
1828 #define MAX_DMAE_C_PER_PORT             8
1829 #define INIT_DMAE_C(bp)                 (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1830                                          BP_VN(bp))
1831 #define PMF_DMAE_C(bp)                  (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1832                                          E1HVN_MAX)
1833
1834 /* PCIE link and speed */
1835 #define PCICFG_LINK_WIDTH               0x1f00000
1836 #define PCICFG_LINK_WIDTH_SHIFT         20
1837 #define PCICFG_LINK_SPEED               0xf0000
1838 #define PCICFG_LINK_SPEED_SHIFT         16
1839
1840
1841 #define BNX2X_NUM_TESTS                 7
1842
1843 #define BNX2X_PHY_LOOPBACK              0
1844 #define BNX2X_MAC_LOOPBACK              1
1845 #define BNX2X_PHY_LOOPBACK_FAILED       1
1846 #define BNX2X_MAC_LOOPBACK_FAILED       2
1847 #define BNX2X_LOOPBACK_FAILED           (BNX2X_MAC_LOOPBACK_FAILED | \
1848                                          BNX2X_PHY_LOOPBACK_FAILED)
1849
1850
1851 #define STROM_ASSERT_ARRAY_SIZE         50
1852
1853
1854 /* must be used on a CID before placing it on a HW ring */
1855 #define HW_CID(bp, x)                   ((BP_PORT(bp) << 23) | \
1856                                          (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1857                                          (x))
1858
1859 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1860 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
1861
1862
1863 #define BNX2X_BTR                       4
1864 #define MAX_SPQ_PENDING                 8
1865
1866 /* CMNG constants, as derived from system spec calculations */
1867 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1868 #define DEF_MIN_RATE                                    100
1869 /* resolution of the rate shaping timer - 400 usec */
1870 #define RS_PERIODIC_TIMEOUT_USEC                        400
1871 /* number of bytes in single QM arbitration cycle -
1872  * coefficient for calculating the fairness timer */
1873 #define QM_ARB_BYTES                                    160000
1874 /* resolution of Min algorithm 1:100 */
1875 #define MIN_RES                                         100
1876 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1877 #define MIN_ABOVE_THRESH                                32768
1878 /* Fairness algorithm integration time coefficient -
1879  * for calculating the actual Tfair */
1880 #define T_FAIR_COEF     ((MIN_ABOVE_THRESH +  QM_ARB_BYTES) * 8 * MIN_RES)
1881 /* Memory of fairness algorithm . 2 cycles */
1882 #define FAIR_MEM                                        2
1883
1884
1885 #define ATTN_NIG_FOR_FUNC               (1L << 8)
1886 #define ATTN_SW_TIMER_4_FUNC            (1L << 9)
1887 #define GPIO_2_FUNC                     (1L << 10)
1888 #define GPIO_3_FUNC                     (1L << 11)
1889 #define GPIO_4_FUNC                     (1L << 12)
1890 #define ATTN_GENERAL_ATTN_1             (1L << 13)
1891 #define ATTN_GENERAL_ATTN_2             (1L << 14)
1892 #define ATTN_GENERAL_ATTN_3             (1L << 15)
1893 #define ATTN_GENERAL_ATTN_4             (1L << 13)
1894 #define ATTN_GENERAL_ATTN_5             (1L << 14)
1895 #define ATTN_GENERAL_ATTN_6             (1L << 15)
1896
1897 #define ATTN_HARD_WIRED_MASK            0xff00
1898 #define ATTENTION_ID                    4
1899
1900
1901 /* stuff added to make the code fit 80Col */
1902
1903 #define BNX2X_PMF_LINK_ASSERT \
1904         GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1905
1906 #define BNX2X_MC_ASSERT_BITS \
1907         (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1908          GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1909          GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1910          GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1911
1912 #define BNX2X_MCP_ASSERT \
1913         GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1914
1915 #define BNX2X_GRC_TIMEOUT       GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1916 #define BNX2X_GRC_RSV           (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1917                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1918                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1919                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1920                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1921                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1922
1923 #define HW_INTERRUT_ASSERT_SET_0 \
1924                                 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1925                                  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1926                                  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1927                                  AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1928 #define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1929                                  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1930                                  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1931                                  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1932                                  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1933                                  AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1934                                  AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1935 #define HW_INTERRUT_ASSERT_SET_1 \
1936                                 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1937                                  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1938                                  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1939                                  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1940                                  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1941                                  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1942                                  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1943                                  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1944                                  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1945                                  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1946                                  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1947 #define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1948                                  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1949                                  AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1950                                  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1951                                  AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1952                                  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1953                                  AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1954                                  AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1955                              AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1956                                  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1957                                  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1958                                  AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1959                                  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1960                                  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1961                                  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1962                                  AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1963 #define HW_INTERRUT_ASSERT_SET_2 \
1964                                 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1965                                  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1966                                  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1967                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1968                                  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1969 #define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1970                                  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1971                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1972                                  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1973                                  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1974                                  AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1975                                  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1976                                  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1977
1978 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1979                 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1980                 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1981                 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1982
1983 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
1984                               AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
1985
1986 #define RSS_FLAGS(bp) \
1987                 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1988                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1989                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1990                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1991                  (bp->multi_mode << \
1992                   TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1993 #define MULTI_MASK                      0x7f
1994
1995
1996 #define DEF_USB_FUNC_OFF        offsetof(struct cstorm_def_status_block_u, func)
1997 #define DEF_CSB_FUNC_OFF        offsetof(struct cstorm_def_status_block_c, func)
1998 #define DEF_XSB_FUNC_OFF        offsetof(struct xstorm_def_status_block, func)
1999 #define DEF_TSB_FUNC_OFF        offsetof(struct tstorm_def_status_block, func)
2000
2001 #define DEF_USB_IGU_INDEX_OFF \
2002                         offsetof(struct cstorm_def_status_block_u, igu_index)
2003 #define DEF_CSB_IGU_INDEX_OFF \
2004                         offsetof(struct cstorm_def_status_block_c, igu_index)
2005 #define DEF_XSB_IGU_INDEX_OFF \
2006                         offsetof(struct xstorm_def_status_block, igu_index)
2007 #define DEF_TSB_IGU_INDEX_OFF \
2008                         offsetof(struct tstorm_def_status_block, igu_index)
2009
2010 #define DEF_USB_SEGMENT_OFF \
2011                         offsetof(struct cstorm_def_status_block_u, segment)
2012 #define DEF_CSB_SEGMENT_OFF \
2013                         offsetof(struct cstorm_def_status_block_c, segment)
2014 #define DEF_XSB_SEGMENT_OFF \
2015                         offsetof(struct xstorm_def_status_block, segment)
2016 #define DEF_TSB_SEGMENT_OFF \
2017                         offsetof(struct tstorm_def_status_block, segment)
2018
2019 #define BNX2X_SP_DSB_INDEX \
2020                 (&bp->def_status_blk->sp_sb.\
2021                                         index_values[HC_SP_INDEX_ETH_DEF_CONS])
2022
2023 #define SET_FLAG(value, mask, flag) \
2024         do {\
2025                 (value) &= ~(mask);\
2026                 (value) |= ((flag) << (mask##_SHIFT));\
2027         } while (0)
2028
2029 #define GET_FLAG(value, mask) \
2030         (((value) & (mask)) >> (mask##_SHIFT))
2031
2032 #define GET_FIELD(value, fname) \
2033         (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2034
2035 #define CAM_IS_INVALID(x) \
2036         (GET_FLAG(x.flags, \
2037         MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2038         (T_ETH_MAC_COMMAND_INVALIDATE))
2039
2040 /* Number of u32 elements in MC hash array */
2041 #define MC_HASH_SIZE                    8
2042 #define MC_HASH_OFFSET(bp, i)           (BAR_TSTRORM_INTMEM + \
2043         TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2044
2045
2046 #ifndef PXP2_REG_PXP2_INT_STS
2047 #define PXP2_REG_PXP2_INT_STS           PXP2_REG_PXP2_INT_STS_0
2048 #endif
2049
2050 #ifndef ETH_MAX_RX_CLIENTS_E2
2051 #define ETH_MAX_RX_CLIENTS_E2           ETH_MAX_RX_CLIENTS_E1H
2052 #endif
2053
2054 #define BNX2X_VPD_LEN                   128
2055 #define VENDOR_ID_LEN                   4
2056
2057 /* Congestion management fairness mode */
2058 #define CMNG_FNS_NONE           0
2059 #define CMNG_FNS_MINMAX         1
2060
2061 #define HC_SEG_ACCESS_DEF               0   /*Driver decision 0-3*/
2062 #define HC_SEG_ACCESS_ATTN              4
2063 #define HC_SEG_ACCESS_NORM              0   /*Driver decision 0-1*/
2064
2065 static const u32 dmae_reg_go_c[] = {
2066         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2067         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2068         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2069         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2070 };
2071
2072 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2073 void bnx2x_notify_link_changed(struct bnx2x *bp);
2074 #endif /* bnx2x.h */