?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux
[linux-btrfs-devel.git] / drivers / net / bnx2x / bnx2x_ethtool.c
blobcf3e47914dd7250063a5245ac2a9779738a3a60d
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #include <linux/ethtool.h>
18 #include <linux/netdevice.h>
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/crc32.h>
22
23
24 #include "bnx2x.h"
25 #include "bnx2x_cmn.h"
26 #include "bnx2x_dump.h"
27 #include "bnx2x_init.h"
28 #include "bnx2x_sp.h"
29
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34 #define MAX_QUEUE_NAME_LEN 4
35 static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39 } bnx2x_q_stats_arr[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
66 };
67
68 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70 static const struct {
71 long offset;
72 int size;
73 u32 flags;
74 #define STATS_FLAGS_PORT 1
75 #define STATS_FLAGS_FUNC 2
76 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78 } bnx2x_stats_arr[] = {
79 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
107 { STATS_OFFSET32(brb_drop_hi),
108 8, STATS_FLAGS_PORT, "rx_brb_discard" },
109 { STATS_OFFSET32(brb_truncate_hi),
110 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
111 { STATS_OFFSET32(pause_frames_received_hi),
112 8, STATS_FLAGS_PORT, "rx_pause_frames" },
113 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
114 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
115 { STATS_OFFSET32(nig_timer_max),
116 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
117 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
118 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
119 { STATS_OFFSET32(rx_skb_alloc_failed),
120 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
121 { STATS_OFFSET32(hw_csum_err),
122 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
123
124 { STATS_OFFSET32(total_bytes_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_bytes" },
126 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
127 8, STATS_FLAGS_PORT, "tx_error_bytes" },
128 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
130 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
132 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
134 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
135 8, STATS_FLAGS_PORT, "tx_mac_errors" },
136 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
137 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
138 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
139 8, STATS_FLAGS_PORT, "tx_single_collisions" },
140 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
141 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
143 8, STATS_FLAGS_PORT, "tx_deferred" },
144 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
147 8, STATS_FLAGS_PORT, "tx_late_collisions" },
148 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_total_collisions" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
151 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
153 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
155 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
157 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
158 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
159 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
160 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
161 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
162 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
163 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
164 { STATS_OFFSET32(pause_frames_sent_hi),
165 8, STATS_FLAGS_PORT, "tx_pause_frames" },
166 { STATS_OFFSET32(total_tpa_aggregations_hi),
167 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
168 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
169 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
170 { STATS_OFFSET32(total_tpa_bytes_hi),
171 8, STATS_FLAGS_FUNC, "tpa_bytes"}
172 };
173
174 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
175 static int bnx2x_get_port_type(struct bnx2x *bp)
176 {
177 int port_type;
178 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
179 switch (bp->link_params.phy[phy_idx].media_type) {
180 case ETH_PHY_SFP_FIBER:
181 case ETH_PHY_XFP_FIBER:
182 case ETH_PHY_KR:
183 case ETH_PHY_CX4:
184 port_type = PORT_FIBRE;
185 break;
186 case ETH_PHY_DA_TWINAX:
187 port_type = PORT_DA;
188 break;
189 case ETH_PHY_BASE_T:
190 port_type = PORT_TP;
191 break;
192 case ETH_PHY_NOT_PRESENT:
193 port_type = PORT_NONE;
194 break;
195 case ETH_PHY_UNSPECIFIED:
196 default:
197 port_type = PORT_OTHER;
198 break;
199 }
200 return port_type;
201 }
202
203 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
204 {
205 struct bnx2x *bp = netdev_priv(dev);
206 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
207
208 /* Dual Media boards present all available port types */
209 cmd->supported = bp->port.supported[cfg_idx] |
210 (bp->port.supported[cfg_idx ^ 1] &
211 (SUPPORTED_TP | SUPPORTED_FIBRE));
212 cmd->advertising = bp->port.advertising[cfg_idx];
213
214 if ((bp->state == BNX2X_STATE_OPEN) &&
215 !(bp->flags & MF_FUNC_DIS) &&
216 (bp->link_vars.link_up)) {
217 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
218 cmd->duplex = bp->link_vars.duplex;
219 } else {
220 ethtool_cmd_speed_set(
221 cmd, bp->link_params.req_line_speed[cfg_idx]);
222 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
223 }
224
225 if (IS_MF(bp))
226 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
227
228 cmd->port = bnx2x_get_port_type(bp);
229
230 cmd->phy_address = bp->mdio.prtad;
231 cmd->transceiver = XCVR_INTERNAL;
232
233 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
234 cmd->autoneg = AUTONEG_ENABLE;
235 else
236 cmd->autoneg = AUTONEG_DISABLE;
237
238 cmd->maxtxpkt = 0;
239 cmd->maxrxpkt = 0;
240
241 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
242 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n"
243 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
244 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
245 cmd->cmd, cmd->supported, cmd->advertising,
246 ethtool_cmd_speed(cmd),
247 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
248 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
249
250 return 0;
251 }
252
253 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
254 {
255 struct bnx2x *bp = netdev_priv(dev);
256 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
257 u32 speed;
258
259 if (IS_MF_SD(bp))
260 return 0;
261
262 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
263 " supported 0x%x advertising 0x%x speed %u\n"
264 " duplex %d port %d phy_address %d transceiver %d\n"
265 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
266 cmd->cmd, cmd->supported, cmd->advertising,
267 ethtool_cmd_speed(cmd),
268 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
269 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
270
271 speed = ethtool_cmd_speed(cmd);
272
273 if (IS_MF_SI(bp)) {
274 u32 part;
275 u32 line_speed = bp->link_vars.line_speed;
276
277 /* use 10G if no link detected */
278 if (!line_speed)
279 line_speed = 10000;
280
281 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
282 BNX2X_DEV_INFO("To set speed BC %X or higher "
283 "is required, please upgrade BC\n",
284 REQ_BC_VER_4_SET_MF_BW);
285 return -EINVAL;
286 }
287
288 part = (speed * 100) / line_speed;
289
290 if (line_speed < speed || !part) {
291 BNX2X_DEV_INFO("Speed setting should be in a range "
292 "from 1%% to 100%% "
293 "of actual line speed\n");
294 return -EINVAL;
295 }
296
297 if (bp->state != BNX2X_STATE_OPEN)
298 /* store value for following "load" */
299 bp->pending_max = part;
300 else
301 bnx2x_update_max_mf_config(bp, part);
302
303 return 0;
304 }
305
306 cfg_idx = bnx2x_get_link_cfg_idx(bp);
307 old_multi_phy_config = bp->link_params.multi_phy_config;
308 switch (cmd->port) {
309 case PORT_TP:
310 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
311 break; /* no port change */
312
313 if (!(bp->port.supported[0] & SUPPORTED_TP ||
314 bp->port.supported[1] & SUPPORTED_TP)) {
315 DP(NETIF_MSG_LINK, "Unsupported port type\n");
316 return -EINVAL;
317 }
318 bp->link_params.multi_phy_config &=
319 ~PORT_HW_CFG_PHY_SELECTION_MASK;
320 if (bp->link_params.multi_phy_config &
321 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
322 bp->link_params.multi_phy_config |=
323 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
324 else
325 bp->link_params.multi_phy_config |=
326 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
327 break;
328 case PORT_FIBRE:
329 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
330 break; /* no port change */
331
332 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
333 bp->port.supported[1] & SUPPORTED_FIBRE)) {
334 DP(NETIF_MSG_LINK, "Unsupported port type\n");
335 return -EINVAL;
336 }
337 bp->link_params.multi_phy_config &=
338 ~PORT_HW_CFG_PHY_SELECTION_MASK;
339 if (bp->link_params.multi_phy_config &
340 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
341 bp->link_params.multi_phy_config |=
342 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
343 else
344 bp->link_params.multi_phy_config |=
345 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
346 break;
347 default:
348 DP(NETIF_MSG_LINK, "Unsupported port type\n");
349 return -EINVAL;
350 }
351 /* Save new config in case command complete successuly */
352 new_multi_phy_config = bp->link_params.multi_phy_config;
353 /* Get the new cfg_idx */
354 cfg_idx = bnx2x_get_link_cfg_idx(bp);
355 /* Restore old config in case command failed */
356 bp->link_params.multi_phy_config = old_multi_phy_config;
357 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
358
359 if (cmd->autoneg == AUTONEG_ENABLE) {
360 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
361 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
362 return -EINVAL;
363 }
364
365 /* advertise the requested speed and duplex if supported */
366 if (cmd->advertising & ~(bp->port.supported[cfg_idx])) {
367 DP(NETIF_MSG_LINK, "Advertisement parameters "
368 "are not supported\n");
369 return -EINVAL;
370 }
371
372 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
373 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
374 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
375 cmd->advertising);
376 if (cmd->advertising) {
377
378 bp->link_params.speed_cap_mask[cfg_idx] = 0;
379 if (cmd->advertising & ADVERTISED_10baseT_Half) {
380 bp->link_params.speed_cap_mask[cfg_idx] |=
381 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
382 }
383 if (cmd->advertising & ADVERTISED_10baseT_Full)
384 bp->link_params.speed_cap_mask[cfg_idx] |=
385 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
386
387 if (cmd->advertising & ADVERTISED_100baseT_Full)
388 bp->link_params.speed_cap_mask[cfg_idx] |=
389 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
390
391 if (cmd->advertising & ADVERTISED_100baseT_Half) {
392 bp->link_params.speed_cap_mask[cfg_idx] |=
393 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
394 }
395 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
396 bp->link_params.speed_cap_mask[cfg_idx] |=
397 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
398 }
399 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
400 ADVERTISED_1000baseKX_Full))
401 bp->link_params.speed_cap_mask[cfg_idx] |=
402 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
403
404 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
405 ADVERTISED_10000baseKX4_Full |
406 ADVERTISED_10000baseKR_Full))
407 bp->link_params.speed_cap_mask[cfg_idx] |=
408 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
409 }
410 } else { /* forced speed */
411 /* advertise the requested speed and duplex if supported */
412 switch (speed) {
413 case SPEED_10:
414 if (cmd->duplex == DUPLEX_FULL) {
415 if (!(bp->port.supported[cfg_idx] &
416 SUPPORTED_10baseT_Full)) {
417 DP(NETIF_MSG_LINK,
418 "10M full not supported\n");
419 return -EINVAL;
420 }
421
422 advertising = (ADVERTISED_10baseT_Full |
423 ADVERTISED_TP);
424 } else {
425 if (!(bp->port.supported[cfg_idx] &
426 SUPPORTED_10baseT_Half)) {
427 DP(NETIF_MSG_LINK,
428 "10M half not supported\n");
429 return -EINVAL;
430 }
431
432 advertising = (ADVERTISED_10baseT_Half |
433 ADVERTISED_TP);
434 }
435 break;
436
437 case SPEED_100:
438 if (cmd->duplex == DUPLEX_FULL) {
439 if (!(bp->port.supported[cfg_idx] &
440 SUPPORTED_100baseT_Full)) {
441 DP(NETIF_MSG_LINK,
442 "100M full not supported\n");
443 return -EINVAL;
444 }
445
446 advertising = (ADVERTISED_100baseT_Full |
447 ADVERTISED_TP);
448 } else {
449 if (!(bp->port.supported[cfg_idx] &
450 SUPPORTED_100baseT_Half)) {
451 DP(NETIF_MSG_LINK,
452 "100M half not supported\n");
453 return -EINVAL;
454 }
455
456 advertising = (ADVERTISED_100baseT_Half |
457 ADVERTISED_TP);
458 }
459 break;
460
461 case SPEED_1000:
462 if (cmd->duplex != DUPLEX_FULL) {
463 DP(NETIF_MSG_LINK, "1G half not supported\n");
464 return -EINVAL;
465 }
466
467 if (!(bp->port.supported[cfg_idx] &
468 SUPPORTED_1000baseT_Full)) {
469 DP(NETIF_MSG_LINK, "1G full not supported\n");
470 return -EINVAL;
471 }
472
473 advertising = (ADVERTISED_1000baseT_Full |
474 ADVERTISED_TP);
475 break;
476
477 case SPEED_2500:
478 if (cmd->duplex != DUPLEX_FULL) {
479 DP(NETIF_MSG_LINK,
480 "2.5G half not supported\n");
481 return -EINVAL;
482 }
483
484 if (!(bp->port.supported[cfg_idx]
485 & SUPPORTED_2500baseX_Full)) {
486 DP(NETIF_MSG_LINK,
487 "2.5G full not supported\n");
488 return -EINVAL;
489 }
490
491 advertising = (ADVERTISED_2500baseX_Full |
492 ADVERTISED_TP);
493 break;
494
495 case SPEED_10000:
496 if (cmd->duplex != DUPLEX_FULL) {
497 DP(NETIF_MSG_LINK, "10G half not supported\n");
498 return -EINVAL;
499 }
500
501 if (!(bp->port.supported[cfg_idx]
502 & SUPPORTED_10000baseT_Full)) {
503 DP(NETIF_MSG_LINK, "10G full not supported\n");
504 return -EINVAL;
505 }
506
507 advertising = (ADVERTISED_10000baseT_Full |
508 ADVERTISED_FIBRE);
509 break;
510
511 default:
512 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
513 return -EINVAL;
514 }
515
516 bp->link_params.req_line_speed[cfg_idx] = speed;
517 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
518 bp->port.advertising[cfg_idx] = advertising;
519 }
520
521 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
522 DP_LEVEL " req_duplex %d advertising 0x%x\n",
523 bp->link_params.req_line_speed[cfg_idx],
524 bp->link_params.req_duplex[cfg_idx],
525 bp->port.advertising[cfg_idx]);
526
527 /* Set new config */
528 bp->link_params.multi_phy_config = new_multi_phy_config;
529 if (netif_running(dev)) {
530 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
531 bnx2x_link_set(bp);
532 }
533
534 return 0;
535 }
536
537 #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
538 #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
539 #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
540 #define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
541 #define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
542
543 static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
544 const struct reg_addr *reg_info)
545 {
546 if (CHIP_IS_E1(bp))
547 return IS_E1_ONLINE(reg_info->info);
548 else if (CHIP_IS_E1H(bp))
549 return IS_E1H_ONLINE(reg_info->info);
550 else if (CHIP_IS_E2(bp))
551 return IS_E2_ONLINE(reg_info->info);
552 else if (CHIP_IS_E3A0(bp))
553 return IS_E3_ONLINE(reg_info->info);
554 else if (CHIP_IS_E3B0(bp))
555 return IS_E3B0_ONLINE(reg_info->info);
556 else
557 return false;
558 }
559
560 /******* Paged registers info selectors ********/
561 static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
562 {
563 if (CHIP_IS_E2(bp))
564 return page_vals_e2;
565 else if (CHIP_IS_E3(bp))
566 return page_vals_e3;
567 else
568 return NULL;
569 }
570
571 static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
572 {
573 if (CHIP_IS_E2(bp))
574 return PAGE_MODE_VALUES_E2;
575 else if (CHIP_IS_E3(bp))
576 return PAGE_MODE_VALUES_E3;
577 else
578 return 0;
579 }
580
581 static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
582 {
583 if (CHIP_IS_E2(bp))
584 return page_write_regs_e2;
585 else if (CHIP_IS_E3(bp))
586 return page_write_regs_e3;
587 else
588 return NULL;
589 }
590
591 static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
592 {
593 if (CHIP_IS_E2(bp))
594 return PAGE_WRITE_REGS_E2;
595 else if (CHIP_IS_E3(bp))
596 return PAGE_WRITE_REGS_E3;
597 else
598 return 0;
599 }
600
601 static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
602 {
603 if (CHIP_IS_E2(bp))
604 return page_read_regs_e2;
605 else if (CHIP_IS_E3(bp))
606 return page_read_regs_e3;
607 else
608 return NULL;
609 }
610
611 static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
612 {
613 if (CHIP_IS_E2(bp))
614 return PAGE_READ_REGS_E2;
615 else if (CHIP_IS_E3(bp))
616 return PAGE_READ_REGS_E3;
617 else
618 return 0;
619 }
620
621 static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
622 {
623 int num_pages = __bnx2x_get_page_reg_num(bp);
624 int page_write_num = __bnx2x_get_page_write_num(bp);
625 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
626 int page_read_num = __bnx2x_get_page_read_num(bp);
627 int regdump_len = 0;
628 int i, j, k;
629
630 for (i = 0; i < REGS_COUNT; i++)
631 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
632 regdump_len += reg_addrs[i].size;
633
634 for (i = 0; i < num_pages; i++)
635 for (j = 0; j < page_write_num; j++)
636 for (k = 0; k < page_read_num; k++)
637 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
638 regdump_len += page_read_addr[k].size;
639
640 return regdump_len;
641 }
642
643 static int bnx2x_get_regs_len(struct net_device *dev)
644 {
645 struct bnx2x *bp = netdev_priv(dev);
646 int regdump_len = 0;
647
648 regdump_len = __bnx2x_get_regs_len(bp);
649 regdump_len *= 4;
650 regdump_len += sizeof(struct dump_hdr);
651
652 return regdump_len;
653 }
654
655 /**
656 * bnx2x_read_pages_regs - read "paged" registers
657 *
658 * @bp device handle
659 * @p output buffer
660 *
661 * Reads "paged" memories: memories that may only be read by first writing to a
662 * specific address ("write address") and then reading from a specific address
663 * ("read address"). There may be more than one write address per "page" and
664 * more than one read address per write address.
665 */
666 static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
667 {
668 u32 i, j, k, n;
669 /* addresses of the paged registers */
670 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
671 /* number of paged registers */
672 int num_pages = __bnx2x_get_page_reg_num(bp);
673 /* write addresses */
674 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
675 /* number of write addresses */
676 int write_num = __bnx2x_get_page_write_num(bp);
677 /* read addresses info */
678 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
679 /* number of read addresses */
680 int read_num = __bnx2x_get_page_read_num(bp);
681
682 for (i = 0; i < num_pages; i++) {
683 for (j = 0; j < write_num; j++) {
684 REG_WR(bp, write_addr[j], page_addr[i]);
685 for (k = 0; k < read_num; k++)
686 if (bnx2x_is_reg_online(bp, &read_addr[k]))
687 for (n = 0; n <
688 read_addr[k].size; n++)
689 *p++ = REG_RD(bp,
690 read_addr[k].addr + n*4);
691 }
692 }
693 }
694
695 static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
696 {
697 u32 i, j;
698
699 /* Read the regular registers */
700 for (i = 0; i < REGS_COUNT; i++)
701 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
702 for (j = 0; j < reg_addrs[i].size; j++)
703 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
704
705 /* Read "paged" registes */
706 bnx2x_read_pages_regs(bp, p);
707 }
708
709 static void bnx2x_get_regs(struct net_device *dev,
710 struct ethtool_regs *regs, void *_p)
711 {
712 u32 *p = _p;
713 struct bnx2x *bp = netdev_priv(dev);
714 struct dump_hdr dump_hdr = {0};
715
716 regs->version = 0;
717 memset(p, 0, regs->len);
718
719 if (!netif_running(bp->dev))
720 return;
721
722 /* Disable parity attentions as long as following dump may
723 * cause false alarms by reading never written registers. We
724 * will re-enable parity attentions right after the dump.
725 */
726 bnx2x_disable_blocks_parity(bp);
727
728 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
729 dump_hdr.dump_sign = dump_sign_all;
730 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
731 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
732 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
733 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
734
735 if (CHIP_IS_E1(bp))
736 dump_hdr.info = RI_E1_ONLINE;
737 else if (CHIP_IS_E1H(bp))
738 dump_hdr.info = RI_E1H_ONLINE;
739 else if (!CHIP_IS_E1x(bp))
740 dump_hdr.info = RI_E2_ONLINE |
741 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
742
743 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
744 p += dump_hdr.hdr_size + 1;
745
746 /* Actually read the registers */
747 __bnx2x_get_regs(bp, p);
748
749 /* Re-enable parity attentions */
750 bnx2x_clear_blocks_parity(bp);
751 bnx2x_enable_blocks_parity(bp);
752 }
753
754 static void bnx2x_get_drvinfo(struct net_device *dev,
755 struct ethtool_drvinfo *info)
756 {
757 struct bnx2x *bp = netdev_priv(dev);
758 u8 phy_fw_ver[PHY_FW_VER_LEN];
759
760 strcpy(info->driver, DRV_MODULE_NAME);
761 strcpy(info->version, DRV_MODULE_VERSION);
762
763 phy_fw_ver[0] = '\0';
764 if (bp->port.pmf) {
765 bnx2x_acquire_phy_lock(bp);
766 bnx2x_get_ext_phy_fw_version(&bp->link_params,
767 (bp->state != BNX2X_STATE_CLOSED),
768 phy_fw_ver, PHY_FW_VER_LEN);
769 bnx2x_release_phy_lock(bp);
770 }
771
772 strncpy(info->fw_version, bp->fw_ver, 32);
773 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
774 "bc %d.%d.%d%s%s",
775 (bp->common.bc_ver & 0xff0000) >> 16,
776 (bp->common.bc_ver & 0xff00) >> 8,
777 (bp->common.bc_ver & 0xff),
778 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
779 strcpy(info->bus_info, pci_name(bp->pdev));
780 info->n_stats = BNX2X_NUM_STATS;
781 info->testinfo_len = BNX2X_NUM_TESTS;
782 info->eedump_len = bp->common.flash_size;
783 info->regdump_len = bnx2x_get_regs_len(dev);
784 }
785
786 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
787 {
788 struct bnx2x *bp = netdev_priv(dev);
789
790 if (bp->flags & NO_WOL_FLAG) {
791 wol->supported = 0;
792 wol->wolopts = 0;
793 } else {
794 wol->supported = WAKE_MAGIC;
795 if (bp->wol)
796 wol->wolopts = WAKE_MAGIC;
797 else
798 wol->wolopts = 0;
799 }
800 memset(&wol->sopass, 0, sizeof(wol->sopass));
801 }
802
803 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
804 {
805 struct bnx2x *bp = netdev_priv(dev);
806
807 if (wol->wolopts & ~WAKE_MAGIC)
808 return -EINVAL;
809
810 if (wol->wolopts & WAKE_MAGIC) {
811 if (bp->flags & NO_WOL_FLAG)
812 return -EINVAL;
813
814 bp->wol = 1;
815 } else
816 bp->wol = 0;
817
818 return 0;
819 }
820
821 static u32 bnx2x_get_msglevel(struct net_device *dev)
822 {
823 struct bnx2x *bp = netdev_priv(dev);
824
825 return bp->msg_enable;
826 }
827
828 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
829 {
830 struct bnx2x *bp = netdev_priv(dev);
831
832 if (capable(CAP_NET_ADMIN)) {
833 /* dump MCP trace */
834 if (level & BNX2X_MSG_MCP)
835 bnx2x_fw_dump_lvl(bp, KERN_INFO);
836 bp->msg_enable = level;
837 }
838 }
839
840 static int bnx2x_nway_reset(struct net_device *dev)
841 {
842 struct bnx2x *bp = netdev_priv(dev);
843
844 if (!bp->port.pmf)
845 return 0;
846
847 if (netif_running(dev)) {
848 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
849 bnx2x_link_set(bp);
850 }
851
852 return 0;
853 }
854
855 static u32 bnx2x_get_link(struct net_device *dev)
856 {
857 struct bnx2x *bp = netdev_priv(dev);
858
859 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
860 return 0;
861
862 return bp->link_vars.link_up;
863 }
864
865 static int bnx2x_get_eeprom_len(struct net_device *dev)
866 {
867 struct bnx2x *bp = netdev_priv(dev);
868
869 return bp->common.flash_size;
870 }
871
872 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
873 {
874 int port = BP_PORT(bp);
875 int count, i;
876 u32 val = 0;
877
878 /* adjust timeout for emulation/FPGA */
879 count = BNX2X_NVRAM_TIMEOUT_COUNT;
880 if (CHIP_REV_IS_SLOW(bp))
881 count *= 100;
882
883 /* request access to nvram interface */
884 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
885 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
886
887 for (i = 0; i < count*10; i++) {
888 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
889 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
890 break;
891
892 udelay(5);
893 }
894
895 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
896 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
897 return -EBUSY;
898 }
899
900 return 0;
901 }
902
903 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
904 {
905 int port = BP_PORT(bp);
906 int count, i;
907 u32 val = 0;
908
909 /* adjust timeout for emulation/FPGA */
910 count = BNX2X_NVRAM_TIMEOUT_COUNT;
911 if (CHIP_REV_IS_SLOW(bp))
912 count *= 100;
913
914 /* relinquish nvram interface */
915 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
916 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
917
918 for (i = 0; i < count*10; i++) {
919 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
920 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
921 break;
922
923 udelay(5);
924 }
925
926 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
927 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
928 return -EBUSY;
929 }
930
931 return 0;
932 }
933
934 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
935 {
936 u32 val;
937
938 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
939
940 /* enable both bits, even on read */
941 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
942 (val | MCPR_NVM_ACCESS_ENABLE_EN |
943 MCPR_NVM_ACCESS_ENABLE_WR_EN));
944 }
945
946 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
947 {
948 u32 val;
949
950 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
951
952 /* disable both bits, even after read */
953 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
954 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
955 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
956 }
957
958 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
959 u32 cmd_flags)
960 {
961 int count, i, rc;
962 u32 val;
963
964 /* build the command word */
965 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
966
967 /* need to clear DONE bit separately */
968 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
969
970 /* address of the NVRAM to read from */
971 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
972 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
973
974 /* issue a read command */
975 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
976
977 /* adjust timeout for emulation/FPGA */
978 count = BNX2X_NVRAM_TIMEOUT_COUNT;
979 if (CHIP_REV_IS_SLOW(bp))
980 count *= 100;
981
982 /* wait for completion */
983 *ret_val = 0;
984 rc = -EBUSY;
985 for (i = 0; i < count; i++) {
986 udelay(5);
987 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
988
989 if (val & MCPR_NVM_COMMAND_DONE) {
990 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
991 /* we read nvram data in cpu order
992 * but ethtool sees it as an array of bytes
993 * converting to big-endian will do the work */
994 *ret_val = cpu_to_be32(val);
995 rc = 0;
996 break;
997 }
998 }
999
1000 return rc;
1001 }
1002
1003 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1004 int buf_size)
1005 {
1006 int rc;
1007 u32 cmd_flags;
1008 __be32 val;
1009
1010 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1011 DP(BNX2X_MSG_NVM,
1012 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1013 offset, buf_size);
1014 return -EINVAL;
1015 }
1016
1017 if (offset + buf_size > bp->common.flash_size) {
1018 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1019 " buf_size (0x%x) > flash_size (0x%x)\n",
1020 offset, buf_size, bp->common.flash_size);
1021 return -EINVAL;
1022 }
1023
1024 /* request access to nvram interface */
1025 rc = bnx2x_acquire_nvram_lock(bp);
1026 if (rc)
1027 return rc;
1028
1029 /* enable access to nvram interface */
1030 bnx2x_enable_nvram_access(bp);
1031
1032 /* read the first word(s) */
1033 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1034 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1035 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1036 memcpy(ret_buf, &val, 4);
1037
1038 /* advance to the next dword */
1039 offset += sizeof(u32);
1040 ret_buf += sizeof(u32);
1041 buf_size -= sizeof(u32);
1042 cmd_flags = 0;
1043 }
1044
1045 if (rc == 0) {
1046 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1047 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1048 memcpy(ret_buf, &val, 4);
1049 }
1050
1051 /* disable access to nvram interface */
1052 bnx2x_disable_nvram_access(bp);
1053 bnx2x_release_nvram_lock(bp);
1054
1055 return rc;
1056 }
1057
1058 static int bnx2x_get_eeprom(struct net_device *dev,
1059 struct ethtool_eeprom *eeprom, u8 *eebuf)
1060 {
1061 struct bnx2x *bp = netdev_priv(dev);
1062 int rc;
1063
1064 if (!netif_running(dev))
1065 return -EAGAIN;
1066
1067 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1068 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1069 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1070 eeprom->len, eeprom->len);
1071
1072 /* parameters already validated in ethtool_get_eeprom */
1073
1074 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1075
1076 return rc;
1077 }
1078
1079 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1080 u32 cmd_flags)
1081 {
1082 int count, i, rc;
1083
1084 /* build the command word */
1085 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1086
1087 /* need to clear DONE bit separately */
1088 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1089
1090 /* write the data */
1091 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1092
1093 /* address of the NVRAM to write to */
1094 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1095 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1096
1097 /* issue the write command */
1098 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1099
1100 /* adjust timeout for emulation/FPGA */
1101 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1102 if (CHIP_REV_IS_SLOW(bp))
1103 count *= 100;
1104
1105 /* wait for completion */
1106 rc = -EBUSY;
1107 for (i = 0; i < count; i++) {
1108 udelay(5);
1109 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1110 if (val & MCPR_NVM_COMMAND_DONE) {
1111 rc = 0;
1112 break;
1113 }
1114 }
1115
1116 return rc;
1117 }
1118
1119 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1120
1121 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1122 int buf_size)
1123 {
1124 int rc;
1125 u32 cmd_flags;
1126 u32 align_offset;
1127 __be32 val;
1128
1129 if (offset + buf_size > bp->common.flash_size) {
1130 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1131 " buf_size (0x%x) > flash_size (0x%x)\n",
1132 offset, buf_size, bp->common.flash_size);
1133 return -EINVAL;
1134 }
1135
1136 /* request access to nvram interface */
1137 rc = bnx2x_acquire_nvram_lock(bp);
1138 if (rc)
1139 return rc;
1140
1141 /* enable access to nvram interface */
1142 bnx2x_enable_nvram_access(bp);
1143
1144 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1145 align_offset = (offset & ~0x03);
1146 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1147
1148 if (rc == 0) {
1149 val &= ~(0xff << BYTE_OFFSET(offset));
1150 val |= (*data_buf << BYTE_OFFSET(offset));
1151
1152 /* nvram data is returned as an array of bytes
1153 * convert it back to cpu order */
1154 val = be32_to_cpu(val);
1155
1156 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1157 cmd_flags);
1158 }
1159
1160 /* disable access to nvram interface */
1161 bnx2x_disable_nvram_access(bp);
1162 bnx2x_release_nvram_lock(bp);
1163
1164 return rc;
1165 }
1166
1167 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1168 int buf_size)
1169 {
1170 int rc;
1171 u32 cmd_flags;
1172 u32 val;
1173 u32 written_so_far;
1174
1175 if (buf_size == 1) /* ethtool */
1176 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1177
1178 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1179 DP(BNX2X_MSG_NVM,
1180 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1181 offset, buf_size);
1182 return -EINVAL;
1183 }
1184
1185 if (offset + buf_size > bp->common.flash_size) {
1186 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1187 " buf_size (0x%x) > flash_size (0x%x)\n",
1188 offset, buf_size, bp->common.flash_size);
1189 return -EINVAL;
1190 }
1191
1192 /* request access to nvram interface */
1193 rc = bnx2x_acquire_nvram_lock(bp);
1194 if (rc)
1195 return rc;
1196
1197 /* enable access to nvram interface */
1198 bnx2x_enable_nvram_access(bp);
1199
1200 written_so_far = 0;
1201 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1202 while ((written_so_far < buf_size) && (rc == 0)) {
1203 if (written_so_far == (buf_size - sizeof(u32)))
1204 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1205 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1206 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1207 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1208 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1209
1210 memcpy(&val, data_buf, 4);
1211
1212 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1213
1214 /* advance to the next dword */
1215 offset += sizeof(u32);
1216 data_buf += sizeof(u32);
1217 written_so_far += sizeof(u32);
1218 cmd_flags = 0;
1219 }
1220
1221 /* disable access to nvram interface */
1222 bnx2x_disable_nvram_access(bp);
1223 bnx2x_release_nvram_lock(bp);
1224
1225 return rc;
1226 }
1227
1228 static int bnx2x_set_eeprom(struct net_device *dev,
1229 struct ethtool_eeprom *eeprom, u8 *eebuf)
1230 {
1231 struct bnx2x *bp = netdev_priv(dev);
1232 int port = BP_PORT(bp);
1233 int rc = 0;
1234 u32 ext_phy_config;
1235 if (!netif_running(dev))
1236 return -EAGAIN;
1237
1238 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1239 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1240 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1241 eeprom->len, eeprom->len);
1242
1243 /* parameters already validated in ethtool_set_eeprom */
1244
1245 /* PHY eeprom can be accessed only by the PMF */
1246 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1247 !bp->port.pmf)
1248 return -EINVAL;
1249
1250 ext_phy_config =
1251 SHMEM_RD(bp,
1252 dev_info.port_hw_config[port].external_phy_config);
1253
1254 if (eeprom->magic == 0x50485950) {
1255 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1256 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1257
1258 bnx2x_acquire_phy_lock(bp);
1259 rc |= bnx2x_link_reset(&bp->link_params,
1260 &bp->link_vars, 0);
1261 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1262 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1263 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1264 MISC_REGISTERS_GPIO_HIGH, port);
1265 bnx2x_release_phy_lock(bp);
1266 bnx2x_link_report(bp);
1267
1268 } else if (eeprom->magic == 0x50485952) {
1269 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1270 if (bp->state == BNX2X_STATE_OPEN) {
1271 bnx2x_acquire_phy_lock(bp);
1272 rc |= bnx2x_link_reset(&bp->link_params,
1273 &bp->link_vars, 1);
1274
1275 rc |= bnx2x_phy_init(&bp->link_params,
1276 &bp->link_vars);
1277 bnx2x_release_phy_lock(bp);
1278 bnx2x_calc_fc_adv(bp);
1279 }
1280 } else if (eeprom->magic == 0x53985943) {
1281 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1282 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1283 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1284
1285 /* DSP Remove Download Mode */
1286 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1287 MISC_REGISTERS_GPIO_LOW, port);
1288
1289 bnx2x_acquire_phy_lock(bp);
1290
1291 bnx2x_sfx7101_sp_sw_reset(bp,
1292 &bp->link_params.phy[EXT_PHY1]);
1293
1294 /* wait 0.5 sec to allow it to run */
1295 msleep(500);
1296 bnx2x_ext_phy_hw_reset(bp, port);
1297 msleep(500);
1298 bnx2x_release_phy_lock(bp);
1299 }
1300 } else
1301 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1302
1303 return rc;
1304 }
1305
1306 static int bnx2x_get_coalesce(struct net_device *dev,
1307 struct ethtool_coalesce *coal)
1308 {
1309 struct bnx2x *bp = netdev_priv(dev);
1310
1311 memset(coal, 0, sizeof(struct ethtool_coalesce));
1312
1313 coal->rx_coalesce_usecs = bp->rx_ticks;
1314 coal->tx_coalesce_usecs = bp->tx_ticks;
1315
1316 return 0;
1317 }
1318
1319 static int bnx2x_set_coalesce(struct net_device *dev,
1320 struct ethtool_coalesce *coal)
1321 {
1322 struct bnx2x *bp = netdev_priv(dev);
1323
1324 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1325 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1326 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1327
1328 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1329 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1330 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1331
1332 if (netif_running(dev))
1333 bnx2x_update_coalesce(bp);
1334
1335 return 0;
1336 }
1337
1338 static void bnx2x_get_ringparam(struct net_device *dev,
1339 struct ethtool_ringparam *ering)
1340 {
1341 struct bnx2x *bp = netdev_priv(dev);
1342
1343 ering->rx_max_pending = MAX_RX_AVAIL;
1344 ering->rx_mini_max_pending = 0;
1345 ering->rx_jumbo_max_pending = 0;
1346
1347 if (bp->rx_ring_size)
1348 ering->rx_pending = bp->rx_ring_size;
1349 else
1350 ering->rx_pending = MAX_RX_AVAIL;
1351
1352 ering->rx_mini_pending = 0;
1353 ering->rx_jumbo_pending = 0;
1354
1355 ering->tx_max_pending = MAX_TX_AVAIL;
1356 ering->tx_pending = bp->tx_ring_size;
1357 }
1358
1359 static int bnx2x_set_ringparam(struct net_device *dev,
1360 struct ethtool_ringparam *ering)
1361 {
1362 struct bnx2x *bp = netdev_priv(dev);
1363
1364 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1365 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1366 return -EAGAIN;
1367 }
1368
1369 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1370 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1371 MIN_RX_SIZE_TPA)) ||
1372 (ering->tx_pending > MAX_TX_AVAIL) ||
1373 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1374 return -EINVAL;
1375
1376 bp->rx_ring_size = ering->rx_pending;
1377 bp->tx_ring_size = ering->tx_pending;
1378
1379 return bnx2x_reload_if_running(dev);
1380 }
1381
1382 static void bnx2x_get_pauseparam(struct net_device *dev,
1383 struct ethtool_pauseparam *epause)
1384 {
1385 struct bnx2x *bp = netdev_priv(dev);
1386 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1387 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1388 BNX2X_FLOW_CTRL_AUTO);
1389
1390 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1391 BNX2X_FLOW_CTRL_RX);
1392 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1393 BNX2X_FLOW_CTRL_TX);
1394
1395 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1396 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1397 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1398 }
1399
1400 static int bnx2x_set_pauseparam(struct net_device *dev,
1401 struct ethtool_pauseparam *epause)
1402 {
1403 struct bnx2x *bp = netdev_priv(dev);
1404 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1405 if (IS_MF(bp))
1406 return 0;
1407
1408 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1409 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1410 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1411
1412 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1413
1414 if (epause->rx_pause)
1415 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1416
1417 if (epause->tx_pause)
1418 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1419
1420 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1421 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1422
1423 if (epause->autoneg) {
1424 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1425 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1426 return -EINVAL;
1427 }
1428
1429 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1430 bp->link_params.req_flow_ctrl[cfg_idx] =
1431 BNX2X_FLOW_CTRL_AUTO;
1432 }
1433 }
1434
1435 DP(NETIF_MSG_LINK,
1436 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1437
1438 if (netif_running(dev)) {
1439 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1440 bnx2x_link_set(bp);
1441 }
1442
1443 return 0;
1444 }
1445
1446 static const struct {
1447 char string[ETH_GSTRING_LEN];
1448 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1449 { "register_test (offline)" },
1450 { "memory_test (offline)" },
1451 { "loopback_test (offline)" },
1452 { "nvram_test (online)" },
1453 { "interrupt_test (online)" },
1454 { "link_test (online)" },
1455 { "idle check (online)" }
1456 };
1457
1458 enum {
1459 BNX2X_CHIP_E1_OFST = 0,
1460 BNX2X_CHIP_E1H_OFST,
1461 BNX2X_CHIP_E2_OFST,
1462 BNX2X_CHIP_E3_OFST,
1463 BNX2X_CHIP_E3B0_OFST,
1464 BNX2X_CHIP_MAX_OFST
1465 };
1466
1467 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1468 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1469 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1470 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1471 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1472
1473 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1474 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1475
1476 static int bnx2x_test_registers(struct bnx2x *bp)
1477 {
1478 int idx, i, rc = -ENODEV;
1479 u32 wr_val = 0, hw;
1480 int port = BP_PORT(bp);
1481 static const struct {
1482 u32 hw;
1483 u32 offset0;
1484 u32 offset1;
1485 u32 mask;
1486 } reg_tbl[] = {
1487 /* 0 */ { BNX2X_CHIP_MASK_ALL,
1488 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1489 { BNX2X_CHIP_MASK_ALL,
1490 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1491 { BNX2X_CHIP_MASK_E1X,
1492 HC_REG_AGG_INT_0, 4, 0x000003ff },
1493 { BNX2X_CHIP_MASK_ALL,
1494 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1495 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1496 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1497 { BNX2X_CHIP_MASK_E3B0,
1498 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1499 { BNX2X_CHIP_MASK_ALL,
1500 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1501 { BNX2X_CHIP_MASK_ALL,
1502 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1503 { BNX2X_CHIP_MASK_ALL,
1504 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1505 { BNX2X_CHIP_MASK_ALL,
1506 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1507 /* 10 */ { BNX2X_CHIP_MASK_ALL,
1508 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1509 { BNX2X_CHIP_MASK_ALL,
1510 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1511 { BNX2X_CHIP_MASK_ALL,
1512 QM_REG_CONNNUM_0, 4, 0x000fffff },
1513 { BNX2X_CHIP_MASK_ALL,
1514 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1515 { BNX2X_CHIP_MASK_ALL,
1516 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1517 { BNX2X_CHIP_MASK_ALL,
1518 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1519 { BNX2X_CHIP_MASK_ALL,
1520 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1521 { BNX2X_CHIP_MASK_ALL,
1522 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1523 { BNX2X_CHIP_MASK_ALL,
1524 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1525 { BNX2X_CHIP_MASK_ALL,
1526 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1527 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1528 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1529 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1530 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1531 { BNX2X_CHIP_MASK_ALL,
1532 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1533 { BNX2X_CHIP_MASK_ALL,
1534 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1535 { BNX2X_CHIP_MASK_ALL,
1536 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1537 { BNX2X_CHIP_MASK_ALL,
1538 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1539 { BNX2X_CHIP_MASK_ALL,
1540 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1541 { BNX2X_CHIP_MASK_ALL,
1542 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1543 { BNX2X_CHIP_MASK_ALL,
1544 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1545 { BNX2X_CHIP_MASK_ALL,
1546 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1547 /* 30 */ { BNX2X_CHIP_MASK_ALL,
1548 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1549 { BNX2X_CHIP_MASK_ALL,
1550 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1551 { BNX2X_CHIP_MASK_ALL,
1552 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1553 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1554 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1555 { BNX2X_CHIP_MASK_ALL,
1556 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1557 { BNX2X_CHIP_MASK_ALL,
1558 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1559 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1560 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1561 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1562 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1563
1564 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1565 };
1566
1567 if (!netif_running(bp->dev))
1568 return rc;
1569
1570 if (CHIP_IS_E1(bp))
1571 hw = BNX2X_CHIP_MASK_E1;
1572 else if (CHIP_IS_E1H(bp))
1573 hw = BNX2X_CHIP_MASK_E1H;
1574 else if (CHIP_IS_E2(bp))
1575 hw = BNX2X_CHIP_MASK_E2;
1576 else if (CHIP_IS_E3B0(bp))
1577 hw = BNX2X_CHIP_MASK_E3B0;
1578 else /* e3 A0 */
1579 hw = BNX2X_CHIP_MASK_E3;
1580
1581 /* Repeat the test twice:
1582 First by writing 0x00000000, second by writing 0xffffffff */
1583 for (idx = 0; idx < 2; idx++) {
1584
1585 switch (idx) {
1586 case 0:
1587 wr_val = 0;
1588 break;
1589 case 1:
1590 wr_val = 0xffffffff;
1591 break;
1592 }
1593
1594 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1595 u32 offset, mask, save_val, val;
1596 if (!(hw & reg_tbl[i].hw))
1597 continue;
1598
1599 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1600 mask = reg_tbl[i].mask;
1601
1602 save_val = REG_RD(bp, offset);
1603
1604 REG_WR(bp, offset, wr_val & mask);
1605
1606 val = REG_RD(bp, offset);
1607
1608 /* Restore the original register's value */
1609 REG_WR(bp, offset, save_val);
1610
1611 /* verify value is as expected */
1612 if ((val & mask) != (wr_val & mask)) {
1613 DP(NETIF_MSG_HW,
1614 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1615 offset, val, wr_val, mask);
1616 goto test_reg_exit;
1617 }
1618 }
1619 }
1620
1621 rc = 0;
1622
1623 test_reg_exit:
1624 return rc;
1625 }
1626
1627 static int bnx2x_test_memory(struct bnx2x *bp)
1628 {
1629 int i, j, rc = -ENODEV;
1630 u32 val, index;
1631 static const struct {
1632 u32 offset;
1633 int size;
1634 } mem_tbl[] = {
1635 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1636 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1637 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1638 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1639 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1640 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1641 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1642
1643 { 0xffffffff, 0 }
1644 };
1645
1646 static const struct {
1647 char *name;
1648 u32 offset;
1649 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1650 } prty_tbl[] = {
1651 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1652 {0x3ffc0, 0, 0, 0} },
1653 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1654 {0x2, 0x2, 0, 0} },
1655 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1656 {0, 0, 0, 0} },
1657 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1658 {0x3ffc0, 0, 0, 0} },
1659 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1660 {0x3ffc0, 0, 0, 0} },
1661 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1662 {0x3ffc1, 0, 0, 0} },
1663
1664 { NULL, 0xffffffff, {0, 0, 0, 0} }
1665 };
1666
1667 if (!netif_running(bp->dev))
1668 return rc;
1669
1670 if (CHIP_IS_E1(bp))
1671 index = BNX2X_CHIP_E1_OFST;
1672 else if (CHIP_IS_E1H(bp))
1673 index = BNX2X_CHIP_E1H_OFST;
1674 else if (CHIP_IS_E2(bp))
1675 index = BNX2X_CHIP_E2_OFST;
1676 else /* e3 */
1677 index = BNX2X_CHIP_E3_OFST;
1678
1679 /* pre-Check the parity status */
1680 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1681 val = REG_RD(bp, prty_tbl[i].offset);
1682 if (val & ~(prty_tbl[i].hw_mask[index])) {
1683 DP(NETIF_MSG_HW,
1684 "%s is 0x%x\n", prty_tbl[i].name, val);
1685 goto test_mem_exit;
1686 }
1687 }
1688
1689 /* Go through all the memories */
1690 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1691 for (j = 0; j < mem_tbl[i].size; j++)
1692 REG_RD(bp, mem_tbl[i].offset + j*4);
1693
1694 /* Check the parity status */
1695 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1696 val = REG_RD(bp, prty_tbl[i].offset);
1697 if (val & ~(prty_tbl[i].hw_mask[index])) {
1698 DP(NETIF_MSG_HW,
1699 "%s is 0x%x\n", prty_tbl[i].name, val);
1700 goto test_mem_exit;
1701 }
1702 }
1703
1704 rc = 0;
1705
1706 test_mem_exit:
1707 return rc;
1708 }
1709
1710 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1711 {
1712 int cnt = 1400;
1713
1714 if (link_up) {
1715 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1716 msleep(20);
1717
1718 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1719 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1720 }
1721 }
1722
1723 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1724 {
1725 unsigned int pkt_size, num_pkts, i;
1726 struct sk_buff *skb;
1727 unsigned char *packet;
1728 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1729 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1730 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
1731 u16 tx_start_idx, tx_idx;
1732 u16 rx_start_idx, rx_idx;
1733 u16 pkt_prod, bd_prod, rx_comp_cons;
1734 struct sw_tx_bd *tx_buf;
1735 struct eth_tx_start_bd *tx_start_bd;
1736 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1737 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
1738 dma_addr_t mapping;
1739 union eth_rx_cqe *cqe;
1740 u8 cqe_fp_flags, cqe_fp_type;
1741 struct sw_rx_bd *rx_buf;
1742 u16 len;
1743 int rc = -ENODEV;
1744
1745 /* check the loopback mode */
1746 switch (loopback_mode) {
1747 case BNX2X_PHY_LOOPBACK:
1748 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1749 return -EINVAL;
1750 break;
1751 case BNX2X_MAC_LOOPBACK:
1752 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ?
1753 LOOPBACK_XMAC : LOOPBACK_BMAC;
1754 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1755 break;
1756 default:
1757 return -EINVAL;
1758 }
1759
1760 /* prepare the loopback packet */
1761 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1762 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1763 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1764 if (!skb) {
1765 rc = -ENOMEM;
1766 goto test_loopback_exit;
1767 }
1768 packet = skb_put(skb, pkt_size);
1769 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1770 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1771 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1772 for (i = ETH_HLEN; i < pkt_size; i++)
1773 packet[i] = (unsigned char) (i & 0xff);
1774 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1775 skb_headlen(skb), DMA_TO_DEVICE);
1776 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1777 rc = -ENOMEM;
1778 dev_kfree_skb(skb);
1779 BNX2X_ERR("Unable to map SKB\n");
1780 goto test_loopback_exit;
1781 }
1782
1783 /* send the loopback packet */
1784 num_pkts = 0;
1785 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
1786 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1787
1788 pkt_prod = txdata->tx_pkt_prod++;
1789 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1790 tx_buf->first_bd = txdata->tx_bd_prod;
1791 tx_buf->skb = skb;
1792 tx_buf->flags = 0;
1793
1794 bd_prod = TX_BD(txdata->tx_bd_prod);
1795 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
1796 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1797 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1798 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1799 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1800 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1801 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1802 SET_FLAG(tx_start_bd->general_data,
1803 ETH_TX_START_BD_ETH_ADDR_TYPE,
1804 UNICAST_ADDRESS);
1805 SET_FLAG(tx_start_bd->general_data,
1806 ETH_TX_START_BD_HDR_NBDS,
1807 1);
1808
1809 /* turn on parsing and get a BD */
1810 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1811
1812 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1813 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
1814
1815 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1816 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1817
1818 wmb();
1819
1820 txdata->tx_db.data.prod += 2;
1821 barrier();
1822 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
1823
1824 mmiowb();
1825 barrier();
1826
1827 num_pkts++;
1828 txdata->tx_bd_prod += 2; /* start + pbd */
1829
1830 udelay(100);
1831
1832 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
1833 if (tx_idx != tx_start_idx + num_pkts)
1834 goto test_loopback_exit;
1835
1836 /* Unlike HC IGU won't generate an interrupt for status block
1837 * updates that have been performed while interrupts were
1838 * disabled.
1839 */
1840 if (bp->common.int_block == INT_BLOCK_IGU) {
1841 /* Disable local BHes to prevent a dead-lock situation between
1842 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1843 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1844 */
1845 local_bh_disable();
1846 bnx2x_tx_int(bp, txdata);
1847 local_bh_enable();
1848 }
1849
1850 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1851 if (rx_idx != rx_start_idx + num_pkts)
1852 goto test_loopback_exit;
1853
1854 rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1855 cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
1856 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1857 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1858 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1859 goto test_loopback_rx_exit;
1860
1861 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1862 if (len != pkt_size)
1863 goto test_loopback_rx_exit;
1864
1865 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1866 dma_sync_single_for_cpu(&bp->pdev->dev,
1867 dma_unmap_addr(rx_buf, mapping),
1868 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
1869 skb = rx_buf->skb;
1870 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1871 for (i = ETH_HLEN; i < pkt_size; i++)
1872 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1873 goto test_loopback_rx_exit;
1874
1875 rc = 0;
1876
1877 test_loopback_rx_exit:
1878
1879 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1880 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1881 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1882 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1883
1884 /* Update producers */
1885 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1886 fp_rx->rx_sge_prod);
1887
1888 test_loopback_exit:
1889 bp->link_params.loopback_mode = LOOPBACK_NONE;
1890
1891 return rc;
1892 }
1893
1894 static int bnx2x_test_loopback(struct bnx2x *bp)
1895 {
1896 int rc = 0, res;
1897
1898 if (BP_NOMCP(bp))
1899 return rc;
1900
1901 if (!netif_running(bp->dev))
1902 return BNX2X_LOOPBACK_FAILED;
1903
1904 bnx2x_netif_stop(bp, 1);
1905 bnx2x_acquire_phy_lock(bp);
1906
1907 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
1908 if (res) {
1909 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1910 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1911 }
1912
1913 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
1914 if (res) {
1915 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1916 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1917 }
1918
1919 bnx2x_release_phy_lock(bp);
1920 bnx2x_netif_start(bp);
1921
1922 return rc;
1923 }
1924
1925 #define CRC32_RESIDUAL 0xdebb20e3
1926
1927 static int bnx2x_test_nvram(struct bnx2x *bp)
1928 {
1929 static const struct {
1930 int offset;
1931 int size;
1932 } nvram_tbl[] = {
1933 { 0, 0x14 }, /* bootstrap */
1934 { 0x14, 0xec }, /* dir */
1935 { 0x100, 0x350 }, /* manuf_info */
1936 { 0x450, 0xf0 }, /* feature_info */
1937 { 0x640, 0x64 }, /* upgrade_key_info */
1938 { 0x708, 0x70 }, /* manuf_key_info */
1939 { 0, 0 }
1940 };
1941 __be32 buf[0x350 / 4];
1942 u8 *data = (u8 *)buf;
1943 int i, rc;
1944 u32 magic, crc;
1945
1946 if (BP_NOMCP(bp))
1947 return 0;
1948
1949 rc = bnx2x_nvram_read(bp, 0, data, 4);
1950 if (rc) {
1951 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1952 goto test_nvram_exit;
1953 }
1954
1955 magic = be32_to_cpu(buf[0]);
1956 if (magic != 0x669955aa) {
1957 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1958 rc = -ENODEV;
1959 goto test_nvram_exit;
1960 }
1961
1962 for (i = 0; nvram_tbl[i].size; i++) {
1963
1964 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1965 nvram_tbl[i].size);
1966 if (rc) {
1967 DP(NETIF_MSG_PROBE,
1968 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1969 goto test_nvram_exit;
1970 }
1971
1972 crc = ether_crc_le(nvram_tbl[i].size, data);
1973 if (crc != CRC32_RESIDUAL) {
1974 DP(NETIF_MSG_PROBE,
1975 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1976 rc = -ENODEV;
1977 goto test_nvram_exit;
1978 }
1979 }
1980
1981 test_nvram_exit:
1982 return rc;
1983 }
1984
1985 /* Send an EMPTY ramrod on the first queue */
1986 static int bnx2x_test_intr(struct bnx2x *bp)
1987 {
1988 struct bnx2x_queue_state_params params = {0};
1989
1990 if (!netif_running(bp->dev))
1991 return -ENODEV;
1992
1993 params.q_obj = &bp->fp->q_obj;
1994 params.cmd = BNX2X_Q_CMD_EMPTY;
1995
1996 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1997
1998 return bnx2x_queue_state_change(bp, &params);
1999 }
2000
2001 static void bnx2x_self_test(struct net_device *dev,
2002 struct ethtool_test *etest, u64 *buf)
2003 {
2004 struct bnx2x *bp = netdev_priv(dev);
2005 u8 is_serdes;
2006 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2007 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
2008 etest->flags |= ETH_TEST_FL_FAILED;
2009 return;
2010 }
2011
2012 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2013
2014 if (!netif_running(dev))
2015 return;
2016
2017 /* offline tests are not supported in MF mode */
2018 if (IS_MF(bp))
2019 etest->flags &= ~ETH_TEST_FL_OFFLINE;
2020 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2021
2022 if (etest->flags & ETH_TEST_FL_OFFLINE) {
2023 int port = BP_PORT(bp);
2024 u32 val;
2025 u8 link_up;
2026
2027 /* save current value of input enable for TX port IF */
2028 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2029 /* disable input for TX port IF */
2030 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2031
2032 link_up = bp->link_vars.link_up;
2033
2034 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2035 bnx2x_nic_load(bp, LOAD_DIAG);
2036 /* wait until link state is restored */
2037 bnx2x_wait_for_link(bp, 1, is_serdes);
2038
2039 if (bnx2x_test_registers(bp) != 0) {
2040 buf[0] = 1;
2041 etest->flags |= ETH_TEST_FL_FAILED;
2042 }
2043 if (bnx2x_test_memory(bp) != 0) {
2044 buf[1] = 1;
2045 etest->flags |= ETH_TEST_FL_FAILED;
2046 }
2047
2048 buf[2] = bnx2x_test_loopback(bp);
2049 if (buf[2] != 0)
2050 etest->flags |= ETH_TEST_FL_FAILED;
2051
2052 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2053
2054 /* restore input for TX port IF */
2055 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2056
2057 bnx2x_nic_load(bp, LOAD_NORMAL);
2058 /* wait until link state is restored */
2059 bnx2x_wait_for_link(bp, link_up, is_serdes);
2060 }
2061 if (bnx2x_test_nvram(bp) != 0) {
2062 buf[3] = 1;
2063 etest->flags |= ETH_TEST_FL_FAILED;
2064 }
2065 if (bnx2x_test_intr(bp) != 0) {
2066 buf[4] = 1;
2067 etest->flags |= ETH_TEST_FL_FAILED;
2068 }
2069
2070 if (bnx2x_link_test(bp, is_serdes) != 0) {
2071 buf[5] = 1;
2072 etest->flags |= ETH_TEST_FL_FAILED;
2073 }
2074
2075 #ifdef BNX2X_EXTRA_DEBUG
2076 bnx2x_panic_dump(bp);
2077 #endif
2078 }
2079
2080 #define IS_PORT_STAT(i) \
2081 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2082 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2083 #define IS_MF_MODE_STAT(bp) \
2084 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2085
2086 /* ethtool statistics are displayed for all regular ethernet queues and the
2087 * fcoe L2 queue if not disabled
2088 */
2089 static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2090 {
2091 return BNX2X_NUM_ETH_QUEUES(bp);
2092 }
2093
2094 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2095 {
2096 struct bnx2x *bp = netdev_priv(dev);
2097 int i, num_stats;
2098
2099 switch (stringset) {
2100 case ETH_SS_STATS:
2101 if (is_multi(bp)) {
2102 num_stats = bnx2x_num_stat_queues(bp) *
2103 BNX2X_NUM_Q_STATS;
2104 if (!IS_MF_MODE_STAT(bp))
2105 num_stats += BNX2X_NUM_STATS;
2106 } else {
2107 if (IS_MF_MODE_STAT(bp)) {
2108 num_stats = 0;
2109 for (i = 0; i < BNX2X_NUM_STATS; i++)
2110 if (IS_FUNC_STAT(i))
2111 num_stats++;
2112 } else
2113 num_stats = BNX2X_NUM_STATS;
2114 }
2115 return num_stats;
2116
2117 case ETH_SS_TEST:
2118 return BNX2X_NUM_TESTS;
2119
2120 default:
2121 return -EINVAL;
2122 }
2123 }
2124
2125 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2126 {
2127 struct bnx2x *bp = netdev_priv(dev);
2128 int i, j, k;
2129 char queue_name[MAX_QUEUE_NAME_LEN+1];
2130
2131 switch (stringset) {
2132 case ETH_SS_STATS:
2133 if (is_multi(bp)) {
2134 k = 0;
2135 for_each_eth_queue(bp, i) {
2136 memset(queue_name, 0, sizeof(queue_name));
2137 sprintf(queue_name, "%d", i);
2138 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2139 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2140 ETH_GSTRING_LEN,
2141 bnx2x_q_stats_arr[j].string,
2142 queue_name);
2143 k += BNX2X_NUM_Q_STATS;
2144 }
2145 if (IS_MF_MODE_STAT(bp))
2146 break;
2147 for (j = 0; j < BNX2X_NUM_STATS; j++)
2148 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2149 bnx2x_stats_arr[j].string);
2150 } else {
2151 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2152 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2153 continue;
2154 strcpy(buf + j*ETH_GSTRING_LEN,
2155 bnx2x_stats_arr[i].string);
2156 j++;
2157 }
2158 }
2159 break;
2160
2161 case ETH_SS_TEST:
2162 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2163 break;
2164 }
2165 }
2166
2167 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2168 struct ethtool_stats *stats, u64 *buf)
2169 {
2170 struct bnx2x *bp = netdev_priv(dev);
2171 u32 *hw_stats, *offset;
2172 int i, j, k;
2173
2174 if (is_multi(bp)) {
2175 k = 0;
2176 for_each_eth_queue(bp, i) {
2177 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2178 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2179 if (bnx2x_q_stats_arr[j].size == 0) {
2180 /* skip this counter */
2181 buf[k + j] = 0;
2182 continue;
2183 }
2184 offset = (hw_stats +
2185 bnx2x_q_stats_arr[j].offset);
2186 if (bnx2x_q_stats_arr[j].size == 4) {
2187 /* 4-byte counter */
2188 buf[k + j] = (u64) *offset;
2189 continue;
2190 }
2191 /* 8-byte counter */
2192 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2193 }
2194 k += BNX2X_NUM_Q_STATS;
2195 }
2196 if (IS_MF_MODE_STAT(bp))
2197 return;
2198 hw_stats = (u32 *)&bp->eth_stats;
2199 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2200 if (bnx2x_stats_arr[j].size == 0) {
2201 /* skip this counter */
2202 buf[k + j] = 0;
2203 continue;
2204 }
2205 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2206 if (bnx2x_stats_arr[j].size == 4) {
2207 /* 4-byte counter */
2208 buf[k + j] = (u64) *offset;
2209 continue;
2210 }
2211 /* 8-byte counter */
2212 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2213 }
2214 } else {
2215 hw_stats = (u32 *)&bp->eth_stats;
2216 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2217 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2218 continue;
2219 if (bnx2x_stats_arr[i].size == 0) {
2220 /* skip this counter */
2221 buf[j] = 0;
2222 j++;
2223 continue;
2224 }
2225 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2226 if (bnx2x_stats_arr[i].size == 4) {
2227 /* 4-byte counter */
2228 buf[j] = (u64) *offset;
2229 j++;
2230 continue;
2231 }
2232 /* 8-byte counter */
2233 buf[j] = HILO_U64(*offset, *(offset + 1));
2234 j++;
2235 }
2236 }
2237 }
2238
2239 static int bnx2x_set_phys_id(struct net_device *dev,
2240 enum ethtool_phys_id_state state)
2241 {
2242 struct bnx2x *bp = netdev_priv(dev);
2243
2244 if (!netif_running(dev))
2245 return -EAGAIN;
2246
2247 if (!bp->port.pmf)
2248 return -EOPNOTSUPP;
2249
2250 switch (state) {
2251 case ETHTOOL_ID_ACTIVE:
2252 return 1; /* cycle on/off once per second */
2253
2254 case ETHTOOL_ID_ON:
2255 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2256 LED_MODE_ON, SPEED_1000);
2257 break;
2258
2259 case ETHTOOL_ID_OFF:
2260 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2261 LED_MODE_FRONT_PANEL_OFF, 0);
2262
2263 break;
2264
2265 case ETHTOOL_ID_INACTIVE:
2266 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2267 LED_MODE_OPER,
2268 bp->link_vars.line_speed);
2269 }
2270
2271 return 0;
2272 }
2273
2274 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2275 void *rules __always_unused)
2276 {
2277 struct bnx2x *bp = netdev_priv(dev);
2278
2279 switch (info->cmd) {
2280 case ETHTOOL_GRXRINGS:
2281 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2282 return 0;
2283
2284 default:
2285 return -EOPNOTSUPP;
2286 }
2287 }
2288
2289 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2290 struct ethtool_rxfh_indir *indir)
2291 {
2292 struct bnx2x *bp = netdev_priv(dev);
2293 size_t copy_size =
2294 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE);
2295 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2296 size_t i;
2297
2298 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2299 return -EOPNOTSUPP;
2300
2301 /* Get the current configuration of the RSS indirection table */
2302 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2303
2304 /*
2305 * We can't use a memcpy() as an internal storage of an
2306 * indirection table is a u8 array while indir->ring_index
2307 * points to an array of u32.
2308 *
2309 * Indirection table contains the FW Client IDs, so we need to
2310 * align the returned table to the Client ID of the leading RSS
2311 * queue.
2312 */
2313 for (i = 0; i < copy_size; i++)
2314 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id;
2315
2316 indir->size = T_ETH_INDIRECTION_TABLE_SIZE;
2317
2318 return 0;
2319 }
2320
2321 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2322 const struct ethtool_rxfh_indir *indir)
2323 {
2324 struct bnx2x *bp = netdev_priv(dev);
2325 size_t i;
2326 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2327 u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2328
2329 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2330 return -EOPNOTSUPP;
2331
2332 /* validate the size */
2333 if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE)
2334 return -EINVAL;
2335
2336 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2337 /* validate the indices */
2338 if (indir->ring_index[i] >= num_eth_queues)
2339 return -EINVAL;
2340 /*
2341 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2342 * as an internal storage of an indirection table is a u8 array
2343 * while indir->ring_index points to an array of u32.
2344 *
2345 * Indirection table contains the FW Client IDs, so we need to
2346 * align the received table to the Client ID of the leading RSS
2347 * queue
2348 */
2349 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id;
2350 }
2351
2352 return bnx2x_config_rss_pf(bp, ind_table, false);
2353 }
2354
2355 static const struct ethtool_ops bnx2x_ethtool_ops = {
2356 .get_settings = bnx2x_get_settings,
2357 .set_settings = bnx2x_set_settings,
2358 .get_drvinfo = bnx2x_get_drvinfo,
2359 .get_regs_len = bnx2x_get_regs_len,
2360 .get_regs = bnx2x_get_regs,
2361 .get_wol = bnx2x_get_wol,
2362 .set_wol = bnx2x_set_wol,
2363 .get_msglevel = bnx2x_get_msglevel,
2364 .set_msglevel = bnx2x_set_msglevel,
2365 .nway_reset = bnx2x_nway_reset,
2366 .get_link = bnx2x_get_link,
2367 .get_eeprom_len = bnx2x_get_eeprom_len,
2368 .get_eeprom = bnx2x_get_eeprom,
2369 .set_eeprom = bnx2x_set_eeprom,
2370 .get_coalesce = bnx2x_get_coalesce,
2371 .set_coalesce = bnx2x_set_coalesce,
2372 .get_ringparam = bnx2x_get_ringparam,
2373 .set_ringparam = bnx2x_set_ringparam,
2374 .get_pauseparam = bnx2x_get_pauseparam,
2375 .set_pauseparam = bnx2x_set_pauseparam,
2376 .self_test = bnx2x_self_test,
2377 .get_sset_count = bnx2x_get_sset_count,
2378 .get_strings = bnx2x_get_strings,
2379 .set_phys_id = bnx2x_set_phys_id,
2380 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2381 .get_rxnfc = bnx2x_get_rxnfc,
2382 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2383 .set_rxfh_indir = bnx2x_set_rxfh_indir,
2384 };
2385
2386 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2387 {
2388 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2389 }
Linux Btrfs Development