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Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux
[linux-btrfs-devel.git] / drivers / net / bnx2x / bnx2x_stats.c
blob9908f2bbcf734b4eaf662f68f420b7741717434f
1 /* bnx2x_stats.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #include "bnx2x_stats.h"
18 #include "bnx2x_cmn.h"
19
20
21 /* Statistics */
22
23 /*
24 * General service functions
25 */
26
27 static inline long bnx2x_hilo(u32 *hiref)
28 {
29 u32 lo = *(hiref + 1);
30 #if (BITS_PER_LONG == 64)
31 u32 hi = *hiref;
32
33 return HILO_U64(hi, lo);
34 #else
35 return lo;
36 #endif
37 }
38
39 /*
40 * Init service functions
41 */
42
43 /* Post the next statistics ramrod. Protect it with the spin in
44 * order to ensure the strict order between statistics ramrods
45 * (each ramrod has a sequence number passed in a
46 * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
47 * sent in order).
48 */
49 static void bnx2x_storm_stats_post(struct bnx2x *bp)
50 {
51 if (!bp->stats_pending) {
52 int rc;
53
54 spin_lock_bh(&bp->stats_lock);
55
56 if (bp->stats_pending) {
57 spin_unlock_bh(&bp->stats_lock);
58 return;
59 }
60
61 bp->fw_stats_req->hdr.drv_stats_counter =
62 cpu_to_le16(bp->stats_counter++);
63
64 DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n",
65 bp->fw_stats_req->hdr.drv_stats_counter);
66
67
68
69 /* send FW stats ramrod */
70 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
71 U64_HI(bp->fw_stats_req_mapping),
72 U64_LO(bp->fw_stats_req_mapping),
73 NONE_CONNECTION_TYPE);
74 if (rc == 0)
75 bp->stats_pending = 1;
76
77 spin_unlock_bh(&bp->stats_lock);
78 }
79 }
80
81 static void bnx2x_hw_stats_post(struct bnx2x *bp)
82 {
83 struct dmae_command *dmae = &bp->stats_dmae;
84 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
85
86 *stats_comp = DMAE_COMP_VAL;
87 if (CHIP_REV_IS_SLOW(bp))
88 return;
89
90 /* loader */
91 if (bp->executer_idx) {
92 int loader_idx = PMF_DMAE_C(bp);
93 u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
94 true, DMAE_COMP_GRC);
95 opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
96
97 memset(dmae, 0, sizeof(struct dmae_command));
98 dmae->opcode = opcode;
99 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
100 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
101 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
102 sizeof(struct dmae_command) *
103 (loader_idx + 1)) >> 2;
104 dmae->dst_addr_hi = 0;
105 dmae->len = sizeof(struct dmae_command) >> 2;
106 if (CHIP_IS_E1(bp))
107 dmae->len--;
108 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
109 dmae->comp_addr_hi = 0;
110 dmae->comp_val = 1;
111
112 *stats_comp = 0;
113 bnx2x_post_dmae(bp, dmae, loader_idx);
114
115 } else if (bp->func_stx) {
116 *stats_comp = 0;
117 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
118 }
119 }
120
121 static int bnx2x_stats_comp(struct bnx2x *bp)
122 {
123 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
124 int cnt = 10;
125
126 might_sleep();
127 while (*stats_comp != DMAE_COMP_VAL) {
128 if (!cnt) {
129 BNX2X_ERR("timeout waiting for stats finished\n");
130 break;
131 }
132 cnt--;
133 usleep_range(1000, 1000);
134 }
135 return 1;
136 }
137
138 /*
139 * Statistics service functions
140 */
141
142 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
143 {
144 struct dmae_command *dmae;
145 u32 opcode;
146 int loader_idx = PMF_DMAE_C(bp);
147 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
148
149 /* sanity */
150 if (!IS_MF(bp) || !bp->port.pmf || !bp->port.port_stx) {
151 BNX2X_ERR("BUG!\n");
152 return;
153 }
154
155 bp->executer_idx = 0;
156
157 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
158
159 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
160 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
161 dmae->src_addr_lo = bp->port.port_stx >> 2;
162 dmae->src_addr_hi = 0;
163 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
164 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
165 dmae->len = DMAE_LEN32_RD_MAX;
166 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
167 dmae->comp_addr_hi = 0;
168 dmae->comp_val = 1;
169
170 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
171 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
172 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
173 dmae->src_addr_hi = 0;
174 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
175 DMAE_LEN32_RD_MAX * 4);
176 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
177 DMAE_LEN32_RD_MAX * 4);
178 dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
179 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
180 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
181 dmae->comp_val = DMAE_COMP_VAL;
182
183 *stats_comp = 0;
184 bnx2x_hw_stats_post(bp);
185 bnx2x_stats_comp(bp);
186 }
187
188 static void bnx2x_port_stats_init(struct bnx2x *bp)
189 {
190 struct dmae_command *dmae;
191 int port = BP_PORT(bp);
192 u32 opcode;
193 int loader_idx = PMF_DMAE_C(bp);
194 u32 mac_addr;
195 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
196
197 /* sanity */
198 if (!bp->link_vars.link_up || !bp->port.pmf) {
199 BNX2X_ERR("BUG!\n");
200 return;
201 }
202
203 bp->executer_idx = 0;
204
205 /* MCP */
206 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
207 true, DMAE_COMP_GRC);
208
209 if (bp->port.port_stx) {
210
211 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
212 dmae->opcode = opcode;
213 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
214 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
215 dmae->dst_addr_lo = bp->port.port_stx >> 2;
216 dmae->dst_addr_hi = 0;
217 dmae->len = sizeof(struct host_port_stats) >> 2;
218 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
219 dmae->comp_addr_hi = 0;
220 dmae->comp_val = 1;
221 }
222
223 if (bp->func_stx) {
224
225 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
226 dmae->opcode = opcode;
227 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
228 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
229 dmae->dst_addr_lo = bp->func_stx >> 2;
230 dmae->dst_addr_hi = 0;
231 dmae->len = sizeof(struct host_func_stats) >> 2;
232 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
233 dmae->comp_addr_hi = 0;
234 dmae->comp_val = 1;
235 }
236
237 /* MAC */
238 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
239 true, DMAE_COMP_GRC);
240
241 /* EMAC is special */
242 if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
243 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
244
245 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
246 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
247 dmae->opcode = opcode;
248 dmae->src_addr_lo = (mac_addr +
249 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
250 dmae->src_addr_hi = 0;
251 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
252 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
253 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
254 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
255 dmae->comp_addr_hi = 0;
256 dmae->comp_val = 1;
257
258 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
259 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
260 dmae->opcode = opcode;
261 dmae->src_addr_lo = (mac_addr +
262 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
263 dmae->src_addr_hi = 0;
264 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
265 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
266 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
267 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
268 dmae->len = 1;
269 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
270 dmae->comp_addr_hi = 0;
271 dmae->comp_val = 1;
272
273 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
274 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
275 dmae->opcode = opcode;
276 dmae->src_addr_lo = (mac_addr +
277 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
278 dmae->src_addr_hi = 0;
279 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
280 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
281 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
282 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
283 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
284 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
285 dmae->comp_addr_hi = 0;
286 dmae->comp_val = 1;
287 } else {
288 u32 tx_src_addr_lo, rx_src_addr_lo;
289 u16 rx_len, tx_len;
290
291 /* configure the params according to MAC type */
292 switch (bp->link_vars.mac_type) {
293 case MAC_TYPE_BMAC:
294 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
295 NIG_REG_INGRESS_BMAC0_MEM);
296
297 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
298 BIGMAC_REGISTER_TX_STAT_GTBYT */
299 if (CHIP_IS_E1x(bp)) {
300 tx_src_addr_lo = (mac_addr +
301 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
302 tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
303 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
304 rx_src_addr_lo = (mac_addr +
305 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
306 rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
307 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
308 } else {
309 tx_src_addr_lo = (mac_addr +
310 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
311 tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
312 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
313 rx_src_addr_lo = (mac_addr +
314 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
315 rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
316 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
317 }
318 break;
319
320 case MAC_TYPE_UMAC: /* handled by MSTAT */
321 case MAC_TYPE_XMAC: /* handled by MSTAT */
322 default:
323 mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
324 tx_src_addr_lo = (mac_addr +
325 MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
326 rx_src_addr_lo = (mac_addr +
327 MSTAT_REG_RX_STAT_GR64_LO) >> 2;
328 tx_len = sizeof(bp->slowpath->
329 mac_stats.mstat_stats.stats_tx) >> 2;
330 rx_len = sizeof(bp->slowpath->
331 mac_stats.mstat_stats.stats_rx) >> 2;
332 break;
333 }
334
335 /* TX stats */
336 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
337 dmae->opcode = opcode;
338 dmae->src_addr_lo = tx_src_addr_lo;
339 dmae->src_addr_hi = 0;
340 dmae->len = tx_len;
341 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
342 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
343 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
344 dmae->comp_addr_hi = 0;
345 dmae->comp_val = 1;
346
347 /* RX stats */
348 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
349 dmae->opcode = opcode;
350 dmae->src_addr_hi = 0;
351 dmae->src_addr_lo = rx_src_addr_lo;
352 dmae->dst_addr_lo =
353 U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
354 dmae->dst_addr_hi =
355 U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
356 dmae->len = rx_len;
357 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
358 dmae->comp_addr_hi = 0;
359 dmae->comp_val = 1;
360 }
361
362 /* NIG */
363 if (!CHIP_IS_E3(bp)) {
364 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
365 dmae->opcode = opcode;
366 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
367 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
368 dmae->src_addr_hi = 0;
369 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
370 offsetof(struct nig_stats, egress_mac_pkt0_lo));
371 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
372 offsetof(struct nig_stats, egress_mac_pkt0_lo));
373 dmae->len = (2*sizeof(u32)) >> 2;
374 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
375 dmae->comp_addr_hi = 0;
376 dmae->comp_val = 1;
377
378 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
379 dmae->opcode = opcode;
380 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
381 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
382 dmae->src_addr_hi = 0;
383 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
384 offsetof(struct nig_stats, egress_mac_pkt1_lo));
385 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
386 offsetof(struct nig_stats, egress_mac_pkt1_lo));
387 dmae->len = (2*sizeof(u32)) >> 2;
388 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
389 dmae->comp_addr_hi = 0;
390 dmae->comp_val = 1;
391 }
392
393 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
394 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
395 true, DMAE_COMP_PCI);
396 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
397 NIG_REG_STAT0_BRB_DISCARD) >> 2;
398 dmae->src_addr_hi = 0;
399 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
400 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
401 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
402
403 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
404 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
405 dmae->comp_val = DMAE_COMP_VAL;
406
407 *stats_comp = 0;
408 }
409
410 static void bnx2x_func_stats_init(struct bnx2x *bp)
411 {
412 struct dmae_command *dmae = &bp->stats_dmae;
413 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
414
415 /* sanity */
416 if (!bp->func_stx) {
417 BNX2X_ERR("BUG!\n");
418 return;
419 }
420
421 bp->executer_idx = 0;
422 memset(dmae, 0, sizeof(struct dmae_command));
423
424 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
425 true, DMAE_COMP_PCI);
426 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
427 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
428 dmae->dst_addr_lo = bp->func_stx >> 2;
429 dmae->dst_addr_hi = 0;
430 dmae->len = sizeof(struct host_func_stats) >> 2;
431 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
432 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
433 dmae->comp_val = DMAE_COMP_VAL;
434
435 *stats_comp = 0;
436 }
437
438 static void bnx2x_stats_start(struct bnx2x *bp)
439 {
440 if (bp->port.pmf)
441 bnx2x_port_stats_init(bp);
442
443 else if (bp->func_stx)
444 bnx2x_func_stats_init(bp);
445
446 bnx2x_hw_stats_post(bp);
447 bnx2x_storm_stats_post(bp);
448 }
449
450 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
451 {
452 bnx2x_stats_comp(bp);
453 bnx2x_stats_pmf_update(bp);
454 bnx2x_stats_start(bp);
455 }
456
457 static void bnx2x_stats_restart(struct bnx2x *bp)
458 {
459 bnx2x_stats_comp(bp);
460 bnx2x_stats_start(bp);
461 }
462
463 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
464 {
465 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
466 struct bnx2x_eth_stats *estats = &bp->eth_stats;
467 struct {
468 u32 lo;
469 u32 hi;
470 } diff;
471
472 if (CHIP_IS_E1x(bp)) {
473 struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
474
475 /* the macros below will use "bmac1_stats" type */
476 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
477 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
478 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
479 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
480 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
481 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
482 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
483 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
484 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
485
486 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
487 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
488 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
489 UPDATE_STAT64(tx_stat_gt127,
490 tx_stat_etherstatspkts65octetsto127octets);
491 UPDATE_STAT64(tx_stat_gt255,
492 tx_stat_etherstatspkts128octetsto255octets);
493 UPDATE_STAT64(tx_stat_gt511,
494 tx_stat_etherstatspkts256octetsto511octets);
495 UPDATE_STAT64(tx_stat_gt1023,
496 tx_stat_etherstatspkts512octetsto1023octets);
497 UPDATE_STAT64(tx_stat_gt1518,
498 tx_stat_etherstatspkts1024octetsto1522octets);
499 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
500 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
501 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
502 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
503 UPDATE_STAT64(tx_stat_gterr,
504 tx_stat_dot3statsinternalmactransmiterrors);
505 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
506
507 } else {
508 struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
509
510 /* the macros below will use "bmac2_stats" type */
511 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
512 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
513 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
514 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
515 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
516 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
517 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
518 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
519 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
520 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
521 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
522 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
523 UPDATE_STAT64(tx_stat_gt127,
524 tx_stat_etherstatspkts65octetsto127octets);
525 UPDATE_STAT64(tx_stat_gt255,
526 tx_stat_etherstatspkts128octetsto255octets);
527 UPDATE_STAT64(tx_stat_gt511,
528 tx_stat_etherstatspkts256octetsto511octets);
529 UPDATE_STAT64(tx_stat_gt1023,
530 tx_stat_etherstatspkts512octetsto1023octets);
531 UPDATE_STAT64(tx_stat_gt1518,
532 tx_stat_etherstatspkts1024octetsto1522octets);
533 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
534 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
535 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
536 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
537 UPDATE_STAT64(tx_stat_gterr,
538 tx_stat_dot3statsinternalmactransmiterrors);
539 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
540 }
541
542 estats->pause_frames_received_hi =
543 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
544 estats->pause_frames_received_lo =
545 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
546
547 estats->pause_frames_sent_hi =
548 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
549 estats->pause_frames_sent_lo =
550 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
551 }
552
553 static void bnx2x_mstat_stats_update(struct bnx2x *bp)
554 {
555 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
556 struct bnx2x_eth_stats *estats = &bp->eth_stats;
557
558 struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
559
560 ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
561 ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
562 ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
563 ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
564 ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
565 ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
566 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
567 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
568 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
569 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
570
571
572 ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
573 ADD_STAT64(stats_tx.tx_gt127,
574 tx_stat_etherstatspkts65octetsto127octets);
575 ADD_STAT64(stats_tx.tx_gt255,
576 tx_stat_etherstatspkts128octetsto255octets);
577 ADD_STAT64(stats_tx.tx_gt511,
578 tx_stat_etherstatspkts256octetsto511octets);
579 ADD_STAT64(stats_tx.tx_gt1023,
580 tx_stat_etherstatspkts512octetsto1023octets);
581 ADD_STAT64(stats_tx.tx_gt1518,
582 tx_stat_etherstatspkts1024octetsto1522octets);
583 ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
584
585 ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
586 ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
587 ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
588
589 ADD_STAT64(stats_tx.tx_gterr,
590 tx_stat_dot3statsinternalmactransmiterrors);
591 ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
592
593 ADD_64(estats->etherstatspkts1024octetsto1522octets_hi,
594 new->stats_tx.tx_gt1518_hi,
595 estats->etherstatspkts1024octetsto1522octets_lo,
596 new->stats_tx.tx_gt1518_lo);
597
598 ADD_64(estats->etherstatspktsover1522octets_hi,
599 new->stats_tx.tx_gt2047_hi,
600 estats->etherstatspktsover1522octets_lo,
601 new->stats_tx.tx_gt2047_lo);
602
603 ADD_64(estats->etherstatspktsover1522octets_hi,
604 new->stats_tx.tx_gt4095_hi,
605 estats->etherstatspktsover1522octets_lo,
606 new->stats_tx.tx_gt4095_lo);
607
608 ADD_64(estats->etherstatspktsover1522octets_hi,
609 new->stats_tx.tx_gt9216_hi,
610 estats->etherstatspktsover1522octets_lo,
611 new->stats_tx.tx_gt9216_lo);
612
613
614 ADD_64(estats->etherstatspktsover1522octets_hi,
615 new->stats_tx.tx_gt16383_hi,
616 estats->etherstatspktsover1522octets_lo,
617 new->stats_tx.tx_gt16383_lo);
618
619 estats->pause_frames_received_hi =
620 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
621 estats->pause_frames_received_lo =
622 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
623
624 estats->pause_frames_sent_hi =
625 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
626 estats->pause_frames_sent_lo =
627 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
628 }
629
630 static void bnx2x_emac_stats_update(struct bnx2x *bp)
631 {
632 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
633 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
634 struct bnx2x_eth_stats *estats = &bp->eth_stats;
635
636 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
637 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
638 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
639 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
640 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
641 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
642 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
643 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
644 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
645 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
646 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
647 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
648 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
649 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
650 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
651 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
652 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
653 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
654 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
655 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
656 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
657 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
658 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
659 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
660 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
661 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
662 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
663 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
664 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
665 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
666 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
667
668 estats->pause_frames_received_hi =
669 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
670 estats->pause_frames_received_lo =
671 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
672 ADD_64(estats->pause_frames_received_hi,
673 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
674 estats->pause_frames_received_lo,
675 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
676
677 estats->pause_frames_sent_hi =
678 pstats->mac_stx[1].tx_stat_outxonsent_hi;
679 estats->pause_frames_sent_lo =
680 pstats->mac_stx[1].tx_stat_outxonsent_lo;
681 ADD_64(estats->pause_frames_sent_hi,
682 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
683 estats->pause_frames_sent_lo,
684 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
685 }
686
687 static int bnx2x_hw_stats_update(struct bnx2x *bp)
688 {
689 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
690 struct nig_stats *old = &(bp->port.old_nig_stats);
691 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
692 struct bnx2x_eth_stats *estats = &bp->eth_stats;
693 struct {
694 u32 lo;
695 u32 hi;
696 } diff;
697
698 switch (bp->link_vars.mac_type) {
699 case MAC_TYPE_BMAC:
700 bnx2x_bmac_stats_update(bp);
701 break;
702
703 case MAC_TYPE_EMAC:
704 bnx2x_emac_stats_update(bp);
705 break;
706
707 case MAC_TYPE_UMAC:
708 case MAC_TYPE_XMAC:
709 bnx2x_mstat_stats_update(bp);
710 break;
711
712 case MAC_TYPE_NONE: /* unreached */
713 DP(BNX2X_MSG_STATS,
714 "stats updated by DMAE but no MAC active\n");
715 return -1;
716
717 default: /* unreached */
718 BNX2X_ERR("Unknown MAC type\n");
719 }
720
721 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
722 new->brb_discard - old->brb_discard);
723 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
724 new->brb_truncate - old->brb_truncate);
725
726 if (!CHIP_IS_E3(bp)) {
727 UPDATE_STAT64_NIG(egress_mac_pkt0,
728 etherstatspkts1024octetsto1522octets);
729 UPDATE_STAT64_NIG(egress_mac_pkt1,
730 etherstatspktsover1522octets);
731 }
732
733 memcpy(old, new, sizeof(struct nig_stats));
734
735 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
736 sizeof(struct mac_stx));
737 estats->brb_drop_hi = pstats->brb_drop_hi;
738 estats->brb_drop_lo = pstats->brb_drop_lo;
739
740 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
741
742 if (!BP_NOMCP(bp)) {
743 u32 nig_timer_max =
744 SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
745 if (nig_timer_max != estats->nig_timer_max) {
746 estats->nig_timer_max = nig_timer_max;
747 BNX2X_ERR("NIG timer max (%u)\n",
748 estats->nig_timer_max);
749 }
750 }
751
752 return 0;
753 }
754
755 static int bnx2x_storm_stats_update(struct bnx2x *bp)
756 {
757 struct tstorm_per_port_stats *tport =
758 &bp->fw_stats_data->port.tstorm_port_statistics;
759 struct tstorm_per_pf_stats *tfunc =
760 &bp->fw_stats_data->pf.tstorm_pf_statistics;
761 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
762 struct bnx2x_eth_stats *estats = &bp->eth_stats;
763 struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
764 int i;
765 u16 cur_stats_counter;
766
767 /* Make sure we use the value of the counter
768 * used for sending the last stats ramrod.
769 */
770 spin_lock_bh(&bp->stats_lock);
771 cur_stats_counter = bp->stats_counter - 1;
772 spin_unlock_bh(&bp->stats_lock);
773
774 /* are storm stats valid? */
775 if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
776 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
777 " xstorm counter (0x%x) != stats_counter (0x%x)\n",
778 le16_to_cpu(counters->xstats_counter), bp->stats_counter);
779 return -EAGAIN;
780 }
781
782 if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
783 DP(BNX2X_MSG_STATS, "stats not updated by ustorm"
784 " ustorm counter (0x%x) != stats_counter (0x%x)\n",
785 le16_to_cpu(counters->ustats_counter), bp->stats_counter);
786 return -EAGAIN;
787 }
788
789 if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
790 DP(BNX2X_MSG_STATS, "stats not updated by cstorm"
791 " cstorm counter (0x%x) != stats_counter (0x%x)\n",
792 le16_to_cpu(counters->cstats_counter), bp->stats_counter);
793 return -EAGAIN;
794 }
795
796 if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
797 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
798 " tstorm counter (0x%x) != stats_counter (0x%x)\n",
799 le16_to_cpu(counters->tstats_counter), bp->stats_counter);
800 return -EAGAIN;
801 }
802
803 memcpy(&(fstats->total_bytes_received_hi),
804 &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
805 sizeof(struct host_func_stats) - 2*sizeof(u32));
806 estats->error_bytes_received_hi = 0;
807 estats->error_bytes_received_lo = 0;
808 estats->etherstatsoverrsizepkts_hi = 0;
809 estats->etherstatsoverrsizepkts_lo = 0;
810 estats->no_buff_discard_hi = 0;
811 estats->no_buff_discard_lo = 0;
812 estats->total_tpa_aggregations_hi = 0;
813 estats->total_tpa_aggregations_lo = 0;
814 estats->total_tpa_aggregated_frames_hi = 0;
815 estats->total_tpa_aggregated_frames_lo = 0;
816 estats->total_tpa_bytes_hi = 0;
817 estats->total_tpa_bytes_lo = 0;
818
819 for_each_eth_queue(bp, i) {
820 struct bnx2x_fastpath *fp = &bp->fp[i];
821 struct tstorm_per_queue_stats *tclient =
822 &bp->fw_stats_data->queue_stats[i].
823 tstorm_queue_statistics;
824 struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
825 struct ustorm_per_queue_stats *uclient =
826 &bp->fw_stats_data->queue_stats[i].
827 ustorm_queue_statistics;
828 struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
829 struct xstorm_per_queue_stats *xclient =
830 &bp->fw_stats_data->queue_stats[i].
831 xstorm_queue_statistics;
832 struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
833 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
834 u32 diff;
835
836 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, "
837 "bcast_sent 0x%x mcast_sent 0x%x\n",
838 i, xclient->ucast_pkts_sent,
839 xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
840
841 DP(BNX2X_MSG_STATS, "---------------\n");
842
843 qstats->total_broadcast_bytes_received_hi =
844 le32_to_cpu(tclient->rcv_bcast_bytes.hi);
845 qstats->total_broadcast_bytes_received_lo =
846 le32_to_cpu(tclient->rcv_bcast_bytes.lo);
847
848 qstats->total_multicast_bytes_received_hi =
849 le32_to_cpu(tclient->rcv_mcast_bytes.hi);
850 qstats->total_multicast_bytes_received_lo =
851 le32_to_cpu(tclient->rcv_mcast_bytes.lo);
852
853 qstats->total_unicast_bytes_received_hi =
854 le32_to_cpu(tclient->rcv_ucast_bytes.hi);
855 qstats->total_unicast_bytes_received_lo =
856 le32_to_cpu(tclient->rcv_ucast_bytes.lo);
857
858 /*
859 * sum to total_bytes_received all
860 * unicast/multicast/broadcast
861 */
862 qstats->total_bytes_received_hi =
863 qstats->total_broadcast_bytes_received_hi;
864 qstats->total_bytes_received_lo =
865 qstats->total_broadcast_bytes_received_lo;
866
867 ADD_64(qstats->total_bytes_received_hi,
868 qstats->total_multicast_bytes_received_hi,
869 qstats->total_bytes_received_lo,
870 qstats->total_multicast_bytes_received_lo);
871
872 ADD_64(qstats->total_bytes_received_hi,
873 qstats->total_unicast_bytes_received_hi,
874 qstats->total_bytes_received_lo,
875 qstats->total_unicast_bytes_received_lo);
876
877 qstats->valid_bytes_received_hi =
878 qstats->total_bytes_received_hi;
879 qstats->valid_bytes_received_lo =
880 qstats->total_bytes_received_lo;
881
882
883 UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
884 total_unicast_packets_received);
885 UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
886 total_multicast_packets_received);
887 UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
888 total_broadcast_packets_received);
889 UPDATE_EXTEND_TSTAT(pkts_too_big_discard,
890 etherstatsoverrsizepkts);
891 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
892
893 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
894 total_unicast_packets_received);
895 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
896 total_multicast_packets_received);
897 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
898 total_broadcast_packets_received);
899 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
900 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
901 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
902
903 qstats->total_broadcast_bytes_transmitted_hi =
904 le32_to_cpu(xclient->bcast_bytes_sent.hi);
905 qstats->total_broadcast_bytes_transmitted_lo =
906 le32_to_cpu(xclient->bcast_bytes_sent.lo);
907
908 qstats->total_multicast_bytes_transmitted_hi =
909 le32_to_cpu(xclient->mcast_bytes_sent.hi);
910 qstats->total_multicast_bytes_transmitted_lo =
911 le32_to_cpu(xclient->mcast_bytes_sent.lo);
912
913 qstats->total_unicast_bytes_transmitted_hi =
914 le32_to_cpu(xclient->ucast_bytes_sent.hi);
915 qstats->total_unicast_bytes_transmitted_lo =
916 le32_to_cpu(xclient->ucast_bytes_sent.lo);
917 /*
918 * sum to total_bytes_transmitted all
919 * unicast/multicast/broadcast
920 */
921 qstats->total_bytes_transmitted_hi =
922 qstats->total_unicast_bytes_transmitted_hi;
923 qstats->total_bytes_transmitted_lo =
924 qstats->total_unicast_bytes_transmitted_lo;
925
926 ADD_64(qstats->total_bytes_transmitted_hi,
927 qstats->total_broadcast_bytes_transmitted_hi,
928 qstats->total_bytes_transmitted_lo,
929 qstats->total_broadcast_bytes_transmitted_lo);
930
931 ADD_64(qstats->total_bytes_transmitted_hi,
932 qstats->total_multicast_bytes_transmitted_hi,
933 qstats->total_bytes_transmitted_lo,
934 qstats->total_multicast_bytes_transmitted_lo);
935
936 UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
937 total_unicast_packets_transmitted);
938 UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
939 total_multicast_packets_transmitted);
940 UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
941 total_broadcast_packets_transmitted);
942
943 UPDATE_EXTEND_TSTAT(checksum_discard,
944 total_packets_received_checksum_discarded);
945 UPDATE_EXTEND_TSTAT(ttl0_discard,
946 total_packets_received_ttl0_discarded);
947
948 UPDATE_EXTEND_XSTAT(error_drop_pkts,
949 total_transmitted_dropped_packets_error);
950
951 /* TPA aggregations completed */
952 UPDATE_EXTEND_USTAT(coalesced_events, total_tpa_aggregations);
953 /* Number of network frames aggregated by TPA */
954 UPDATE_EXTEND_USTAT(coalesced_pkts,
955 total_tpa_aggregated_frames);
956 /* Total number of bytes in completed TPA aggregations */
957 qstats->total_tpa_bytes_lo =
958 le32_to_cpu(uclient->coalesced_bytes.lo);
959 qstats->total_tpa_bytes_hi =
960 le32_to_cpu(uclient->coalesced_bytes.hi);
961
962 /* TPA stats per-function */
963 ADD_64(estats->total_tpa_aggregations_hi,
964 qstats->total_tpa_aggregations_hi,
965 estats->total_tpa_aggregations_lo,
966 qstats->total_tpa_aggregations_lo);
967 ADD_64(estats->total_tpa_aggregated_frames_hi,
968 qstats->total_tpa_aggregated_frames_hi,
969 estats->total_tpa_aggregated_frames_lo,
970 qstats->total_tpa_aggregated_frames_lo);
971 ADD_64(estats->total_tpa_bytes_hi,
972 qstats->total_tpa_bytes_hi,
973 estats->total_tpa_bytes_lo,
974 qstats->total_tpa_bytes_lo);
975
976 ADD_64(fstats->total_bytes_received_hi,
977 qstats->total_bytes_received_hi,
978 fstats->total_bytes_received_lo,
979 qstats->total_bytes_received_lo);
980 ADD_64(fstats->total_bytes_transmitted_hi,
981 qstats->total_bytes_transmitted_hi,
982 fstats->total_bytes_transmitted_lo,
983 qstats->total_bytes_transmitted_lo);
984 ADD_64(fstats->total_unicast_packets_received_hi,
985 qstats->total_unicast_packets_received_hi,
986 fstats->total_unicast_packets_received_lo,
987 qstats->total_unicast_packets_received_lo);
988 ADD_64(fstats->total_multicast_packets_received_hi,
989 qstats->total_multicast_packets_received_hi,
990 fstats->total_multicast_packets_received_lo,
991 qstats->total_multicast_packets_received_lo);
992 ADD_64(fstats->total_broadcast_packets_received_hi,
993 qstats->total_broadcast_packets_received_hi,
994 fstats->total_broadcast_packets_received_lo,
995 qstats->total_broadcast_packets_received_lo);
996 ADD_64(fstats->total_unicast_packets_transmitted_hi,
997 qstats->total_unicast_packets_transmitted_hi,
998 fstats->total_unicast_packets_transmitted_lo,
999 qstats->total_unicast_packets_transmitted_lo);
1000 ADD_64(fstats->total_multicast_packets_transmitted_hi,
1001 qstats->total_multicast_packets_transmitted_hi,
1002 fstats->total_multicast_packets_transmitted_lo,
1003 qstats->total_multicast_packets_transmitted_lo);
1004 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
1005 qstats->total_broadcast_packets_transmitted_hi,
1006 fstats->total_broadcast_packets_transmitted_lo,
1007 qstats->total_broadcast_packets_transmitted_lo);
1008 ADD_64(fstats->valid_bytes_received_hi,
1009 qstats->valid_bytes_received_hi,
1010 fstats->valid_bytes_received_lo,
1011 qstats->valid_bytes_received_lo);
1012
1013 ADD_64(estats->etherstatsoverrsizepkts_hi,
1014 qstats->etherstatsoverrsizepkts_hi,
1015 estats->etherstatsoverrsizepkts_lo,
1016 qstats->etherstatsoverrsizepkts_lo);
1017 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
1018 estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
1019 }
1020
1021 ADD_64(fstats->total_bytes_received_hi,
1022 estats->rx_stat_ifhcinbadoctets_hi,
1023 fstats->total_bytes_received_lo,
1024 estats->rx_stat_ifhcinbadoctets_lo);
1025
1026 ADD_64(fstats->total_bytes_received_hi,
1027 tfunc->rcv_error_bytes.hi,
1028 fstats->total_bytes_received_lo,
1029 tfunc->rcv_error_bytes.lo);
1030
1031 memcpy(estats, &(fstats->total_bytes_received_hi),
1032 sizeof(struct host_func_stats) - 2*sizeof(u32));
1033
1034 ADD_64(estats->error_bytes_received_hi,
1035 tfunc->rcv_error_bytes.hi,
1036 estats->error_bytes_received_lo,
1037 tfunc->rcv_error_bytes.lo);
1038
1039 ADD_64(estats->etherstatsoverrsizepkts_hi,
1040 estats->rx_stat_dot3statsframestoolong_hi,
1041 estats->etherstatsoverrsizepkts_lo,
1042 estats->rx_stat_dot3statsframestoolong_lo);
1043 ADD_64(estats->error_bytes_received_hi,
1044 estats->rx_stat_ifhcinbadoctets_hi,
1045 estats->error_bytes_received_lo,
1046 estats->rx_stat_ifhcinbadoctets_lo);
1047
1048 if (bp->port.pmf) {
1049 estats->mac_filter_discard =
1050 le32_to_cpu(tport->mac_filter_discard);
1051 estats->mf_tag_discard =
1052 le32_to_cpu(tport->mf_tag_discard);
1053 estats->brb_truncate_discard =
1054 le32_to_cpu(tport->brb_truncate_discard);
1055 estats->mac_discard = le32_to_cpu(tport->mac_discard);
1056 }
1057
1058 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
1059
1060 bp->stats_pending = 0;
1061
1062 return 0;
1063 }
1064
1065 static void bnx2x_net_stats_update(struct bnx2x *bp)
1066 {
1067 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1068 struct net_device_stats *nstats = &bp->dev->stats;
1069 unsigned long tmp;
1070 int i;
1071
1072 nstats->rx_packets =
1073 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
1074 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
1075 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
1076
1077 nstats->tx_packets =
1078 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
1079 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
1080 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
1081
1082 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
1083
1084 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
1085
1086 tmp = estats->mac_discard;
1087 for_each_rx_queue(bp, i)
1088 tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
1089 nstats->rx_dropped = tmp;
1090
1091 nstats->tx_dropped = 0;
1092
1093 nstats->multicast =
1094 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
1095
1096 nstats->collisions =
1097 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
1098
1099 nstats->rx_length_errors =
1100 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
1101 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
1102 nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
1103 bnx2x_hilo(&estats->brb_truncate_hi);
1104 nstats->rx_crc_errors =
1105 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
1106 nstats->rx_frame_errors =
1107 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
1108 nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
1109 nstats->rx_missed_errors = 0;
1110
1111 nstats->rx_errors = nstats->rx_length_errors +
1112 nstats->rx_over_errors +
1113 nstats->rx_crc_errors +
1114 nstats->rx_frame_errors +
1115 nstats->rx_fifo_errors +
1116 nstats->rx_missed_errors;
1117
1118 nstats->tx_aborted_errors =
1119 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
1120 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
1121 nstats->tx_carrier_errors =
1122 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
1123 nstats->tx_fifo_errors = 0;
1124 nstats->tx_heartbeat_errors = 0;
1125 nstats->tx_window_errors = 0;
1126
1127 nstats->tx_errors = nstats->tx_aborted_errors +
1128 nstats->tx_carrier_errors +
1129 bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
1130 }
1131
1132 static void bnx2x_drv_stats_update(struct bnx2x *bp)
1133 {
1134 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1135 int i;
1136
1137 estats->driver_xoff = 0;
1138 estats->rx_err_discard_pkt = 0;
1139 estats->rx_skb_alloc_failed = 0;
1140 estats->hw_csum_err = 0;
1141 for_each_queue(bp, i) {
1142 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
1143
1144 estats->driver_xoff += qstats->driver_xoff;
1145 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
1146 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
1147 estats->hw_csum_err += qstats->hw_csum_err;
1148 }
1149 }
1150
1151 static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
1152 {
1153 u32 val;
1154
1155 if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
1156 val = SHMEM2_RD(bp, edebug_driver_if[1]);
1157
1158 if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
1159 return true;
1160 }
1161
1162 return false;
1163 }
1164
1165 static void bnx2x_stats_update(struct bnx2x *bp)
1166 {
1167 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1168
1169 if (bnx2x_edebug_stats_stopped(bp))
1170 return;
1171
1172 if (*stats_comp != DMAE_COMP_VAL)
1173 return;
1174
1175 if (bp->port.pmf)
1176 bnx2x_hw_stats_update(bp);
1177
1178 if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
1179 BNX2X_ERR("storm stats were not updated for 3 times\n");
1180 bnx2x_panic();
1181 return;
1182 }
1183
1184 bnx2x_net_stats_update(bp);
1185 bnx2x_drv_stats_update(bp);
1186
1187 if (netif_msg_timer(bp)) {
1188 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1189 int i, cos;
1190
1191 netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
1192 estats->brb_drop_lo, estats->brb_truncate_lo);
1193
1194 for_each_eth_queue(bp, i) {
1195 struct bnx2x_fastpath *fp = &bp->fp[i];
1196 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1197
1198 printk(KERN_DEBUG "%s: rx usage(%4u) *rx_cons_sb(%u)"
1199 " rx pkt(%lu) rx calls(%lu %lu)\n",
1200 fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
1201 fp->rx_comp_cons),
1202 le16_to_cpu(*fp->rx_cons_sb),
1203 bnx2x_hilo(&qstats->
1204 total_unicast_packets_received_hi),
1205 fp->rx_calls, fp->rx_pkt);
1206 }
1207
1208 for_each_eth_queue(bp, i) {
1209 struct bnx2x_fastpath *fp = &bp->fp[i];
1210 struct bnx2x_fp_txdata *txdata;
1211 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1212 struct netdev_queue *txq;
1213
1214 printk(KERN_DEBUG "%s: tx pkt(%lu) (Xoff events %u)",
1215 fp->name, bnx2x_hilo(
1216 &qstats->total_unicast_packets_transmitted_hi),
1217 qstats->driver_xoff);
1218
1219 for_each_cos_in_tx_queue(fp, cos) {
1220 txdata = &fp->txdata[cos];
1221 txq = netdev_get_tx_queue(bp->dev,
1222 FP_COS_TO_TXQ(fp, cos));
1223
1224 printk(KERN_DEBUG "%d: tx avail(%4u)"
1225 " *tx_cons_sb(%u)"
1226 " tx calls (%lu)"
1227 " %s\n",
1228 cos,
1229 bnx2x_tx_avail(bp, txdata),
1230 le16_to_cpu(*txdata->tx_cons_sb),
1231 txdata->tx_pkt,
1232 (netif_tx_queue_stopped(txq) ?
1233 "Xoff" : "Xon")
1234 );
1235 }
1236 }
1237 }
1238
1239 bnx2x_hw_stats_post(bp);
1240 bnx2x_storm_stats_post(bp);
1241 }
1242
1243 static void bnx2x_port_stats_stop(struct bnx2x *bp)
1244 {
1245 struct dmae_command *dmae;
1246 u32 opcode;
1247 int loader_idx = PMF_DMAE_C(bp);
1248 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1249
1250 bp->executer_idx = 0;
1251
1252 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
1253
1254 if (bp->port.port_stx) {
1255
1256 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1257 if (bp->func_stx)
1258 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1259 opcode, DMAE_COMP_GRC);
1260 else
1261 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1262 opcode, DMAE_COMP_PCI);
1263
1264 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1265 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1266 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1267 dmae->dst_addr_hi = 0;
1268 dmae->len = sizeof(struct host_port_stats) >> 2;
1269 if (bp->func_stx) {
1270 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
1271 dmae->comp_addr_hi = 0;
1272 dmae->comp_val = 1;
1273 } else {
1274 dmae->comp_addr_lo =
1275 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1276 dmae->comp_addr_hi =
1277 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1278 dmae->comp_val = DMAE_COMP_VAL;
1279
1280 *stats_comp = 0;
1281 }
1282 }
1283
1284 if (bp->func_stx) {
1285
1286 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1287 dmae->opcode =
1288 bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
1289 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
1290 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
1291 dmae->dst_addr_lo = bp->func_stx >> 2;
1292 dmae->dst_addr_hi = 0;
1293 dmae->len = sizeof(struct host_func_stats) >> 2;
1294 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1295 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1296 dmae->comp_val = DMAE_COMP_VAL;
1297
1298 *stats_comp = 0;
1299 }
1300 }
1301
1302 static void bnx2x_stats_stop(struct bnx2x *bp)
1303 {
1304 int update = 0;
1305
1306 bnx2x_stats_comp(bp);
1307
1308 if (bp->port.pmf)
1309 update = (bnx2x_hw_stats_update(bp) == 0);
1310
1311 update |= (bnx2x_storm_stats_update(bp) == 0);
1312
1313 if (update) {
1314 bnx2x_net_stats_update(bp);
1315
1316 if (bp->port.pmf)
1317 bnx2x_port_stats_stop(bp);
1318
1319 bnx2x_hw_stats_post(bp);
1320 bnx2x_stats_comp(bp);
1321 }
1322 }
1323
1324 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
1325 {
1326 }
1327
1328 static const struct {
1329 void (*action)(struct bnx2x *bp);
1330 enum bnx2x_stats_state next_state;
1331 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
1332 /* state event */
1333 {
1334 /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
1335 /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
1336 /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
1337 /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
1338 },
1339 {
1340 /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
1341 /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
1342 /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
1343 /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
1344 }
1345 };
1346
1347 void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
1348 {
1349 enum bnx2x_stats_state state;
1350 if (unlikely(bp->panic))
1351 return;
1352 bnx2x_stats_stm[bp->stats_state][event].action(bp);
1353 spin_lock_bh(&bp->stats_lock);
1354 state = bp->stats_state;
1355 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
1356 spin_unlock_bh(&bp->stats_lock);
1357
1358 if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
1359 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
1360 state, event, bp->stats_state);
1361 }
1362
1363 static void bnx2x_port_stats_base_init(struct bnx2x *bp)
1364 {
1365 struct dmae_command *dmae;
1366 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1367
1368 /* sanity */
1369 if (!bp->port.pmf || !bp->port.port_stx) {
1370 BNX2X_ERR("BUG!\n");
1371 return;
1372 }
1373
1374 bp->executer_idx = 0;
1375
1376 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1377 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
1378 true, DMAE_COMP_PCI);
1379 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1380 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1381 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1382 dmae->dst_addr_hi = 0;
1383 dmae->len = sizeof(struct host_port_stats) >> 2;
1384 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1385 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1386 dmae->comp_val = DMAE_COMP_VAL;
1387
1388 *stats_comp = 0;
1389 bnx2x_hw_stats_post(bp);
1390 bnx2x_stats_comp(bp);
1391 }
1392
1393 static void bnx2x_func_stats_base_init(struct bnx2x *bp)
1394 {
1395 int vn, vn_max = IS_MF(bp) ? BP_MAX_VN_NUM(bp) : E1VN_MAX;
1396 u32 func_stx;
1397
1398 /* sanity */
1399 if (!bp->port.pmf || !bp->func_stx) {
1400 BNX2X_ERR("BUG!\n");
1401 return;
1402 }
1403
1404 /* save our func_stx */
1405 func_stx = bp->func_stx;
1406
1407 for (vn = VN_0; vn < vn_max; vn++) {
1408 int mb_idx = BP_FW_MB_IDX_VN(bp, vn);
1409
1410 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1411 bnx2x_func_stats_init(bp);
1412 bnx2x_hw_stats_post(bp);
1413 bnx2x_stats_comp(bp);
1414 }
1415
1416 /* restore our func_stx */
1417 bp->func_stx = func_stx;
1418 }
1419
1420 static void bnx2x_func_stats_base_update(struct bnx2x *bp)
1421 {
1422 struct dmae_command *dmae = &bp->stats_dmae;
1423 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1424
1425 /* sanity */
1426 if (!bp->func_stx) {
1427 BNX2X_ERR("BUG!\n");
1428 return;
1429 }
1430
1431 bp->executer_idx = 0;
1432 memset(dmae, 0, sizeof(struct dmae_command));
1433
1434 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
1435 true, DMAE_COMP_PCI);
1436 dmae->src_addr_lo = bp->func_stx >> 2;
1437 dmae->src_addr_hi = 0;
1438 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
1439 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
1440 dmae->len = sizeof(struct host_func_stats) >> 2;
1441 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1442 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1443 dmae->comp_val = DMAE_COMP_VAL;
1444
1445 *stats_comp = 0;
1446 bnx2x_hw_stats_post(bp);
1447 bnx2x_stats_comp(bp);
1448 }
1449
1450 /**
1451 * This function will prepare the statistics ramrod data the way
1452 * we will only have to increment the statistics counter and
1453 * send the ramrod each time we have to.
1454 *
1455 * @param bp
1456 */
1457 static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
1458 {
1459 int i;
1460 struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
1461
1462 dma_addr_t cur_data_offset;
1463 struct stats_query_entry *cur_query_entry;
1464
1465 stats_hdr->cmd_num = bp->fw_stats_num;
1466 stats_hdr->drv_stats_counter = 0;
1467
1468 /* storm_counters struct contains the counters of completed
1469 * statistics requests per storm which are incremented by FW
1470 * each time it completes hadning a statistics ramrod. We will
1471 * check these counters in the timer handler and discard a
1472 * (statistics) ramrod completion.
1473 */
1474 cur_data_offset = bp->fw_stats_data_mapping +
1475 offsetof(struct bnx2x_fw_stats_data, storm_counters);
1476
1477 stats_hdr->stats_counters_addrs.hi =
1478 cpu_to_le32(U64_HI(cur_data_offset));
1479 stats_hdr->stats_counters_addrs.lo =
1480 cpu_to_le32(U64_LO(cur_data_offset));
1481
1482 /* prepare to the first stats ramrod (will be completed with
1483 * the counters equal to zero) - init counters to somethig different.
1484 */
1485 memset(&bp->fw_stats_data->storm_counters, 0xff,
1486 sizeof(struct stats_counter));
1487
1488 /**** Port FW statistics data ****/
1489 cur_data_offset = bp->fw_stats_data_mapping +
1490 offsetof(struct bnx2x_fw_stats_data, port);
1491
1492 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
1493
1494 cur_query_entry->kind = STATS_TYPE_PORT;
1495 /* For port query index is a DONT CARE */
1496 cur_query_entry->index = BP_PORT(bp);
1497 /* For port query funcID is a DONT CARE */
1498 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1499 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1500 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1501
1502 /**** PF FW statistics data ****/
1503 cur_data_offset = bp->fw_stats_data_mapping +
1504 offsetof(struct bnx2x_fw_stats_data, pf);
1505
1506 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
1507
1508 cur_query_entry->kind = STATS_TYPE_PF;
1509 /* For PF query index is a DONT CARE */
1510 cur_query_entry->index = BP_PORT(bp);
1511 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1512 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1513 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1514
1515 /**** Clients' queries ****/
1516 cur_data_offset = bp->fw_stats_data_mapping +
1517 offsetof(struct bnx2x_fw_stats_data, queue_stats);
1518
1519 for_each_eth_queue(bp, i) {
1520 cur_query_entry =
1521 &bp->fw_stats_req->
1522 query[BNX2X_FIRST_QUEUE_QUERY_IDX + i];
1523
1524 cur_query_entry->kind = STATS_TYPE_QUEUE;
1525 cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
1526 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1527 cur_query_entry->address.hi =
1528 cpu_to_le32(U64_HI(cur_data_offset));
1529 cur_query_entry->address.lo =
1530 cpu_to_le32(U64_LO(cur_data_offset));
1531
1532 cur_data_offset += sizeof(struct per_queue_stats);
1533 }
1534 }
1535
1536 void bnx2x_stats_init(struct bnx2x *bp)
1537 {
1538 int /*abs*/port = BP_PORT(bp);
1539 int mb_idx = BP_FW_MB_IDX(bp);
1540 int i;
1541
1542 bp->stats_pending = 0;
1543 bp->executer_idx = 0;
1544 bp->stats_counter = 0;
1545
1546 /* port and func stats for management */
1547 if (!BP_NOMCP(bp)) {
1548 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
1549 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1550
1551 } else {
1552 bp->port.port_stx = 0;
1553 bp->func_stx = 0;
1554 }
1555 DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
1556 bp->port.port_stx, bp->func_stx);
1557
1558 port = BP_PORT(bp);
1559 /* port stats */
1560 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
1561 bp->port.old_nig_stats.brb_discard =
1562 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1563 bp->port.old_nig_stats.brb_truncate =
1564 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
1565 if (!CHIP_IS_E3(bp)) {
1566 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
1567 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
1568 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
1569 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
1570 }
1571
1572 /* function stats */
1573 for_each_queue(bp, i) {
1574 struct bnx2x_fastpath *fp = &bp->fp[i];
1575
1576 memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
1577 memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
1578 memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
1579 memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
1580 }
1581
1582 /* Prepare statistics ramrod data */
1583 bnx2x_prep_fw_stats_req(bp);
1584
1585 memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
1586 memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
1587
1588 bp->stats_state = STATS_STATE_DISABLED;
1589
1590 if (bp->port.pmf) {
1591 if (bp->port.port_stx)
1592 bnx2x_port_stats_base_init(bp);
1593
1594 if (bp->func_stx)
1595 bnx2x_func_stats_base_init(bp);
1596
1597 } else if (bp->func_stx)
1598 bnx2x_func_stats_base_update(bp);
1599 }
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