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Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux
[linux-btrfs-devel.git] / drivers / net / sfc / siena.c
blob2c3bd93fab542d797c7769e438ee8269b283bb88
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
18 #include "bitfield.h"
19 #include "efx.h"
20 #include "nic.h"
21 #include "mac.h"
22 #include "spi.h"
23 #include "regs.h"
24 #include "io.h"
25 #include "phy.h"
26 #include "workarounds.h"
27 #include "mcdi.h"
28 #include "mcdi_pcol.h"
29
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32 static void siena_init_wol(struct efx_nic *efx);
33
34
35 static void siena_push_irq_moderation(struct efx_channel *channel)
36 {
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52 }
53
54 static void siena_push_multicast_hash(struct efx_nic *efx)
55 {
56 WARN_ON(!mutex_is_locked(&efx->mac_lock));
57
58 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
59 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
60 NULL, 0, NULL);
61 }
62
63 static int siena_mdio_write(struct net_device *net_dev,
64 int prtad, int devad, u16 addr, u16 value)
65 {
66 struct efx_nic *efx = netdev_priv(net_dev);
67 uint32_t status;
68 int rc;
69
70 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
71 addr, value, &status);
72 if (rc)
73 return rc;
74 if (status != MC_CMD_MDIO_STATUS_GOOD)
75 return -EIO;
76
77 return 0;
78 }
79
80 static int siena_mdio_read(struct net_device *net_dev,
81 int prtad, int devad, u16 addr)
82 {
83 struct efx_nic *efx = netdev_priv(net_dev);
84 uint16_t value;
85 uint32_t status;
86 int rc;
87
88 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
89 addr, &value, &status);
90 if (rc)
91 return rc;
92 if (status != MC_CMD_MDIO_STATUS_GOOD)
93 return -EIO;
94
95 return (int)value;
96 }
97
98 /* This call is responsible for hooking in the MAC and PHY operations */
99 static int siena_probe_port(struct efx_nic *efx)
100 {
101 int rc;
102
103 /* Hook in PHY operations table */
104 efx->phy_op = &efx_mcdi_phy_ops;
105
106 /* Set up MDIO structure for PHY */
107 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
108 efx->mdio.mdio_read = siena_mdio_read;
109 efx->mdio.mdio_write = siena_mdio_write;
110
111 /* Fill out MDIO structure, loopback modes, and initial link state */
112 rc = efx->phy_op->probe(efx);
113 if (rc != 0)
114 return rc;
115
116 /* Allocate buffer for stats */
117 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
118 MC_CMD_MAC_NSTATS * sizeof(u64));
119 if (rc)
120 return rc;
121 netif_dbg(efx, probe, efx->net_dev,
122 "stats buffer at %llx (virt %p phys %llx)\n",
123 (u64)efx->stats_buffer.dma_addr,
124 efx->stats_buffer.addr,
125 (u64)virt_to_phys(efx->stats_buffer.addr));
126
127 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
128
129 return 0;
130 }
131
132 static void siena_remove_port(struct efx_nic *efx)
133 {
134 efx->phy_op->remove(efx);
135 efx_nic_free_buffer(efx, &efx->stats_buffer);
136 }
137
138 static const struct efx_nic_register_test siena_register_tests[] = {
139 { FR_AZ_ADR_REGION,
140 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
141 { FR_CZ_USR_EV_CFG,
142 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
143 { FR_AZ_RX_CFG,
144 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
145 { FR_AZ_TX_CFG,
146 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
147 { FR_AZ_TX_RESERVED,
148 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
149 { FR_AZ_SRM_TX_DC_CFG,
150 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
151 { FR_AZ_RX_DC_CFG,
152 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
153 { FR_AZ_RX_DC_PF_WM,
154 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
155 { FR_BZ_DP_CTRL,
156 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
157 { FR_BZ_RX_RSS_TKEY,
158 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
159 { FR_CZ_RX_RSS_IPV6_REG1,
160 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
161 { FR_CZ_RX_RSS_IPV6_REG2,
162 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
163 { FR_CZ_RX_RSS_IPV6_REG3,
164 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
165 };
166
167 static int siena_test_registers(struct efx_nic *efx)
168 {
169 return efx_nic_test_registers(efx, siena_register_tests,
170 ARRAY_SIZE(siena_register_tests));
171 }
172
173 /**************************************************************************
174 *
175 * Device reset
176 *
177 **************************************************************************
178 */
179
180 static enum reset_type siena_map_reset_reason(enum reset_type reason)
181 {
182 return RESET_TYPE_ALL;
183 }
184
185 static int siena_map_reset_flags(u32 *flags)
186 {
187 enum {
188 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
189 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
190 ETH_RESET_PHY),
191 SIENA_RESET_MC = (SIENA_RESET_PORT |
192 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
193 };
194
195 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
196 *flags &= ~SIENA_RESET_MC;
197 return RESET_TYPE_WORLD;
198 }
199
200 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
201 *flags &= ~SIENA_RESET_PORT;
202 return RESET_TYPE_ALL;
203 }
204
205 /* no invisible reset implemented */
206
207 return -EINVAL;
208 }
209
210 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
211 {
212 int rc;
213
214 /* Recover from a failed assertion pre-reset */
215 rc = efx_mcdi_handle_assertion(efx);
216 if (rc)
217 return rc;
218
219 if (method == RESET_TYPE_WORLD)
220 return efx_mcdi_reset_mc(efx);
221 else
222 return efx_mcdi_reset_port(efx);
223 }
224
225 static int siena_probe_nvconfig(struct efx_nic *efx)
226 {
227 return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
228 }
229
230 static int siena_probe_nic(struct efx_nic *efx)
231 {
232 struct siena_nic_data *nic_data;
233 bool already_attached = 0;
234 efx_oword_t reg;
235 int rc;
236
237 /* Allocate storage for hardware specific data */
238 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
239 if (!nic_data)
240 return -ENOMEM;
241 efx->nic_data = nic_data;
242
243 if (efx_nic_fpga_ver(efx) != 0) {
244 netif_err(efx, probe, efx->net_dev,
245 "Siena FPGA not supported\n");
246 rc = -ENODEV;
247 goto fail1;
248 }
249
250 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
251 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
252
253 efx_mcdi_init(efx);
254
255 /* Recover from a failed assertion before probing */
256 rc = efx_mcdi_handle_assertion(efx);
257 if (rc)
258 goto fail1;
259
260 /* Let the BMC know that the driver is now in charge of link and
261 * filter settings. We must do this before we reset the NIC */
262 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
263 if (rc) {
264 netif_err(efx, probe, efx->net_dev,
265 "Unable to register driver with MCPU\n");
266 goto fail2;
267 }
268 if (already_attached)
269 /* Not a fatal error */
270 netif_err(efx, probe, efx->net_dev,
271 "Host already registered with MCPU\n");
272
273 /* Now we can reset the NIC */
274 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
275 if (rc) {
276 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
277 goto fail3;
278 }
279
280 siena_init_wol(efx);
281
282 /* Allocate memory for INT_KER */
283 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
284 if (rc)
285 goto fail4;
286 BUG_ON(efx->irq_status.dma_addr & 0x0f);
287
288 netif_dbg(efx, probe, efx->net_dev,
289 "INT_KER at %llx (virt %p phys %llx)\n",
290 (unsigned long long)efx->irq_status.dma_addr,
291 efx->irq_status.addr,
292 (unsigned long long)virt_to_phys(efx->irq_status.addr));
293
294 /* Read in the non-volatile configuration */
295 rc = siena_probe_nvconfig(efx);
296 if (rc == -EINVAL) {
297 netif_err(efx, probe, efx->net_dev,
298 "NVRAM is invalid therefore using defaults\n");
299 efx->phy_type = PHY_TYPE_NONE;
300 efx->mdio.prtad = MDIO_PRTAD_NONE;
301 } else if (rc) {
302 goto fail5;
303 }
304
305 return 0;
306
307 fail5:
308 efx_nic_free_buffer(efx, &efx->irq_status);
309 fail4:
310 fail3:
311 efx_mcdi_drv_attach(efx, false, NULL);
312 fail2:
313 fail1:
314 kfree(efx->nic_data);
315 return rc;
316 }
317
318 /* This call performs hardware-specific global initialisation, such as
319 * defining the descriptor cache sizes and number of RSS channels.
320 * It does not set up any buffers, descriptor rings or event queues.
321 */
322 static int siena_init_nic(struct efx_nic *efx)
323 {
324 efx_oword_t temp;
325 int rc;
326
327 /* Recover from a failed assertion post-reset */
328 rc = efx_mcdi_handle_assertion(efx);
329 if (rc)
330 return rc;
331
332 /* Squash TX of packets of 16 bytes or less */
333 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
334 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
335 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
336
337 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
338 * descriptors (which is bad).
339 */
340 efx_reado(efx, &temp, FR_AZ_TX_CFG);
341 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
342 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
343 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
344
345 efx_reado(efx, &temp, FR_AZ_RX_CFG);
346 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
347 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
348 /* Enable hash insertion. This is broken for the 'Falcon' hash
349 * if IPv6 hashing is also enabled, so also select Toeplitz
350 * TCP/IPv4 and IPv4 hashes. */
351 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
352 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
353 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
354 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
355
356 /* Set hash key for IPv4 */
357 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
358 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
359
360 /* Enable IPv6 RSS */
361 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
362 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
363 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
364 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
365 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
366 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
367 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
368 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
369 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
370 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
371 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
372 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
373
374 /* Enable event logging */
375 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
376 if (rc)
377 return rc;
378
379 /* Set destination of both TX and RX Flush events */
380 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
381 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
382
383 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
384 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
385
386 efx_nic_init_common(efx);
387 return 0;
388 }
389
390 static void siena_remove_nic(struct efx_nic *efx)
391 {
392 efx_nic_free_buffer(efx, &efx->irq_status);
393
394 siena_reset_hw(efx, RESET_TYPE_ALL);
395
396 /* Relinquish the device back to the BMC */
397 if (efx_nic_has_mc(efx))
398 efx_mcdi_drv_attach(efx, false, NULL);
399
400 /* Tear down the private nic state */
401 kfree(efx->nic_data);
402 efx->nic_data = NULL;
403 }
404
405 #define STATS_GENERATION_INVALID ((__force __le64)(-1))
406
407 static int siena_try_update_nic_stats(struct efx_nic *efx)
408 {
409 __le64 *dma_stats;
410 struct efx_mac_stats *mac_stats;
411 __le64 generation_start, generation_end;
412
413 mac_stats = &efx->mac_stats;
414 dma_stats = efx->stats_buffer.addr;
415
416 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
417 if (generation_end == STATS_GENERATION_INVALID)
418 return 0;
419 rmb();
420
421 #define MAC_STAT(M, D) \
422 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
423
424 MAC_STAT(tx_bytes, TX_BYTES);
425 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
426 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
427 mac_stats->tx_bad_bytes);
428 MAC_STAT(tx_packets, TX_PKTS);
429 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
430 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
431 MAC_STAT(tx_control, TX_CONTROL_PKTS);
432 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
433 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
434 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
435 MAC_STAT(tx_lt64, TX_LT64_PKTS);
436 MAC_STAT(tx_64, TX_64_PKTS);
437 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
438 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
439 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
440 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
441 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
442 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
443 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
444 mac_stats->tx_collision = 0;
445 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
446 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
447 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
448 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
449 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
450 mac_stats->tx_collision = (mac_stats->tx_single_collision +
451 mac_stats->tx_multiple_collision +
452 mac_stats->tx_excessive_collision +
453 mac_stats->tx_late_collision);
454 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
455 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
456 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
457 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
458 MAC_STAT(rx_bytes, RX_BYTES);
459 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
460 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
461 mac_stats->rx_bad_bytes);
462 MAC_STAT(rx_packets, RX_PKTS);
463 MAC_STAT(rx_good, RX_GOOD_PKTS);
464 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
465 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
466 MAC_STAT(rx_control, RX_CONTROL_PKTS);
467 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
468 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
469 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
470 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
471 MAC_STAT(rx_64, RX_64_PKTS);
472 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
473 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
474 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
475 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
476 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
477 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
478 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
479 mac_stats->rx_bad_lt64 = 0;
480 mac_stats->rx_bad_64_to_15xx = 0;
481 mac_stats->rx_bad_15xx_to_jumbo = 0;
482 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
483 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
484 mac_stats->rx_missed = 0;
485 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
486 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
487 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
488 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
489 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
490 mac_stats->rx_good_lt64 = 0;
491
492 efx->n_rx_nodesc_drop_cnt =
493 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
494
495 #undef MAC_STAT
496
497 rmb();
498 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
499 if (generation_end != generation_start)
500 return -EAGAIN;
501
502 return 0;
503 }
504
505 static void siena_update_nic_stats(struct efx_nic *efx)
506 {
507 int retry;
508
509 /* If we're unlucky enough to read statistics wduring the DMA, wait
510 * up to 10ms for it to finish (typically takes <500us) */
511 for (retry = 0; retry < 100; ++retry) {
512 if (siena_try_update_nic_stats(efx) == 0)
513 return;
514 udelay(100);
515 }
516
517 /* Use the old values instead */
518 }
519
520 static void siena_start_nic_stats(struct efx_nic *efx)
521 {
522 __le64 *dma_stats = efx->stats_buffer.addr;
523
524 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
525
526 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
527 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
528 }
529
530 static void siena_stop_nic_stats(struct efx_nic *efx)
531 {
532 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
533 }
534
535 /**************************************************************************
536 *
537 * Wake on LAN
538 *
539 **************************************************************************
540 */
541
542 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
543 {
544 struct siena_nic_data *nic_data = efx->nic_data;
545
546 wol->supported = WAKE_MAGIC;
547 if (nic_data->wol_filter_id != -1)
548 wol->wolopts = WAKE_MAGIC;
549 else
550 wol->wolopts = 0;
551 memset(&wol->sopass, 0, sizeof(wol->sopass));
552 }
553
554
555 static int siena_set_wol(struct efx_nic *efx, u32 type)
556 {
557 struct siena_nic_data *nic_data = efx->nic_data;
558 int rc;
559
560 if (type & ~WAKE_MAGIC)
561 return -EINVAL;
562
563 if (type & WAKE_MAGIC) {
564 if (nic_data->wol_filter_id != -1)
565 efx_mcdi_wol_filter_remove(efx,
566 nic_data->wol_filter_id);
567 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
568 &nic_data->wol_filter_id);
569 if (rc)
570 goto fail;
571
572 pci_wake_from_d3(efx->pci_dev, true);
573 } else {
574 rc = efx_mcdi_wol_filter_reset(efx);
575 nic_data->wol_filter_id = -1;
576 pci_wake_from_d3(efx->pci_dev, false);
577 if (rc)
578 goto fail;
579 }
580
581 return 0;
582 fail:
583 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
584 __func__, type, rc);
585 return rc;
586 }
587
588
589 static void siena_init_wol(struct efx_nic *efx)
590 {
591 struct siena_nic_data *nic_data = efx->nic_data;
592 int rc;
593
594 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
595
596 if (rc != 0) {
597 /* If it failed, attempt to get into a synchronised
598 * state with MC by resetting any set WoL filters */
599 efx_mcdi_wol_filter_reset(efx);
600 nic_data->wol_filter_id = -1;
601 } else if (nic_data->wol_filter_id != -1) {
602 pci_wake_from_d3(efx->pci_dev, true);
603 }
604 }
605
606
607 /**************************************************************************
608 *
609 * Revision-dependent attributes used by efx.c and nic.c
610 *
611 **************************************************************************
612 */
613
614 const struct efx_nic_type siena_a0_nic_type = {
615 .probe = siena_probe_nic,
616 .remove = siena_remove_nic,
617 .init = siena_init_nic,
618 .fini = efx_port_dummy_op_void,
619 .monitor = NULL,
620 .map_reset_reason = siena_map_reset_reason,
621 .map_reset_flags = siena_map_reset_flags,
622 .reset = siena_reset_hw,
623 .probe_port = siena_probe_port,
624 .remove_port = siena_remove_port,
625 .prepare_flush = efx_port_dummy_op_void,
626 .update_stats = siena_update_nic_stats,
627 .start_stats = siena_start_nic_stats,
628 .stop_stats = siena_stop_nic_stats,
629 .set_id_led = efx_mcdi_set_id_led,
630 .push_irq_moderation = siena_push_irq_moderation,
631 .push_multicast_hash = siena_push_multicast_hash,
632 .reconfigure_port = efx_mcdi_phy_reconfigure,
633 .get_wol = siena_get_wol,
634 .set_wol = siena_set_wol,
635 .resume_wol = siena_init_wol,
636 .test_registers = siena_test_registers,
637 .test_nvram = efx_mcdi_nvram_test_all,
638 .default_mac_ops = &efx_mcdi_mac_operations,
639
640 .revision = EFX_REV_SIENA_A0,
641 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
642 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
643 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
644 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
645 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
646 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
647 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
648 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
649 .rx_buffer_hash_size = 0x10,
650 .rx_buffer_padding = 0,
651 .max_interrupt_mode = EFX_INT_MODE_MSIX,
652 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
653 * interrupt handler only supports 32
654 * channels */
655 .tx_dc_base = 0x88000,
656 .rx_dc_base = 0x68000,
657 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
658 NETIF_F_RXHASH | NETIF_F_NTUPLE),
659 };
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