drivers/net/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_MAX_TXD                      4096
  57 #define IXGBE_MIN_TXD                        64
  58
  59 #define IXGBE_DEFAULT_RXD                   512
  60 #define IXGBE_MAX_RXD                      4096
  61 #define IXGBE_MIN_RXD                        64
  62
  63 /* flow control */
  64 #define IXGBE_MIN_FCRTL                    0x40
  65 #define IXGBE_MAX_FCRTL                 0x7FF80
  66 #define IXGBE_MIN_FCRTH                   0x600
  67 #define IXGBE_MAX_FCRTH                 0x7FFF0
  68 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  69 #define IXGBE_MIN_FCPAUSE                     0
  70 #define IXGBE_MAX_FCPAUSE                0xFFFF
  71
  72 /* Supported Rx Buffer Sizes */
  73 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  74 #define IXGBE_RXBUFFER_2048  2048
  75 #define IXGBE_RXBUFFER_4096  4096
  76 #define IXGBE_RXBUFFER_8192  8192
  77 #define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */
  78
  79 /*
  80  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  81  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  82  * this adds up to 512 bytes of extra data meaning the smallest allocation
  83  * we could have is 1K.
  84  * i.e. RXBUFFER_512 --> size-1024 slab
  85  */
  86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  87
  88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  89
  90 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  91 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  92
  93 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  94 #define IXGBE_TX_FLAGS_VLAN             (u32)(1 << 1)
  95 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 2)
  96 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 3)
  97 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 4)
  98 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 5)
  99 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
 101 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 102
 103 #define IXGBE_MAX_RSC_INT_RATE          162760
 104
 105 #define IXGBE_MAX_VF_MC_ENTRIES         30
 106 #define IXGBE_MAX_VF_FUNCTIONS          64
 107 #define IXGBE_MAX_VFTA_ENTRIES          128
 108 #define MAX_EMULATION_MAC_ADDRS         16
 109 #define IXGBE_MAX_PF_MACVLANS           15
 110 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 111
 112 struct vf_data_storage {
 113         unsigned char vf_mac_addresses[ETH_ALEN];
 114         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 115         u16 num_vf_mc_hashes;
 116         u16 default_vf_vlan_id;
 117         u16 vlans_enabled;
 118         bool clear_to_send;
 119         bool pf_set_mac;
 120         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 121         u16 pf_qos;
 122         u16 tx_rate;
 123 };
 124
 125 struct vf_macvlans {
 126         struct list_head l;
 127         int vf;
 128         int rar_entry;
 129         bool free;
 130         bool is_macvlan;
 131         u8 vf_macvlan[ETH_ALEN];
 132 };
 133
 134 /* wrapper around a pointer to a socket buffer,
 135  * so a DMA handle can be stored along with the buffer */
 136 struct ixgbe_tx_buffer {
 137         struct sk_buff *skb;
 138         dma_addr_t dma;
 139         unsigned long time_stamp;
 140         u16 length;
 141         u16 next_to_watch;
 142         unsigned int bytecount;
 143         u16 gso_segs;
 144         u8 mapped_as_page;
 145 };
 146
 147 struct ixgbe_rx_buffer {
 148         struct sk_buff *skb;
 149         dma_addr_t dma;
 150         struct page *page;
 151         dma_addr_t page_dma;
 152         unsigned int page_offset;
 153 };
 154
 155 struct ixgbe_queue_stats {
 156         u64 packets;
 157         u64 bytes;
 158 };
 159
 160 struct ixgbe_tx_queue_stats {
 161         u64 restart_queue;
 162         u64 tx_busy;
 163         u64 completed;
 164         u64 tx_done_old;
 165 };
 166
 167 struct ixgbe_rx_queue_stats {
 168         u64 rsc_count;
 169         u64 rsc_flush;
 170         u64 non_eop_descs;
 171         u64 alloc_rx_page_failed;
 172         u64 alloc_rx_buff_failed;
 173 };
 174
 175 enum ixbge_ring_state_t {
 176         __IXGBE_TX_FDIR_INIT_DONE,
 177         __IXGBE_TX_DETECT_HANG,
 178         __IXGBE_HANG_CHECK_ARMED,
 179         __IXGBE_RX_PS_ENABLED,
 180         __IXGBE_RX_RSC_ENABLED,
 181 };
 182
 183 #define ring_is_ps_enabled(ring) \
 184         test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 185 #define set_ring_ps_enabled(ring) \
 186         set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 187 #define clear_ring_ps_enabled(ring) \
 188         clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 189 #define check_for_tx_hang(ring) \
 190         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 191 #define set_check_for_tx_hang(ring) \
 192         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 193 #define clear_check_for_tx_hang(ring) \
 194         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 195 #define ring_is_rsc_enabled(ring) \
 196         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 197 #define set_ring_rsc_enabled(ring) \
 198         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 199 #define clear_ring_rsc_enabled(ring) \
 200         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 201 struct ixgbe_ring {
 202         void *desc;                     /* descriptor ring memory */
 203         struct device *dev;             /* device for DMA mapping */
 204         struct net_device *netdev;      /* netdev ring belongs to */
 205         union {
 206                 struct ixgbe_tx_buffer *tx_buffer_info;
 207                 struct ixgbe_rx_buffer *rx_buffer_info;
 208         };
 209         unsigned long state;
 210         u8 atr_sample_rate;
 211         u8 atr_count;
 212         u16 count;                      /* amount of descriptors */
 213         u16 rx_buf_len;
 214         u16 next_to_use;
 215         u16 next_to_clean;
 216
 217         u8 queue_index; /* needed for multiqueue queue management */
 218         u8 reg_idx;                     /* holds the special value that gets
 219                                          * the hardware register offset
 220                                          * associated with this ring, which is
 221                                          * different for DCB and RSS modes
 222                                          */
 223         u8 dcb_tc;
 224
 225         u16 work_limit;                 /* max work per interrupt */
 226
 227         u8 __iomem *tail;
 228
 229         unsigned int total_bytes;
 230         unsigned int total_packets;
 231
 232         struct ixgbe_queue_stats stats;
 233         struct u64_stats_sync syncp;
 234         union {
 235                 struct ixgbe_tx_queue_stats tx_stats;
 236                 struct ixgbe_rx_queue_stats rx_stats;
 237         };
 238         int numa_node;
 239         unsigned int size;              /* length in bytes */
 240         dma_addr_t dma;                 /* phys. address of descriptor ring */
 241         struct rcu_head rcu;
 242         struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 243 } ____cacheline_internodealigned_in_smp;
 244
 245 enum ixgbe_ring_f_enum {
 246         RING_F_NONE = 0,
 247         RING_F_DCB,
 248         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 249         RING_F_RSS,
 250         RING_F_FDIR,
 251 #ifdef IXGBE_FCOE
 252         RING_F_FCOE,
 253 #endif /* IXGBE_FCOE */
 254
 255         RING_F_ARRAY_SIZE      /* must be last in enum set */
 256 };
 257
 258 #define IXGBE_MAX_DCB_INDICES  64
 259 #define IXGBE_MAX_RSS_INDICES  16
 260 #define IXGBE_MAX_VMDQ_INDICES 64
 261 #define IXGBE_MAX_FDIR_INDICES 64
 262 #ifdef IXGBE_FCOE
 263 #define IXGBE_MAX_FCOE_INDICES  8
 264 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 265 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 266 #else
 267 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 268 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 269 #endif /* IXGBE_FCOE */
 270 struct ixgbe_ring_feature {
 271         int indices;
 272         int mask;
 273 } ____cacheline_internodealigned_in_smp;
 274
 275
 276 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 277                               ? 8 : 1)
 278 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 279
 280 /* MAX_MSIX_Q_VECTORS of these are allocated,
 281  * but we only use one per queue-specific vector.
 282  */
 283 struct ixgbe_q_vector {
 284         struct ixgbe_adapter *adapter;
 285         unsigned int v_idx; /* index of q_vector within array, also used for
 286                              * finding the bit in EICR and friends that
 287                              * represents the vector for this ring */
 288 #ifdef CONFIG_IXGBE_DCA
 289         int cpu;            /* CPU for DCA */
 290 #endif
 291         struct napi_struct napi;
 292         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
 293         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
 294         u8 rxr_count;     /* Rx ring count assigned to this vector */
 295         u8 txr_count;     /* Tx ring count assigned to this vector */
 296         u8 tx_itr;
 297         u8 rx_itr;
 298         u32 eitr;
 299         cpumask_var_t affinity_mask;
 300         char name[IFNAMSIZ + 9];
 301 };
 302
 303 /* Helper macros to switch between ints/sec and what the register uses.
 304  * And yes, it's the same math going both ways.  The lowest value
 305  * supported by all of the ixgbe hardware is 8.
 306  */
 307 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 308         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
 309 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 310
 311 #define IXGBE_DESC_UNUSED(R) \
 312         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 313         (R)->next_to_clean - (R)->next_to_use - 1)
 314
 315 #define IXGBE_RX_DESC_ADV(R, i)     \
 316         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 317 #define IXGBE_TX_DESC_ADV(R, i)     \
 318         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 319 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 320         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 321
 322 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 323 #ifdef IXGBE_FCOE
 324 /* Use 3K as the baby jumbo frame size for FCoE */
 325 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 326 #endif /* IXGBE_FCOE */
 327
 328 #define OTHER_VECTOR 1
 329 #define NON_Q_VECTORS (OTHER_VECTOR)
 330
 331 #define MAX_MSIX_VECTORS_82599 64
 332 #define MAX_MSIX_Q_VECTORS_82599 64
 333 #define MAX_MSIX_VECTORS_82598 18
 334 #define MAX_MSIX_Q_VECTORS_82598 16
 335
 336 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 337 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 338
 339 #define MIN_MSIX_Q_VECTORS 2
 340 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 341
 342 /* board specific private data structure */
 343 struct ixgbe_adapter {
 344         unsigned long state;
 345
 346         /* Some features need tri-state capability,
 347          * thus the additional *_CAPABLE flags.
 348          */
 349         u32 flags;
 350 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 351 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 352 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 353 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 354 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 355 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 356 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 357 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 358 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 359 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 360 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 361 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 362 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 363 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 364 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 365 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 366 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 367 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 368 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 369 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 370 #define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 23)
 371 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 24)
 372 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 25)
 373 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 26)
 374 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 27)
 375 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 28)
 376 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 29)
 377
 378         u32 flags2;
 379 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 380 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 381 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 382 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)
 383 #define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)
 384 #define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)
 385 #define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)
 386 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)
 387
 388         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 389         u16 bd_number;
 390         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 391
 392         /* DCB parameters */
 393         struct ieee_pfc *ixgbe_ieee_pfc;
 394         struct ieee_ets *ixgbe_ieee_ets;
 395         struct ixgbe_dcb_config dcb_cfg;
 396         struct ixgbe_dcb_config temp_dcb_cfg;
 397         u8 dcb_set_bitmap;
 398         u8 dcbx_cap;
 399         enum ixgbe_fc_mode last_lfc_mode;
 400
 401         /* Interrupt Throttle Rate */
 402         u32 rx_itr_setting;
 403         u32 tx_itr_setting;
 404         u16 eitr_low;
 405         u16 eitr_high;
 406
 407         /* TX */
 408         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 409         int num_tx_queues;
 410         u32 tx_timeout_count;
 411         bool detect_tx_hung;
 412
 413         u64 restart_queue;
 414         u64 lsc_int;
 415
 416         /* RX */
 417         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
 418         int num_rx_queues;
 419         int num_rx_pools;               /* == num_rx_queues in 82598 */
 420         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 421         u64 hw_csum_rx_error;
 422         u64 hw_rx_no_dma_resources;
 423         u64 non_eop_descs;
 424         int num_msix_vectors;
 425         int max_msix_q_vectors;         /* true count of q_vectors for device */
 426         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 427         struct msix_entry *msix_entries;
 428
 429         u32 alloc_rx_page_failed;
 430         u32 alloc_rx_buff_failed;
 431
 432 /* default to trying for four seconds */
 433 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 434
 435         /* OS defined structs */
 436         struct net_device *netdev;
 437         struct pci_dev *pdev;
 438
 439         u32 test_icr;
 440         struct ixgbe_ring test_tx_ring;
 441         struct ixgbe_ring test_rx_ring;
 442
 443         /* structs defined in ixgbe_hw.h */
 444         struct ixgbe_hw hw;
 445         u16 msg_enable;
 446         struct ixgbe_hw_stats stats;
 447
 448         /* Interrupt Throttle Rate */
 449         u32 rx_eitr_param;
 450         u32 tx_eitr_param;
 451
 452         u64 tx_busy;
 453         unsigned int tx_ring_count;
 454         unsigned int rx_ring_count;
 455
 456         u32 link_speed;
 457         bool link_up;
 458         unsigned long link_check_timeout;
 459
 460         struct work_struct service_task;
 461         struct timer_list service_timer;
 462         u32 fdir_pballoc;
 463         u32 atr_sample_rate;
 464         unsigned long fdir_overflow; /* number of times ATR was backed off */
 465         spinlock_t fdir_perfect_lock;
 466 #ifdef IXGBE_FCOE
 467         struct ixgbe_fcoe fcoe;
 468 #endif /* IXGBE_FCOE */
 469         u64 rsc_total_count;
 470         u64 rsc_total_flush;
 471         u32 wol;
 472         u16 eeprom_version;
 473
 474         int node;
 475         u32 led_reg;
 476         u32 interrupt_event;
 477         char lsc_int_name[IFNAMSIZ + 9];
 478
 479         /* SR-IOV */
 480         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 481         unsigned int num_vfs;
 482         struct vf_data_storage *vfinfo;
 483         int vf_rate_link_speed;
 484         struct vf_macvlans vf_mvs;
 485         struct vf_macvlans *mv_list;
 486         bool antispoofing_enabled;
 487 };
 488
 489 enum ixbge_state_t {
 490         __IXGBE_TESTING,
 491         __IXGBE_RESETTING,
 492         __IXGBE_DOWN,
 493         __IXGBE_SERVICE_SCHED,
 494         __IXGBE_IN_SFP_INIT,
 495 };
 496
 497 struct ixgbe_rsc_cb {
 498         dma_addr_t dma;
 499         u16 skb_cnt;
 500         bool delay_unmap;
 501 };
 502 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
 503
 504 enum ixgbe_boards {
 505         board_82598,
 506         board_82599,
 507         board_X540,
 508 };
 509
 510 extern struct ixgbe_info ixgbe_82598_info;
 511 extern struct ixgbe_info ixgbe_82599_info;
 512 extern struct ixgbe_info ixgbe_X540_info;
 513 #ifdef CONFIG_IXGBE_DCB
 514 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 515 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 516                               struct ixgbe_dcb_config *dst_dcb_cfg,
 517                               int tc_max);
 518 #endif
 519
 520 extern char ixgbe_driver_name[];
 521 extern const char ixgbe_driver_version[];
 522
 523 extern int ixgbe_up(struct ixgbe_adapter *adapter);
 524 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 525 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 526 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 527 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 528 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 529 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 530 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 531 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 532 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 533 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 534 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 535                                    struct ixgbe_ring *);
 536 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 537 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 538 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 539 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 540                                          struct ixgbe_adapter *,
 541                                          struct ixgbe_ring *);
 542 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 543                                              struct ixgbe_tx_buffer *);
 544 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 545 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 546 extern int ethtool_ioctl(struct ifreq *ifr);
 547 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 548 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 549 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
 550 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 551                                                  union ixgbe_atr_hash_dword input,
 552                                                  union ixgbe_atr_hash_dword common,
 553                                                  u8 queue);
 554 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
 555                                       union ixgbe_atr_input *input,
 556                                       struct ixgbe_atr_input_masks *input_masks,
 557                                       u16 soft_id, u8 queue);
 558 extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
 559                                    struct ixgbe_ring *ring);
 560 extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
 561                                struct ixgbe_ring *ring);
 562 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 563 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 564 #ifdef IXGBE_FCOE
 565 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 566 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
 567                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 568                      u32 tx_flags, u8 *hdr_len);
 569 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 570 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 571                           union ixgbe_adv_rx_desc *rx_desc,
 572                           struct sk_buff *skb);
 573 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 574                               struct scatterlist *sgl, unsigned int sgc);
 575 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 576                                  struct scatterlist *sgl, unsigned int sgc);
 577 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 578 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 579 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 580 #ifdef CONFIG_IXGBE_DCB
 581 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 582 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 583 #endif /* CONFIG_IXGBE_DCB */
 584 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 585 #endif /* IXGBE_FCOE */
 586
 587 #endif /* _IXGBE_H_ */