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Input: wacom - fix touch parsing on newer Bamboos
[linux-btrfs-devel.git] / drivers / net / wireless / rtlwifi / rtl8192ce / hw.c
blobdefb4370cf74f500c787a8cb93859eaa11271b2a
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "../rtl8192c/fw_common.h"
41 #include "dm.h"
42 #include "led.h"
43 #include "hw.h"
44
45 #define LLT_CONFIG 5
46
47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
48 u8 set_bits, u8 clear_bits)
49 {
50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52
53 rtlpci->reg_bcn_ctrl_val |= set_bits;
54 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
55
56 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
57 }
58
59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
60 {
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
62 u8 tmp1byte;
63
64 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
65 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
66 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
67 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
68 tmp1byte &= ~(BIT(0));
69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
70 }
71
72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
73 {
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 u8 tmp1byte;
76
77 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
78 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
79 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
80 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
81 tmp1byte |= BIT(0);
82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
83 }
84
85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
86 {
87 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
88 }
89
90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
91 {
92 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
93 }
94
95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
96 {
97 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
99 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
100
101 switch (variable) {
102 case HW_VAR_RCR:
103 *((u32 *) (val)) = rtlpci->receive_config;
104 break;
105 case HW_VAR_RF_STATE:
106 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
107 break;
108 case HW_VAR_FWLPS_RF_ON:{
109 enum rf_pwrstate rfState;
110 u32 val_rcr;
111
112 rtlpriv->cfg->ops->get_hw_reg(hw,
113 HW_VAR_RF_STATE,
114 (u8 *) (&rfState));
115 if (rfState == ERFOFF) {
116 *((bool *) (val)) = true;
117 } else {
118 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
119 val_rcr &= 0x00070000;
120 if (val_rcr)
121 *((bool *) (val)) = false;
122 else
123 *((bool *) (val)) = true;
124 }
125 break;
126 }
127 case HW_VAR_FW_PSMODE_STATUS:
128 *((bool *) (val)) = ppsc->fw_current_inpsmode;
129 break;
130 case HW_VAR_CORRECT_TSF:{
131 u64 tsf;
132 u32 *ptsf_low = (u32 *)&tsf;
133 u32 *ptsf_high = ((u32 *)&tsf) + 1;
134
135 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
136 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
137
138 *((u64 *) (val)) = tsf;
139
140 break;
141 }
142 default:
143 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
144 ("switch case not process\n"));
145 break;
146 }
147 }
148
149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150 {
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
153 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
157 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
158 u8 idx;
159
160 switch (variable) {
161 case HW_VAR_ETHER_ADDR:{
162 for (idx = 0; idx < ETH_ALEN; idx++) {
163 rtl_write_byte(rtlpriv, (REG_MACID + idx),
164 val[idx]);
165 }
166 break;
167 }
168 case HW_VAR_BASIC_RATE:{
169 u16 rate_cfg = ((u16 *) val)[0];
170 u8 rate_index = 0;
171 rate_cfg &= 0x15f;
172 rate_cfg |= 0x01;
173 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
174 rtl_write_byte(rtlpriv, REG_RRSR + 1,
175 (rate_cfg >> 8) & 0xff);
176 while (rate_cfg > 0x1) {
177 rate_cfg = (rate_cfg >> 1);
178 rate_index++;
179 }
180 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
181 rate_index);
182 break;
183 }
184 case HW_VAR_BSSID:{
185 for (idx = 0; idx < ETH_ALEN; idx++) {
186 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
187 val[idx]);
188 }
189 break;
190 }
191 case HW_VAR_SIFS:{
192 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
193 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
194
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
197
198 if (!mac->ht_enable)
199 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
200 0x0e0e);
201 else
202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
203 *((u16 *) val));
204 break;
205 }
206 case HW_VAR_SLOT_TIME:{
207 u8 e_aci;
208
209 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
210 ("HW_VAR_SLOT_TIME %x\n", val[0]));
211
212 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
213
214 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
215 rtlpriv->cfg->ops->set_hw_reg(hw,
216 HW_VAR_AC_PARAM,
217 (u8 *) (&e_aci));
218 }
219 break;
220 }
221 case HW_VAR_ACK_PREAMBLE:{
222 u8 reg_tmp;
223 u8 short_preamble = (bool) (*(u8 *) val);
224 reg_tmp = (mac->cur_40_prime_sc) << 5;
225 if (short_preamble)
226 reg_tmp |= 0x80;
227
228 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
229 break;
230 }
231 case HW_VAR_AMPDU_MIN_SPACE:{
232 u8 min_spacing_to_set;
233 u8 sec_min_space;
234
235 min_spacing_to_set = *((u8 *) val);
236 if (min_spacing_to_set <= 7) {
237 sec_min_space = 0;
238
239 if (min_spacing_to_set < sec_min_space)
240 min_spacing_to_set = sec_min_space;
241
242 mac->min_space_cfg = ((mac->min_space_cfg &
243 0xf8) |
244 min_spacing_to_set);
245
246 *val = min_spacing_to_set;
247
248 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
249 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
250 mac->min_space_cfg));
251
252 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
253 mac->min_space_cfg);
254 }
255 break;
256 }
257 case HW_VAR_SHORTGI_DENSITY:{
258 u8 density_to_set;
259
260 density_to_set = *((u8 *) val);
261 mac->min_space_cfg |= (density_to_set << 3);
262
263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
265 mac->min_space_cfg));
266
267 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
268 mac->min_space_cfg);
269
270 break;
271 }
272 case HW_VAR_AMPDU_FACTOR:{
273 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
274 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
275
276 u8 factor_toset;
277 u8 *p_regtoset = NULL;
278 u8 index = 0;
279
280 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
281 (rtlpcipriv->bt_coexist.bt_coexist_type ==
282 BT_CSR_BC4))
283 p_regtoset = regtoset_bt;
284 else
285 p_regtoset = regtoset_normal;
286
287 factor_toset = *((u8 *) val);
288 if (factor_toset <= 3) {
289 factor_toset = (1 << (factor_toset + 2));
290 if (factor_toset > 0xf)
291 factor_toset = 0xf;
292
293 for (index = 0; index < 4; index++) {
294 if ((p_regtoset[index] & 0xf0) >
295 (factor_toset << 4))
296 p_regtoset[index] =
297 (p_regtoset[index] & 0x0f) |
298 (factor_toset << 4);
299
300 if ((p_regtoset[index] & 0x0f) >
301 factor_toset)
302 p_regtoset[index] =
303 (p_regtoset[index] & 0xf0) |
304 (factor_toset);
305
306 rtl_write_byte(rtlpriv,
307 (REG_AGGLEN_LMT + index),
308 p_regtoset[index]);
309
310 }
311
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset));
315 }
316 break;
317 }
318 case HW_VAR_AC_PARAM:{
319 u8 e_aci = *((u8 *) val);
320 rtl92c_dm_init_edca_turbo(hw);
321
322 if (rtlpci->acm_method != eAcmWay2_SW)
323 rtlpriv->cfg->ops->set_hw_reg(hw,
324 HW_VAR_ACM_CTRL,
325 (u8 *) (&e_aci));
326 break;
327 }
328 case HW_VAR_ACM_CTRL:{
329 u8 e_aci = *((u8 *) val);
330 union aci_aifsn *p_aci_aifsn =
331 (union aci_aifsn *)(&(mac->ac[0].aifs));
332 u8 acm = p_aci_aifsn->f.acm;
333 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
334
335 acm_ctrl =
336 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
337
338 if (acm) {
339 switch (e_aci) {
340 case AC0_BE:
341 acm_ctrl |= AcmHw_BeqEn;
342 break;
343 case AC2_VI:
344 acm_ctrl |= AcmHw_ViqEn;
345 break;
346 case AC3_VO:
347 acm_ctrl |= AcmHw_VoqEn;
348 break;
349 default:
350 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
351 ("HW_VAR_ACM_CTRL acm set "
352 "failed: eACI is %d\n", acm));
353 break;
354 }
355 } else {
356 switch (e_aci) {
357 case AC0_BE:
358 acm_ctrl &= (~AcmHw_BeqEn);
359 break;
360 case AC2_VI:
361 acm_ctrl &= (~AcmHw_ViqEn);
362 break;
363 case AC3_VO:
364 acm_ctrl &= (~AcmHw_BeqEn);
365 break;
366 default:
367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
368 ("switch case not process\n"));
369 break;
370 }
371 }
372
373 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
374 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
375 "Write 0x%X\n", acm_ctrl));
376 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
377 break;
378 }
379 case HW_VAR_RCR:{
380 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
381 rtlpci->receive_config = ((u32 *) (val))[0];
382 break;
383 }
384 case HW_VAR_RETRY_LIMIT:{
385 u8 retry_limit = ((u8 *) (val))[0];
386
387 rtl_write_word(rtlpriv, REG_RL,
388 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
389 retry_limit << RETRY_LIMIT_LONG_SHIFT);
390 break;
391 }
392 case HW_VAR_DUAL_TSF_RST:
393 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
394 break;
395 case HW_VAR_EFUSE_BYTES:
396 rtlefuse->efuse_usedbytes = *((u16 *) val);
397 break;
398 case HW_VAR_EFUSE_USAGE:
399 rtlefuse->efuse_usedpercentage = *((u8 *) val);
400 break;
401 case HW_VAR_IO_CMD:
402 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
403 break;
404 case HW_VAR_WPA_CONFIG:
405 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
406 break;
407 case HW_VAR_SET_RPWM:{
408 u8 rpwm_val;
409
410 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
411 udelay(1);
412
413 if (rpwm_val & BIT(7)) {
414 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
415 (*(u8 *) val));
416 } else {
417 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
418 ((*(u8 *) val) | BIT(7)));
419 }
420
421 break;
422 }
423 case HW_VAR_H2C_FW_PWRMODE:{
424 u8 psmode = (*(u8 *) val);
425
426 if ((psmode != FW_PS_ACTIVE_MODE) &&
427 (!IS_92C_SERIAL(rtlhal->version))) {
428 rtl92c_dm_rf_saving(hw, true);
429 }
430
431 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
432 break;
433 }
434 case HW_VAR_FW_PSMODE_STATUS:
435 ppsc->fw_current_inpsmode = *((bool *) val);
436 break;
437 case HW_VAR_H2C_FW_JOINBSSRPT:{
438 u8 mstatus = (*(u8 *) val);
439 u8 tmp_regcr, tmp_reg422;
440 bool recover = false;
441
442 if (mstatus == RT_MEDIA_CONNECT) {
443 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
444 NULL);
445
446 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
447 rtl_write_byte(rtlpriv, REG_CR + 1,
448 (tmp_regcr | BIT(0)));
449
450 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
451 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
452
453 tmp_reg422 =
454 rtl_read_byte(rtlpriv,
455 REG_FWHW_TXQ_CTRL + 2);
456 if (tmp_reg422 & BIT(6))
457 recover = true;
458 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
459 tmp_reg422 & (~BIT(6)));
460
461 rtl92c_set_fw_rsvdpagepkt(hw, 0);
462
463 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
464 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
465
466 if (recover) {
467 rtl_write_byte(rtlpriv,
468 REG_FWHW_TXQ_CTRL + 2,
469 tmp_reg422);
470 }
471
472 rtl_write_byte(rtlpriv, REG_CR + 1,
473 (tmp_regcr & ~(BIT(0))));
474 }
475 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
476
477 break;
478 }
479 case HW_VAR_AID:{
480 u16 u2btmp;
481 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
482 u2btmp &= 0xC000;
483 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
484 mac->assoc_id));
485
486 break;
487 }
488 case HW_VAR_CORRECT_TSF:{
489 u8 btype_ibss = ((u8 *) (val))[0];
490
491 if (btype_ibss == true)
492 _rtl92ce_stop_tx_beacon(hw);
493
494 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
495
496 rtl_write_dword(rtlpriv, REG_TSFTR,
497 (u32) (mac->tsf & 0xffffffff));
498 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
499 (u32) ((mac->tsf >> 32) & 0xffffffff));
500
501 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
502
503 if (btype_ibss == true)
504 _rtl92ce_resume_tx_beacon(hw);
505
506 break;
507
508 }
509 default:
510 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
511 "not process\n"));
512 break;
513 }
514 }
515
516 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
517 {
518 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 bool status = true;
520 long count = 0;
521 u32 value = _LLT_INIT_ADDR(address) |
522 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
523
524 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
525
526 do {
527 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
528 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
529 break;
530
531 if (count > POLLING_LLT_THRESHOLD) {
532 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
533 ("Failed to polling write LLT done at "
534 "address %d!\n", address));
535 status = false;
536 break;
537 }
538 } while (++count);
539
540 return status;
541 }
542
543 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
544 {
545 struct rtl_priv *rtlpriv = rtl_priv(hw);
546 unsigned short i;
547 u8 txpktbuf_bndy;
548 u8 maxPage;
549 bool status;
550
551 #if LLT_CONFIG == 1
552 maxPage = 255;
553 txpktbuf_bndy = 252;
554 #elif LLT_CONFIG == 2
555 maxPage = 127;
556 txpktbuf_bndy = 124;
557 #elif LLT_CONFIG == 3
558 maxPage = 255;
559 txpktbuf_bndy = 174;
560 #elif LLT_CONFIG == 4
561 maxPage = 255;
562 txpktbuf_bndy = 246;
563 #elif LLT_CONFIG == 5
564 maxPage = 255;
565 txpktbuf_bndy = 246;
566 #endif
567
568 #if LLT_CONFIG == 1
569 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
570 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
571 #elif LLT_CONFIG == 2
572 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
573 #elif LLT_CONFIG == 3
574 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
575 #elif LLT_CONFIG == 4
576 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
577 #elif LLT_CONFIG == 5
578 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
579
580 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
581 #endif
582
583 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
584 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
585
586 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
587 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
588
589 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
590 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
591 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
592
593 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
594 status = _rtl92ce_llt_write(hw, i, i + 1);
595 if (true != status)
596 return status;
597 }
598
599 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
600 if (true != status)
601 return status;
602
603 for (i = txpktbuf_bndy; i < maxPage; i++) {
604 status = _rtl92ce_llt_write(hw, i, (i + 1));
605 if (true != status)
606 return status;
607 }
608
609 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
610 if (true != status)
611 return status;
612
613 return true;
614 }
615
616 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
617 {
618 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
619 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
620 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
621 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
622
623 if (rtlpci->up_first_time)
624 return;
625
626 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
627 rtl92ce_sw_led_on(hw, pLed0);
628 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
629 rtl92ce_sw_led_on(hw, pLed0);
630 else
631 rtl92ce_sw_led_off(hw, pLed0);
632 }
633
634 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
635 {
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
638 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
639 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
640
641 unsigned char bytetmp;
642 unsigned short wordtmp;
643 u16 retry;
644
645 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
646 if (rtlpcipriv->bt_coexist.bt_coexistence) {
647 u32 value32;
648 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
649 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
650 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
651 }
652 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
653 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
654
655 if (rtlpcipriv->bt_coexist.bt_coexistence) {
656 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
657
658 u4b_tmp &= (~0x00024800);
659 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
660 }
661
662 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
663 udelay(2);
664
665 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
666 udelay(2);
667
668 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
669 udelay(2);
670
671 retry = 0;
672 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
673 rtl_read_dword(rtlpriv, 0xEC),
674 bytetmp));
675
676 while ((bytetmp & BIT(0)) && retry < 1000) {
677 retry++;
678 udelay(50);
679 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
680 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
681 rtl_read_dword(rtlpriv,
682 0xEC),
683 bytetmp));
684 udelay(50);
685 }
686
687 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
688
689 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
690 udelay(2);
691
692 if (rtlpcipriv->bt_coexist.bt_coexistence) {
693 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
694 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
695 }
696
697 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
698
699 if (_rtl92ce_llt_table_init(hw) == false)
700 return false;
701
702 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
703 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
704
705 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
706
707 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
708 wordtmp &= 0xf;
709 wordtmp |= 0xF771;
710 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
711
712 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
713 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
714 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
715
716 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
717
718 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
719 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
720 DMA_BIT_MASK(32));
721 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
722 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
723 DMA_BIT_MASK(32));
724 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
725 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
726 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
727 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
728 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
729 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
730 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
731 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
732 rtl_write_dword(rtlpriv, REG_HQ_DESA,
733 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
734 DMA_BIT_MASK(32));
735 rtl_write_dword(rtlpriv, REG_RX_DESA,
736 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
737 DMA_BIT_MASK(32));
738
739 if (IS_92C_SERIAL(rtlhal->version))
740 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
741 else
742 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
743
744 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
745
746 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
747 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
748 do {
749 retry++;
750 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
751 } while ((retry < 200) && (bytetmp & BIT(7)));
752
753 _rtl92ce_gen_refresh_led_state(hw);
754
755 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
756
757 return true;
758 }
759
760 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
761 {
762 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
763 struct rtl_priv *rtlpriv = rtl_priv(hw);
764 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
765 u8 reg_bw_opmode;
766 u32 reg_ratr, reg_prsr;
767
768 reg_bw_opmode = BW_OPMODE_20MHZ;
769 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
770 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
771 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
772
773 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
774
775 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
776
777 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
778
779 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
780
781 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
782
783 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
784
785 rtl_write_word(rtlpriv, REG_RL, 0x0707);
786
787 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
788
789 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
790
791 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
792 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
793 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
794 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
795
796 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
797 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
798 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
799 else
800 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
801
802 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
803
804 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
805
806 rtlpci->reg_bcn_ctrl_val = 0x1f;
807 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
808
809 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
810
811 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
812
813 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
814 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
815
816 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
817 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
818 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
819 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
820 } else {
821 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
822 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
823 }
824
825 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
826 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
827 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
828 else
829 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
830
831 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
832
833 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
834 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
835
836 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
837
838 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
839
840 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
841 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
842
843 }
844
845 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
846 {
847 struct rtl_priv *rtlpriv = rtl_priv(hw);
848 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
849
850 rtl_write_byte(rtlpriv, 0x34b, 0x93);
851 rtl_write_word(rtlpriv, 0x350, 0x870c);
852 rtl_write_byte(rtlpriv, 0x352, 0x1);
853
854 if (ppsc->support_backdoor)
855 rtl_write_byte(rtlpriv, 0x349, 0x1b);
856 else
857 rtl_write_byte(rtlpriv, 0x349, 0x03);
858
859 rtl_write_word(rtlpriv, 0x350, 0x2718);
860 rtl_write_byte(rtlpriv, 0x352, 0x1);
861 }
862
863 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
864 {
865 struct rtl_priv *rtlpriv = rtl_priv(hw);
866 u8 sec_reg_value;
867
868 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
869 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
870 rtlpriv->sec.pairwise_enc_algorithm,
871 rtlpriv->sec.group_enc_algorithm));
872
873 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
874 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
875 "hw encryption\n"));
876 return;
877 }
878
879 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
880
881 if (rtlpriv->sec.use_defaultkey) {
882 sec_reg_value |= SCR_TxUseDK;
883 sec_reg_value |= SCR_RxUseDK;
884 }
885
886 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
887
888 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
889
890 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
891 ("The SECR-value %x\n", sec_reg_value));
892
893 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
894
895 }
896
897 int rtl92ce_hw_init(struct ieee80211_hw *hw)
898 {
899 struct rtl_priv *rtlpriv = rtl_priv(hw);
900 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
901 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
902 struct rtl_phy *rtlphy = &(rtlpriv->phy);
903 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
904 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
905 static bool iqk_initialized; /* initialized to false */
906 bool rtstatus = true;
907 bool is92c;
908 int err;
909 u8 tmp_u1b;
910
911 rtlpci->being_init_adapter = true;
912 rtlpriv->intf_ops->disable_aspm(hw);
913 rtstatus = _rtl92ce_init_mac(hw);
914 if (rtstatus != true) {
915 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
916 err = 1;
917 return err;
918 }
919
920 err = rtl92c_download_fw(hw);
921 if (err) {
922 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
923 ("Failed to download FW. Init HW "
924 "without FW now..\n"));
925 err = 1;
926 rtlhal->fw_ready = false;
927 return err;
928 } else {
929 rtlhal->fw_ready = true;
930 }
931
932 rtlhal->last_hmeboxnum = 0;
933 rtl92c_phy_mac_config(hw);
934 rtl92c_phy_bb_config(hw);
935 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
936 rtl92c_phy_rf_config(hw);
937 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
938 RF_CHNLBW, RFREG_OFFSET_MASK);
939 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
940 RF_CHNLBW, RFREG_OFFSET_MASK);
941 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
942 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
943 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
944 _rtl92ce_hw_configure(hw);
945 rtl_cam_reset_all_entry(hw);
946 rtl92ce_enable_hw_security_config(hw);
947
948 ppsc->rfpwr_state = ERFON;
949
950 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
951 _rtl92ce_enable_aspm_back_door(hw);
952 rtlpriv->intf_ops->enable_aspm(hw);
953
954 rtl8192ce_bt_hw_init(hw);
955
956 if (ppsc->rfpwr_state == ERFON) {
957 rtl92c_phy_set_rfpath_switch(hw, 1);
958 if (iqk_initialized) {
959 rtl92c_phy_iq_calibrate(hw, true);
960 } else {
961 rtl92c_phy_iq_calibrate(hw, false);
962 iqk_initialized = true;
963 }
964
965 rtl92c_dm_check_txpower_tracking(hw);
966 rtl92c_phy_lc_calibrate(hw);
967 }
968
969 is92c = IS_92C_SERIAL(rtlhal->version);
970 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
971 if (!(tmp_u1b & BIT(0))) {
972 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
973 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
974 }
975
976 if (!(tmp_u1b & BIT(1)) && is92c) {
977 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
978 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
979 }
980
981 if (!(tmp_u1b & BIT(4))) {
982 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
983 tmp_u1b &= 0x0F;
984 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
985 udelay(10);
986 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
987 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
988 }
989 rtl92c_dm_init(hw);
990 rtlpci->being_init_adapter = false;
991 return err;
992 }
993
994 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
995 {
996 struct rtl_priv *rtlpriv = rtl_priv(hw);
997 struct rtl_phy *rtlphy = &(rtlpriv->phy);
998 enum version_8192c version = VERSION_UNKNOWN;
999 u32 value32;
1000
1001 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1002 if (value32 & TRP_VAUX_EN) {
1003 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1004 VERSION_A_CHIP_88C;
1005 } else {
1006 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1007 VERSION_B_CHIP_88C;
1008 }
1009
1010 switch (version) {
1011 case VERSION_B_CHIP_92C:
1012 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1013 ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1014 break;
1015 case VERSION_B_CHIP_88C:
1016 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1017 ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1018 break;
1019 case VERSION_A_CHIP_92C:
1020 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1021 ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1022 break;
1023 case VERSION_A_CHIP_88C:
1024 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1025 ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1026 break;
1027 default:
1028 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1029 ("Chip Version ID: Unknown. Bug?\n"));
1030 break;
1031 }
1032
1033 switch (version & 0x3) {
1034 case CHIP_88C:
1035 rtlphy->rf_type = RF_1T1R;
1036 break;
1037 case CHIP_92C:
1038 rtlphy->rf_type = RF_2T2R;
1039 break;
1040 case CHIP_92C_1T2R:
1041 rtlphy->rf_type = RF_1T2R;
1042 break;
1043 default:
1044 rtlphy->rf_type = RF_1T1R;
1045 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1046 ("ERROR RF_Type is set!!"));
1047 break;
1048 }
1049
1050 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1051 ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1052 "RF_2T2R" : "RF_1T1R"));
1053
1054 return version;
1055 }
1056
1057 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1058 enum nl80211_iftype type)
1059 {
1060 struct rtl_priv *rtlpriv = rtl_priv(hw);
1061 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1062 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1063 bt_msr &= 0xfc;
1064
1065 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1066 type == NL80211_IFTYPE_STATION) {
1067 _rtl92ce_stop_tx_beacon(hw);
1068 _rtl92ce_enable_bcn_sub_func(hw);
1069 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1070 _rtl92ce_resume_tx_beacon(hw);
1071 _rtl92ce_disable_bcn_sub_func(hw);
1072 } else {
1073 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1074 ("Set HW_VAR_MEDIA_STATUS: "
1075 "No such media status(%x).\n", type));
1076 }
1077
1078 switch (type) {
1079 case NL80211_IFTYPE_UNSPECIFIED:
1080 bt_msr |= MSR_NOLINK;
1081 ledaction = LED_CTL_LINK;
1082 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1083 ("Set Network type to NO LINK!\n"));
1084 break;
1085 case NL80211_IFTYPE_ADHOC:
1086 bt_msr |= MSR_ADHOC;
1087 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1088 ("Set Network type to Ad Hoc!\n"));
1089 break;
1090 case NL80211_IFTYPE_STATION:
1091 bt_msr |= MSR_INFRA;
1092 ledaction = LED_CTL_LINK;
1093 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1094 ("Set Network type to STA!\n"));
1095 break;
1096 case NL80211_IFTYPE_AP:
1097 bt_msr |= MSR_AP;
1098 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1099 ("Set Network type to AP!\n"));
1100 break;
1101 default:
1102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1103 ("Network type %d not support!\n", type));
1104 return 1;
1105 break;
1106
1107 }
1108
1109 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1110 rtlpriv->cfg->ops->led_control(hw, ledaction);
1111 if ((bt_msr & 0xfc) == MSR_AP)
1112 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1113 else
1114 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1115 return 0;
1116 }
1117
1118 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1119 {
1120 struct rtl_priv *rtlpriv = rtl_priv(hw);
1121 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1122
1123 if (rtlpriv->psc.rfpwr_state != ERFON)
1124 return;
1125
1126 if (check_bssid == true) {
1127 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1128 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1129 (u8 *) (&reg_rcr));
1130 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1131 } else if (check_bssid == false) {
1132 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1133 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1134 rtlpriv->cfg->ops->set_hw_reg(hw,
1135 HW_VAR_RCR, (u8 *) (&reg_rcr));
1136 }
1137
1138 }
1139
1140 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1141 {
1142 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143
1144 if (_rtl92ce_set_media_status(hw, type))
1145 return -EOPNOTSUPP;
1146
1147 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1148 if (type != NL80211_IFTYPE_AP)
1149 rtl92ce_set_check_bssid(hw, true);
1150 } else {
1151 rtl92ce_set_check_bssid(hw, false);
1152 }
1153
1154 return 0;
1155 }
1156
1157 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1158 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1159 {
1160 struct rtl_priv *rtlpriv = rtl_priv(hw);
1161 rtl92c_dm_init_edca_turbo(hw);
1162 switch (aci) {
1163 case AC1_BK:
1164 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1165 break;
1166 case AC0_BE:
1167 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1168 break;
1169 case AC2_VI:
1170 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1171 break;
1172 case AC3_VO:
1173 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1174 break;
1175 default:
1176 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1177 break;
1178 }
1179 }
1180
1181 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1182 {
1183 struct rtl_priv *rtlpriv = rtl_priv(hw);
1184 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1185
1186 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1187 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1188 rtlpci->irq_enabled = true;
1189 }
1190
1191 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1192 {
1193 struct rtl_priv *rtlpriv = rtl_priv(hw);
1194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1195
1196 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1197 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1198 rtlpci->irq_enabled = false;
1199 }
1200
1201 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1202 {
1203 struct rtl_priv *rtlpriv = rtl_priv(hw);
1204 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1206 u8 u1b_tmp;
1207 u32 u4b_tmp;
1208
1209 rtlpriv->intf_ops->enable_aspm(hw);
1210 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1211 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1212 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1213 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1214 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1215 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1216 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1217 rtl92c_firmware_selfreset(hw);
1218 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1219 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1220 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1221 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1222 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1223 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1224 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1225 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1226 (u1b_tmp << 8));
1227 } else {
1228 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1229 (u1b_tmp << 8));
1230 }
1231 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1232 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1233 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1234 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1235 if (rtlpcipriv->bt_coexist.bt_coexistence) {
1236 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1237 u4b_tmp |= 0x03824800;
1238 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1239 } else {
1240 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1241 }
1242
1243 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1244 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1245 }
1246
1247 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1248 {
1249 struct rtl_priv *rtlpriv = rtl_priv(hw);
1250 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1251 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1252 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1253 enum nl80211_iftype opmode;
1254
1255 mac->link_state = MAC80211_NOLINK;
1256 opmode = NL80211_IFTYPE_UNSPECIFIED;
1257 _rtl92ce_set_media_status(hw, opmode);
1258 if (rtlpci->driver_is_goingto_unload ||
1259 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1260 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1261 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1262 _rtl92ce_poweroff_adapter(hw);
1263 }
1264
1265 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1266 u32 *p_inta, u32 *p_intb)
1267 {
1268 struct rtl_priv *rtlpriv = rtl_priv(hw);
1269 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1270
1271 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1272 rtl_write_dword(rtlpriv, ISR, *p_inta);
1273
1274 /*
1275 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1276 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1277 */
1278 }
1279
1280 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1281 {
1282
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1285 u16 bcn_interval, atim_window;
1286
1287 bcn_interval = mac->beacon_interval;
1288 atim_window = 2; /*FIX MERGE */
1289 rtl92ce_disable_interrupt(hw);
1290 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1291 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1292 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1293 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1294 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1295 rtl_write_byte(rtlpriv, 0x606, 0x30);
1296 rtl92ce_enable_interrupt(hw);
1297 }
1298
1299 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1300 {
1301 struct rtl_priv *rtlpriv = rtl_priv(hw);
1302 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1303 u16 bcn_interval = mac->beacon_interval;
1304
1305 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1306 ("beacon_interval:%d\n", bcn_interval));
1307 rtl92ce_disable_interrupt(hw);
1308 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1309 rtl92ce_enable_interrupt(hw);
1310 }
1311
1312 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1313 u32 add_msr, u32 rm_msr)
1314 {
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1317
1318 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1319 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1320
1321 if (add_msr)
1322 rtlpci->irq_mask[0] |= add_msr;
1323 if (rm_msr)
1324 rtlpci->irq_mask[0] &= (~rm_msr);
1325 rtl92ce_disable_interrupt(hw);
1326 rtl92ce_enable_interrupt(hw);
1327 }
1328
1329 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1330 bool autoload_fail,
1331 u8 *hwinfo)
1332 {
1333 struct rtl_priv *rtlpriv = rtl_priv(hw);
1334 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1335 u8 rf_path, index, tempval;
1336 u16 i;
1337
1338 for (rf_path = 0; rf_path < 2; rf_path++) {
1339 for (i = 0; i < 3; i++) {
1340 if (!autoload_fail) {
1341 rtlefuse->
1342 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1343 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1344 rtlefuse->
1345 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1346 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1347 i];
1348 } else {
1349 rtlefuse->
1350 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1351 EEPROM_DEFAULT_TXPOWERLEVEL;
1352 rtlefuse->
1353 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1354 EEPROM_DEFAULT_TXPOWERLEVEL;
1355 }
1356 }
1357 }
1358
1359 for (i = 0; i < 3; i++) {
1360 if (!autoload_fail)
1361 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1362 else
1363 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1364 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1365 (tempval & 0xf);
1366 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1367 ((tempval & 0xf0) >> 4);
1368 }
1369
1370 for (rf_path = 0; rf_path < 2; rf_path++)
1371 for (i = 0; i < 3; i++)
1372 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1373 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1374 i,
1375 rtlefuse->
1376 eeprom_chnlarea_txpwr_cck[rf_path][i]));
1377 for (rf_path = 0; rf_path < 2; rf_path++)
1378 for (i = 0; i < 3; i++)
1379 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1380 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1381 rf_path, i,
1382 rtlefuse->
1383 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1384 for (rf_path = 0; rf_path < 2; rf_path++)
1385 for (i = 0; i < 3; i++)
1386 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1387 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1388 rf_path, i,
1389 rtlefuse->
1390 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1391 [i]));
1392
1393 for (rf_path = 0; rf_path < 2; rf_path++) {
1394 for (i = 0; i < 14; i++) {
1395 index = _rtl92c_get_chnl_group((u8) i);
1396
1397 rtlefuse->txpwrlevel_cck[rf_path][i] =
1398 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1399 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1400 rtlefuse->
1401 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1402
1403 if ((rtlefuse->
1404 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1405 rtlefuse->
1406 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1407 > 0) {
1408 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1409 rtlefuse->
1410 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1411 [index] -
1412 rtlefuse->
1413 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1414 [index];
1415 } else {
1416 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1417 }
1418 }
1419
1420 for (i = 0; i < 14; i++) {
1421 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1422 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1423 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1424 rtlefuse->txpwrlevel_cck[rf_path][i],
1425 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1426 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1427 }
1428 }
1429
1430 for (i = 0; i < 3; i++) {
1431 if (!autoload_fail) {
1432 rtlefuse->eeprom_pwrlimit_ht40[i] =
1433 hwinfo[EEPROM_TXPWR_GROUP + i];
1434 rtlefuse->eeprom_pwrlimit_ht20[i] =
1435 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1436 } else {
1437 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1438 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1439 }
1440 }
1441
1442 for (rf_path = 0; rf_path < 2; rf_path++) {
1443 for (i = 0; i < 14; i++) {
1444 index = _rtl92c_get_chnl_group((u8) i);
1445
1446 if (rf_path == RF90_PATH_A) {
1447 rtlefuse->pwrgroup_ht20[rf_path][i] =
1448 (rtlefuse->eeprom_pwrlimit_ht20[index]
1449 & 0xf);
1450 rtlefuse->pwrgroup_ht40[rf_path][i] =
1451 (rtlefuse->eeprom_pwrlimit_ht40[index]
1452 & 0xf);
1453 } else if (rf_path == RF90_PATH_B) {
1454 rtlefuse->pwrgroup_ht20[rf_path][i] =
1455 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1456 & 0xf0) >> 4);
1457 rtlefuse->pwrgroup_ht40[rf_path][i] =
1458 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1459 & 0xf0) >> 4);
1460 }
1461
1462 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1463 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1464 rf_path, i,
1465 rtlefuse->pwrgroup_ht20[rf_path][i]));
1466 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1467 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1468 rf_path, i,
1469 rtlefuse->pwrgroup_ht40[rf_path][i]));
1470 }
1471 }
1472
1473 for (i = 0; i < 14; i++) {
1474 index = _rtl92c_get_chnl_group((u8) i);
1475
1476 if (!autoload_fail)
1477 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1478 else
1479 tempval = EEPROM_DEFAULT_HT20_DIFF;
1480
1481 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1482 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1483 ((tempval >> 4) & 0xF);
1484
1485 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1486 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1487
1488 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1489 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1490
1491 index = _rtl92c_get_chnl_group((u8) i);
1492
1493 if (!autoload_fail)
1494 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1495 else
1496 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1497
1498 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1499 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1500 ((tempval >> 4) & 0xF);
1501 }
1502
1503 rtlefuse->legacy_ht_txpowerdiff =
1504 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1505
1506 for (i = 0; i < 14; i++)
1507 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1508 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1509 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1510 for (i = 0; i < 14; i++)
1511 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1512 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1513 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1514 for (i = 0; i < 14; i++)
1515 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1516 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1517 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1518 for (i = 0; i < 14; i++)
1519 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1520 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1521 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1522
1523 if (!autoload_fail)
1524 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1525 else
1526 rtlefuse->eeprom_regulatory = 0;
1527 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1528 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1529
1530 if (!autoload_fail) {
1531 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1532 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1533 } else {
1534 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1535 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1536 }
1537 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1538 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1539 rtlefuse->eeprom_tssi[RF90_PATH_A],
1540 rtlefuse->eeprom_tssi[RF90_PATH_B]));
1541
1542 if (!autoload_fail)
1543 tempval = hwinfo[EEPROM_THERMAL_METER];
1544 else
1545 tempval = EEPROM_DEFAULT_THERMALMETER;
1546 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1547
1548 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1549 rtlefuse->apk_thermalmeterignore = true;
1550
1551 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1552 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1553 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1554 }
1555
1556 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1557 {
1558 struct rtl_priv *rtlpriv = rtl_priv(hw);
1559 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1560 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1561 u16 i, usvalue;
1562 u8 hwinfo[HWSET_MAX_SIZE];
1563 u16 eeprom_id;
1564
1565 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1566 rtl_efuse_shadow_map_update(hw);
1567
1568 memcpy((void *)hwinfo,
1569 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1570 HWSET_MAX_SIZE);
1571 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1572 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1573 ("RTL819X Not boot from eeprom, check it !!"));
1574 }
1575
1576 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1577 hwinfo, HWSET_MAX_SIZE);
1578
1579 eeprom_id = *((u16 *)&hwinfo[0]);
1580 if (eeprom_id != RTL8190_EEPROM_ID) {
1581 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1582 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1583 rtlefuse->autoload_failflag = true;
1584 } else {
1585 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1586 rtlefuse->autoload_failflag = false;
1587 }
1588
1589 if (rtlefuse->autoload_failflag == true)
1590 return;
1591
1592 for (i = 0; i < 6; i += 2) {
1593 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1594 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1595 }
1596
1597 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1598 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1599
1600 _rtl92ce_read_txpower_info_from_hwpg(hw,
1601 rtlefuse->autoload_failflag,
1602 hwinfo);
1603
1604 rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1605 rtlefuse->autoload_failflag,
1606 hwinfo);
1607
1608 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1609 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1610 rtlefuse->txpwr_fromeprom = true;
1611 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1612
1613 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1614 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1615
1616 /* set channel paln to world wide 13 */
1617 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1618
1619 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1620 switch (rtlefuse->eeprom_oemid) {
1621 case EEPROM_CID_DEFAULT:
1622 if (rtlefuse->eeprom_did == 0x8176) {
1623 if ((rtlefuse->eeprom_svid == 0x103C &&
1624 rtlefuse->eeprom_smid == 0x1629))
1625 rtlhal->oem_id = RT_CID_819x_HP;
1626 else
1627 rtlhal->oem_id = RT_CID_DEFAULT;
1628 } else {
1629 rtlhal->oem_id = RT_CID_DEFAULT;
1630 }
1631 break;
1632 case EEPROM_CID_TOSHIBA:
1633 rtlhal->oem_id = RT_CID_TOSHIBA;
1634 break;
1635 case EEPROM_CID_QMI:
1636 rtlhal->oem_id = RT_CID_819x_QMI;
1637 break;
1638 case EEPROM_CID_WHQL:
1639 default:
1640 rtlhal->oem_id = RT_CID_DEFAULT;
1641 break;
1642
1643 }
1644 }
1645
1646 }
1647
1648 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1649 {
1650 struct rtl_priv *rtlpriv = rtl_priv(hw);
1651 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1652 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1653
1654 switch (rtlhal->oem_id) {
1655 case RT_CID_819x_HP:
1656 pcipriv->ledctl.led_opendrain = true;
1657 break;
1658 case RT_CID_819x_Lenovo:
1659 case RT_CID_DEFAULT:
1660 case RT_CID_TOSHIBA:
1661 case RT_CID_CCX:
1662 case RT_CID_819x_Acer:
1663 case RT_CID_WHQL:
1664 default:
1665 break;
1666 }
1667 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1668 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1669 }
1670
1671 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1672 {
1673 struct rtl_priv *rtlpriv = rtl_priv(hw);
1674 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1675 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1676 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1677 u8 tmp_u1b;
1678
1679 rtlhal->version = _rtl92ce_read_chip_version(hw);
1680 if (get_rf_type(rtlphy) == RF_1T1R)
1681 rtlpriv->dm.rfpath_rxenable[0] = true;
1682 else
1683 rtlpriv->dm.rfpath_rxenable[0] =
1684 rtlpriv->dm.rfpath_rxenable[1] = true;
1685 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1686 rtlhal->version));
1687 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1688 if (tmp_u1b & BIT(4)) {
1689 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1690 rtlefuse->epromtype = EEPROM_93C46;
1691 } else {
1692 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1693 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1694 }
1695 if (tmp_u1b & BIT(5)) {
1696 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1697 rtlefuse->autoload_failflag = false;
1698 _rtl92ce_read_adapter_info(hw);
1699 } else {
1700 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1701 }
1702 _rtl92ce_hal_customized_behavior(hw);
1703 }
1704
1705 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1706 struct ieee80211_sta *sta)
1707 {
1708 struct rtl_priv *rtlpriv = rtl_priv(hw);
1709 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1710 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1711 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1712 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1713 u32 ratr_value;
1714 u8 ratr_index = 0;
1715 u8 nmode = mac->ht_enable;
1716 u8 mimo_ps = IEEE80211_SMPS_OFF;
1717 u16 shortgi_rate;
1718 u32 tmp_ratr_value;
1719 u8 curtxbw_40mhz = mac->bw_40;
1720 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1721 1 : 0;
1722 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1723 1 : 0;
1724 enum wireless_mode wirelessmode = mac->mode;
1725
1726 if (rtlhal->current_bandtype == BAND_ON_5G)
1727 ratr_value = sta->supp_rates[1] << 4;
1728 else
1729 ratr_value = sta->supp_rates[0];
1730 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1731 sta->ht_cap.mcs.rx_mask[0] << 12);
1732 switch (wirelessmode) {
1733 case WIRELESS_MODE_B:
1734 if (ratr_value & 0x0000000c)
1735 ratr_value &= 0x0000000d;
1736 else
1737 ratr_value &= 0x0000000f;
1738 break;
1739 case WIRELESS_MODE_G:
1740 ratr_value &= 0x00000FF5;
1741 break;
1742 case WIRELESS_MODE_N_24G:
1743 case WIRELESS_MODE_N_5G:
1744 nmode = 1;
1745 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1746 ratr_value &= 0x0007F005;
1747 } else {
1748 u32 ratr_mask;
1749
1750 if (get_rf_type(rtlphy) == RF_1T2R ||
1751 get_rf_type(rtlphy) == RF_1T1R)
1752 ratr_mask = 0x000ff005;
1753 else
1754 ratr_mask = 0x0f0ff005;
1755
1756 ratr_value &= ratr_mask;
1757 }
1758 break;
1759 default:
1760 if (rtlphy->rf_type == RF_1T2R)
1761 ratr_value &= 0x000ff0ff;
1762 else
1763 ratr_value &= 0x0f0ff0ff;
1764
1765 break;
1766 }
1767
1768 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1769 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1770 (rtlpcipriv->bt_coexist.bt_cur_state) &&
1771 (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1772 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1773 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1774 ratr_value &= 0x0fffcfc0;
1775 else
1776 ratr_value &= 0x0FFFFFFF;
1777
1778 if (nmode && ((curtxbw_40mhz &&
1779 curshortgi_40mhz) || (!curtxbw_40mhz &&
1780 curshortgi_20mhz))) {
1781
1782 ratr_value |= 0x10000000;
1783 tmp_ratr_value = (ratr_value >> 12);
1784
1785 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1786 if ((1 << shortgi_rate) & tmp_ratr_value)
1787 break;
1788 }
1789
1790 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1791 (shortgi_rate << 4) | (shortgi_rate);
1792 }
1793
1794 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1795
1796 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1797 ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1798 }
1799
1800 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1801 struct ieee80211_sta *sta, u8 rssi_level)
1802 {
1803 struct rtl_priv *rtlpriv = rtl_priv(hw);
1804 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1805 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1807 struct rtl_sta_info *sta_entry = NULL;
1808 u32 ratr_bitmap;
1809 u8 ratr_index;
1810 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1811 ? 1 : 0;
1812 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1813 1 : 0;
1814 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1815 1 : 0;
1816 enum wireless_mode wirelessmode = 0;
1817 bool shortgi = false;
1818 u8 rate_mask[5];
1819 u8 macid = 0;
1820 u8 mimo_ps = IEEE80211_SMPS_OFF;
1821
1822 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1823 wirelessmode = sta_entry->wireless_mode;
1824 if (mac->opmode == NL80211_IFTYPE_STATION)
1825 curtxbw_40mhz = mac->bw_40;
1826 else if (mac->opmode == NL80211_IFTYPE_AP ||
1827 mac->opmode == NL80211_IFTYPE_ADHOC)
1828 macid = sta->aid + 1;
1829
1830 if (rtlhal->current_bandtype == BAND_ON_5G)
1831 ratr_bitmap = sta->supp_rates[1] << 4;
1832 else
1833 ratr_bitmap = sta->supp_rates[0];
1834 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1835 sta->ht_cap.mcs.rx_mask[0] << 12);
1836 switch (wirelessmode) {
1837 case WIRELESS_MODE_B:
1838 ratr_index = RATR_INX_WIRELESS_B;
1839 if (ratr_bitmap & 0x0000000c)
1840 ratr_bitmap &= 0x0000000d;
1841 else
1842 ratr_bitmap &= 0x0000000f;
1843 break;
1844 case WIRELESS_MODE_G:
1845 ratr_index = RATR_INX_WIRELESS_GB;
1846
1847 if (rssi_level == 1)
1848 ratr_bitmap &= 0x00000f00;
1849 else if (rssi_level == 2)
1850 ratr_bitmap &= 0x00000ff0;
1851 else
1852 ratr_bitmap &= 0x00000ff5;
1853 break;
1854 case WIRELESS_MODE_A:
1855 ratr_index = RATR_INX_WIRELESS_A;
1856 ratr_bitmap &= 0x00000ff0;
1857 break;
1858 case WIRELESS_MODE_N_24G:
1859 case WIRELESS_MODE_N_5G:
1860 ratr_index = RATR_INX_WIRELESS_NGB;
1861
1862 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1863 if (rssi_level == 1)
1864 ratr_bitmap &= 0x00070000;
1865 else if (rssi_level == 2)
1866 ratr_bitmap &= 0x0007f000;
1867 else
1868 ratr_bitmap &= 0x0007f005;
1869 } else {
1870 if (rtlphy->rf_type == RF_1T2R ||
1871 rtlphy->rf_type == RF_1T1R) {
1872 if (curtxbw_40mhz) {
1873 if (rssi_level == 1)
1874 ratr_bitmap &= 0x000f0000;
1875 else if (rssi_level == 2)
1876 ratr_bitmap &= 0x000ff000;
1877 else
1878 ratr_bitmap &= 0x000ff015;
1879 } else {
1880 if (rssi_level == 1)
1881 ratr_bitmap &= 0x000f0000;
1882 else if (rssi_level == 2)
1883 ratr_bitmap &= 0x000ff000;
1884 else
1885 ratr_bitmap &= 0x000ff005;
1886 }
1887 } else {
1888 if (curtxbw_40mhz) {
1889 if (rssi_level == 1)
1890 ratr_bitmap &= 0x0f0f0000;
1891 else if (rssi_level == 2)
1892 ratr_bitmap &= 0x0f0ff000;
1893 else
1894 ratr_bitmap &= 0x0f0ff015;
1895 } else {
1896 if (rssi_level == 1)
1897 ratr_bitmap &= 0x0f0f0000;
1898 else if (rssi_level == 2)
1899 ratr_bitmap &= 0x0f0ff000;
1900 else
1901 ratr_bitmap &= 0x0f0ff005;
1902 }
1903 }
1904 }
1905
1906 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1907 (!curtxbw_40mhz && curshortgi_20mhz)) {
1908
1909 if (macid == 0)
1910 shortgi = true;
1911 else if (macid == 1)
1912 shortgi = false;
1913 }
1914 break;
1915 default:
1916 ratr_index = RATR_INX_WIRELESS_NGB;
1917
1918 if (rtlphy->rf_type == RF_1T2R)
1919 ratr_bitmap &= 0x000ff0ff;
1920 else
1921 ratr_bitmap &= 0x0f0ff0ff;
1922 break;
1923 }
1924 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1925 ("ratr_bitmap :%x\n", ratr_bitmap));
1926 *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1927 (ratr_index << 28));
1928 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1929 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1930 "ratr_val:%x, %x:%x:%x:%x:%x\n",
1931 ratr_index, ratr_bitmap,
1932 rate_mask[0], rate_mask[1],
1933 rate_mask[2], rate_mask[3],
1934 rate_mask[4]));
1935 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1936
1937 if (macid != 0)
1938 sta_entry->ratr_index = ratr_index;
1939 }
1940
1941 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1942 struct ieee80211_sta *sta, u8 rssi_level)
1943 {
1944 struct rtl_priv *rtlpriv = rtl_priv(hw);
1945
1946 if (rtlpriv->dm.useramask)
1947 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1948 else
1949 rtl92ce_update_hal_rate_table(hw, sta);
1950 }
1951
1952 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1953 {
1954 struct rtl_priv *rtlpriv = rtl_priv(hw);
1955 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1956 u16 sifs_timer;
1957
1958 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1959 (u8 *)&mac->slot_time);
1960 if (!mac->ht_enable)
1961 sifs_timer = 0x0a0a;
1962 else
1963 sifs_timer = 0x1010;
1964 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1965 }
1966
1967 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1968 {
1969 struct rtl_priv *rtlpriv = rtl_priv(hw);
1970 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1971 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1972 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
1973 u8 u1tmp;
1974 bool actuallyset = false;
1975 unsigned long flag;
1976
1977 if (rtlpci->being_init_adapter)
1978 return false;
1979
1980 if (ppsc->swrf_processing)
1981 return false;
1982
1983 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1984 if (ppsc->rfchange_inprogress) {
1985 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1986 return false;
1987 } else {
1988 ppsc->rfchange_inprogress = true;
1989 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1990 }
1991
1992 cur_rfstate = ppsc->rfpwr_state;
1993
1994 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1995 REG_MAC_PINMUX_CFG)&~(BIT(3)));
1996
1997 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1998 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1999
2000 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
2001 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2002 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
2003
2004 e_rfpowerstate_toset = ERFON;
2005 ppsc->hwradiooff = false;
2006 actuallyset = true;
2007 } else if ((ppsc->hwradiooff == false)
2008 && (e_rfpowerstate_toset == ERFOFF)) {
2009 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2010 ("GPIOChangeRF - HW Radio OFF, RF OFF\n"));
2011
2012 e_rfpowerstate_toset = ERFOFF;
2013 ppsc->hwradiooff = true;
2014 actuallyset = true;
2015 }
2016
2017 if (actuallyset) {
2018 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2019 ppsc->rfchange_inprogress = false;
2020 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2021 } else {
2022 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2023 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2024
2025 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2026 ppsc->rfchange_inprogress = false;
2027 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2028 }
2029
2030 *valid = 1;
2031 return !ppsc->hwradiooff;
2032
2033 }
2034
2035 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2036 u8 *p_macaddr, bool is_group, u8 enc_algo,
2037 bool is_wepkey, bool clear_all)
2038 {
2039 struct rtl_priv *rtlpriv = rtl_priv(hw);
2040 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2041 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2042 u8 *macaddr = p_macaddr;
2043 u32 entry_id = 0;
2044 bool is_pairwise = false;
2045
2046 static u8 cam_const_addr[4][6] = {
2047 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2048 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2049 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2050 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2051 };
2052 static u8 cam_const_broad[] = {
2053 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2054 };
2055
2056 if (clear_all) {
2057 u8 idx = 0;
2058 u8 cam_offset = 0;
2059 u8 clear_number = 5;
2060
2061 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2062
2063 for (idx = 0; idx < clear_number; idx++) {
2064 rtl_cam_mark_invalid(hw, cam_offset + idx);
2065 rtl_cam_empty_entry(hw, cam_offset + idx);
2066
2067 if (idx < 5) {
2068 memset(rtlpriv->sec.key_buf[idx], 0,
2069 MAX_KEY_LEN);
2070 rtlpriv->sec.key_len[idx] = 0;
2071 }
2072 }
2073
2074 } else {
2075 switch (enc_algo) {
2076 case WEP40_ENCRYPTION:
2077 enc_algo = CAM_WEP40;
2078 break;
2079 case WEP104_ENCRYPTION:
2080 enc_algo = CAM_WEP104;
2081 break;
2082 case TKIP_ENCRYPTION:
2083 enc_algo = CAM_TKIP;
2084 break;
2085 case AESCCMP_ENCRYPTION:
2086 enc_algo = CAM_AES;
2087 break;
2088 default:
2089 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2090 "not process\n"));
2091 enc_algo = CAM_TKIP;
2092 break;
2093 }
2094
2095 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2096 macaddr = cam_const_addr[key_index];
2097 entry_id = key_index;
2098 } else {
2099 if (is_group) {
2100 macaddr = cam_const_broad;
2101 entry_id = key_index;
2102 } else {
2103 if (mac->opmode == NL80211_IFTYPE_AP) {
2104 entry_id = rtl_cam_get_free_entry(hw,
2105 p_macaddr);
2106 if (entry_id >= TOTAL_CAM_ENTRY) {
2107 RT_TRACE(rtlpriv, COMP_SEC,
2108 DBG_EMERG,
2109 ("Can not find free hw"
2110 " security cam entry\n"));
2111 return;
2112 }
2113 } else {
2114 entry_id = CAM_PAIRWISE_KEY_POSITION;
2115 }
2116
2117 key_index = PAIRWISE_KEYIDX;
2118 is_pairwise = true;
2119 }
2120 }
2121
2122 if (rtlpriv->sec.key_len[key_index] == 0) {
2123 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2124 ("delete one entry, entry_id is %d\n",
2125 entry_id));
2126 if (mac->opmode == NL80211_IFTYPE_AP)
2127 rtl_cam_del_entry(hw, p_macaddr);
2128 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2129 } else {
2130 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2131 ("The insert KEY length is %d\n",
2132 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2133 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2134 ("The insert KEY is %x %x\n",
2135 rtlpriv->sec.key_buf[0][0],
2136 rtlpriv->sec.key_buf[0][1]));
2137
2138 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2139 ("add one entry\n"));
2140 if (is_pairwise) {
2141 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2142 "Pairwiase Key content :",
2143 rtlpriv->sec.pairwise_key,
2144 rtlpriv->sec.
2145 key_len[PAIRWISE_KEYIDX]);
2146
2147 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2148 ("set Pairwiase key\n"));
2149
2150 rtl_cam_add_one_entry(hw, macaddr, key_index,
2151 entry_id, enc_algo,
2152 CAM_CONFIG_NO_USEDK,
2153 rtlpriv->sec.
2154 key_buf[key_index]);
2155 } else {
2156 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2157 ("set group key\n"));
2158
2159 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2160 rtl_cam_add_one_entry(hw,
2161 rtlefuse->dev_addr,
2162 PAIRWISE_KEYIDX,
2163 CAM_PAIRWISE_KEY_POSITION,
2164 enc_algo,
2165 CAM_CONFIG_NO_USEDK,
2166 rtlpriv->sec.key_buf
2167 [entry_id]);
2168 }
2169
2170 rtl_cam_add_one_entry(hw, macaddr, key_index,
2171 entry_id, enc_algo,
2172 CAM_CONFIG_NO_USEDK,
2173 rtlpriv->sec.key_buf[entry_id]);
2174 }
2175
2176 }
2177 }
2178 }
2179
2180 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2181 {
2182 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2183
2184 rtlpcipriv->bt_coexist.bt_coexistence =
2185 rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2186 rtlpcipriv->bt_coexist.bt_ant_num =
2187 rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2188 rtlpcipriv->bt_coexist.bt_coexist_type =
2189 rtlpcipriv->bt_coexist.eeprom_bt_type;
2190
2191 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2192 rtlpcipriv->bt_coexist.bt_ant_isolation =
2193 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2194 else
2195 rtlpcipriv->bt_coexist.bt_ant_isolation =
2196 rtlpcipriv->bt_coexist.reg_bt_iso;
2197
2198 rtlpcipriv->bt_coexist.bt_radio_shared_type =
2199 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2200
2201 if (rtlpcipriv->bt_coexist.bt_coexistence) {
2202
2203 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2204 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2205 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2206 rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2207 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2208 rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2209 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2210 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2211 else
2212 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2213
2214 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2215 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2216 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2217 }
2218 }
2219
2220 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2221 bool auto_load_fail, u8 *hwinfo)
2222 {
2223 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2224 u8 value;
2225
2226 if (!auto_load_fail) {
2227 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2228 ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2229 value = hwinfo[RF_OPTION4];
2230 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2231 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2232 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2233 ((value & 0x10) >> 4);
2234 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2235 ((value & 0x20) >> 5);
2236 } else {
2237 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2238 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2239 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2240 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2241 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2242 }
2243
2244 rtl8192ce_bt_var_init(hw);
2245 }
2246
2247 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2248 {
2249 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2250
2251 /* 0:Low, 1:High, 2:From Efuse. */
2252 rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2253 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2254 rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2255 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2256 rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2257 }
2258
2259
2260 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2261 {
2262 struct rtl_priv *rtlpriv = rtl_priv(hw);
2263 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2264 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2265
2266 u8 u1_tmp;
2267
2268 if (rtlpcipriv->bt_coexist.bt_coexistence &&
2269 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2270 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2271
2272 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2273 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2274
2275 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2276 BIT_OFFSET_LEN_MASK_32(0, 1);
2277 u1_tmp = u1_tmp |
2278 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2279 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2280 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2281 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2282 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2283
2284 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2285 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2286 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2287
2288 /* Config to 1T1R. */
2289 if (rtlphy->rf_type == RF_1T1R) {
2290 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2291 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2292 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2293
2294 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2295 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2296 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2297 }
2298 }
2299 }
2300
2301 void rtl92ce_suspend(struct ieee80211_hw *hw)
2302 {
2303 }
2304
2305 void rtl92ce_resume(struct ieee80211_hw *hw)
2306 {
2307 }
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