?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Input: wacom - fix touch parsing on newer Bamboos
[linux-btrfs-devel.git] / drivers / staging / gma500 / psb_drv.c
blobaa87b1b6a44adea18ca675ba7962dcf512dd61f8
1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "psb_fb.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_bios.h"
30 #include <drm/drm_pciids.h>
31 #include "psb_powermgmt.h"
32 #include <linux/cpu.h>
33 #include <linux/notifier.h>
34 #include <linux/spinlock.h>
35 #include <linux/pm_runtime.h>
36 #include <acpi/video.h>
37
38 int drm_psb_debug;
39 static int drm_psb_trap_pagefaults;
40
41 int drm_psb_no_fb;
42
43 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
44
45 MODULE_PARM_DESC(debug, "Enable debug output");
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(debug, drm_psb_debug, int, 0600);
49 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
50 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
51
52
53 static struct pci_device_id pciidlist[] = {
54 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
55 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
64 { 0, 0, 0}
65 };
66 MODULE_DEVICE_TABLE(pci, pciidlist);
67
68 /*
69 * Standard IOCTLs.
70 */
71
72 #define DRM_IOCTL_PSB_KMS_OFF \
73 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
74 #define DRM_IOCTL_PSB_KMS_ON \
75 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
76 #define DRM_IOCTL_PSB_SIZES \
77 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
78 struct drm_psb_sizes_arg)
79 #define DRM_IOCTL_PSB_FUSE_REG \
80 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
81 #define DRM_IOCTL_PSB_DC_STATE \
82 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
83 struct drm_psb_dc_state_arg)
84 #define DRM_IOCTL_PSB_ADB \
85 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
86 #define DRM_IOCTL_PSB_MODE_OPERATION \
87 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
88 struct drm_psb_mode_operation_arg)
89 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
90 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
91 struct drm_psb_stolen_memory_arg)
92 #define DRM_IOCTL_PSB_REGISTER_RW \
93 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
94 struct drm_psb_register_rw_arg)
95 #define DRM_IOCTL_PSB_DPST \
96 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
97 uint32_t)
98 #define DRM_IOCTL_PSB_GAMMA \
99 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
100 struct drm_psb_dpst_lut_arg)
101 #define DRM_IOCTL_PSB_DPST_BL \
102 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
103 uint32_t)
104 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
105 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
106 struct drm_psb_get_pipe_from_crtc_id_arg)
107
108 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
109 struct drm_file *file_priv);
110 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
111 struct drm_file *file_priv);
112 static int psb_adb_ioctl(struct drm_device *dev, void *data,
113 struct drm_file *file_priv);
114 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv);
116 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv);
118 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
119 struct drm_file *file_priv);
120 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
121 struct drm_file *file_priv);
122 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
123 struct drm_file *file_priv);
124 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
125 struct drm_file *file_priv);
126
127 #define PSB_IOCTL_DEF(ioctl, func, flags) \
128 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
129
130 static struct drm_ioctl_desc psb_ioctls[] = {
131 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
132 DRM_ROOT_ONLY),
133 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
134 psbfb_kms_on_ioctl,
135 DRM_ROOT_ONLY),
136 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
137 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
138 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
139 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
140 DRM_AUTH),
141 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
142 DRM_AUTH),
143 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
144 DRM_AUTH),
145 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
146 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
147 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
148 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
149 psb_intel_get_pipe_from_crtc_id, 0),
150
151 };
152
153 static void psb_lastclose(struct drm_device *dev)
154 {
155 return;
156 }
157
158 static void psb_do_takedown(struct drm_device *dev)
159 {
160 /* FIXME: do we need to clean up the gtt here ? */
161 }
162
163 void mrst_get_fuse_settings(struct drm_device *dev)
164 {
165 struct drm_psb_private *dev_priv = dev->dev_private;
166 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
167 uint32_t fuse_value = 0;
168 uint32_t fuse_value_tmp = 0;
169
170 #define FB_REG06 0xD0810600
171 #define FB_MIPI_DISABLE (1 << 11)
172 #define FB_REG09 0xD0810900
173 #define FB_REG09 0xD0810900
174 #define FB_SKU_MASK 0x7000
175 #define FB_SKU_SHIFT 12
176 #define FB_SKU_100 0
177 #define FB_SKU_100L 1
178 #define FB_SKU_83 2
179 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
180 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
181
182 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
183
184 DRM_INFO("internal display is %s\n",
185 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
186
187 /*prevent Runtime suspend at start*/
188 if (dev_priv->iLVDS_enable) {
189 dev_priv->is_lvds_on = true;
190 dev_priv->is_mipi_on = false;
191 }
192 else {
193 dev_priv->is_mipi_on = true;
194 dev_priv->is_lvds_on = false;
195 }
196
197 dev_priv->video_device_fuse = fuse_value;
198
199 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
200 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
201
202 DRM_INFO("SKU values is 0x%x. \n", fuse_value);
203 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
204
205 dev_priv->fuse_reg_value = fuse_value;
206
207 switch (fuse_value_tmp) {
208 case FB_SKU_100:
209 dev_priv->core_freq = 200;
210 break;
211 case FB_SKU_100L:
212 dev_priv->core_freq = 100;
213 break;
214 case FB_SKU_83:
215 dev_priv->core_freq = 166;
216 break;
217 default:
218 DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
219 dev_priv->core_freq = 0;
220 }
221 DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
222 pci_dev_put(pci_root);
223 }
224
225 void mid_get_pci_revID (struct drm_psb_private *dev_priv)
226 {
227 uint32_t platform_rev_id = 0;
228 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
229
230 /*get the revison ID, B0:D2:F0;0x08 */
231 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
232 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
233 pci_dev_put(pci_gfx_root);
234 PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id);
235 }
236
237 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
238 {
239 struct mrst_vbt *vbt = &dev_priv->vbt_data;
240 u32 platform_config_address;
241 u16 new_size;
242 u8 *vbt_virtual;
243 u8 bpi;
244 u8 number_desc = 0;
245 struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
246 struct gct_r10_timing_info ti;
247 void *pGCT;
248 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
249
250 /*get the address of the platform config vbt, B0:D2:F0;0xFC */
251 pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
252 pci_dev_put(pci_gfx_root);
253 DRM_INFO("drm platform config address is %x\n",
254 platform_config_address);
255
256 /* check for platform config address == 0. */
257 /* this means fw doesn't support vbt */
258
259 if (platform_config_address == 0) {
260 vbt->size = 0;
261 return;
262 }
263
264 /* get the virtual address of the vbt */
265 vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
266
267 memcpy(vbt, vbt_virtual, sizeof(*vbt));
268 iounmap(vbt_virtual); /* Free virtual address space */
269
270 printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
271
272 switch (vbt->revision) {
273 case 0:
274 vbt->mrst_gct = NULL;
275 vbt->mrst_gct = \
276 ioremap(platform_config_address + sizeof(*vbt) - 4,
277 vbt->size - sizeof(*vbt) + 4);
278 pGCT = vbt->mrst_gct;
279 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
280 dev_priv->gct_data.bpi = bpi;
281 dev_priv->gct_data.pt =
282 ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
283 memcpy(&dev_priv->gct_data.DTD,
284 &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
285 sizeof(struct mrst_timing_info));
286 dev_priv->gct_data.Panel_Port_Control =
287 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
288 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
289 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
290 break;
291 case 1:
292 vbt->mrst_gct = NULL;
293 vbt->mrst_gct = \
294 ioremap(platform_config_address + sizeof(*vbt) - 4,
295 vbt->size - sizeof(*vbt) + 4);
296 pGCT = vbt->mrst_gct;
297 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
298 dev_priv->gct_data.bpi = bpi;
299 dev_priv->gct_data.pt =
300 ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
301 memcpy(&dev_priv->gct_data.DTD,
302 &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
303 sizeof(struct mrst_timing_info));
304 dev_priv->gct_data.Panel_Port_Control =
305 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
306 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
307 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
308 break;
309 case 0x10:
310 /*header definition changed from rev 01 (v2) to rev 10h. */
311 /*so, some values have changed location*/
312 new_size = vbt->checksum; /*checksum contains lo size byte*/
313 /*LSB of mrst_gct contains hi size byte*/
314 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
315
316 vbt->checksum = vbt->size; /*size contains the checksum*/
317 if (new_size > 0xff)
318 vbt->size = 0xff; /*restrict size to 255*/
319 else
320 vbt->size = new_size;
321
322 /* number of descriptors defined in the GCT */
323 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
324 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
325 vbt->mrst_gct = NULL;
326 vbt->mrst_gct = \
327 ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
328 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
329 pGCT = vbt->mrst_gct;
330 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
331 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
332
333 /*copy the GCT display timings into a temp structure*/
334 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
335
336 /*now copy the temp struct into the dev_priv->gct_data*/
337 dp_ti->pixel_clock = ti.pixel_clock;
338 dp_ti->hactive_hi = ti.hactive_hi;
339 dp_ti->hactive_lo = ti.hactive_lo;
340 dp_ti->hblank_hi = ti.hblank_hi;
341 dp_ti->hblank_lo = ti.hblank_lo;
342 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
343 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
344 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
345 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
346 dp_ti->vactive_hi = ti.vactive_hi;
347 dp_ti->vactive_lo = ti.vactive_lo;
348 dp_ti->vblank_hi = ti.vblank_hi;
349 dp_ti->vblank_lo = ti.vblank_lo;
350 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
351 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
352 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
353 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
354
355 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
356 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
357 *((u8 *)pGCT + 0x0d);
358 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
359 (*((u8 *)pGCT + 0x0e)) << 8;
360 break;
361 default:
362 printk(KERN_ERR "Unknown revision of GCT!\n");
363 vbt->size = 0;
364 }
365 }
366
367 static void psb_get_core_freq(struct drm_device *dev)
368 {
369 uint32_t clock;
370 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
371 struct drm_psb_private *dev_priv = dev->dev_private;
372
373 /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
374 /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
375
376 pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
377 pci_read_config_dword(pci_root, 0xD4, &clock);
378 pci_dev_put(pci_root);
379
380 switch (clock & 0x07) {
381 case 0:
382 dev_priv->core_freq = 100;
383 break;
384 case 1:
385 dev_priv->core_freq = 133;
386 break;
387 case 2:
388 dev_priv->core_freq = 150;
389 break;
390 case 3:
391 dev_priv->core_freq = 178;
392 break;
393 case 4:
394 dev_priv->core_freq = 200;
395 break;
396 case 5:
397 case 6:
398 case 7:
399 dev_priv->core_freq = 266;
400 default:
401 dev_priv->core_freq = 0;
402 }
403 }
404
405 static int psb_do_init(struct drm_device *dev)
406 {
407 struct drm_psb_private *dev_priv =
408 (struct drm_psb_private *) dev->dev_private;
409 struct psb_gtt *pg = dev_priv->pg;
410
411 uint32_t stolen_gtt;
412 uint32_t tt_start;
413 uint32_t tt_pages;
414
415 int ret = -ENOMEM;
416
417 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
418 DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
419 ret = -EINVAL;
420 goto out_err;
421 }
422
423
424 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
425 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
426 stolen_gtt =
427 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
428
429 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
430 (stolen_gtt << PAGE_SHIFT) * 1024;
431
432 if (1 || drm_debug) {
433 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
434 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
435 DRM_INFO("SGX core id = 0x%08x\n", core_id);
436 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
437 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
438 _PSB_CC_REVISION_MAJOR_SHIFT,
439 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
440 _PSB_CC_REVISION_MINOR_SHIFT);
441 DRM_INFO
442 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
443 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
444 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
445 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
446 _PSB_CC_REVISION_DESIGNER_SHIFT);
447 }
448
449
450 spin_lock_init(&dev_priv->irqmask_lock);
451
452 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
453 pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
454 tt_start = dev_priv->gatt_free_offset - pg->mmu_gatt_start;
455 tt_pages -= tt_start >> PAGE_SHIFT;
456 /* FIXME: can we kill ta_mem_size ? */
457 dev_priv->sizes.ta_mem_size = 0;
458
459 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
460 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
461 PSB_RSGX32(PSB_CR_BIF_BANK1);
462 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
463 PSB_CR_BIF_CTRL);
464 psb_spank(dev_priv);
465
466 /* mmu_gatt ?? */
467 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
468
469 return 0;
470 out_err:
471 psb_do_takedown(dev);
472 return ret;
473 }
474
475 static int psb_driver_unload(struct drm_device *dev)
476 {
477 struct drm_psb_private *dev_priv =
478 (struct drm_psb_private *) dev->dev_private;
479
480 /* Kill vblank etc here */
481
482 psb_backlight_exit(); /*writes minimum value to backlight HW reg */
483
484 if (drm_psb_no_fb == 0)
485 psb_modeset_cleanup(dev);
486
487 if (dev_priv) {
488 psb_lid_timer_takedown(dev_priv);
489
490 psb_do_takedown(dev);
491
492
493 if (dev_priv->pf_pd) {
494 psb_mmu_free_pagedir(dev_priv->pf_pd);
495 dev_priv->pf_pd = NULL;
496 }
497 if (dev_priv->mmu) {
498 struct psb_gtt *pg = dev_priv->pg;
499
500 down_read(&pg->sem);
501 psb_mmu_remove_pfn_sequence(
502 psb_mmu_get_default_pd
503 (dev_priv->mmu),
504 pg->mmu_gatt_start,
505 dev_priv->vram_stolen_size >> PAGE_SHIFT);
506 up_read(&pg->sem);
507 psb_mmu_driver_takedown(dev_priv->mmu);
508 dev_priv->mmu = NULL;
509 }
510 psb_gtt_takedown(dev);
511 if (dev_priv->scratch_page) {
512 __free_page(dev_priv->scratch_page);
513 dev_priv->scratch_page = NULL;
514 }
515 if (dev_priv->vdc_reg) {
516 iounmap(dev_priv->vdc_reg);
517 dev_priv->vdc_reg = NULL;
518 }
519 if (dev_priv->sgx_reg) {
520 iounmap(dev_priv->sgx_reg);
521 dev_priv->sgx_reg = NULL;
522 }
523
524 kfree(dev_priv);
525 dev->dev_private = NULL;
526
527 /*destroy VBT data*/
528 psb_intel_destroy_bios(dev);
529 }
530
531 gma_power_uninit(dev);
532
533 return 0;
534 }
535
536
537 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
538 {
539 struct drm_psb_private *dev_priv;
540 unsigned long resource_start;
541 struct psb_gtt *pg;
542 unsigned long irqflags;
543 int ret = -ENOMEM;
544 uint32_t tt_pages;
545 struct drm_connector *connector;
546 struct psb_intel_output *psb_intel_output;
547
548 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
549 if (dev_priv == NULL)
550 return -ENOMEM;
551
552 if (IS_MRST(dev))
553 dev_priv->num_pipe = 1;
554 else
555 dev_priv->num_pipe = 2;
556
557 dev_priv->dev = dev;
558
559 dev->dev_private = (void *) dev_priv;
560 dev_priv->chipset = chipset;
561
562 PSB_DEBUG_INIT("Mapping MMIO\n");
563 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
564
565 dev_priv->vdc_reg =
566 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
567 if (!dev_priv->vdc_reg)
568 goto out_err;
569
570 if (IS_MRST(dev))
571 dev_priv->sgx_reg = ioremap(resource_start + MRST_SGX_OFFSET,
572 PSB_SGX_SIZE);
573 else
574 dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
575 PSB_SGX_SIZE);
576
577 if (!dev_priv->sgx_reg)
578 goto out_err;
579
580 if (IS_MRST(dev)) {
581 mrst_get_fuse_settings(dev);
582 mrst_get_vbt_data(dev_priv);
583 mid_get_pci_revID(dev_priv);
584 } else {
585 psb_get_core_freq(dev);
586 psb_intel_opregion_init(dev);
587 psb_intel_init_bios(dev);
588 }
589
590 /* Init OSPM support */
591 gma_power_init(dev);
592
593 ret = -ENOMEM;
594
595 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
596 if (!dev_priv->scratch_page)
597 goto out_err;
598
599 set_pages_uc(dev_priv->scratch_page, 1);
600
601 ret = psb_gtt_init(dev, 0);
602 if (ret)
603 goto out_err;
604
605 dev_priv->mmu = psb_mmu_driver_init((void *)0,
606 drm_psb_trap_pagefaults, 0,
607 dev_priv);
608 if (!dev_priv->mmu)
609 goto out_err;
610
611 pg = dev_priv->pg;
612
613 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
614 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
615
616
617 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
618 if (!dev_priv->pf_pd)
619 goto out_err;
620
621 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
622 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
623
624 ret = psb_do_init(dev);
625 if (ret)
626 return ret;
627
628 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
629 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
630
631 /* igd_opregion_init(&dev_priv->opregion_dev); */
632 acpi_video_register();
633 if (dev_priv->lid_state)
634 psb_lid_timer_init(dev_priv);
635
636 ret = drm_vblank_init(dev, dev_priv->num_pipe);
637 if (ret)
638 goto out_err;
639
640 /*
641 * Install interrupt handlers prior to powering off SGX or else we will
642 * crash.
643 */
644 dev_priv->vdc_irq_mask = 0;
645 dev_priv->pipestat[0] = 0;
646 dev_priv->pipestat[1] = 0;
647 dev_priv->pipestat[2] = 0;
648 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
649 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
650 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
651 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
652 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
653 if (drm_core_check_feature(dev, DRIVER_MODESET))
654 drm_irq_install(dev);
655
656 dev->vblank_disable_allowed = 1;
657
658 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
659
660 dev->driver->get_vblank_counter = psb_get_vblank_counter;
661
662 if (drm_psb_no_fb == 0) {
663 psb_modeset_init(dev);
664 psb_fbdev_init(dev);
665 drm_kms_helper_poll_init(dev);
666 }
667
668 /* Only add backlight support if we have LVDS output */
669 list_for_each_entry(connector, &dev->mode_config.connector_list,
670 head) {
671 psb_intel_output = to_psb_intel_output(connector);
672
673 switch (psb_intel_output->type) {
674 case INTEL_OUTPUT_LVDS:
675 ret = psb_backlight_init(dev);
676 break;
677 }
678 }
679
680 if (ret)
681 return ret;
682 #if 0
683 /*enable runtime pm at last*/
684 pm_runtime_enable(&dev->pdev->dev);
685 pm_runtime_set_active(&dev->pdev->dev);
686 #endif
687 /*Intel drm driver load is done, continue doing pvr load*/
688 DRM_DEBUG("Pvr driver load\n");
689 return 0;
690 out_err:
691 psb_driver_unload(dev);
692 return ret;
693 }
694
695 int psb_driver_device_is_agp(struct drm_device *dev)
696 {
697 return 0;
698 }
699
700
701 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
702 struct drm_file *file_priv)
703 {
704 struct drm_psb_private *dev_priv = psb_priv(dev);
705 struct drm_psb_sizes_arg *arg =
706 (struct drm_psb_sizes_arg *) data;
707
708 *arg = dev_priv->sizes;
709 return 0;
710 }
711
712 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
713 struct drm_file *file_priv)
714 {
715 uint32_t flags;
716 uint32_t obj_id;
717 struct drm_mode_object *obj;
718 struct drm_connector *connector;
719 struct drm_crtc *crtc;
720 struct drm_psb_dc_state_arg *arg =
721 (struct drm_psb_dc_state_arg *)data;
722
723 flags = arg->flags;
724 obj_id = arg->obj_id;
725
726 if (flags & PSB_DC_CRTC_MASK) {
727 obj = drm_mode_object_find(dev, obj_id,
728 DRM_MODE_OBJECT_CRTC);
729 if (!obj) {
730 DRM_DEBUG("Invalid CRTC object.\n");
731 return -EINVAL;
732 }
733
734 crtc = obj_to_crtc(obj);
735
736 mutex_lock(&dev->mode_config.mutex);
737 if (drm_helper_crtc_in_use(crtc)) {
738 if (flags & PSB_DC_CRTC_SAVE)
739 crtc->funcs->save(crtc);
740 else
741 crtc->funcs->restore(crtc);
742 }
743 mutex_unlock(&dev->mode_config.mutex);
744
745 return 0;
746 } else if (flags & PSB_DC_OUTPUT_MASK) {
747 obj = drm_mode_object_find(dev, obj_id,
748 DRM_MODE_OBJECT_CONNECTOR);
749 if (!obj) {
750 DRM_DEBUG("Invalid connector id.\n");
751 return -EINVAL;
752 }
753
754 connector = obj_to_connector(obj);
755 if (flags & PSB_DC_OUTPUT_SAVE)
756 connector->funcs->save(connector);
757 else
758 connector->funcs->restore(connector);
759
760 return 0;
761 }
762
763 DRM_DEBUG("Bad flags 0x%x\n", flags);
764 return -EINVAL;
765 }
766
767 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
768 struct drm_file *file_priv)
769 {
770 struct drm_psb_private *dev_priv = psb_priv(dev);
771 uint32_t *arg = data;
772 struct backlight_device bd;
773 dev_priv->blc_adj2 = *arg;
774
775 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
776 bd.props.brightness = psb_get_brightness(&bd);
777 psb_set_brightness(&bd);
778 #endif
779 return 0;
780 }
781
782 static int psb_adb_ioctl(struct drm_device *dev, void *data,
783 struct drm_file *file_priv)
784 {
785 struct drm_psb_private *dev_priv = psb_priv(dev);
786 uint32_t *arg = data;
787 struct backlight_device bd;
788 dev_priv->blc_adj1 = *arg;
789
790 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
791 bd.props.brightness = psb_get_brightness(&bd);
792 psb_set_brightness(&bd);
793 #endif
794 return 0;
795 }
796
797 /* return the current mode to the dpst module */
798 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
799 struct drm_file *file_priv)
800 {
801 struct drm_psb_private *dev_priv = psb_priv(dev);
802 uint32_t *arg = data;
803 uint32_t x;
804 uint32_t y;
805 uint32_t reg;
806
807 if (!gma_power_begin(dev, 0))
808 return -EIO;
809
810 reg = PSB_RVDC32(PIPEASRC);
811
812 gma_power_end(dev);
813
814 /* horizontal is the left 16 bits */
815 x = reg >> 16;
816 /* vertical is the right 16 bits */
817 y = reg & 0x0000ffff;
818
819 /* the values are the image size minus one */
820 x++;
821 y++;
822
823 *arg = (x << 16) | y;
824
825 return 0;
826 }
827 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
828 struct drm_file *file_priv)
829 {
830 struct drm_psb_dpst_lut_arg *lut_arg = data;
831 struct drm_mode_object *obj;
832 struct drm_crtc *crtc;
833 struct drm_connector *connector;
834 struct psb_intel_crtc *psb_intel_crtc;
835 int i = 0;
836 int32_t obj_id;
837
838 obj_id = lut_arg->output_id;
839 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
840 if (!obj) {
841 DRM_DEBUG("Invalid Connector object.\n");
842 return -EINVAL;
843 }
844
845 connector = obj_to_connector(obj);
846 crtc = connector->encoder->crtc;
847 psb_intel_crtc = to_psb_intel_crtc(crtc);
848
849 for (i = 0; i < 256; i++)
850 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
851
852 psb_intel_crtc_load_lut(crtc);
853
854 return 0;
855 }
856
857 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
858 struct drm_file *file_priv)
859 {
860 uint32_t obj_id;
861 uint16_t op;
862 struct drm_mode_modeinfo *umode;
863 struct drm_display_mode *mode = NULL;
864 struct drm_psb_mode_operation_arg *arg;
865 struct drm_mode_object *obj;
866 struct drm_connector *connector;
867 struct drm_framebuffer *drm_fb;
868 struct psb_framebuffer *psb_fb;
869 struct drm_connector_helper_funcs *connector_funcs;
870 int ret = 0;
871 int resp = MODE_OK;
872 struct drm_psb_private *dev_priv = psb_priv(dev);
873
874 arg = (struct drm_psb_mode_operation_arg *)data;
875 obj_id = arg->obj_id;
876 op = arg->operation;
877
878 switch (op) {
879 case PSB_MODE_OPERATION_SET_DC_BASE:
880 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
881 if (!obj) {
882 DRM_ERROR("Invalid FB id %d\n", obj_id);
883 return -EINVAL;
884 }
885
886 drm_fb = obj_to_fb(obj);
887 psb_fb = to_psb_fb(drm_fb);
888
889 if (gma_power_begin(dev, 0)) {
890 REG_WRITE(DSPASURF, psb_fb->gtt->offset);
891 REG_READ(DSPASURF);
892 gma_power_end(dev);
893 } else {
894 dev_priv->saveDSPASURF = psb_fb->gtt->offset;
895 }
896
897 return 0;
898 case PSB_MODE_OPERATION_MODE_VALID:
899 umode = &arg->mode;
900
901 mutex_lock(&dev->mode_config.mutex);
902
903 obj = drm_mode_object_find(dev, obj_id,
904 DRM_MODE_OBJECT_CONNECTOR);
905 if (!obj) {
906 ret = -EINVAL;
907 goto mode_op_out;
908 }
909
910 connector = obj_to_connector(obj);
911
912 mode = drm_mode_create(dev);
913 if (!mode) {
914 ret = -ENOMEM;
915 goto mode_op_out;
916 }
917
918 /* drm_crtc_convert_umode(mode, umode); */
919 {
920 mode->clock = umode->clock;
921 mode->hdisplay = umode->hdisplay;
922 mode->hsync_start = umode->hsync_start;
923 mode->hsync_end = umode->hsync_end;
924 mode->htotal = umode->htotal;
925 mode->hskew = umode->hskew;
926 mode->vdisplay = umode->vdisplay;
927 mode->vsync_start = umode->vsync_start;
928 mode->vsync_end = umode->vsync_end;
929 mode->vtotal = umode->vtotal;
930 mode->vscan = umode->vscan;
931 mode->vrefresh = umode->vrefresh;
932 mode->flags = umode->flags;
933 mode->type = umode->type;
934 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
935 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
936 }
937
938 connector_funcs = (struct drm_connector_helper_funcs *)
939 connector->helper_private;
940
941 if (connector_funcs->mode_valid) {
942 resp = connector_funcs->mode_valid(connector, mode);
943 arg->data = (void *)resp;
944 }
945
946 /*do some clean up work*/
947 if (mode)
948 drm_mode_destroy(dev, mode);
949 mode_op_out:
950 mutex_unlock(&dev->mode_config.mutex);
951 return ret;
952
953 default:
954 DRM_DEBUG("Unsupported psb mode operation");
955 return -EOPNOTSUPP;
956 }
957
958 return 0;
959 }
960
961 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
963 {
964 struct drm_psb_private *dev_priv = psb_priv(dev);
965 struct drm_psb_stolen_memory_arg *arg = data;
966
967 arg->base = dev_priv->stolen_base;
968 arg->size = dev_priv->vram_stolen_size;
969
970 return 0;
971 }
972
973 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
974 struct drm_file *file_priv)
975 {
976 struct drm_psb_private *dev_priv = psb_priv(dev);
977 struct drm_psb_register_rw_arg *arg = data;
978 bool usage = arg->b_force_hw_on ? true : false;
979
980 if (arg->display_write_mask != 0) {
981 if (gma_power_begin(dev, usage)) {
982 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
983 PSB_WVDC32(arg->display.pfit_controls,
984 PFIT_CONTROL);
985 if (arg->display_write_mask &
986 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
987 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
988 PFIT_AUTO_RATIOS);
989 if (arg->display_write_mask &
990 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
991 PSB_WVDC32(
992 arg->display.pfit_programmed_scale_ratios,
993 PFIT_PGM_RATIOS);
994 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
995 PSB_WVDC32(arg->display.pipeasrc,
996 PIPEASRC);
997 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
998 PSB_WVDC32(arg->display.pipebsrc,
999 PIPEBSRC);
1000 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1001 PSB_WVDC32(arg->display.vtotal_a,
1002 VTOTAL_A);
1003 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1004 PSB_WVDC32(arg->display.vtotal_b,
1005 VTOTAL_B);
1006 gma_power_end(dev);
1007 } else {
1008 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1009 dev_priv->savePFIT_CONTROL =
1010 arg->display.pfit_controls;
1011 if (arg->display_write_mask &
1012 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1013 dev_priv->savePFIT_AUTO_RATIOS =
1014 arg->display.pfit_autoscale_ratios;
1015 if (arg->display_write_mask &
1016 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1017 dev_priv->savePFIT_PGM_RATIOS =
1018 arg->display.pfit_programmed_scale_ratios;
1019 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1020 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1021 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1022 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1023 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1024 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1025 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1026 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1027 }
1028 }
1029
1030 if (arg->display_read_mask != 0) {
1031 if (gma_power_begin(dev, usage)) {
1032 if (arg->display_read_mask &
1033 REGRWBITS_PFIT_CONTROLS)
1034 arg->display.pfit_controls =
1035 PSB_RVDC32(PFIT_CONTROL);
1036 if (arg->display_read_mask &
1037 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1038 arg->display.pfit_autoscale_ratios =
1039 PSB_RVDC32(PFIT_AUTO_RATIOS);
1040 if (arg->display_read_mask &
1041 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1042 arg->display.pfit_programmed_scale_ratios =
1043 PSB_RVDC32(PFIT_PGM_RATIOS);
1044 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1045 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1046 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1047 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1048 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1049 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1050 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1051 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1052 gma_power_end(dev);
1053 } else {
1054 if (arg->display_read_mask &
1055 REGRWBITS_PFIT_CONTROLS)
1056 arg->display.pfit_controls =
1057 dev_priv->savePFIT_CONTROL;
1058 if (arg->display_read_mask &
1059 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1060 arg->display.pfit_autoscale_ratios =
1061 dev_priv->savePFIT_AUTO_RATIOS;
1062 if (arg->display_read_mask &
1063 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1064 arg->display.pfit_programmed_scale_ratios =
1065 dev_priv->savePFIT_PGM_RATIOS;
1066 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1067 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1068 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1069 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1070 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1071 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1072 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1073 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1074 }
1075 }
1076
1077 if (arg->overlay_write_mask != 0) {
1078 if (gma_power_begin(dev, usage)) {
1079 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1080 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1081 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1082 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1083 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1084 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1085 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1086 }
1087 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1088 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1089 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1090 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1091 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1092 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1093 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1094 }
1095
1096 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1097 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1098
1099 if (arg->overlay.b_wait_vblank) {
1100 /* Wait for 20ms.*/
1101 unsigned long vblank_timeout = jiffies
1102 + HZ/50;
1103 uint32_t temp;
1104 while (time_before_eq(jiffies,
1105 vblank_timeout)) {
1106 temp = PSB_RVDC32(OV_DOVASTA);
1107 if ((temp & (0x1 << 31)) != 0)
1108 break;
1109 cpu_relax();
1110 }
1111 }
1112 }
1113 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1114 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1115 if (arg->overlay.b_wait_vblank) {
1116 /* Wait for 20ms.*/
1117 unsigned long vblank_timeout =
1118 jiffies + HZ/50;
1119 uint32_t temp;
1120 while (time_before_eq(jiffies,
1121 vblank_timeout)) {
1122 temp = PSB_RVDC32(OVC_DOVCSTA);
1123 if ((temp & (0x1 << 31)) != 0)
1124 break;
1125 cpu_relax();
1126 }
1127 }
1128 }
1129 gma_power_end(dev);
1130 } else {
1131 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1132 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1133 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1134 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1135 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1136 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1137 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1138 }
1139 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1140 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1141 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1142 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1143 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1144 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1145 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1146 }
1147 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1148 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1149 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1150 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1151 }
1152 }
1153
1154 if (arg->overlay_read_mask != 0) {
1155 if (gma_power_begin(dev, usage)) {
1156 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1157 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1158 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1159 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1160 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1161 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1162 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1163 }
1164 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1165 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1166 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1167 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1168 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1169 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1170 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1171 }
1172 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1173 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1174 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1175 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1176 gma_power_end(dev);
1177 } else {
1178 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1179 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1180 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1181 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1182 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1183 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1184 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1185 }
1186 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1187 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1188 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1189 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1190 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1191 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1192 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1193 }
1194 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1195 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1196 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1197 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1198 }
1199 }
1200
1201 if (arg->sprite_enable_mask != 0) {
1202 if (gma_power_begin(dev, usage)) {
1203 PSB_WVDC32(0x1F3E, DSPARB);
1204 PSB_WVDC32(arg->sprite.dspa_control
1205 | PSB_RVDC32(DSPACNTR), DSPACNTR);
1206 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1207 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1208 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1209 PSB_RVDC32(DSPASURF);
1210 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1211 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1212 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1213 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1214 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1215 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1216 PSB_RVDC32(DSPCSURF);
1217 gma_power_end(dev);
1218 }
1219 }
1220
1221 if (arg->sprite_disable_mask != 0) {
1222 if (gma_power_begin(dev, usage)) {
1223 PSB_WVDC32(0x3F3E, DSPARB);
1224 PSB_WVDC32(0x0, DSPCCNTR);
1225 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1226 PSB_RVDC32(DSPCSURF);
1227 gma_power_end(dev);
1228 }
1229 }
1230
1231 if (arg->subpicture_enable_mask != 0) {
1232 if (gma_power_begin(dev, usage)) {
1233 uint32_t temp;
1234 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1235 temp = PSB_RVDC32(DSPACNTR);
1236 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1237 temp &= ~DISPPLANE_BOTTOM;
1238 temp |= DISPPLANE_32BPP;
1239 PSB_WVDC32(temp, DSPACNTR);
1240
1241 temp = PSB_RVDC32(DSPABASE);
1242 PSB_WVDC32(temp, DSPABASE);
1243 PSB_RVDC32(DSPABASE);
1244 temp = PSB_RVDC32(DSPASURF);
1245 PSB_WVDC32(temp, DSPASURF);
1246 PSB_RVDC32(DSPASURF);
1247 }
1248 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1249 temp = PSB_RVDC32(DSPBCNTR);
1250 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1251 temp &= ~DISPPLANE_BOTTOM;
1252 temp |= DISPPLANE_32BPP;
1253 PSB_WVDC32(temp, DSPBCNTR);
1254
1255 temp = PSB_RVDC32(DSPBBASE);
1256 PSB_WVDC32(temp, DSPBBASE);
1257 PSB_RVDC32(DSPBBASE);
1258 temp = PSB_RVDC32(DSPBSURF);
1259 PSB_WVDC32(temp, DSPBSURF);
1260 PSB_RVDC32(DSPBSURF);
1261 }
1262 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1263 temp = PSB_RVDC32(DSPCCNTR);
1264 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1265 temp &= ~DISPPLANE_BOTTOM;
1266 temp |= DISPPLANE_32BPP;
1267 PSB_WVDC32(temp, DSPCCNTR);
1268
1269 temp = PSB_RVDC32(DSPCBASE);
1270 PSB_WVDC32(temp, DSPCBASE);
1271 PSB_RVDC32(DSPCBASE);
1272 temp = PSB_RVDC32(DSPCSURF);
1273 PSB_WVDC32(temp, DSPCSURF);
1274 PSB_RVDC32(DSPCSURF);
1275 }
1276 gma_power_end(dev);
1277 }
1278 }
1279
1280 if (arg->subpicture_disable_mask != 0) {
1281 if (gma_power_begin(dev, usage)) {
1282 uint32_t temp;
1283 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1284 temp = PSB_RVDC32(DSPACNTR);
1285 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1286 temp |= DISPPLANE_32BPP_NO_ALPHA;
1287 PSB_WVDC32(temp, DSPACNTR);
1288
1289 temp = PSB_RVDC32(DSPABASE);
1290 PSB_WVDC32(temp, DSPABASE);
1291 PSB_RVDC32(DSPABASE);
1292 temp = PSB_RVDC32(DSPASURF);
1293 PSB_WVDC32(temp, DSPASURF);
1294 PSB_RVDC32(DSPASURF);
1295 }
1296 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1297 temp = PSB_RVDC32(DSPBCNTR);
1298 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1299 temp |= DISPPLANE_32BPP_NO_ALPHA;
1300 PSB_WVDC32(temp, DSPBCNTR);
1301
1302 temp = PSB_RVDC32(DSPBBASE);
1303 PSB_WVDC32(temp, DSPBBASE);
1304 PSB_RVDC32(DSPBBASE);
1305 temp = PSB_RVDC32(DSPBSURF);
1306 PSB_WVDC32(temp, DSPBSURF);
1307 PSB_RVDC32(DSPBSURF);
1308 }
1309 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1310 temp = PSB_RVDC32(DSPCCNTR);
1311 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1312 temp |= DISPPLANE_32BPP_NO_ALPHA;
1313 PSB_WVDC32(temp, DSPCCNTR);
1314
1315 temp = PSB_RVDC32(DSPCBASE);
1316 PSB_WVDC32(temp, DSPCBASE);
1317 PSB_RVDC32(DSPCBASE);
1318 temp = PSB_RVDC32(DSPCSURF);
1319 PSB_WVDC32(temp, DSPCSURF);
1320 PSB_RVDC32(DSPCSURF);
1321 }
1322 gma_power_end(dev);
1323 }
1324 }
1325
1326 return 0;
1327 }
1328
1329 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1330 {
1331 return 0;
1332 }
1333
1334 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1335 {
1336 }
1337
1338 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1339 unsigned long arg)
1340 {
1341 struct drm_file *file_priv = filp->private_data;
1342 struct drm_device *dev = file_priv->minor->dev;
1343 struct drm_psb_private *dev_priv = dev->dev_private;
1344 static unsigned int runtime_allowed;
1345 unsigned int nr = DRM_IOCTL_NR(cmd);
1346
1347 DRM_DEBUG("cmd = %x, nr = %x\n", cmd, nr);
1348
1349 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1350 runtime_allowed++;
1351 pm_runtime_allow(&dev->pdev->dev);
1352 dev_priv->rpm_enabled = 1;
1353 }
1354 return drm_ioctl(filp, cmd, arg);
1355
1356 /* FIXME: do we need to wrap the other side of this */
1357 }
1358
1359
1360 /* When a client dies:
1361 * - Check for and clean up flipped page state
1362 */
1363 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1364 {
1365 }
1366
1367 static void psb_remove(struct pci_dev *pdev)
1368 {
1369 struct drm_device *dev = pci_get_drvdata(pdev);
1370 drm_put_dev(dev);
1371 }
1372
1373 static const struct dev_pm_ops psb_pm_ops = {
1374 .runtime_suspend = psb_runtime_suspend,
1375 .runtime_resume = psb_runtime_resume,
1376 .runtime_idle = psb_runtime_idle,
1377 };
1378
1379 static struct vm_operations_struct psb_gem_vm_ops = {
1380 .fault = psb_gem_fault,
1381 .open = drm_gem_vm_open,
1382 .close = drm_gem_vm_close,
1383 };
1384
1385 static struct drm_driver driver = {
1386 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1387 DRIVER_IRQ_VBL | DRIVER_MODESET| DRIVER_GEM ,
1388 .load = psb_driver_load,
1389 .unload = psb_driver_unload,
1390
1391 .ioctls = psb_ioctls,
1392 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1393 .device_is_agp = psb_driver_device_is_agp,
1394 .irq_preinstall = psb_irq_preinstall,
1395 .irq_postinstall = psb_irq_postinstall,
1396 .irq_uninstall = psb_irq_uninstall,
1397 .irq_handler = psb_irq_handler,
1398 .enable_vblank = psb_enable_vblank,
1399 .disable_vblank = psb_disable_vblank,
1400 .get_vblank_counter = psb_get_vblank_counter,
1401 .lastclose = psb_lastclose,
1402 .open = psb_driver_open,
1403 .preclose = psb_driver_preclose,
1404 .postclose = psb_driver_close,
1405 .reclaim_buffers = drm_core_reclaim_buffers,
1406
1407 .gem_init_object = psb_gem_init_object,
1408 .gem_free_object = psb_gem_free_object,
1409 .gem_vm_ops = &psb_gem_vm_ops,
1410 .dumb_create = psb_gem_dumb_create,
1411 .dumb_map_offset = psb_gem_dumb_map_gtt,
1412 .dumb_destroy = psb_gem_dumb_destroy,
1413
1414 .fops = {
1415 .owner = THIS_MODULE,
1416 .open = drm_open,
1417 .release = drm_release,
1418 .unlocked_ioctl = psb_unlocked_ioctl,
1419 .mmap = drm_gem_mmap,
1420 .poll = drm_poll,
1421 .fasync = drm_fasync,
1422 .read = drm_read,
1423 },
1424 .name = DRIVER_NAME,
1425 .desc = DRIVER_DESC,
1426 .date = PSB_DRM_DRIVER_DATE,
1427 .major = PSB_DRM_DRIVER_MAJOR,
1428 .minor = PSB_DRM_DRIVER_MINOR,
1429 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1430 };
1431
1432 static struct pci_driver psb_pci_driver = {
1433 .name = DRIVER_NAME,
1434 .id_table = pciidlist,
1435 .resume = gma_power_resume,
1436 .suspend = gma_power_suspend,
1437 .probe = psb_probe,
1438 .remove = psb_remove,
1439 #ifdef CONFIG_PM
1440 .driver.pm = &psb_pm_ops,
1441 #endif
1442 };
1443
1444 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1445 {
1446 /* MLD Added this from Inaky's patch */
1447 if (pci_enable_msi(pdev))
1448 DRM_ERROR("Enable MSI failed!\n");
1449 return drm_get_pci_dev(pdev, ent, &driver);
1450 }
1451
1452 static int __init psb_init(void)
1453 {
1454 return drm_pci_init(&driver, &psb_pci_driver);
1455 }
1456
1457 static void __exit psb_exit(void)
1458 {
1459 drm_pci_exit(&driver, &psb_pci_driver);
1460 }
1461
1462 late_initcall(psb_init);
1463 module_exit(psb_exit);
1464
1465 MODULE_AUTHOR(DRIVER_AUTHOR);
1466 MODULE_DESCRIPTION(DRIVER_DESC);
1467 MODULE_LICENSE("GPL");
Linux Btrfs Development