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Input: wacom - fix touch parsing on newer Bamboos
[linux-btrfs-devel.git] / drivers / staging / xgifb / vb_init.c
blob33c6876d2a805095c2e19d8b1bc13d2478776a3c
1 #include "vgatypes.h"
2
3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/delay.h> /* udelay */
6 #include "XGIfb.h"
7
8 #include "vb_def.h"
9 #include "vb_struct.h"
10 #include "vb_util.h"
11 #include "vb_setmode.h"
12 #include "vb_init.h"
13 #include "vb_ext.h"
14
15
16 #include <linux/io.h>
17
18 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
19
20 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
21 { 2, 13, 9, 64, 0x45},
22 { 2, 12, 9, 32, 0x35},
23 { 2, 12, 8, 16, 0x31},
24 { 2, 11, 8, 8, 0x21} };
25
26 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
27 { 2, 14, 11, 128, 0x5D},
28 { 2, 14, 10, 64, 0x59},
29 { 2, 13, 11, 64, 0x4D},
30 { 2, 14, 9, 32, 0x55},
31 { 2, 13, 10, 32, 0x49},
32 { 2, 12, 11, 32, 0x3D},
33 { 2, 14, 8, 16, 0x51},
34 { 2, 13, 9, 16, 0x45},
35 { 2, 12, 10, 16, 0x39},
36 { 2, 13, 8, 8, 0x41},
37 { 2, 12, 9, 8, 0x35},
38 { 2, 12, 8, 4, 0x31} };
39
40 static int XGINew_RAMType;
41
42 static unsigned char
43 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
44 struct vb_device_info *pVBInfo)
45 {
46 unsigned char data, temp;
47
48 if (HwDeviceExtension->jChipType < XG20) {
49 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
50 data = *pVBInfo->pSoftSetting & 0x07;
51 return data;
52 } else {
53 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
54 if (data == 0)
55 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
56 0x02) >> 1;
57 return data;
58 }
59 } else if (HwDeviceExtension->jChipType == XG27) {
60 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
61 data = *pVBInfo->pSoftSetting & 0x07;
62 return data;
63 }
64 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
65 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
66 if ((temp & 0x88) == 0x80)
67 data = 0; /* DDR */
68 else
69 data = 1; /* DDRII */
70 return data;
71 } else if (HwDeviceExtension->jChipType == XG21) {
72 /* Independent GPIO control */
73 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
74 udelay(800);
75 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
76 /* GPIOF 0:DVI 1:DVO */
77 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
78 /* HOTPLUG_SUPPORT */
79 /* for current XG20 & XG21, GPIOH is floating, driver will
80 * fix DDR temporarily */
81 if (temp & 0x01) /* DVI read GPIOH */
82 data = 1; /* DDRII */
83 else
84 data = 0; /* DDR */
85 /* ~HOTPLUG_SUPPORT */
86 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
87 return data;
88 } else {
89 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
90
91 if (data == 1)
92 data++;
93
94 return data;
95 }
96 }
97
98 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
99 struct vb_device_info *pVBInfo)
100 {
101 xgifb_reg_set(P3c4, 0x18, 0x01);
102 xgifb_reg_set(P3c4, 0x19, 0x20);
103 xgifb_reg_set(P3c4, 0x16, 0x00);
104 xgifb_reg_set(P3c4, 0x16, 0x80);
105
106 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
107 mdelay(3);
108 xgifb_reg_set(P3c4, 0x18, 0x00);
109 xgifb_reg_set(P3c4, 0x19, 0x20);
110 xgifb_reg_set(P3c4, 0x16, 0x00);
111 xgifb_reg_set(P3c4, 0x16, 0x80);
112 }
113
114 udelay(60);
115 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
116 xgifb_reg_set(P3c4, 0x19, 0x01);
117 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
118 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
119 mdelay(1);
120 xgifb_reg_set(P3c4, 0x1B, 0x03);
121 udelay(500);
122 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
123 xgifb_reg_set(P3c4, 0x19, 0x00);
124 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
125 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
126 xgifb_reg_set(P3c4, 0x1B, 0x00);
127 }
128
129 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
130 struct vb_device_info *pVBInfo)
131 {
132
133 xgifb_reg_set(pVBInfo->P3c4,
134 0x28,
135 pVBInfo->MCLKData[XGINew_RAMType].SR28);
136 xgifb_reg_set(pVBInfo->P3c4,
137 0x29,
138 pVBInfo->MCLKData[XGINew_RAMType].SR29);
139 xgifb_reg_set(pVBInfo->P3c4,
140 0x2A,
141 pVBInfo->MCLKData[XGINew_RAMType].SR2A);
142
143 xgifb_reg_set(pVBInfo->P3c4,
144 0x2E,
145 pVBInfo->ECLKData[XGINew_RAMType].SR2E);
146 xgifb_reg_set(pVBInfo->P3c4,
147 0x2F,
148 pVBInfo->ECLKData[XGINew_RAMType].SR2F);
149 xgifb_reg_set(pVBInfo->P3c4,
150 0x30,
151 pVBInfo->ECLKData[XGINew_RAMType].SR30);
152
153 /* [Vicent] 2004/07/07,
154 * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
155 /* [Hsuan] 2004/08/20,
156 * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
157 * Set SR32 D[1:0] = 10b */
158 if (HwDeviceExtension->jChipType == XG42) {
159 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&
160 (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&
161 (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&
162 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||
163 ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&
164 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
165 xgifb_reg_set(pVBInfo->P3c4,
166 0x32,
167 ((unsigned char) xgifb_reg_get(
168 pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
169 }
170 }
171
172 static void XGINew_DDRII_Bootup_XG27(
173 struct xgi_hw_device_info *HwDeviceExtension,
174 unsigned long P3c4, struct vb_device_info *pVBInfo)
175 {
176 unsigned long P3d4 = P3c4 + 0x10;
177 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
178 pVBInfo);
179 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
180
181 /* Set Double Frequency */
182 /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
183 xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
184
185 udelay(200);
186
187 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
188 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
189 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
190 udelay(15);
191 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
192 udelay(15);
193
194 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
195 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
196 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
197 udelay(15);
198 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
199 udelay(15);
200
201 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
202 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
203 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
204 udelay(30);
205 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
206 udelay(15);
207
208 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
209 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
210 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
211 udelay(30);
212 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
213 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
214 /* udelay(15); */
215
216 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
217 udelay(60);
218 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
219
220 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
221 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
222 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
223
224 udelay(30);
225 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
226 udelay(15);
227
228 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
229 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
230 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
231 udelay(30);
232 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
233 udelay(15);
234
235 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
236 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
237 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
238 udelay(30);
239 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
240 udelay(15);
241
242 /* Set SR1B refresh control 000:close; 010:open */
243 xgifb_reg_set(P3c4, 0x1B, 0x04);
244 udelay(200);
245
246 }
247
248 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
249 unsigned long P3c4, struct vb_device_info *pVBInfo)
250 {
251 unsigned long P3d4 = P3c4 + 0x10;
252
253 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
254 pVBInfo);
255 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
256
257 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
258
259 udelay(200);
260 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
261 xgifb_reg_set(P3c4, 0x19, 0x80);
262 xgifb_reg_set(P3c4, 0x16, 0x05);
263 xgifb_reg_set(P3c4, 0x16, 0x85);
264
265 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
266 xgifb_reg_set(P3c4, 0x19, 0xC0);
267 xgifb_reg_set(P3c4, 0x16, 0x05);
268 xgifb_reg_set(P3c4, 0x16, 0x85);
269
270 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
271 xgifb_reg_set(P3c4, 0x19, 0x40);
272 xgifb_reg_set(P3c4, 0x16, 0x05);
273 xgifb_reg_set(P3c4, 0x16, 0x85);
274
275 /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
276 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
277 xgifb_reg_set(P3c4, 0x19, 0x02);
278 xgifb_reg_set(P3c4, 0x16, 0x05);
279 xgifb_reg_set(P3c4, 0x16, 0x85);
280
281 udelay(15);
282 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
283 udelay(30);
284 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
285 udelay(100);
286
287 /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
288 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
289 xgifb_reg_set(P3c4, 0x19, 0x00);
290 xgifb_reg_set(P3c4, 0x16, 0x05);
291 xgifb_reg_set(P3c4, 0x16, 0x85);
292
293 udelay(200);
294 }
295
296 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
297 struct vb_device_info *pVBInfo)
298 {
299 xgifb_reg_set(P3c4, 0x18, 0x01);
300 xgifb_reg_set(P3c4, 0x19, 0x40);
301 xgifb_reg_set(P3c4, 0x16, 0x00);
302 xgifb_reg_set(P3c4, 0x16, 0x80);
303 udelay(60);
304
305 xgifb_reg_set(P3c4, 0x18, 0x00);
306 xgifb_reg_set(P3c4, 0x19, 0x40);
307 xgifb_reg_set(P3c4, 0x16, 0x00);
308 xgifb_reg_set(P3c4, 0x16, 0x80);
309 udelay(60);
310 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
311 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
312 xgifb_reg_set(P3c4, 0x19, 0x01);
313 xgifb_reg_set(P3c4, 0x16, 0x03);
314 xgifb_reg_set(P3c4, 0x16, 0x83);
315 mdelay(1);
316 xgifb_reg_set(P3c4, 0x1B, 0x03);
317 udelay(500);
318 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
319 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
320 xgifb_reg_set(P3c4, 0x19, 0x00);
321 xgifb_reg_set(P3c4, 0x16, 0x03);
322 xgifb_reg_set(P3c4, 0x16, 0x83);
323 xgifb_reg_set(P3c4, 0x1B, 0x00);
324 }
325
326 static void XGINew_DDR1x_DefaultRegister(
327 struct xgi_hw_device_info *HwDeviceExtension,
328 unsigned long Port, struct vb_device_info *pVBInfo)
329 {
330 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
331
332 if (HwDeviceExtension->jChipType >= XG20) {
333 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
334 xgifb_reg_set(P3d4,
335 0x82,
336 pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
337 xgifb_reg_set(P3d4,
338 0x85,
339 pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
340 xgifb_reg_set(P3d4,
341 0x86,
342 pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
343
344 xgifb_reg_set(P3d4, 0x98, 0x01);
345 xgifb_reg_set(P3d4, 0x9A, 0x02);
346
347 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
348 } else {
349 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
350
351 switch (HwDeviceExtension->jChipType) {
352 case XG41:
353 case XG42:
354 /* CR82 */
355 xgifb_reg_set(P3d4,
356 0x82,
357 pVBInfo->CR40[11][XGINew_RAMType]);
358 /* CR85 */
359 xgifb_reg_set(P3d4,
360 0x85,
361 pVBInfo->CR40[12][XGINew_RAMType]);
362 /* CR86 */
363 xgifb_reg_set(P3d4,
364 0x86,
365 pVBInfo->CR40[13][XGINew_RAMType]);
366 break;
367 default:
368 xgifb_reg_set(P3d4, 0x82, 0x88);
369 xgifb_reg_set(P3d4, 0x86, 0x00);
370 /* Insert read command for delay */
371 xgifb_reg_get(P3d4, 0x86);
372 xgifb_reg_set(P3d4, 0x86, 0x88);
373 xgifb_reg_get(P3d4, 0x86);
374 xgifb_reg_set(P3d4,
375 0x86,
376 pVBInfo->CR40[13][XGINew_RAMType]);
377 xgifb_reg_set(P3d4, 0x82, 0x77);
378 xgifb_reg_set(P3d4, 0x85, 0x00);
379
380 /* Insert read command for delay */
381 xgifb_reg_get(P3d4, 0x85);
382 xgifb_reg_set(P3d4, 0x85, 0x88);
383
384 /* Insert read command for delay */
385 xgifb_reg_get(P3d4, 0x85);
386 /* CR85 */
387 xgifb_reg_set(P3d4,
388 0x85,
389 pVBInfo->CR40[12][XGINew_RAMType]);
390 /* CR82 */
391 xgifb_reg_set(P3d4,
392 0x82,
393 pVBInfo->CR40[11][XGINew_RAMType]);
394 break;
395 }
396
397 xgifb_reg_set(P3d4, 0x97, 0x00);
398 xgifb_reg_set(P3d4, 0x98, 0x01);
399 xgifb_reg_set(P3d4, 0x9A, 0x02);
400 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
401 }
402 }
403
404 static void XGINew_DDR2_DefaultRegister(
405 struct xgi_hw_device_info *HwDeviceExtension,
406 unsigned long Port, struct vb_device_info *pVBInfo)
407 {
408 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
409
410 /* keep following setting sequence, each setting in
411 * the same reg insert idle */
412 xgifb_reg_set(P3d4, 0x82, 0x77);
413 xgifb_reg_set(P3d4, 0x86, 0x00);
414 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
415 xgifb_reg_set(P3d4, 0x86, 0x88);
416 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
417 /* CR86 */
418 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
419 xgifb_reg_set(P3d4, 0x82, 0x77);
420 xgifb_reg_set(P3d4, 0x85, 0x00);
421 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
422 xgifb_reg_set(P3d4, 0x85, 0x88);
423 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
424 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
425 if (HwDeviceExtension->jChipType == XG27)
426 /* CR82 */
427 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);
428 else
429 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
430
431 xgifb_reg_set(P3d4, 0x98, 0x01);
432 xgifb_reg_set(P3d4, 0x9A, 0x02);
433 if (HwDeviceExtension->jChipType == XG27)
434 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
435 else
436 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
437 }
438
439 static void XGINew_SetDRAMDefaultRegister340(
440 struct xgi_hw_device_info *HwDeviceExtension,
441 unsigned long Port, struct vb_device_info *pVBInfo)
442 {
443 unsigned char temp, temp1, temp2, temp3, i, j, k;
444
445 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
446
447 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
448 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
449 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
450 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
451
452 temp2 = 0;
453 for (i = 0; i < 4; i++) {
454 /* CR6B DQS fine tune delay */
455 temp = pVBInfo->CR6B[XGINew_RAMType][i];
456 for (j = 0; j < 4; j++) {
457 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
458 temp2 |= temp1;
459 xgifb_reg_set(P3d4, 0x6B, temp2);
460 /* Insert read command for delay */
461 xgifb_reg_get(P3d4, 0x6B);
462 temp2 &= 0xF0;
463 temp2 += 0x10;
464 }
465 }
466
467 temp2 = 0;
468 for (i = 0; i < 4; i++) {
469 /* CR6E DQM fine tune delay */
470 temp = pVBInfo->CR6E[XGINew_RAMType][i];
471 for (j = 0; j < 4; j++) {
472 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
473 temp2 |= temp1;
474 xgifb_reg_set(P3d4, 0x6E, temp2);
475 /* Insert read command for delay */
476 xgifb_reg_get(P3d4, 0x6E);
477 temp2 &= 0xF0;
478 temp2 += 0x10;
479 }
480 }
481
482 temp3 = 0;
483 for (k = 0; k < 4; k++) {
484 /* CR6E_D[1:0] select channel */
485 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
486 temp2 = 0;
487 for (i = 0; i < 8; i++) {
488 /* CR6F DQ fine tune delay */
489 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];
490 for (j = 0; j < 4; j++) {
491 temp1 = (temp >> (2 * j)) & 0x03;
492 temp2 |= temp1;
493 xgifb_reg_set(P3d4, 0x6F, temp2);
494 /* Insert read command for delay */
495 xgifb_reg_get(P3d4, 0x6F);
496 temp2 &= 0xF8;
497 temp2 += 0x08;
498 }
499 }
500 temp3 += 0x01;
501 }
502
503 xgifb_reg_set(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
504 xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
505
506 temp2 = 0x80;
507 /* CR89 terminator type select */
508 temp = pVBInfo->CR89[XGINew_RAMType][0];
509 for (j = 0; j < 4; j++) {
510 temp1 = (temp >> (2 * j)) & 0x03;
511 temp2 |= temp1;
512 xgifb_reg_set(P3d4, 0x89, temp2);
513 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
514 temp2 &= 0xF0;
515 temp2 += 0x10;
516 }
517
518 temp = pVBInfo->CR89[XGINew_RAMType][1];
519 temp1 = temp & 0x03;
520 temp2 |= temp1;
521 xgifb_reg_set(P3d4, 0x89, temp2);
522
523 temp = pVBInfo->CR40[3][XGINew_RAMType];
524 temp1 = temp & 0x0F;
525 temp2 = (temp >> 4) & 0x07;
526 temp3 = temp & 0x80;
527 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
528 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
529 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
530 xgifb_reg_set(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
531
532 if (HwDeviceExtension->jChipType == XG27)
533 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
534
535 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
536 xgifb_reg_set(P3d4, (0x90 + j),
537 pVBInfo->CR40[14 + j][XGINew_RAMType]);
538
539 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
540 xgifb_reg_set(P3d4, (0xC3 + j),
541 pVBInfo->CR40[21 + j][XGINew_RAMType]);
542
543 for (j = 0; j < 2; j++) /* CR8A - CR8B */
544 xgifb_reg_set(P3d4, (0x8A + j),
545 pVBInfo->CR40[1 + j][XGINew_RAMType]);
546
547 if ((HwDeviceExtension->jChipType == XG41) ||
548 (HwDeviceExtension->jChipType == XG42))
549 xgifb_reg_set(P3d4, 0x8C, 0x87);
550
551 xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
552
553 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
554 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
555 xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
556 if (XGINew_RAMType) {
557 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
558 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
559 if (HwDeviceExtension->jChipType == XG27)
560 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
561
562 } else {
563 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
564 }
565 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
566
567 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
568 if (temp == 0) {
569 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
570 } else {
571 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
572 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
573 }
574 xgifb_reg_set(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
575 }
576
577 static void XGINew_SetDRAMSizingType(int index,
578 unsigned short DRAMTYPE_TABLE[][5],
579 struct vb_device_info *pVBInfo)
580 {
581 unsigned short data;
582
583 data = DRAMTYPE_TABLE[index][4];
584 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
585 udelay(15);
586 /* should delay 50 ns */
587 }
588
589 static unsigned short XGINew_SetDRAMSizeReg(int index,
590 unsigned short DRAMTYPE_TABLE[][5],
591 struct vb_device_info *pVBInfo)
592 {
593 unsigned short data = 0, memsize = 0;
594 int RankSize;
595 unsigned char ChannelNo;
596
597 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
598 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
599 data &= 0x80;
600
601 if (data == 0x80)
602 RankSize *= 2;
603
604 data = 0;
605
606 if (XGINew_ChannelAB == 3)
607 ChannelNo = 4;
608 else
609 ChannelNo = XGINew_ChannelAB;
610
611 if (ChannelNo * RankSize <= 256) {
612 while ((RankSize >>= 1) > 0)
613 data += 0x10;
614
615 memsize = data >> 4;
616
617 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
618 xgifb_reg_set(pVBInfo->P3c4,
619 0x14,
620 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
621 (data & 0xF0));
622
623 /* data |= XGINew_ChannelAB << 2; */
624 /* data |= (XGINew_DataBusWidth / 64) << 1; */
625 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
626
627 /* should delay */
628 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
629 }
630 return memsize;
631 }
632
633 static unsigned short XGINew_SetDRAMSize20Reg(int index,
634 unsigned short DRAMTYPE_TABLE[][5],
635 struct vb_device_info *pVBInfo)
636 {
637 unsigned short data = 0, memsize = 0;
638 int RankSize;
639 unsigned char ChannelNo;
640
641 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
642 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
643 data &= 0x80;
644
645 if (data == 0x80)
646 RankSize *= 2;
647
648 data = 0;
649
650 if (XGINew_ChannelAB == 3)
651 ChannelNo = 4;
652 else
653 ChannelNo = XGINew_ChannelAB;
654
655 if (ChannelNo * RankSize <= 256) {
656 while ((RankSize >>= 1) > 0)
657 data += 0x10;
658
659 memsize = data >> 4;
660
661 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
662 xgifb_reg_set(pVBInfo->P3c4,
663 0x14,
664 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
665 (data & 0xF0));
666 udelay(15);
667
668 /* data |= XGINew_ChannelAB << 2; */
669 /* data |= (XGINew_DataBusWidth / 64) << 1; */
670 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
671
672 /* should delay */
673 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
674 }
675 return memsize;
676 }
677
678 static int XGINew_ReadWriteRest(unsigned short StopAddr,
679 unsigned short StartAddr, struct vb_device_info *pVBInfo)
680 {
681 int i;
682 unsigned long Position = 0;
683
684 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
685
686 for (i = StartAddr; i <= StopAddr; i++) {
687 Position = 1 << i;
688 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
689 }
690
691 udelay(500); /* [Vicent] 2004/04/16.
692 Fix #1759 Memory Size error in Multi-Adapter. */
693
694 Position = 0;
695
696 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
697 return 0;
698
699 for (i = StartAddr; i <= StopAddr; i++) {
700 Position = 1 << i;
701 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) !=
702 Position)
703 return 0;
704 }
705 return 1;
706 }
707
708 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
709 {
710 unsigned char data;
711
712 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
713
714 if ((data & 0x10) == 0) {
715 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
716 data = (data & 0x02) >> 1;
717 return data;
718 } else {
719 return data & 0x01;
720 }
721 }
722
723 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
724 struct vb_device_info *pVBInfo)
725 {
726 unsigned char data;
727
728 switch (HwDeviceExtension->jChipType) {
729 case XG20:
730 case XG21:
731 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
732 data = data & 0x01;
733 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
734
735 if (data == 0) { /* Single_32_16 */
736
737 if ((HwDeviceExtension->ulVideoMemorySize - 1)
738 > 0x1000000) {
739
740 XGINew_DataBusWidth = 32; /* 32 bits */
741 /* 22bit + 2 rank + 32bit */
742 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
743 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
744 udelay(15);
745
746 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
747 return;
748
749 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
750 0x800000) {
751 /* 22bit + 1 rank + 32bit */
752 xgifb_reg_set(pVBInfo->P3c4,
753 0x13,
754 0x31);
755 xgifb_reg_set(pVBInfo->P3c4,
756 0x14,
757 0x42);
758 udelay(15);
759
760 if (XGINew_ReadWriteRest(23,
761 23,
762 pVBInfo) == 1)
763 return;
764 }
765 }
766
767 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
768 0x800000) {
769 XGINew_DataBusWidth = 16; /* 16 bits */
770 /* 22bit + 2 rank + 16bit */
771 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
772 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
773 udelay(15);
774
775 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
776 return;
777 else
778 xgifb_reg_set(pVBInfo->P3c4,
779 0x13,
780 0x31);
781 udelay(15);
782 }
783
784 } else { /* Dual_16_8 */
785 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
786 0x800000) {
787 XGINew_DataBusWidth = 16; /* 16 bits */
788 /* (0x31:12x8x2) 22bit + 2 rank */
789 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
790 /* 0x41:16Mx16 bit*/
791 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
792 udelay(15);
793
794 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
795 return;
796
797 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
798 0x400000) {
799 /* (0x31:12x8x2) 22bit + 1 rank */
800 xgifb_reg_set(pVBInfo->P3c4,
801 0x13,
802 0x31);
803 /* 0x31:8Mx16 bit*/
804 xgifb_reg_set(pVBInfo->P3c4,
805 0x14,
806 0x31);
807 udelay(15);
808
809 if (XGINew_ReadWriteRest(22,
810 22,
811 pVBInfo) == 1)
812 return;
813 }
814 }
815
816 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
817 0x400000) {
818 XGINew_DataBusWidth = 8; /* 8 bits */
819 /* (0x31:12x8x2) 22bit + 2 rank */
820 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
821 /* 0x30:8Mx8 bit*/
822 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
823 udelay(15);
824
825 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
826 return;
827 else /* (0x31:12x8x2) 22bit + 1 rank */
828 xgifb_reg_set(pVBInfo->P3c4,
829 0x13,
830 0x31);
831 udelay(15);
832 }
833 }
834 break;
835
836 case XG27:
837 XGINew_DataBusWidth = 16; /* 16 bits */
838 XGINew_ChannelAB = 1; /* Single channel */
839 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
840 break;
841 case XG41:
842 if (XGINew_CheckFrequence(pVBInfo) == 1) {
843 XGINew_DataBusWidth = 32; /* 32 bits */
844 XGINew_ChannelAB = 3; /* Quad Channel */
845 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
846 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
847
848 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
849 return;
850
851 XGINew_ChannelAB = 2; /* Dual channels */
852 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
853
854 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
855 return;
856
857 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
858
859 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
860 return;
861
862 XGINew_ChannelAB = 3;
863 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
864 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
865
866 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
867 return;
868
869 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
870
871 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
872 return;
873 else
874 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
875 } else { /* DDR */
876 XGINew_DataBusWidth = 64; /* 64 bits */
877 XGINew_ChannelAB = 2; /* Dual channels */
878 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
879 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
880
881 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
882 return;
883
884 XGINew_ChannelAB = 1; /* Single channels */
885 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
886
887 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
888 return;
889
890 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
891
892 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
893 return;
894
895 XGINew_ChannelAB = 2; /* Dual channels */
896 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
897 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
898
899 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
900 return;
901
902 XGINew_ChannelAB = 1; /* Single channels */
903 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
904
905 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
906 return;
907 else
908 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
909 }
910
911 break;
912
913 case XG42:
914 /*
915 XG42 SR14 D[3] Reserve
916 D[2] = 1, Dual Channel
917 = 0, Single Channel
918
919 It's Different from Other XG40 Series.
920 */
921 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
922 XGINew_DataBusWidth = 32; /* 32 bits */
923 XGINew_ChannelAB = 2; /* 2 Channel */
924 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
925 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
926
927 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
928 return;
929
930 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
931 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
932 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
933 return;
934
935 XGINew_ChannelAB = 1; /* Single Channel */
936 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
937 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
938
939 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
940 return;
941 else {
942 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
943 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
944 }
945 } else { /* DDR */
946 XGINew_DataBusWidth = 64; /* 64 bits */
947 XGINew_ChannelAB = 1; /* 1 channels */
948 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
949 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
950
951 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
952 return;
953 else {
954 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
955 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
956 }
957 }
958
959 break;
960
961 default: /* XG40 */
962
963 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
964 XGINew_DataBusWidth = 32; /* 32 bits */
965 XGINew_ChannelAB = 3;
966 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
967 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
968
969 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
970 return;
971
972 XGINew_ChannelAB = 2; /* 2 channels */
973 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
974
975 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
976 return;
977
978 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
979 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
980
981 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
982 XGINew_ChannelAB = 3; /* 4 channels */
983 } else {
984 XGINew_ChannelAB = 2; /* 2 channels */
985 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
986 }
987 } else { /* DDR */
988 XGINew_DataBusWidth = 64; /* 64 bits */
989 XGINew_ChannelAB = 2; /* 2 channels */
990 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
991 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
992
993 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
994 return;
995 } else {
996 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
997 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
998 }
999 }
1000 break;
1001 }
1002 }
1003
1004 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1005 struct vb_device_info *pVBInfo)
1006 {
1007 int i;
1008 unsigned short memsize, addr;
1009
1010 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1011 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1012 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1013
1014 if (HwDeviceExtension->jChipType >= XG20) {
1015 for (i = 0; i < 12; i++) {
1016 XGINew_SetDRAMSizingType(i,
1017 XGINew_DDRDRAM_TYPE20,
1018 pVBInfo);
1019 memsize = XGINew_SetDRAMSize20Reg(i,
1020 XGINew_DDRDRAM_TYPE20,
1021 pVBInfo);
1022 if (memsize == 0)
1023 continue;
1024
1025 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1026 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1027 (unsigned long) (1 << addr))
1028 continue;
1029
1030 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1031 return 1;
1032 }
1033 } else {
1034 for (i = 0; i < 4; i++) {
1035 XGINew_SetDRAMSizingType(i,
1036 XGINew_DDRDRAM_TYPE340,
1037 pVBInfo);
1038 memsize = XGINew_SetDRAMSizeReg(i,
1039 XGINew_DDRDRAM_TYPE340,
1040 pVBInfo);
1041
1042 if (memsize == 0)
1043 continue;
1044
1045 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1046 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1047 (unsigned long) (1 << addr))
1048 continue;
1049
1050 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1051 return 1;
1052 }
1053 }
1054 return 0;
1055 }
1056
1057 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1058 struct vb_device_info *pVBInfo)
1059 {
1060 unsigned short data;
1061
1062 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1063 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1064
1065 XGISetModeNew(HwDeviceExtension, 0x2e);
1066
1067 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1068 /* disable read cache */
1069 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1070 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1071
1072 /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1073 /* data |= 0x20 ; */
1074 /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1075 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1076 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1077 /* enable read cache */
1078 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1079 }
1080
1081 static void ReadVBIOSTablData(unsigned char ChipType,
1082 struct vb_device_info *pVBInfo)
1083 {
1084 volatile unsigned char *pVideoMemory =
1085 (unsigned char *) pVBInfo->ROMAddr;
1086 unsigned long i;
1087 unsigned char j, k;
1088 /* Volari customize data area end */
1089
1090 if (ChipType == XG21) {
1091 pVBInfo->IF_DEF_LVDS = 0;
1092 if (pVideoMemory[0x65] & 0x1) {
1093 pVBInfo->IF_DEF_LVDS = 1;
1094 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1095 j = pVideoMemory[i - 1];
1096 if (j != 0xff) {
1097 k = 0;
1098 do {
1099 pVBInfo->XG21_LVDSCapList[k].
1100 LVDS_Capability
1101 = pVideoMemory[i] |
1102 (pVideoMemory[i + 1] << 8);
1103 pVBInfo->XG21_LVDSCapList[k].LVDSHT
1104 = pVideoMemory[i + 2] |
1105 (pVideoMemory[i + 3] << 8);
1106 pVBInfo->XG21_LVDSCapList[k].LVDSVT
1107 = pVideoMemory[i + 4] |
1108 (pVideoMemory[i + 5] << 8);
1109 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1110 = pVideoMemory[i + 6] |
1111 (pVideoMemory[i + 7] << 8);
1112 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1113 = pVideoMemory[i + 8] |
1114 (pVideoMemory[i + 9] << 8);
1115 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1116 = pVideoMemory[i + 10] |
1117 (pVideoMemory[i + 11] << 8);
1118 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1119 = pVideoMemory[i + 12] |
1120 (pVideoMemory[i + 13] << 8);
1121 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1122 = pVideoMemory[i + 14] |
1123 (pVideoMemory[i + 15] << 8);
1124 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1125 = pVideoMemory[i + 16] |
1126 (pVideoMemory[i + 17] << 8);
1127 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1128 = pVideoMemory[i + 18];
1129 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1130 = pVideoMemory[i + 19];
1131 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1132 = pVideoMemory[i + 20];
1133 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1134 = pVideoMemory[i + 21];
1135 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1136 = pVideoMemory[i + 22];
1137 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1138 = pVideoMemory[i + 23];
1139 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1140 = pVideoMemory[i + 24];
1141 i += 25;
1142 j--;
1143 k++;
1144 } while ((j > 0) &&
1145 (k < (sizeof(XGI21_LCDCapList) /
1146 sizeof(struct
1147 XGI21_LVDSCapStruct))));
1148 } else {
1149 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1150 = pVideoMemory[i] |
1151 (pVideoMemory[i + 1] << 8);
1152 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1153 = pVideoMemory[i + 2] |
1154 (pVideoMemory[i + 3] << 8);
1155 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1156 = pVideoMemory[i + 4] |
1157 (pVideoMemory[i + 5] << 8);
1158 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1159 = pVideoMemory[i + 6] |
1160 (pVideoMemory[i + 7] << 8);
1161 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1162 = pVideoMemory[i + 8] |
1163 (pVideoMemory[i + 9] << 8);
1164 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1165 = pVideoMemory[i + 10] |
1166 (pVideoMemory[i + 11] << 8);
1167 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1168 = pVideoMemory[i + 12] |
1169 (pVideoMemory[i + 13] << 8);
1170 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1171 = pVideoMemory[i + 14] |
1172 (pVideoMemory[i + 15] << 8);
1173 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1174 = pVideoMemory[i + 16] |
1175 (pVideoMemory[i + 17] << 8);
1176 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1177 = pVideoMemory[i + 18];
1178 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1179 = pVideoMemory[i + 19];
1180 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1181 = pVideoMemory[i + 20];
1182 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1183 = pVideoMemory[i + 21];
1184 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1185 = pVideoMemory[i + 22];
1186 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1187 = pVideoMemory[i + 23];
1188 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1189 = pVideoMemory[i + 24];
1190 }
1191 }
1192 }
1193 }
1194
1195 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1196 struct vb_device_info *pVBInfo)
1197 {
1198 unsigned short tempbx = 0, temp, tempcx, CR3CData;
1199
1200 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1201
1202 if (temp & Monitor1Sense)
1203 tempbx |= ActiveCRT1;
1204 if (temp & LCDSense)
1205 tempbx |= ActiveLCD;
1206 if (temp & Monitor2Sense)
1207 tempbx |= ActiveCRT2;
1208 if (temp & TVSense) {
1209 tempbx |= ActiveTV;
1210 if (temp & AVIDEOSense)
1211 tempbx |= (ActiveAVideo << 8);
1212 if (temp & SVIDEOSense)
1213 tempbx |= (ActiveSVideo << 8);
1214 if (temp & SCARTSense)
1215 tempbx |= (ActiveSCART << 8);
1216 if (temp & HiTVSense)
1217 tempbx |= (ActiveHiTV << 8);
1218 if (temp & YPbPrSense)
1219 tempbx |= (ActiveYPbPr << 8);
1220 }
1221
1222 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1223 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1224
1225 if (tempbx & tempcx) {
1226 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1227 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1228 tempcx = 0x1FF0;
1229 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1230 tempbx = 0x1FF0;
1231 }
1232 } else {
1233 tempcx = 0x1FF0;
1234 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1235 tempbx = 0x1FF0;
1236 }
1237
1238 tempbx &= tempcx;
1239 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1240 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1241 }
1242
1243 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1244 struct vb_device_info *pVBInfo)
1245 {
1246 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1247
1248 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1249 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1250 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1251
1252 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1253 if (temp & ActiveCRT2)
1254 tempcl = SetCRT2ToRAMDAC;
1255 }
1256
1257 if (temp & ActiveLCD) {
1258 tempcl |= SetCRT2ToLCD;
1259 if (temp & DriverMode) {
1260 if (temp & ActiveTV) {
1261 tempch = SetToLCDA | EnableDualEdge;
1262 temp ^= SetCRT2ToLCD;
1263
1264 if ((temp >> 8) & ActiveAVideo)
1265 tempcl |= SetCRT2ToAVIDEO;
1266 if ((temp >> 8) & ActiveSVideo)
1267 tempcl |= SetCRT2ToSVIDEO;
1268 if ((temp >> 8) & ActiveSCART)
1269 tempcl |= SetCRT2ToSCART;
1270
1271 if (pVBInfo->IF_DEF_HiVision == 1) {
1272 if ((temp >> 8) & ActiveHiTV)
1273 tempcl |= SetCRT2ToHiVisionTV;
1274 }
1275
1276 if (pVBInfo->IF_DEF_YPbPr == 1) {
1277 if ((temp >> 8) & ActiveYPbPr)
1278 tempch |= SetYPbPr;
1279 }
1280 }
1281 }
1282 } else {
1283 if ((temp >> 8) & ActiveAVideo)
1284 tempcl |= SetCRT2ToAVIDEO;
1285 if ((temp >> 8) & ActiveSVideo)
1286 tempcl |= SetCRT2ToSVIDEO;
1287 if ((temp >> 8) & ActiveSCART)
1288 tempcl |= SetCRT2ToSCART;
1289
1290 if (pVBInfo->IF_DEF_HiVision == 1) {
1291 if ((temp >> 8) & ActiveHiTV)
1292 tempcl |= SetCRT2ToHiVisionTV;
1293 }
1294
1295 if (pVBInfo->IF_DEF_YPbPr == 1) {
1296 if ((temp >> 8) & ActiveYPbPr)
1297 tempch |= SetYPbPr;
1298 }
1299 }
1300
1301 tempcl |= SetSimuScanMode;
1302 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1303 || (temp & ActiveCRT2)))
1304 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1305 if ((temp & ActiveLCD) && (temp & ActiveTV))
1306 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1307 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1308
1309 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1310 CR31Data &= ~(SetNotSimuMode >> 8);
1311 if (!(temp & ActiveCRT1))
1312 CR31Data |= (SetNotSimuMode >> 8);
1313 CR31Data &= ~(DisableCRT2Display >> 8);
1314 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1315 CR31Data |= (DisableCRT2Display >> 8);
1316 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1317
1318 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1319 CR38Data &= ~SetYPbPr;
1320 CR38Data |= tempch;
1321 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1322
1323 }
1324
1325 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1326 struct vb_device_info *pVBInfo)
1327 {
1328 unsigned char Temp;
1329 volatile unsigned char *pVideoMemory =
1330 (unsigned char *) pVBInfo->ROMAddr;
1331
1332 pVBInfo->IF_DEF_LVDS = 0;
1333
1334 #if 1
1335 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1336 pVBInfo->IF_DEF_LVDS = 1;
1337 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1338 /* LVDS on chip */
1339 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1340 } else {
1341 #endif
1342 /* Enable GPIOA/B read */
1343 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1344 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1345 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1346 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1347 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1348 /* Enable read GPIOF */
1349 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1350 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1351 if (!Temp)
1352 xgifb_reg_and_or(pVBInfo->P3d4,
1353 0x38,
1354 ~0xE0,
1355 0x80); /* TMDS on chip */
1356 else
1357 xgifb_reg_and_or(pVBInfo->P3d4,
1358 0x38,
1359 ~0xE0,
1360 0xA0); /* Only DVO on chip */
1361 /* Disable read GPIOF */
1362 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1363 }
1364 #if 1
1365 }
1366 #endif
1367 }
1368
1369 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1370 struct vb_device_info *pVBInfo)
1371 {
1372 unsigned char Temp, bCR4A;
1373
1374 pVBInfo->IF_DEF_LVDS = 0;
1375 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1376 /* Enable GPIOA/B/C read */
1377 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1378 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1379 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1380
1381 if (Temp <= 0x02) {
1382 pVBInfo->IF_DEF_LVDS = 1;
1383 /* LVDS setting */
1384 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1385 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1386 } else {
1387 /* TMDS/DVO setting */
1388 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1389 }
1390 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1391
1392 }
1393
1394 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1395 {
1396 unsigned char CR38, CR4A, temp;
1397
1398 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1399 /* enable GPIOE read */
1400 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1401 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1402 temp = 0;
1403 if ((CR38 & 0xE0) > 0x80) {
1404 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1405 temp &= 0x08;
1406 temp >>= 3;
1407 }
1408
1409 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1410
1411 return temp;
1412 }
1413
1414 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1415 {
1416 unsigned char CR4A, temp;
1417
1418 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1419 /* enable GPIOA/B/C read */
1420 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1421 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1422 if (temp <= 2)
1423 temp &= 0x03;
1424 else
1425 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1426
1427 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1428
1429 return temp;
1430 }
1431
1432 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1433 {
1434 struct vb_device_info VBINF;
1435 struct vb_device_info *pVBInfo = &VBINF;
1436 unsigned char i, temp = 0, temp1;
1437 /* VBIOSVersion[5]; */
1438 volatile unsigned char *pVideoMemory;
1439
1440 /* unsigned long j, k; */
1441
1442 unsigned long Temp;
1443
1444 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1445
1446 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1447
1448 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1449
1450 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1451
1452 /* Newdebugcode(0x99); */
1453
1454
1455 /* if (pVBInfo->ROMAddr == 0) */
1456 /* return(0); */
1457
1458 if (pVBInfo->FBAddr == NULL) {
1459 printk("\n pVBInfo->FBAddr == 0 ");
1460 return 0;
1461 }
1462 printk("1");
1463 if (pVBInfo->BaseAddr == 0) {
1464 printk("\npVBInfo->BaseAddr == 0 ");
1465 return 0;
1466 }
1467 printk("2");
1468
1469 outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1470
1471 pVBInfo->ISXPDOS = 0;
1472 printk("3");
1473
1474 printk("4");
1475
1476 /* VBIOSVersion[4] = 0x0; */
1477
1478 /* 09/07/99 modify by domao */
1479
1480 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1481 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1482 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1483 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1484 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1485 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1486 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1487 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1488 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1489 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1490 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1491 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1492 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1493 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1494 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1495 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1496 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1497 printk("5");
1498
1499 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1500 /* Run XGI_GetVBType before InitTo330Pointer */
1501 XGI_GetVBType(pVBInfo);
1502
1503 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1504
1505 /* ReadVBIOSData */
1506 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1507
1508 /* 1.Openkey */
1509 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1510 printk("6");
1511
1512 /* GetXG21Sense (GPIO) */
1513 if (HwDeviceExtension->jChipType == XG21)
1514 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1515
1516 if (HwDeviceExtension->jChipType == XG27)
1517 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1518
1519 printk("7");
1520
1521 /* 2.Reset Extended register */
1522
1523 for (i = 0x06; i < 0x20; i++)
1524 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1525
1526 for (i = 0x21; i <= 0x27; i++)
1527 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1528
1529 /* for(i = 0x06; i <= 0x27; i++) */
1530 /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1531
1532 printk("8");
1533
1534 for (i = 0x31; i <= 0x3B; i++)
1535 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1536 printk("9");
1537
1538 /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1539 if (HwDeviceExtension->jChipType == XG42)
1540 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1541
1542 /* for (i = 0x30; i <= 0x3F; i++) */
1543 /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1544
1545 for (i = 0x79; i <= 0x7C; i++)
1546 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1547
1548 printk("10");
1549
1550 if (HwDeviceExtension->jChipType >= XG20)
1551 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1552
1553 /* 3.SetMemoryClock
1554
1555 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,
1556 pVBInfo);
1557 */
1558
1559 printk("11");
1560
1561 /* 4.SetDefExt1Regs begin */
1562 xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1563 if (HwDeviceExtension->jChipType == XG27) {
1564 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1565 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1566 }
1567 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1568 xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1569 /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1570 /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1571 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1572 /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1573 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1574 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1575 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1576
1577 /* SR11 = 0x0F; */
1578 /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1579
1580 printk("12");
1581
1582 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1583 /* Set AGP Rate */
1584 /*
1585 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1586 temp1 &= 0x02;
1587 if (temp1 == 0x02) {
1588 outl(0x80000000, 0xcf8);
1589 ChipsetID = inl(0x0cfc);
1590 outl(0x8000002C, 0xcf8);
1591 VendorID = inl(0x0cfc);
1592 VendorID &= 0x0000FFFF;
1593 outl(0x8001002C, 0xcf8);
1594 GraphicVendorID = inl(0x0cfc);
1595 GraphicVendorID &= 0x0000FFFF;
1596
1597 if (ChipsetID == 0x7301039)
1598 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1599
1600 ChipsetID &= 0x0000FFFF;
1601
1602 if ((ChipsetID == 0x700E) ||
1603 (ChipsetID == 0x1022) ||
1604 (ChipsetID == 0x1106) ||
1605 (ChipsetID == 0x10DE)) {
1606 if (ChipsetID == 0x1106) {
1607 if ((VendorID == 0x1019) &&
1608 (GraphicVendorID == 0x1019))
1609 xgifb_reg_set(pVBInfo->P3d4,
1610 0x5F,
1611 0x0D);
1612 else
1613 xgifb_reg_set(pVBInfo->P3d4,
1614 0x5F,
1615 0x0B);
1616 } else {
1617 xgifb_reg_set(pVBInfo->P3d4,
1618 0x5F,
1619 0x0B);
1620 }
1621 }
1622 }
1623 */
1624
1625 printk("13");
1626
1627 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1628 for (i = 0x47; i <= 0x4C; i++)
1629 xgifb_reg_set(pVBInfo->P3d4,
1630 i,
1631 pVBInfo->AGPReg[i - 0x47]);
1632
1633 for (i = 0x70; i <= 0x71; i++)
1634 xgifb_reg_set(pVBInfo->P3d4,
1635 i,
1636 pVBInfo->AGPReg[6 + i - 0x70]);
1637
1638 for (i = 0x74; i <= 0x77; i++)
1639 xgifb_reg_set(pVBInfo->P3d4,
1640 i,
1641 pVBInfo->AGPReg[8 + i - 0x74]);
1642 /* Set AGP customize registers (in SetDefAGPRegs) End */
1643 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1644 /* outl(0x80000000, 0xcf8); */
1645 /* ChipsetID = inl(0x0cfc); */
1646 /* if (ChipsetID == 0x25308086) */
1647 /* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1648
1649 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,
1650 0x50,
1651 0,
1652 &Temp); /* Get */
1653 Temp >>= 20;
1654 Temp &= 0xF;
1655
1656 if (Temp == 1)
1657 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1658 printk("14");
1659 } /* != XG20 */
1660
1661 /* Set PCI */
1662 xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1663 xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1664 xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1665 printk("15");
1666
1667 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1668 /* Set VB */
1669 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1670 /* alan, disable VideoCapture */
1671 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1672 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1673 /* chk if BCLK>=100MHz */
1674 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1675 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1676
1677 xgifb_reg_set(pVBInfo->Part1Port,
1678 0x02,
1679 (*pVBInfo->pCRT2Data_1_2));
1680
1681 printk("16");
1682
1683 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1684 } /* != XG20 */
1685
1686 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1687
1688 if ((HwDeviceExtension->jChipType == XG42) &&
1689 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1690 /* Not DDR */
1691 xgifb_reg_set(pVBInfo->P3c4,
1692 0x31,
1693 (*pVBInfo->pSR31 & 0x3F) | 0x40);
1694 xgifb_reg_set(pVBInfo->P3c4,
1695 0x32,
1696 (*pVBInfo->pSR32 & 0xFC) | 0x01);
1697 } else {
1698 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1699 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1700 }
1701 xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1702 printk("17");
1703
1704 /*
1705 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
1706
1707 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1708 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1709 if (pVBInfo->IF_DEF_LVDS == 0) {
1710 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1711 xgifb_reg_set(pVBInfo->Part4Port,
1712 0x0D,
1713 *pVBInfo->pCRT2Data_4_D);
1714 xgifb_reg_set(pVBInfo->Part4Port,
1715 0x0E,
1716 *pVBInfo->pCRT2Data_4_E);
1717 xgifb_reg_set(pVBInfo->Part4Port,
1718 0x10,
1719 *pVBInfo->pCRT2Data_4_10);
1720 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1721 }
1722
1723 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1724 }
1725 } /* != XG20 */
1726 printk("18");
1727
1728 printk("181");
1729
1730 printk("182");
1731
1732 XGI_SenseCRT1(pVBInfo);
1733
1734 printk("183");
1735 /* XGINew_DetectMonitor(HwDeviceExtension); */
1736 pVBInfo->IF_DEF_CH7007 = 0;
1737 if ((HwDeviceExtension->jChipType == XG21) &&
1738 (pVBInfo->IF_DEF_CH7007)) {
1739 printk("184");
1740 /* sense CRT2 */
1741 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo);
1742 printk("185");
1743
1744 }
1745 if (HwDeviceExtension->jChipType == XG21) {
1746 printk("186");
1747
1748 xgifb_reg_and_or(pVBInfo->P3d4,
1749 0x32,
1750 ~Monitor1Sense,
1751 Monitor1Sense); /* Z9 default has CRT */
1752 temp = GetXG21FPBits(pVBInfo);
1753 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1754 printk("187");
1755
1756 }
1757 if (HwDeviceExtension->jChipType == XG27) {
1758 xgifb_reg_and_or(pVBInfo->P3d4,
1759 0x32,
1760 ~Monitor1Sense,
1761 Monitor1Sense); /* Z9 default has CRT */
1762 temp = GetXG27FPBits(pVBInfo);
1763 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1764 }
1765 printk("19");
1766
1767 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
1768 pVBInfo);
1769
1770 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1771 pVBInfo->P3d4,
1772 pVBInfo);
1773
1774 printk("20");
1775 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1776 printk("21");
1777
1778 printk("22");
1779
1780 /* SetDefExt2Regs begin */
1781 /*
1782 AGP = 1;
1783 temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1784 temp &= 0x30;
1785 if (temp == 0x30)
1786 AGP = 0;
1787
1788 if (AGP == 0)
1789 *pVBInfo->pSR21 &= 0xEF;
1790
1791 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1792 if (AGP == 1)
1793 *pVBInfo->pSR22 &= 0x20;
1794 xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1795 */
1796 /* base = 0x80000000; */
1797 /* OutPortLong(0xcf8, base); */
1798 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1799 /* if (Temp == 0x1039) { */
1800 xgifb_reg_set(pVBInfo->P3c4,
1801 0x22,
1802 (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1803 /* } else { */
1804 /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1805 /* } */
1806
1807 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1808
1809 printk("23");
1810
1811 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1812 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1813
1814 printk("24");
1815
1816 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1817 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1818 printk("25");
1819
1820 return 1;
1821 } /* end of init */
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