nfsd4: typo logical vs bitwise negate for want_mask
[linux-btrfs-devel.git] / arch / arm / mach-s5p64x0 / clock.c
blobb52c6e2f37a66868ab34b2bee2d79b669a59a887
1 /* linux/arch/arm/mach-s5p64x0/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P64X0 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
21 #include <linux/io.h>
23 #include <mach/hardware.h>
24 #include <mach/map.h>
25 #include <mach/regs-clock.h>
27 #include <plat/cpu-freq.h>
28 #include <plat/clock.h>
29 #include <plat/cpu.h>
30 #include <plat/pll.h>
31 #include <plat/s5p-clock.h>
32 #include <plat/clock-clksrc.h>
33 #include <plat/s5p6440.h>
34 #include <plat/s5p6450.h>
36 struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
45 struct clksrc_clk clk_mout_mpll = {
46 .clk = {
47 .name = "mout_mpll",
48 .id = -1,
50 .sources = &clk_src_mpll,
51 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
54 struct clksrc_clk clk_mout_epll = {
55 .clk = {
56 .name = "mout_epll",
57 .id = -1,
59 .sources = &clk_src_epll,
60 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
63 enum perf_level {
64 L0 = 532*1000,
65 L1 = 266*1000,
66 L2 = 133*1000,
69 static const u32 clock_table[][3] = {
70 /*{ARM_CLK, DIVarm, DIVhclk}*/
71 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
72 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
76 unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
78 unsigned long rate = clk_get_rate(clk->parent);
79 u32 clkdiv;
81 /* divisor mask starts at bit0, so no need to shift */
82 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
84 return rate / (clkdiv + 1);
87 unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
89 u32 iter;
91 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
92 if (rate > clock_table[iter][0])
93 return clock_table[iter-1][0];
96 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
99 int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
101 u32 round_tmp;
102 u32 iter;
103 u32 clk_div0_tmp;
104 u32 cur_rate = clk->ops->get_rate(clk);
105 unsigned long flags;
107 round_tmp = clk->ops->round_rate(clk, rate);
108 if (round_tmp == cur_rate)
109 return 0;
112 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
113 if (round_tmp == clock_table[iter][0])
114 break;
117 if (iter >= ARRAY_SIZE(clock_table))
118 iter = ARRAY_SIZE(clock_table) - 1;
120 local_irq_save(flags);
121 if (cur_rate > round_tmp) {
122 /* Frequency Down */
123 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
124 clk_div0_tmp |= clock_table[iter][1];
125 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
127 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
128 ~(S5P64X0_CLKDIV0_HCLK_MASK);
129 clk_div0_tmp |= clock_table[iter][2];
130 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
133 } else {
134 /* Frequency Up */
135 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
136 ~(S5P64X0_CLKDIV0_HCLK_MASK);
137 clk_div0_tmp |= clock_table[iter][2];
138 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
140 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
141 clk_div0_tmp |= clock_table[iter][1];
142 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
144 local_irq_restore(flags);
146 clk->rate = clock_table[iter][0];
148 return 0;
151 struct clk_ops s5p64x0_clkarm_ops = {
152 .get_rate = s5p64x0_armclk_get_rate,
153 .set_rate = s5p64x0_armclk_set_rate,
154 .round_rate = s5p64x0_armclk_round_rate,
157 struct clksrc_clk clk_armclk = {
158 .clk = {
159 .name = "armclk",
160 .id = 1,
161 .parent = &clk_mout_apll.clk,
162 .ops = &s5p64x0_clkarm_ops,
164 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
167 struct clksrc_clk clk_dout_mpll = {
168 .clk = {
169 .name = "dout_mpll",
170 .id = -1,
171 .parent = &clk_mout_mpll.clk,
173 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
176 struct clk *clkset_hclk_low_list[] = {
177 &clk_mout_apll.clk,
178 &clk_mout_mpll.clk,
181 struct clksrc_sources clkset_hclk_low = {
182 .sources = clkset_hclk_low_list,
183 .nr_sources = ARRAY_SIZE(clkset_hclk_low_list),
186 int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
188 return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
191 int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
193 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
196 int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
198 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
201 int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
203 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
206 int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
208 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
211 int s5p64x0_mem_ctrl(struct clk *clk, int enable)
213 return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
216 int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
218 unsigned long flags;
219 u32 val;
221 /* can't rely on clock lock, this register has other usages */
222 local_irq_save(flags);
224 val = __raw_readl(S5P64X0_OTHERS);
225 if (enable)
226 val |= S5P64X0_OTHERS_USB_SIG_MASK;
227 else
228 val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
230 __raw_writel(val, S5P64X0_OTHERS);
232 local_irq_restore(flags);
234 return 0;