2 * arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
4 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* WM8505 Interrupt Sources */
23 #define IRQ_UHCI 0 /* UHC FS (UHCI?) */
24 #define IRQ_EHCI 1 /* UHC HS */
25 #define IRQ_UDCDMA 2 /* UDC DMA */
27 #define IRQ_PS2MOUSE 4 /* PS/2 Mouse */
28 #define IRQ_UDC 5 /* UDC */
29 #define IRQ_EXT0 6 /* External Interrupt 0 */
30 #define IRQ_EXT1 7 /* External Interrupt 1 */
31 #define IRQ_KEYPAD 8 /* Keypad */
32 #define IRQ_DMA 9 /* DMA Controller */
33 #define IRQ_ETHER 10 /* Ethernet MAC */
36 #define IRQ_EXT2 13 /* External Interrupt 2 */
37 #define IRQ_EXT3 14 /* External Interrupt 3 */
38 #define IRQ_EXT4 15 /* External Interrupt 4 */
39 #define IRQ_APB 16 /* APB Bridge */
40 #define IRQ_DMA0 17 /* DMA Channel 0 */
41 #define IRQ_I2C1 18 /* I2C 1 */
42 #define IRQ_I2C0 19 /* I2C 0 */
43 #define IRQ_SDMMC 20 /* SD/MMC Controller */
44 #define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */
45 #define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */
46 #define IRQ_PS2KBD 23 /* PS/2 Keyboard */
47 #define IRQ_SPI0 24 /* SPI 0 */
48 #define IRQ_SPI1 25 /* SPI 1 */
49 #define IRQ_SPI2 26 /* SPI 2 */
50 #define IRQ_DMA1 27 /* DMA Channel 1 */
51 #define IRQ_NAND 28 /* NAND Flash Controller */
52 #define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */
53 #define IRQ_UART5 30 /* UART 5 */
54 #define IRQ_UART4 31 /* UART 4 */
55 #define IRQ_UART0 32 /* UART 0 */
56 #define IRQ_UART1 33 /* UART 1 */
57 #define IRQ_DMA2 34 /* DMA Channel 2 */
58 #define IRQ_I2S 35 /* I2S */
59 #define IRQ_PMCOS0 36 /* PMC OS Timer 0 */
60 #define IRQ_PMCOS1 37 /* PMC OS Timer 1 */
61 #define IRQ_PMCOS2 38 /* PMC OS Timer 2 */
62 #define IRQ_PMCOS3 39 /* PMC OS Timer 3 */
63 #define IRQ_DMA3 40 /* DMA Channel 3 */
64 #define IRQ_DMA4 41 /* DMA Channel 4 */
65 #define IRQ_AC97 42 /* AC97 Interface */
67 #define IRQ_NOR 44 /* NOR Flash Controller */
68 #define IRQ_DMA5 45 /* DMA Channel 5 */
69 #define IRQ_DMA6 46 /* DMA Channel 6 */
70 #define IRQ_UART2 47 /* UART 2 */
71 #define IRQ_RTC 48 /* RTC Interrupt */
72 #define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */
73 #define IRQ_UART3 50 /* UART 3 */
74 #define IRQ_DMA7 51 /* DMA Channel 7 */
75 #define IRQ_EXT5 52 /* External Interrupt 5 */
76 #define IRQ_EXT6 53 /* External Interrupt 6 */
77 #define IRQ_EXT7 54 /* External Interrupt 7 */
78 #define IRQ_CIR 55 /* CIR */
79 #define IRQ_SIC0 56 /* SIC IRQ0 */
80 #define IRQ_SIC1 57 /* SIC IRQ1 */
81 #define IRQ_SIC2 58 /* SIC IRQ2 */
82 #define IRQ_SIC3 59 /* SIC IRQ3 */
83 #define IRQ_SIC4 60 /* SIC IRQ4 */
84 #define IRQ_SIC5 61 /* SIC IRQ5 */
85 #define IRQ_SIC6 62 /* SIC IRQ6 */
86 #define IRQ_SIC7 63 /* SIC IRQ7 */
88 #define IRQ_JPEGDEC 65 /* JPEG Decoder */
89 #define IRQ_SAE 66 /* SAE (?) */
91 #define IRQ_VPU 79 /* Video Processing Unit */
92 #define IRQ_VPP 80 /* Video Post-Processor */
93 #define IRQ_VID 81 /* Video Digital Input Interface */
94 #define IRQ_SPU 82 /* SPU (?) */
95 #define IRQ_PIP 83 /* PIP Error */
96 #define IRQ_GE 84 /* Graphic Engine */
97 #define IRQ_GOV 85 /* Graphic Overlay Engine */
98 #define IRQ_DVO 86 /* Digital Video Output */
100 #define IRQ_DMA8 92 /* DMA Channel 8 */
101 #define IRQ_DMA9 93 /* DMA Channel 9 */
102 #define IRQ_DMA10 94 /* DMA Channel 10 */
103 #define IRQ_DMA11 95 /* DMA Channel 11 */
104 #define IRQ_DMA12 96 /* DMA Channel 12 */
105 #define IRQ_DMA13 97 /* DMA Channel 13 */
106 #define IRQ_DMA14 98 /* DMA Channel 14 */
107 #define IRQ_DMA15 99 /* DMA Channel 15 */
109 #define IRQ_GOVW 111 /* GOVW (?) */
110 #define IRQ_GOVRSDSCD 112 /* GOVR SDSCD (?) */
111 #define IRQ_GOVRSDMIF 113 /* GOVR SDMIF (?) */
112 #define IRQ_GOVRHDSCD 114 /* GOVR HDSCD (?) */
113 #define IRQ_GOVRHDMIF 115 /* GOVR HDMIF (?) */
115 #define WM8505_NR_IRQS 116
