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nfsd4: typo logical vs bitwise negate for want_mask
[linux-btrfs-devel.git] / arch / arm / plat-omap / mcbsp.c
blob6c62af108710c89fc6f36e814bbf36beec338fb8
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25
26 #include <plat/mcbsp.h>
27 #include <plat/omap_device.h>
28 #include <linux/pm_runtime.h>
29
30 /* XXX These "sideways" includes are a sign that something is wrong */
31 #include "../mach-omap2/cm2xxx_3xxx.h"
32 #include "../mach-omap2/cm-regbits-34xx.h"
33
34 struct omap_mcbsp **mcbsp_ptr;
35 int omap_mcbsp_count, omap_mcbsp_cache_size;
36
37 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
38 {
39 if (cpu_class_is_omap1()) {
40 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
41 __raw_writew((u16)val, mcbsp->io_base + reg);
42 } else if (cpu_is_omap2420()) {
43 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
44 __raw_writew((u16)val, mcbsp->io_base + reg);
45 } else {
46 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
47 __raw_writel(val, mcbsp->io_base + reg);
48 }
49 }
50
51 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
52 {
53 if (cpu_class_is_omap1()) {
54 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
55 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
56 } else if (cpu_is_omap2420()) {
57 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
58 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
59 } else {
60 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
61 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
62 }
63 }
64
65 #ifdef CONFIG_ARCH_OMAP3
66 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
67 {
68 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
69 }
70
71 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
72 {
73 return __raw_readl(mcbsp->st_data->io_base_st + reg);
74 }
75 #endif
76
77 #define MCBSP_READ(mcbsp, reg) \
78 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
79 #define MCBSP_WRITE(mcbsp, reg, val) \
80 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
81 #define MCBSP_READ_CACHE(mcbsp, reg) \
82 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
83
84 #define MCBSP_ST_READ(mcbsp, reg) \
85 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
86 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
87 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
88
89 static void omap_mcbsp_dump_reg(u8 id)
90 {
91 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
92
93 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
94 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
95 MCBSP_READ(mcbsp, DRR2));
96 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
97 MCBSP_READ(mcbsp, DRR1));
98 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
99 MCBSP_READ(mcbsp, DXR2));
100 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
101 MCBSP_READ(mcbsp, DXR1));
102 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
103 MCBSP_READ(mcbsp, SPCR2));
104 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
105 MCBSP_READ(mcbsp, SPCR1));
106 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
107 MCBSP_READ(mcbsp, RCR2));
108 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
109 MCBSP_READ(mcbsp, RCR1));
110 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
111 MCBSP_READ(mcbsp, XCR2));
112 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
113 MCBSP_READ(mcbsp, XCR1));
114 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
115 MCBSP_READ(mcbsp, SRGR2));
116 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
117 MCBSP_READ(mcbsp, SRGR1));
118 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
119 MCBSP_READ(mcbsp, PCR0));
120 dev_dbg(mcbsp->dev, "***********************\n");
121 }
122
123 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
124 {
125 struct omap_mcbsp *mcbsp_tx = dev_id;
126 u16 irqst_spcr2;
127
128 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
129 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
130
131 if (irqst_spcr2 & XSYNC_ERR) {
132 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
133 irqst_spcr2);
134 /* Writing zero to XSYNC_ERR clears the IRQ */
135 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
136 }
137
138 return IRQ_HANDLED;
139 }
140
141 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
142 {
143 struct omap_mcbsp *mcbsp_rx = dev_id;
144 u16 irqst_spcr1;
145
146 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
147 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
148
149 if (irqst_spcr1 & RSYNC_ERR) {
150 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
151 irqst_spcr1);
152 /* Writing zero to RSYNC_ERR clears the IRQ */
153 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
154 }
155
156 return IRQ_HANDLED;
157 }
158
159 /*
160 * omap_mcbsp_config simply write a config to the
161 * appropriate McBSP.
162 * You either call this function or set the McBSP registers
163 * by yourself before calling omap_mcbsp_start().
164 */
165 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
166 {
167 struct omap_mcbsp *mcbsp;
168
169 if (!omap_mcbsp_check_valid_id(id)) {
170 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
171 return;
172 }
173 mcbsp = id_to_mcbsp_ptr(id);
174
175 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
176 mcbsp->id, mcbsp->phys_base);
177
178 /* We write the given config */
179 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
180 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
181 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
182 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
183 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
184 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
185 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
186 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
187 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
188 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
189 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
190 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
191 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
192 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
193 }
194 }
195 EXPORT_SYMBOL(omap_mcbsp_config);
196
197 /**
198 * omap_mcbsp_dma_params - returns the dma channel number
199 * @id - mcbsp id
200 * @stream - indicates the direction of data flow (rx or tx)
201 *
202 * Returns the dma channel number for the rx channel or tx channel
203 * based on the value of @stream for the requested mcbsp given by @id
204 */
205 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
206 {
207 struct omap_mcbsp *mcbsp;
208
209 if (!omap_mcbsp_check_valid_id(id)) {
210 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
211 return -ENODEV;
212 }
213 mcbsp = id_to_mcbsp_ptr(id);
214
215 if (stream)
216 return mcbsp->dma_rx_sync;
217 else
218 return mcbsp->dma_tx_sync;
219 }
220 EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
221
222 /**
223 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
224 * @id - mcbsp id
225 * @stream - indicates the direction of data flow (rx or tx)
226 *
227 * Returns the address of mcbsp data transmit register or data receive register
228 * to be used by DMA for transferring/receiving data based on the value of
229 * @stream for the requested mcbsp given by @id
230 */
231 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
232 {
233 struct omap_mcbsp *mcbsp;
234 int data_reg;
235
236 if (!omap_mcbsp_check_valid_id(id)) {
237 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
238 return -ENODEV;
239 }
240 mcbsp = id_to_mcbsp_ptr(id);
241
242 data_reg = mcbsp->phys_dma_base;
243
244 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
245 if (stream)
246 data_reg += OMAP_MCBSP_REG_DRR1;
247 else
248 data_reg += OMAP_MCBSP_REG_DXR1;
249 } else {
250 if (stream)
251 data_reg += OMAP_MCBSP_REG_DRR;
252 else
253 data_reg += OMAP_MCBSP_REG_DXR;
254 }
255
256 return data_reg;
257 }
258 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
259
260 #ifdef CONFIG_ARCH_OMAP3
261 static struct omap_device *find_omap_device_by_dev(struct device *dev)
262 {
263 struct platform_device *pdev = container_of(dev,
264 struct platform_device, dev);
265 return container_of(pdev, struct omap_device, pdev);
266 }
267
268 static void omap_st_on(struct omap_mcbsp *mcbsp)
269 {
270 unsigned int w;
271 struct omap_device *od;
272
273 od = find_omap_device_by_dev(mcbsp->dev);
274
275 /*
276 * Sidetone uses McBSP ICLK - which must not idle when sidetones
277 * are enabled or sidetones start sounding ugly.
278 */
279 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
280 w &= ~(1 << (mcbsp->id - 2));
281 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
282
283 /* Enable McBSP Sidetone */
284 w = MCBSP_READ(mcbsp, SSELCR);
285 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
286
287 /* Enable Sidetone from Sidetone Core */
288 w = MCBSP_ST_READ(mcbsp, SSELCR);
289 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
290 }
291
292 static void omap_st_off(struct omap_mcbsp *mcbsp)
293 {
294 unsigned int w;
295 struct omap_device *od;
296
297 od = find_omap_device_by_dev(mcbsp->dev);
298
299 w = MCBSP_ST_READ(mcbsp, SSELCR);
300 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
301
302 w = MCBSP_READ(mcbsp, SSELCR);
303 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
304
305 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
306 w |= 1 << (mcbsp->id - 2);
307 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
308 }
309
310 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
311 {
312 u16 val, i;
313 struct omap_device *od;
314
315 od = find_omap_device_by_dev(mcbsp->dev);
316
317 val = MCBSP_ST_READ(mcbsp, SSELCR);
318
319 if (val & ST_COEFFWREN)
320 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
321
322 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
323
324 for (i = 0; i < 128; i++)
325 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
326
327 i = 0;
328
329 val = MCBSP_ST_READ(mcbsp, SSELCR);
330 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
331 val = MCBSP_ST_READ(mcbsp, SSELCR);
332
333 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
334
335 if (i == 1000)
336 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
337 }
338
339 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
340 {
341 u16 w;
342 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
343 struct omap_device *od;
344
345 od = find_omap_device_by_dev(mcbsp->dev);
346
347 w = MCBSP_ST_READ(mcbsp, SSELCR);
348
349 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
350 ST_CH1GAIN(st_data->ch1gain));
351 }
352
353 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
354 {
355 struct omap_mcbsp *mcbsp;
356 struct omap_mcbsp_st_data *st_data;
357 int ret = 0;
358
359 if (!omap_mcbsp_check_valid_id(id)) {
360 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
361 return -ENODEV;
362 }
363
364 mcbsp = id_to_mcbsp_ptr(id);
365 st_data = mcbsp->st_data;
366
367 if (!st_data)
368 return -ENOENT;
369
370 spin_lock_irq(&mcbsp->lock);
371 if (channel == 0)
372 st_data->ch0gain = chgain;
373 else if (channel == 1)
374 st_data->ch1gain = chgain;
375 else
376 ret = -EINVAL;
377
378 if (st_data->enabled)
379 omap_st_chgain(mcbsp);
380 spin_unlock_irq(&mcbsp->lock);
381
382 return ret;
383 }
384 EXPORT_SYMBOL(omap_st_set_chgain);
385
386 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
387 {
388 struct omap_mcbsp *mcbsp;
389 struct omap_mcbsp_st_data *st_data;
390 int ret = 0;
391
392 if (!omap_mcbsp_check_valid_id(id)) {
393 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
394 return -ENODEV;
395 }
396
397 mcbsp = id_to_mcbsp_ptr(id);
398 st_data = mcbsp->st_data;
399
400 if (!st_data)
401 return -ENOENT;
402
403 spin_lock_irq(&mcbsp->lock);
404 if (channel == 0)
405 *chgain = st_data->ch0gain;
406 else if (channel == 1)
407 *chgain = st_data->ch1gain;
408 else
409 ret = -EINVAL;
410 spin_unlock_irq(&mcbsp->lock);
411
412 return ret;
413 }
414 EXPORT_SYMBOL(omap_st_get_chgain);
415
416 static int omap_st_start(struct omap_mcbsp *mcbsp)
417 {
418 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
419
420 if (st_data && st_data->enabled && !st_data->running) {
421 omap_st_fir_write(mcbsp, st_data->taps);
422 omap_st_chgain(mcbsp);
423
424 if (!mcbsp->free) {
425 omap_st_on(mcbsp);
426 st_data->running = 1;
427 }
428 }
429
430 return 0;
431 }
432
433 int omap_st_enable(unsigned int id)
434 {
435 struct omap_mcbsp *mcbsp;
436 struct omap_mcbsp_st_data *st_data;
437
438 if (!omap_mcbsp_check_valid_id(id)) {
439 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
440 return -ENODEV;
441 }
442
443 mcbsp = id_to_mcbsp_ptr(id);
444 st_data = mcbsp->st_data;
445
446 if (!st_data)
447 return -ENODEV;
448
449 spin_lock_irq(&mcbsp->lock);
450 st_data->enabled = 1;
451 omap_st_start(mcbsp);
452 spin_unlock_irq(&mcbsp->lock);
453
454 return 0;
455 }
456 EXPORT_SYMBOL(omap_st_enable);
457
458 static int omap_st_stop(struct omap_mcbsp *mcbsp)
459 {
460 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
461
462 if (st_data && st_data->running) {
463 if (!mcbsp->free) {
464 omap_st_off(mcbsp);
465 st_data->running = 0;
466 }
467 }
468
469 return 0;
470 }
471
472 int omap_st_disable(unsigned int id)
473 {
474 struct omap_mcbsp *mcbsp;
475 struct omap_mcbsp_st_data *st_data;
476 int ret = 0;
477
478 if (!omap_mcbsp_check_valid_id(id)) {
479 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
480 return -ENODEV;
481 }
482
483 mcbsp = id_to_mcbsp_ptr(id);
484 st_data = mcbsp->st_data;
485
486 if (!st_data)
487 return -ENODEV;
488
489 spin_lock_irq(&mcbsp->lock);
490 omap_st_stop(mcbsp);
491 st_data->enabled = 0;
492 spin_unlock_irq(&mcbsp->lock);
493
494 return ret;
495 }
496 EXPORT_SYMBOL(omap_st_disable);
497
498 int omap_st_is_enabled(unsigned int id)
499 {
500 struct omap_mcbsp *mcbsp;
501 struct omap_mcbsp_st_data *st_data;
502
503 if (!omap_mcbsp_check_valid_id(id)) {
504 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
505 return -ENODEV;
506 }
507
508 mcbsp = id_to_mcbsp_ptr(id);
509 st_data = mcbsp->st_data;
510
511 if (!st_data)
512 return -ENODEV;
513
514
515 return st_data->enabled;
516 }
517 EXPORT_SYMBOL(omap_st_is_enabled);
518
519 /*
520 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
521 * The threshold parameter is 1 based, and it is converted (threshold - 1)
522 * for the THRSH2 register.
523 */
524 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
525 {
526 struct omap_mcbsp *mcbsp;
527
528 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
529 return;
530
531 if (!omap_mcbsp_check_valid_id(id)) {
532 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
533 return;
534 }
535 mcbsp = id_to_mcbsp_ptr(id);
536
537 if (threshold && threshold <= mcbsp->max_tx_thres)
538 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
539 }
540 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
541
542 /*
543 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
544 * The threshold parameter is 1 based, and it is converted (threshold - 1)
545 * for the THRSH1 register.
546 */
547 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
548 {
549 struct omap_mcbsp *mcbsp;
550
551 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
552 return;
553
554 if (!omap_mcbsp_check_valid_id(id)) {
555 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
556 return;
557 }
558 mcbsp = id_to_mcbsp_ptr(id);
559
560 if (threshold && threshold <= mcbsp->max_rx_thres)
561 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
562 }
563 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
564
565 /*
566 * omap_mcbsp_get_max_tx_thres just return the current configured
567 * maximum threshold for transmission
568 */
569 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
570 {
571 struct omap_mcbsp *mcbsp;
572
573 if (!omap_mcbsp_check_valid_id(id)) {
574 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
575 return -ENODEV;
576 }
577 mcbsp = id_to_mcbsp_ptr(id);
578
579 return mcbsp->max_tx_thres;
580 }
581 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
582
583 /*
584 * omap_mcbsp_get_max_rx_thres just return the current configured
585 * maximum threshold for reception
586 */
587 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
588 {
589 struct omap_mcbsp *mcbsp;
590
591 if (!omap_mcbsp_check_valid_id(id)) {
592 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
593 return -ENODEV;
594 }
595 mcbsp = id_to_mcbsp_ptr(id);
596
597 return mcbsp->max_rx_thres;
598 }
599 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
600
601 u16 omap_mcbsp_get_fifo_size(unsigned int id)
602 {
603 struct omap_mcbsp *mcbsp;
604
605 if (!omap_mcbsp_check_valid_id(id)) {
606 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
607 return -ENODEV;
608 }
609 mcbsp = id_to_mcbsp_ptr(id);
610
611 return mcbsp->pdata->buffer_size;
612 }
613 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
614
615 /*
616 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
617 */
618 u16 omap_mcbsp_get_tx_delay(unsigned int id)
619 {
620 struct omap_mcbsp *mcbsp;
621 u16 buffstat;
622
623 if (!omap_mcbsp_check_valid_id(id)) {
624 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
625 return -ENODEV;
626 }
627 mcbsp = id_to_mcbsp_ptr(id);
628
629 /* Returns the number of free locations in the buffer */
630 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
631
632 /* Number of slots are different in McBSP ports */
633 return mcbsp->pdata->buffer_size - buffstat;
634 }
635 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
636
637 /*
638 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
639 * to reach the threshold value (when the DMA will be triggered to read it)
640 */
641 u16 omap_mcbsp_get_rx_delay(unsigned int id)
642 {
643 struct omap_mcbsp *mcbsp;
644 u16 buffstat, threshold;
645
646 if (!omap_mcbsp_check_valid_id(id)) {
647 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
648 return -ENODEV;
649 }
650 mcbsp = id_to_mcbsp_ptr(id);
651
652 /* Returns the number of used locations in the buffer */
653 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
654 /* RX threshold */
655 threshold = MCBSP_READ(mcbsp, THRSH1);
656
657 /* Return the number of location till we reach the threshold limit */
658 if (threshold <= buffstat)
659 return 0;
660 else
661 return threshold - buffstat;
662 }
663 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
664
665 /*
666 * omap_mcbsp_get_dma_op_mode just return the current configured
667 * operating mode for the mcbsp channel
668 */
669 int omap_mcbsp_get_dma_op_mode(unsigned int id)
670 {
671 struct omap_mcbsp *mcbsp;
672 int dma_op_mode;
673
674 if (!omap_mcbsp_check_valid_id(id)) {
675 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
676 return -ENODEV;
677 }
678 mcbsp = id_to_mcbsp_ptr(id);
679
680 dma_op_mode = mcbsp->dma_op_mode;
681
682 return dma_op_mode;
683 }
684 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
685
686 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
687 {
688 struct omap_device *od;
689
690 od = find_omap_device_by_dev(mcbsp->dev);
691 /*
692 * Enable wakup behavior, smart idle and all wakeups
693 * REVISIT: some wakeups may be unnecessary
694 */
695 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
696 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
697 }
698 }
699
700 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
701 {
702 struct omap_device *od;
703
704 od = find_omap_device_by_dev(mcbsp->dev);
705
706 /*
707 * Disable wakup behavior, smart idle and all wakeups
708 */
709 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
710 /*
711 * HW bug workaround - If no_idle mode is taken, we need to
712 * go to smart_idle before going to always_idle, or the
713 * device will not hit retention anymore.
714 */
715
716 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
717 }
718 }
719 #else
720 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
721 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
722 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
723 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
724 #endif
725
726 int omap_mcbsp_request(unsigned int id)
727 {
728 struct omap_mcbsp *mcbsp;
729 void *reg_cache;
730 int err;
731
732 if (!omap_mcbsp_check_valid_id(id)) {
733 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
734 return -ENODEV;
735 }
736 mcbsp = id_to_mcbsp_ptr(id);
737
738 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
739 if (!reg_cache) {
740 return -ENOMEM;
741 }
742
743 spin_lock(&mcbsp->lock);
744 if (!mcbsp->free) {
745 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
746 mcbsp->id);
747 err = -EBUSY;
748 goto err_kfree;
749 }
750
751 mcbsp->free = false;
752 mcbsp->reg_cache = reg_cache;
753 spin_unlock(&mcbsp->lock);
754
755 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
756 mcbsp->pdata->ops->request(id);
757
758 pm_runtime_get_sync(mcbsp->dev);
759
760 /* Do procedure specific to omap34xx arch, if applicable */
761 omap34xx_mcbsp_request(mcbsp);
762
763 /*
764 * Make sure that transmitter, receiver and sample-rate generator are
765 * not running before activating IRQs.
766 */
767 MCBSP_WRITE(mcbsp, SPCR1, 0);
768 MCBSP_WRITE(mcbsp, SPCR2, 0);
769
770 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
771 0, "McBSP", (void *)mcbsp);
772 if (err != 0) {
773 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
774 "for McBSP%d\n", mcbsp->tx_irq,
775 mcbsp->id);
776 goto err_clk_disable;
777 }
778
779 if (mcbsp->rx_irq) {
780 err = request_irq(mcbsp->rx_irq,
781 omap_mcbsp_rx_irq_handler,
782 0, "McBSP", (void *)mcbsp);
783 if (err != 0) {
784 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
785 "for McBSP%d\n", mcbsp->rx_irq,
786 mcbsp->id);
787 goto err_free_irq;
788 }
789 }
790
791 return 0;
792 err_free_irq:
793 free_irq(mcbsp->tx_irq, (void *)mcbsp);
794 err_clk_disable:
795 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
796 mcbsp->pdata->ops->free(id);
797
798 /* Do procedure specific to omap34xx arch, if applicable */
799 omap34xx_mcbsp_free(mcbsp);
800
801 pm_runtime_put_sync(mcbsp->dev);
802
803 spin_lock(&mcbsp->lock);
804 mcbsp->free = true;
805 mcbsp->reg_cache = NULL;
806 err_kfree:
807 spin_unlock(&mcbsp->lock);
808 kfree(reg_cache);
809
810 return err;
811 }
812 EXPORT_SYMBOL(omap_mcbsp_request);
813
814 void omap_mcbsp_free(unsigned int id)
815 {
816 struct omap_mcbsp *mcbsp;
817 void *reg_cache;
818
819 if (!omap_mcbsp_check_valid_id(id)) {
820 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
821 return;
822 }
823 mcbsp = id_to_mcbsp_ptr(id);
824
825 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
826 mcbsp->pdata->ops->free(id);
827
828 /* Do procedure specific to omap34xx arch, if applicable */
829 omap34xx_mcbsp_free(mcbsp);
830
831 pm_runtime_put_sync(mcbsp->dev);
832
833 if (mcbsp->rx_irq)
834 free_irq(mcbsp->rx_irq, (void *)mcbsp);
835 free_irq(mcbsp->tx_irq, (void *)mcbsp);
836
837 reg_cache = mcbsp->reg_cache;
838
839 spin_lock(&mcbsp->lock);
840 if (mcbsp->free)
841 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
842 else
843 mcbsp->free = true;
844 mcbsp->reg_cache = NULL;
845 spin_unlock(&mcbsp->lock);
846
847 if (reg_cache)
848 kfree(reg_cache);
849 }
850 EXPORT_SYMBOL(omap_mcbsp_free);
851
852 /*
853 * Here we start the McBSP, by enabling transmitter, receiver or both.
854 * If no transmitter or receiver is active prior calling, then sample-rate
855 * generator and frame sync are started.
856 */
857 void omap_mcbsp_start(unsigned int id, int tx, int rx)
858 {
859 struct omap_mcbsp *mcbsp;
860 int enable_srg = 0;
861 u16 w;
862
863 if (!omap_mcbsp_check_valid_id(id)) {
864 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
865 return;
866 }
867 mcbsp = id_to_mcbsp_ptr(id);
868
869 if (cpu_is_omap34xx())
870 omap_st_start(mcbsp);
871
872 /* Only enable SRG, if McBSP is master */
873 w = MCBSP_READ_CACHE(mcbsp, PCR0);
874 if (w & (FSXM | FSRM | CLKXM | CLKRM))
875 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
876 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
877
878 if (enable_srg) {
879 /* Start the sample generator */
880 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
881 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
882 }
883
884 /* Enable transmitter and receiver */
885 tx &= 1;
886 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
887 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
888
889 rx &= 1;
890 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
891 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
892
893 /*
894 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
895 * REVISIT: 100us may give enough time for two CLKSRG, however
896 * due to some unknown PM related, clock gating etc. reason it
897 * is now at 500us.
898 */
899 udelay(500);
900
901 if (enable_srg) {
902 /* Start frame sync */
903 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
904 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
905 }
906
907 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
908 /* Release the transmitter and receiver */
909 w = MCBSP_READ_CACHE(mcbsp, XCCR);
910 w &= ~(tx ? XDISABLE : 0);
911 MCBSP_WRITE(mcbsp, XCCR, w);
912 w = MCBSP_READ_CACHE(mcbsp, RCCR);
913 w &= ~(rx ? RDISABLE : 0);
914 MCBSP_WRITE(mcbsp, RCCR, w);
915 }
916
917 /* Dump McBSP Regs */
918 omap_mcbsp_dump_reg(id);
919 }
920 EXPORT_SYMBOL(omap_mcbsp_start);
921
922 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
923 {
924 struct omap_mcbsp *mcbsp;
925 int idle;
926 u16 w;
927
928 if (!omap_mcbsp_check_valid_id(id)) {
929 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
930 return;
931 }
932
933 mcbsp = id_to_mcbsp_ptr(id);
934
935 /* Reset transmitter */
936 tx &= 1;
937 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
938 w = MCBSP_READ_CACHE(mcbsp, XCCR);
939 w |= (tx ? XDISABLE : 0);
940 MCBSP_WRITE(mcbsp, XCCR, w);
941 }
942 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
943 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
944
945 /* Reset receiver */
946 rx &= 1;
947 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
948 w = MCBSP_READ_CACHE(mcbsp, RCCR);
949 w |= (rx ? RDISABLE : 0);
950 MCBSP_WRITE(mcbsp, RCCR, w);
951 }
952 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
953 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
954
955 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
956 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
957
958 if (idle) {
959 /* Reset the sample rate generator */
960 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
961 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
962 }
963
964 if (cpu_is_omap34xx())
965 omap_st_stop(mcbsp);
966 }
967 EXPORT_SYMBOL(omap_mcbsp_stop);
968
969 /*
970 * The following functions are only required on an OMAP1-only build.
971 * mach-omap2/mcbsp.c contains the real functions
972 */
973 #ifndef CONFIG_ARCH_OMAP2PLUS
974 int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
975 {
976 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
977 __func__);
978 return -EINVAL;
979 }
980
981 void omap2_mcbsp1_mux_clkr_src(u8 mux)
982 {
983 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
984 __func__);
985 return;
986 }
987
988 void omap2_mcbsp1_mux_fsr_src(u8 mux)
989 {
990 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
991 __func__);
992 return;
993 }
994 #endif
995
996 #ifdef CONFIG_ARCH_OMAP3
997 #define max_thres(m) (mcbsp->pdata->buffer_size)
998 #define valid_threshold(m, val) ((val) <= max_thres(m))
999 #define THRESHOLD_PROP_BUILDER(prop) \
1000 static ssize_t prop##_show(struct device *dev, \
1001 struct device_attribute *attr, char *buf) \
1002 { \
1003 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1004 \
1005 return sprintf(buf, "%u\n", mcbsp->prop); \
1006 } \
1007 \
1008 static ssize_t prop##_store(struct device *dev, \
1009 struct device_attribute *attr, \
1010 const char *buf, size_t size) \
1011 { \
1012 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1013 unsigned long val; \
1014 int status; \
1015 \
1016 status = strict_strtoul(buf, 0, &val); \
1017 if (status) \
1018 return status; \
1019 \
1020 if (!valid_threshold(mcbsp, val)) \
1021 return -EDOM; \
1022 \
1023 mcbsp->prop = val; \
1024 return size; \
1025 } \
1026 \
1027 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1028
1029 THRESHOLD_PROP_BUILDER(max_tx_thres);
1030 THRESHOLD_PROP_BUILDER(max_rx_thres);
1031
1032 static const char *dma_op_modes[] = {
1033 "element", "threshold", "frame",
1034 };
1035
1036 static ssize_t dma_op_mode_show(struct device *dev,
1037 struct device_attribute *attr, char *buf)
1038 {
1039 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1040 int dma_op_mode, i = 0;
1041 ssize_t len = 0;
1042 const char * const *s;
1043
1044 dma_op_mode = mcbsp->dma_op_mode;
1045
1046 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1047 if (dma_op_mode == i)
1048 len += sprintf(buf + len, "[%s] ", *s);
1049 else
1050 len += sprintf(buf + len, "%s ", *s);
1051 }
1052 len += sprintf(buf + len, "\n");
1053
1054 return len;
1055 }
1056
1057 static ssize_t dma_op_mode_store(struct device *dev,
1058 struct device_attribute *attr,
1059 const char *buf, size_t size)
1060 {
1061 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1062 const char * const *s;
1063 int i = 0;
1064
1065 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1066 if (sysfs_streq(buf, *s))
1067 break;
1068
1069 if (i == ARRAY_SIZE(dma_op_modes))
1070 return -EINVAL;
1071
1072 spin_lock_irq(&mcbsp->lock);
1073 if (!mcbsp->free) {
1074 size = -EBUSY;
1075 goto unlock;
1076 }
1077 mcbsp->dma_op_mode = i;
1078
1079 unlock:
1080 spin_unlock_irq(&mcbsp->lock);
1081
1082 return size;
1083 }
1084
1085 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1086
1087 static ssize_t st_taps_show(struct device *dev,
1088 struct device_attribute *attr, char *buf)
1089 {
1090 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1091 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1092 ssize_t status = 0;
1093 int i;
1094
1095 spin_lock_irq(&mcbsp->lock);
1096 for (i = 0; i < st_data->nr_taps; i++)
1097 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1098 st_data->taps[i]);
1099 if (i)
1100 status += sprintf(&buf[status], "\n");
1101 spin_unlock_irq(&mcbsp->lock);
1102
1103 return status;
1104 }
1105
1106 static ssize_t st_taps_store(struct device *dev,
1107 struct device_attribute *attr,
1108 const char *buf, size_t size)
1109 {
1110 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1111 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1112 int val, tmp, status, i = 0;
1113
1114 spin_lock_irq(&mcbsp->lock);
1115 memset(st_data->taps, 0, sizeof(st_data->taps));
1116 st_data->nr_taps = 0;
1117
1118 do {
1119 status = sscanf(buf, "%d%n", &val, &tmp);
1120 if (status < 0 || status == 0) {
1121 size = -EINVAL;
1122 goto out;
1123 }
1124 if (val < -32768 || val > 32767) {
1125 size = -EINVAL;
1126 goto out;
1127 }
1128 st_data->taps[i++] = val;
1129 buf += tmp;
1130 if (*buf != ',')
1131 break;
1132 buf++;
1133 } while (1);
1134
1135 st_data->nr_taps = i;
1136
1137 out:
1138 spin_unlock_irq(&mcbsp->lock);
1139
1140 return size;
1141 }
1142
1143 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1144
1145 static const struct attribute *additional_attrs[] = {
1146 &dev_attr_max_tx_thres.attr,
1147 &dev_attr_max_rx_thres.attr,
1148 &dev_attr_dma_op_mode.attr,
1149 NULL,
1150 };
1151
1152 static const struct attribute_group additional_attr_group = {
1153 .attrs = (struct attribute **)additional_attrs,
1154 };
1155
1156 static inline int __devinit omap_additional_add(struct device *dev)
1157 {
1158 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1159 }
1160
1161 static inline void __devexit omap_additional_remove(struct device *dev)
1162 {
1163 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1164 }
1165
1166 static const struct attribute *sidetone_attrs[] = {
1167 &dev_attr_st_taps.attr,
1168 NULL,
1169 };
1170
1171 static const struct attribute_group sidetone_attr_group = {
1172 .attrs = (struct attribute **)sidetone_attrs,
1173 };
1174
1175 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1176 {
1177 struct platform_device *pdev;
1178 struct resource *res;
1179 struct omap_mcbsp_st_data *st_data;
1180 int err;
1181
1182 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1183 if (!st_data) {
1184 err = -ENOMEM;
1185 goto err1;
1186 }
1187
1188 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1189
1190 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1191 st_data->io_base_st = ioremap(res->start, resource_size(res));
1192 if (!st_data->io_base_st) {
1193 err = -ENOMEM;
1194 goto err2;
1195 }
1196
1197 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1198 if (err)
1199 goto err3;
1200
1201 mcbsp->st_data = st_data;
1202 return 0;
1203
1204 err3:
1205 iounmap(st_data->io_base_st);
1206 err2:
1207 kfree(st_data);
1208 err1:
1209 return err;
1210
1211 }
1212
1213 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1214 {
1215 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1216
1217 if (st_data) {
1218 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1219 iounmap(st_data->io_base_st);
1220 kfree(st_data);
1221 }
1222 }
1223
1224 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1225 {
1226 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1227 if (cpu_is_omap34xx()) {
1228 /*
1229 * Initially configure the maximum thresholds to a safe value.
1230 * The McBSP FIFO usage with these values should not go under
1231 * 16 locations.
1232 * If the whole FIFO without safety buffer is used, than there
1233 * is a possibility that the DMA will be not able to push the
1234 * new data on time, causing channel shifts in runtime.
1235 */
1236 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1237 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1238 /*
1239 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1240 * for mcbsp2 instances.
1241 */
1242 if (omap_additional_add(mcbsp->dev))
1243 dev_warn(mcbsp->dev,
1244 "Unable to create additional controls\n");
1245
1246 if (mcbsp->id == 2 || mcbsp->id == 3)
1247 if (omap_st_add(mcbsp))
1248 dev_warn(mcbsp->dev,
1249 "Unable to create sidetone controls\n");
1250
1251 } else {
1252 mcbsp->max_tx_thres = -EINVAL;
1253 mcbsp->max_rx_thres = -EINVAL;
1254 }
1255 }
1256
1257 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1258 {
1259 if (cpu_is_omap34xx()) {
1260 omap_additional_remove(mcbsp->dev);
1261
1262 if (mcbsp->id == 2 || mcbsp->id == 3)
1263 omap_st_remove(mcbsp);
1264 }
1265 }
1266 #else
1267 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1268 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1269 #endif /* CONFIG_ARCH_OMAP3 */
1270
1271 /*
1272 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1273 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1274 */
1275 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1276 {
1277 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1278 struct omap_mcbsp *mcbsp;
1279 int id = pdev->id - 1;
1280 struct resource *res;
1281 int ret = 0;
1282
1283 if (!pdata) {
1284 dev_err(&pdev->dev, "McBSP device initialized without"
1285 "platform data\n");
1286 ret = -EINVAL;
1287 goto exit;
1288 }
1289
1290 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1291
1292 if (id >= omap_mcbsp_count) {
1293 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1294 ret = -EINVAL;
1295 goto exit;
1296 }
1297
1298 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1299 if (!mcbsp) {
1300 ret = -ENOMEM;
1301 goto exit;
1302 }
1303
1304 spin_lock_init(&mcbsp->lock);
1305 mcbsp->id = id + 1;
1306 mcbsp->free = true;
1307
1308 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1309 if (!res) {
1310 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1311 if (!res) {
1312 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1313 "resource\n", __func__, pdev->id);
1314 ret = -ENOMEM;
1315 goto exit;
1316 }
1317 }
1318 mcbsp->phys_base = res->start;
1319 omap_mcbsp_cache_size = resource_size(res);
1320 mcbsp->io_base = ioremap(res->start, resource_size(res));
1321 if (!mcbsp->io_base) {
1322 ret = -ENOMEM;
1323 goto err_ioremap;
1324 }
1325
1326 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1327 if (!res)
1328 mcbsp->phys_dma_base = mcbsp->phys_base;
1329 else
1330 mcbsp->phys_dma_base = res->start;
1331
1332 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1333 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1334
1335 /* From OMAP4 there will be a single irq line */
1336 if (mcbsp->tx_irq == -ENXIO)
1337 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1338
1339 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1340 if (!res) {
1341 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1342 __func__, pdev->id);
1343 ret = -ENODEV;
1344 goto err_res;
1345 }
1346 mcbsp->dma_rx_sync = res->start;
1347
1348 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1349 if (!res) {
1350 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1351 __func__, pdev->id);
1352 ret = -ENODEV;
1353 goto err_res;
1354 }
1355 mcbsp->dma_tx_sync = res->start;
1356
1357 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1358 if (IS_ERR(mcbsp->fclk)) {
1359 ret = PTR_ERR(mcbsp->fclk);
1360 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1361 goto err_res;
1362 }
1363
1364 mcbsp->pdata = pdata;
1365 mcbsp->dev = &pdev->dev;
1366 mcbsp_ptr[id] = mcbsp;
1367 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1368 platform_set_drvdata(pdev, mcbsp);
1369 pm_runtime_enable(mcbsp->dev);
1370
1371 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1372 omap34xx_device_init(mcbsp);
1373
1374 return 0;
1375
1376 err_res:
1377 iounmap(mcbsp->io_base);
1378 err_ioremap:
1379 kfree(mcbsp);
1380 exit:
1381 return ret;
1382 }
1383
1384 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1385 {
1386 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1387
1388 platform_set_drvdata(pdev, NULL);
1389 if (mcbsp) {
1390
1391 if (mcbsp->pdata && mcbsp->pdata->ops &&
1392 mcbsp->pdata->ops->free)
1393 mcbsp->pdata->ops->free(mcbsp->id);
1394
1395 omap34xx_device_exit(mcbsp);
1396
1397 clk_put(mcbsp->fclk);
1398
1399 iounmap(mcbsp->io_base);
1400 kfree(mcbsp);
1401 }
1402
1403 return 0;
1404 }
1405
1406 static struct platform_driver omap_mcbsp_driver = {
1407 .probe = omap_mcbsp_probe,
1408 .remove = __devexit_p(omap_mcbsp_remove),
1409 .driver = {
1410 .name = "omap-mcbsp",
1411 },
1412 };
1413
1414 int __init omap_mcbsp_init(void)
1415 {
1416 /* Register the McBSP driver */
1417 return platform_driver_register(&omap_mcbsp_driver);
1418 }
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