?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
nfsd4: typo logical vs bitwise negate for want_mask
[linux-btrfs-devel.git] / arch / mips / kernel / traps.c
blobb7517e3abc8527721fdffca5ded64a035d33fddb
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/kprobes.h>
29 #include <linux/notifier.h>
30 #include <linux/kdb.h>
31 #include <linux/irq.h>
32 #include <linux/perf_event.h>
33
34 #include <asm/bootinfo.h>
35 #include <asm/branch.h>
36 #include <asm/break.h>
37 #include <asm/cop2.h>
38 #include <asm/cpu.h>
39 #include <asm/dsp.h>
40 #include <asm/fpu.h>
41 #include <asm/fpu_emulator.h>
42 #include <asm/mipsregs.h>
43 #include <asm/mipsmtregs.h>
44 #include <asm/module.h>
45 #include <asm/pgtable.h>
46 #include <asm/ptrace.h>
47 #include <asm/sections.h>
48 #include <asm/system.h>
49 #include <asm/tlbdebug.h>
50 #include <asm/traps.h>
51 #include <asm/uaccess.h>
52 #include <asm/watch.h>
53 #include <asm/mmu_context.h>
54 #include <asm/types.h>
55 #include <asm/stacktrace.h>
56 #include <asm/uasm.h>
57
58 extern void check_wait(void);
59 extern asmlinkage void r4k_wait(void);
60 extern asmlinkage void rollback_handle_int(void);
61 extern asmlinkage void handle_int(void);
62 extern asmlinkage void handle_tlbm(void);
63 extern asmlinkage void handle_tlbl(void);
64 extern asmlinkage void handle_tlbs(void);
65 extern asmlinkage void handle_adel(void);
66 extern asmlinkage void handle_ades(void);
67 extern asmlinkage void handle_ibe(void);
68 extern asmlinkage void handle_dbe(void);
69 extern asmlinkage void handle_sys(void);
70 extern asmlinkage void handle_bp(void);
71 extern asmlinkage void handle_ri(void);
72 extern asmlinkage void handle_ri_rdhwr_vivt(void);
73 extern asmlinkage void handle_ri_rdhwr(void);
74 extern asmlinkage void handle_cpu(void);
75 extern asmlinkage void handle_ov(void);
76 extern asmlinkage void handle_tr(void);
77 extern asmlinkage void handle_fpe(void);
78 extern asmlinkage void handle_mdmx(void);
79 extern asmlinkage void handle_watch(void);
80 extern asmlinkage void handle_mt(void);
81 extern asmlinkage void handle_dsp(void);
82 extern asmlinkage void handle_mcheck(void);
83 extern asmlinkage void handle_reserved(void);
84
85 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
86 struct mips_fpu_struct *ctx, int has_fpu,
87 void *__user *fault_addr);
88
89 void (*board_be_init)(void);
90 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
91 void (*board_nmi_handler_setup)(void);
92 void (*board_ejtag_handler_setup)(void);
93 void (*board_bind_eic_interrupt)(int irq, int regset);
94
95
96 static void show_raw_backtrace(unsigned long reg29)
97 {
98 unsigned long *sp = (unsigned long *)(reg29 & ~3);
99 unsigned long addr;
100
101 printk("Call Trace:");
102 #ifdef CONFIG_KALLSYMS
103 printk("\n");
104 #endif
105 while (!kstack_end(sp)) {
106 unsigned long __user *p =
107 (unsigned long __user *)(unsigned long)sp++;
108 if (__get_user(addr, p)) {
109 printk(" (Bad stack address)");
110 break;
111 }
112 if (__kernel_text_address(addr))
113 print_ip_sym(addr);
114 }
115 printk("\n");
116 }
117
118 #ifdef CONFIG_KALLSYMS
119 int raw_show_trace;
120 static int __init set_raw_show_trace(char *str)
121 {
122 raw_show_trace = 1;
123 return 1;
124 }
125 __setup("raw_show_trace", set_raw_show_trace);
126 #endif
127
128 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
129 {
130 unsigned long sp = regs->regs[29];
131 unsigned long ra = regs->regs[31];
132 unsigned long pc = regs->cp0_epc;
133
134 if (raw_show_trace || !__kernel_text_address(pc)) {
135 show_raw_backtrace(sp);
136 return;
137 }
138 printk("Call Trace:\n");
139 do {
140 print_ip_sym(pc);
141 pc = unwind_stack(task, &sp, pc, &ra);
142 } while (pc);
143 printk("\n");
144 }
145
146 /*
147 * This routine abuses get_user()/put_user() to reference pointers
148 * with at least a bit of error checking ...
149 */
150 static void show_stacktrace(struct task_struct *task,
151 const struct pt_regs *regs)
152 {
153 const int field = 2 * sizeof(unsigned long);
154 long stackdata;
155 int i;
156 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
157
158 printk("Stack :");
159 i = 0;
160 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
161 if (i && ((i % (64 / field)) == 0))
162 printk("\n ");
163 if (i > 39) {
164 printk(" ...");
165 break;
166 }
167
168 if (__get_user(stackdata, sp++)) {
169 printk(" (Bad stack address)");
170 break;
171 }
172
173 printk(" %0*lx", field, stackdata);
174 i++;
175 }
176 printk("\n");
177 show_backtrace(task, regs);
178 }
179
180 void show_stack(struct task_struct *task, unsigned long *sp)
181 {
182 struct pt_regs regs;
183 if (sp) {
184 regs.regs[29] = (unsigned long)sp;
185 regs.regs[31] = 0;
186 regs.cp0_epc = 0;
187 } else {
188 if (task && task != current) {
189 regs.regs[29] = task->thread.reg29;
190 regs.regs[31] = 0;
191 regs.cp0_epc = task->thread.reg31;
192 #ifdef CONFIG_KGDB_KDB
193 } else if (atomic_read(&kgdb_active) != -1 &&
194 kdb_current_regs) {
195 memcpy(&regs, kdb_current_regs, sizeof(regs));
196 #endif /* CONFIG_KGDB_KDB */
197 } else {
198 prepare_frametrace(&regs);
199 }
200 }
201 show_stacktrace(task, &regs);
202 }
203
204 /*
205 * The architecture-independent dump_stack generator
206 */
207 void dump_stack(void)
208 {
209 struct pt_regs regs;
210
211 prepare_frametrace(&regs);
212 show_backtrace(current, &regs);
213 }
214
215 EXPORT_SYMBOL(dump_stack);
216
217 static void show_code(unsigned int __user *pc)
218 {
219 long i;
220 unsigned short __user *pc16 = NULL;
221
222 printk("\nCode:");
223
224 if ((unsigned long)pc & 1)
225 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
226 for(i = -3 ; i < 6 ; i++) {
227 unsigned int insn;
228 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
229 printk(" (Bad address in epc)\n");
230 break;
231 }
232 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
233 }
234 }
235
236 static void __show_regs(const struct pt_regs *regs)
237 {
238 const int field = 2 * sizeof(unsigned long);
239 unsigned int cause = regs->cp0_cause;
240 int i;
241
242 printk("Cpu %d\n", smp_processor_id());
243
244 /*
245 * Saved main processor registers
246 */
247 for (i = 0; i < 32; ) {
248 if ((i % 4) == 0)
249 printk("$%2d :", i);
250 if (i == 0)
251 printk(" %0*lx", field, 0UL);
252 else if (i == 26 || i == 27)
253 printk(" %*s", field, "");
254 else
255 printk(" %0*lx", field, regs->regs[i]);
256
257 i++;
258 if ((i % 4) == 0)
259 printk("\n");
260 }
261
262 #ifdef CONFIG_CPU_HAS_SMARTMIPS
263 printk("Acx : %0*lx\n", field, regs->acx);
264 #endif
265 printk("Hi : %0*lx\n", field, regs->hi);
266 printk("Lo : %0*lx\n", field, regs->lo);
267
268 /*
269 * Saved cp0 registers
270 */
271 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
272 (void *) regs->cp0_epc);
273 printk(" %s\n", print_tainted());
274 printk("ra : %0*lx %pS\n", field, regs->regs[31],
275 (void *) regs->regs[31]);
276
277 printk("Status: %08x ", (uint32_t) regs->cp0_status);
278
279 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
280 if (regs->cp0_status & ST0_KUO)
281 printk("KUo ");
282 if (regs->cp0_status & ST0_IEO)
283 printk("IEo ");
284 if (regs->cp0_status & ST0_KUP)
285 printk("KUp ");
286 if (regs->cp0_status & ST0_IEP)
287 printk("IEp ");
288 if (regs->cp0_status & ST0_KUC)
289 printk("KUc ");
290 if (regs->cp0_status & ST0_IEC)
291 printk("IEc ");
292 } else {
293 if (regs->cp0_status & ST0_KX)
294 printk("KX ");
295 if (regs->cp0_status & ST0_SX)
296 printk("SX ");
297 if (regs->cp0_status & ST0_UX)
298 printk("UX ");
299 switch (regs->cp0_status & ST0_KSU) {
300 case KSU_USER:
301 printk("USER ");
302 break;
303 case KSU_SUPERVISOR:
304 printk("SUPERVISOR ");
305 break;
306 case KSU_KERNEL:
307 printk("KERNEL ");
308 break;
309 default:
310 printk("BAD_MODE ");
311 break;
312 }
313 if (regs->cp0_status & ST0_ERL)
314 printk("ERL ");
315 if (regs->cp0_status & ST0_EXL)
316 printk("EXL ");
317 if (regs->cp0_status & ST0_IE)
318 printk("IE ");
319 }
320 printk("\n");
321
322 printk("Cause : %08x\n", cause);
323
324 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
325 if (1 <= cause && cause <= 5)
326 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
327
328 printk("PrId : %08x (%s)\n", read_c0_prid(),
329 cpu_name_string());
330 }
331
332 /*
333 * FIXME: really the generic show_regs should take a const pointer argument.
334 */
335 void show_regs(struct pt_regs *regs)
336 {
337 __show_regs((struct pt_regs *)regs);
338 }
339
340 void show_registers(struct pt_regs *regs)
341 {
342 const int field = 2 * sizeof(unsigned long);
343
344 __show_regs(regs);
345 print_modules();
346 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
347 current->comm, current->pid, current_thread_info(), current,
348 field, current_thread_info()->tp_value);
349 if (cpu_has_userlocal) {
350 unsigned long tls;
351
352 tls = read_c0_userlocal();
353 if (tls != current_thread_info()->tp_value)
354 printk("*HwTLS: %0*lx\n", field, tls);
355 }
356
357 show_stacktrace(current, regs);
358 show_code((unsigned int __user *) regs->cp0_epc);
359 printk("\n");
360 }
361
362 static int regs_to_trapnr(struct pt_regs *regs)
363 {
364 return (regs->cp0_cause >> 2) & 0x1f;
365 }
366
367 static DEFINE_SPINLOCK(die_lock);
368
369 void __noreturn die(const char *str, struct pt_regs *regs)
370 {
371 static int die_counter;
372 int sig = SIGSEGV;
373 #ifdef CONFIG_MIPS_MT_SMTC
374 unsigned long dvpret = dvpe();
375 #endif /* CONFIG_MIPS_MT_SMTC */
376
377 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
378 sig = 0;
379
380 console_verbose();
381 spin_lock_irq(&die_lock);
382 bust_spinlocks(1);
383 #ifdef CONFIG_MIPS_MT_SMTC
384 mips_mt_regdump(dvpret);
385 #endif /* CONFIG_MIPS_MT_SMTC */
386
387 printk("%s[#%d]:\n", str, ++die_counter);
388 show_registers(regs);
389 add_taint(TAINT_DIE);
390 spin_unlock_irq(&die_lock);
391
392 if (in_interrupt())
393 panic("Fatal exception in interrupt");
394
395 if (panic_on_oops) {
396 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
397 ssleep(5);
398 panic("Fatal exception");
399 }
400
401 do_exit(sig);
402 }
403
404 extern struct exception_table_entry __start___dbe_table[];
405 extern struct exception_table_entry __stop___dbe_table[];
406
407 __asm__(
408 " .section __dbe_table, \"a\"\n"
409 " .previous \n");
410
411 /* Given an address, look for it in the exception tables. */
412 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
413 {
414 const struct exception_table_entry *e;
415
416 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
417 if (!e)
418 e = search_module_dbetables(addr);
419 return e;
420 }
421
422 asmlinkage void do_be(struct pt_regs *regs)
423 {
424 const int field = 2 * sizeof(unsigned long);
425 const struct exception_table_entry *fixup = NULL;
426 int data = regs->cp0_cause & 4;
427 int action = MIPS_BE_FATAL;
428
429 /* XXX For now. Fixme, this searches the wrong table ... */
430 if (data && !user_mode(regs))
431 fixup = search_dbe_tables(exception_epc(regs));
432
433 if (fixup)
434 action = MIPS_BE_FIXUP;
435
436 if (board_be_handler)
437 action = board_be_handler(regs, fixup != NULL);
438
439 switch (action) {
440 case MIPS_BE_DISCARD:
441 return;
442 case MIPS_BE_FIXUP:
443 if (fixup) {
444 regs->cp0_epc = fixup->nextinsn;
445 return;
446 }
447 break;
448 default:
449 break;
450 }
451
452 /*
453 * Assume it would be too dangerous to continue ...
454 */
455 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
456 data ? "Data" : "Instruction",
457 field, regs->cp0_epc, field, regs->regs[31]);
458 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
459 == NOTIFY_STOP)
460 return;
461
462 die_if_kernel("Oops", regs);
463 force_sig(SIGBUS, current);
464 }
465
466 /*
467 * ll/sc, rdhwr, sync emulation
468 */
469
470 #define OPCODE 0xfc000000
471 #define BASE 0x03e00000
472 #define RT 0x001f0000
473 #define OFFSET 0x0000ffff
474 #define LL 0xc0000000
475 #define SC 0xe0000000
476 #define SPEC0 0x00000000
477 #define SPEC3 0x7c000000
478 #define RD 0x0000f800
479 #define FUNC 0x0000003f
480 #define SYNC 0x0000000f
481 #define RDHWR 0x0000003b
482
483 /*
484 * The ll_bit is cleared by r*_switch.S
485 */
486
487 unsigned int ll_bit;
488 struct task_struct *ll_task;
489
490 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
491 {
492 unsigned long value, __user *vaddr;
493 long offset;
494
495 /*
496 * analyse the ll instruction that just caused a ri exception
497 * and put the referenced address to addr.
498 */
499
500 /* sign extend offset */
501 offset = opcode & OFFSET;
502 offset <<= 16;
503 offset >>= 16;
504
505 vaddr = (unsigned long __user *)
506 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
507
508 if ((unsigned long)vaddr & 3)
509 return SIGBUS;
510 if (get_user(value, vaddr))
511 return SIGSEGV;
512
513 preempt_disable();
514
515 if (ll_task == NULL || ll_task == current) {
516 ll_bit = 1;
517 } else {
518 ll_bit = 0;
519 }
520 ll_task = current;
521
522 preempt_enable();
523
524 regs->regs[(opcode & RT) >> 16] = value;
525
526 return 0;
527 }
528
529 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
530 {
531 unsigned long __user *vaddr;
532 unsigned long reg;
533 long offset;
534
535 /*
536 * analyse the sc instruction that just caused a ri exception
537 * and put the referenced address to addr.
538 */
539
540 /* sign extend offset */
541 offset = opcode & OFFSET;
542 offset <<= 16;
543 offset >>= 16;
544
545 vaddr = (unsigned long __user *)
546 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
547 reg = (opcode & RT) >> 16;
548
549 if ((unsigned long)vaddr & 3)
550 return SIGBUS;
551
552 preempt_disable();
553
554 if (ll_bit == 0 || ll_task != current) {
555 regs->regs[reg] = 0;
556 preempt_enable();
557 return 0;
558 }
559
560 preempt_enable();
561
562 if (put_user(regs->regs[reg], vaddr))
563 return SIGSEGV;
564
565 regs->regs[reg] = 1;
566
567 return 0;
568 }
569
570 /*
571 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
572 * opcodes are supposed to result in coprocessor unusable exceptions if
573 * executed on ll/sc-less processors. That's the theory. In practice a
574 * few processors such as NEC's VR4100 throw reserved instruction exceptions
575 * instead, so we're doing the emulation thing in both exception handlers.
576 */
577 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
578 {
579 if ((opcode & OPCODE) == LL) {
580 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
581 1, regs, 0);
582 return simulate_ll(regs, opcode);
583 }
584 if ((opcode & OPCODE) == SC) {
585 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
586 1, regs, 0);
587 return simulate_sc(regs, opcode);
588 }
589
590 return -1; /* Must be something else ... */
591 }
592
593 /*
594 * Simulate trapping 'rdhwr' instructions to provide user accessible
595 * registers not implemented in hardware.
596 */
597 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
598 {
599 struct thread_info *ti = task_thread_info(current);
600
601 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
602 int rd = (opcode & RD) >> 11;
603 int rt = (opcode & RT) >> 16;
604 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
605 1, regs, 0);
606 switch (rd) {
607 case 0: /* CPU number */
608 regs->regs[rt] = smp_processor_id();
609 return 0;
610 case 1: /* SYNCI length */
611 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
612 current_cpu_data.icache.linesz);
613 return 0;
614 case 2: /* Read count register */
615 regs->regs[rt] = read_c0_count();
616 return 0;
617 case 3: /* Count register resolution */
618 switch (current_cpu_data.cputype) {
619 case CPU_20KC:
620 case CPU_25KF:
621 regs->regs[rt] = 1;
622 break;
623 default:
624 regs->regs[rt] = 2;
625 }
626 return 0;
627 case 29:
628 regs->regs[rt] = ti->tp_value;
629 return 0;
630 default:
631 return -1;
632 }
633 }
634
635 /* Not ours. */
636 return -1;
637 }
638
639 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
640 {
641 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
642 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
643 1, regs, 0);
644 return 0;
645 }
646
647 return -1; /* Must be something else ... */
648 }
649
650 asmlinkage void do_ov(struct pt_regs *regs)
651 {
652 siginfo_t info;
653
654 die_if_kernel("Integer overflow", regs);
655
656 info.si_code = FPE_INTOVF;
657 info.si_signo = SIGFPE;
658 info.si_errno = 0;
659 info.si_addr = (void __user *) regs->cp0_epc;
660 force_sig_info(SIGFPE, &info, current);
661 }
662
663 static int process_fpemu_return(int sig, void __user *fault_addr)
664 {
665 if (sig == SIGSEGV || sig == SIGBUS) {
666 struct siginfo si = {0};
667 si.si_addr = fault_addr;
668 si.si_signo = sig;
669 if (sig == SIGSEGV) {
670 if (find_vma(current->mm, (unsigned long)fault_addr))
671 si.si_code = SEGV_ACCERR;
672 else
673 si.si_code = SEGV_MAPERR;
674 } else {
675 si.si_code = BUS_ADRERR;
676 }
677 force_sig_info(sig, &si, current);
678 return 1;
679 } else if (sig) {
680 force_sig(sig, current);
681 return 1;
682 } else {
683 return 0;
684 }
685 }
686
687 /*
688 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
689 */
690 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
691 {
692 siginfo_t info = {0};
693
694 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
695 == NOTIFY_STOP)
696 return;
697 die_if_kernel("FP exception in kernel code", regs);
698
699 if (fcr31 & FPU_CSR_UNI_X) {
700 int sig;
701 void __user *fault_addr = NULL;
702
703 /*
704 * Unimplemented operation exception. If we've got the full
705 * software emulator on-board, let's use it...
706 *
707 * Force FPU to dump state into task/thread context. We're
708 * moving a lot of data here for what is probably a single
709 * instruction, but the alternative is to pre-decode the FP
710 * register operands before invoking the emulator, which seems
711 * a bit extreme for what should be an infrequent event.
712 */
713 /* Ensure 'resume' not overwrite saved fp context again. */
714 lose_fpu(1);
715
716 /* Run the emulator */
717 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
718 &fault_addr);
719
720 /*
721 * We can't allow the emulated instruction to leave any of
722 * the cause bit set in $fcr31.
723 */
724 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
725
726 /* Restore the hardware register state */
727 own_fpu(1); /* Using the FPU again. */
728
729 /* If something went wrong, signal */
730 process_fpemu_return(sig, fault_addr);
731
732 return;
733 } else if (fcr31 & FPU_CSR_INV_X)
734 info.si_code = FPE_FLTINV;
735 else if (fcr31 & FPU_CSR_DIV_X)
736 info.si_code = FPE_FLTDIV;
737 else if (fcr31 & FPU_CSR_OVF_X)
738 info.si_code = FPE_FLTOVF;
739 else if (fcr31 & FPU_CSR_UDF_X)
740 info.si_code = FPE_FLTUND;
741 else if (fcr31 & FPU_CSR_INE_X)
742 info.si_code = FPE_FLTRES;
743 else
744 info.si_code = __SI_FAULT;
745 info.si_signo = SIGFPE;
746 info.si_errno = 0;
747 info.si_addr = (void __user *) regs->cp0_epc;
748 force_sig_info(SIGFPE, &info, current);
749 }
750
751 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
752 const char *str)
753 {
754 siginfo_t info;
755 char b[40];
756
757 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
758 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
759 return;
760 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
761
762 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
763 return;
764
765 /*
766 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
767 * insns, even for trap and break codes that indicate arithmetic
768 * failures. Weird ...
769 * But should we continue the brokenness??? --macro
770 */
771 switch (code) {
772 case BRK_OVERFLOW:
773 case BRK_DIVZERO:
774 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
775 die_if_kernel(b, regs);
776 if (code == BRK_DIVZERO)
777 info.si_code = FPE_INTDIV;
778 else
779 info.si_code = FPE_INTOVF;
780 info.si_signo = SIGFPE;
781 info.si_errno = 0;
782 info.si_addr = (void __user *) regs->cp0_epc;
783 force_sig_info(SIGFPE, &info, current);
784 break;
785 case BRK_BUG:
786 die_if_kernel("Kernel bug detected", regs);
787 force_sig(SIGTRAP, current);
788 break;
789 case BRK_MEMU:
790 /*
791 * Address errors may be deliberately induced by the FPU
792 * emulator to retake control of the CPU after executing the
793 * instruction in the delay slot of an emulated branch.
794 *
795 * Terminate if exception was recognized as a delay slot return
796 * otherwise handle as normal.
797 */
798 if (do_dsemulret(regs))
799 return;
800
801 die_if_kernel("Math emu break/trap", regs);
802 force_sig(SIGTRAP, current);
803 break;
804 default:
805 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
806 die_if_kernel(b, regs);
807 force_sig(SIGTRAP, current);
808 }
809 }
810
811 asmlinkage void do_bp(struct pt_regs *regs)
812 {
813 unsigned int opcode, bcode;
814
815 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
816 goto out_sigsegv;
817
818 /*
819 * There is the ancient bug in the MIPS assemblers that the break
820 * code starts left to bit 16 instead to bit 6 in the opcode.
821 * Gas is bug-compatible, but not always, grrr...
822 * We handle both cases with a simple heuristics. --macro
823 */
824 bcode = ((opcode >> 6) & ((1 << 20) - 1));
825 if (bcode >= (1 << 10))
826 bcode >>= 10;
827
828 /*
829 * notify the kprobe handlers, if instruction is likely to
830 * pertain to them.
831 */
832 switch (bcode) {
833 case BRK_KPROBE_BP:
834 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
835 return;
836 else
837 break;
838 case BRK_KPROBE_SSTEPBP:
839 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
840 return;
841 else
842 break;
843 default:
844 break;
845 }
846
847 do_trap_or_bp(regs, bcode, "Break");
848 return;
849
850 out_sigsegv:
851 force_sig(SIGSEGV, current);
852 }
853
854 asmlinkage void do_tr(struct pt_regs *regs)
855 {
856 unsigned int opcode, tcode = 0;
857
858 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
859 goto out_sigsegv;
860
861 /* Immediate versions don't provide a code. */
862 if (!(opcode & OPCODE))
863 tcode = ((opcode >> 6) & ((1 << 10) - 1));
864
865 do_trap_or_bp(regs, tcode, "Trap");
866 return;
867
868 out_sigsegv:
869 force_sig(SIGSEGV, current);
870 }
871
872 asmlinkage void do_ri(struct pt_regs *regs)
873 {
874 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
875 unsigned long old_epc = regs->cp0_epc;
876 unsigned int opcode = 0;
877 int status = -1;
878
879 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
880 == NOTIFY_STOP)
881 return;
882
883 die_if_kernel("Reserved instruction in kernel code", regs);
884
885 if (unlikely(compute_return_epc(regs) < 0))
886 return;
887
888 if (unlikely(get_user(opcode, epc) < 0))
889 status = SIGSEGV;
890
891 if (!cpu_has_llsc && status < 0)
892 status = simulate_llsc(regs, opcode);
893
894 if (status < 0)
895 status = simulate_rdhwr(regs, opcode);
896
897 if (status < 0)
898 status = simulate_sync(regs, opcode);
899
900 if (status < 0)
901 status = SIGILL;
902
903 if (unlikely(status > 0)) {
904 regs->cp0_epc = old_epc; /* Undo skip-over. */
905 force_sig(status, current);
906 }
907 }
908
909 /*
910 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
911 * emulated more than some threshold number of instructions, force migration to
912 * a "CPU" that has FP support.
913 */
914 static void mt_ase_fp_affinity(void)
915 {
916 #ifdef CONFIG_MIPS_MT_FPAFF
917 if (mt_fpemul_threshold > 0 &&
918 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
919 /*
920 * If there's no FPU present, or if the application has already
921 * restricted the allowed set to exclude any CPUs with FPUs,
922 * we'll skip the procedure.
923 */
924 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
925 cpumask_t tmask;
926
927 current->thread.user_cpus_allowed
928 = current->cpus_allowed;
929 cpus_and(tmask, current->cpus_allowed,
930 mt_fpu_cpumask);
931 set_cpus_allowed_ptr(current, &tmask);
932 set_thread_flag(TIF_FPUBOUND);
933 }
934 }
935 #endif /* CONFIG_MIPS_MT_FPAFF */
936 }
937
938 /*
939 * No lock; only written during early bootup by CPU 0.
940 */
941 static RAW_NOTIFIER_HEAD(cu2_chain);
942
943 int __ref register_cu2_notifier(struct notifier_block *nb)
944 {
945 return raw_notifier_chain_register(&cu2_chain, nb);
946 }
947
948 int cu2_notifier_call_chain(unsigned long val, void *v)
949 {
950 return raw_notifier_call_chain(&cu2_chain, val, v);
951 }
952
953 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
954 void *data)
955 {
956 struct pt_regs *regs = data;
957
958 switch (action) {
959 default:
960 die_if_kernel("Unhandled kernel unaligned access or invalid "
961 "instruction", regs);
962 /* Fall through */
963
964 case CU2_EXCEPTION:
965 force_sig(SIGILL, current);
966 }
967
968 return NOTIFY_OK;
969 }
970
971 asmlinkage void do_cpu(struct pt_regs *regs)
972 {
973 unsigned int __user *epc;
974 unsigned long old_epc;
975 unsigned int opcode;
976 unsigned int cpid;
977 int status;
978 unsigned long __maybe_unused flags;
979
980 die_if_kernel("do_cpu invoked from kernel context!", regs);
981
982 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
983
984 switch (cpid) {
985 case 0:
986 epc = (unsigned int __user *)exception_epc(regs);
987 old_epc = regs->cp0_epc;
988 opcode = 0;
989 status = -1;
990
991 if (unlikely(compute_return_epc(regs) < 0))
992 return;
993
994 if (unlikely(get_user(opcode, epc) < 0))
995 status = SIGSEGV;
996
997 if (!cpu_has_llsc && status < 0)
998 status = simulate_llsc(regs, opcode);
999
1000 if (status < 0)
1001 status = simulate_rdhwr(regs, opcode);
1002
1003 if (status < 0)
1004 status = SIGILL;
1005
1006 if (unlikely(status > 0)) {
1007 regs->cp0_epc = old_epc; /* Undo skip-over. */
1008 force_sig(status, current);
1009 }
1010
1011 return;
1012
1013 case 1:
1014 if (used_math()) /* Using the FPU again. */
1015 own_fpu(1);
1016 else { /* First time FPU user. */
1017 init_fpu();
1018 set_used_math();
1019 }
1020
1021 if (!raw_cpu_has_fpu) {
1022 int sig;
1023 void __user *fault_addr = NULL;
1024 sig = fpu_emulator_cop1Handler(regs,
1025 &current->thread.fpu,
1026 0, &fault_addr);
1027 if (!process_fpemu_return(sig, fault_addr))
1028 mt_ase_fp_affinity();
1029 }
1030
1031 return;
1032
1033 case 2:
1034 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1035 return;
1036
1037 case 3:
1038 break;
1039 }
1040
1041 force_sig(SIGILL, current);
1042 }
1043
1044 asmlinkage void do_mdmx(struct pt_regs *regs)
1045 {
1046 force_sig(SIGILL, current);
1047 }
1048
1049 /*
1050 * Called with interrupts disabled.
1051 */
1052 asmlinkage void do_watch(struct pt_regs *regs)
1053 {
1054 u32 cause;
1055
1056 /*
1057 * Clear WP (bit 22) bit of cause register so we don't loop
1058 * forever.
1059 */
1060 cause = read_c0_cause();
1061 cause &= ~(1 << 22);
1062 write_c0_cause(cause);
1063
1064 /*
1065 * If the current thread has the watch registers loaded, save
1066 * their values and send SIGTRAP. Otherwise another thread
1067 * left the registers set, clear them and continue.
1068 */
1069 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1070 mips_read_watch_registers();
1071 local_irq_enable();
1072 force_sig(SIGTRAP, current);
1073 } else {
1074 mips_clear_watch_registers();
1075 local_irq_enable();
1076 }
1077 }
1078
1079 asmlinkage void do_mcheck(struct pt_regs *regs)
1080 {
1081 const int field = 2 * sizeof(unsigned long);
1082 int multi_match = regs->cp0_status & ST0_TS;
1083
1084 show_regs(regs);
1085
1086 if (multi_match) {
1087 printk("Index : %0x\n", read_c0_index());
1088 printk("Pagemask: %0x\n", read_c0_pagemask());
1089 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1090 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1091 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1092 printk("\n");
1093 dump_tlb_all();
1094 }
1095
1096 show_code((unsigned int __user *) regs->cp0_epc);
1097
1098 /*
1099 * Some chips may have other causes of machine check (e.g. SB1
1100 * graduation timer)
1101 */
1102 panic("Caught Machine Check exception - %scaused by multiple "
1103 "matching entries in the TLB.",
1104 (multi_match) ? "" : "not ");
1105 }
1106
1107 asmlinkage void do_mt(struct pt_regs *regs)
1108 {
1109 int subcode;
1110
1111 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1112 >> VPECONTROL_EXCPT_SHIFT;
1113 switch (subcode) {
1114 case 0:
1115 printk(KERN_DEBUG "Thread Underflow\n");
1116 break;
1117 case 1:
1118 printk(KERN_DEBUG "Thread Overflow\n");
1119 break;
1120 case 2:
1121 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1122 break;
1123 case 3:
1124 printk(KERN_DEBUG "Gating Storage Exception\n");
1125 break;
1126 case 4:
1127 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1128 break;
1129 case 5:
1130 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1131 break;
1132 default:
1133 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1134 subcode);
1135 break;
1136 }
1137 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1138
1139 force_sig(SIGILL, current);
1140 }
1141
1142
1143 asmlinkage void do_dsp(struct pt_regs *regs)
1144 {
1145 if (cpu_has_dsp)
1146 panic("Unexpected DSP exception\n");
1147
1148 force_sig(SIGILL, current);
1149 }
1150
1151 asmlinkage void do_reserved(struct pt_regs *regs)
1152 {
1153 /*
1154 * Game over - no way to handle this if it ever occurs. Most probably
1155 * caused by a new unknown cpu type or after another deadly
1156 * hard/software error.
1157 */
1158 show_regs(regs);
1159 panic("Caught reserved exception %ld - should not happen.",
1160 (regs->cp0_cause & 0x7f) >> 2);
1161 }
1162
1163 static int __initdata l1parity = 1;
1164 static int __init nol1parity(char *s)
1165 {
1166 l1parity = 0;
1167 return 1;
1168 }
1169 __setup("nol1par", nol1parity);
1170 static int __initdata l2parity = 1;
1171 static int __init nol2parity(char *s)
1172 {
1173 l2parity = 0;
1174 return 1;
1175 }
1176 __setup("nol2par", nol2parity);
1177
1178 /*
1179 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1180 * it different ways.
1181 */
1182 static inline void parity_protection_init(void)
1183 {
1184 switch (current_cpu_type()) {
1185 case CPU_24K:
1186 case CPU_34K:
1187 case CPU_74K:
1188 case CPU_1004K:
1189 {
1190 #define ERRCTL_PE 0x80000000
1191 #define ERRCTL_L2P 0x00800000
1192 unsigned long errctl;
1193 unsigned int l1parity_present, l2parity_present;
1194
1195 errctl = read_c0_ecc();
1196 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1197
1198 /* probe L1 parity support */
1199 write_c0_ecc(errctl | ERRCTL_PE);
1200 back_to_back_c0_hazard();
1201 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1202
1203 /* probe L2 parity support */
1204 write_c0_ecc(errctl|ERRCTL_L2P);
1205 back_to_back_c0_hazard();
1206 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1207
1208 if (l1parity_present && l2parity_present) {
1209 if (l1parity)
1210 errctl |= ERRCTL_PE;
1211 if (l1parity ^ l2parity)
1212 errctl |= ERRCTL_L2P;
1213 } else if (l1parity_present) {
1214 if (l1parity)
1215 errctl |= ERRCTL_PE;
1216 } else if (l2parity_present) {
1217 if (l2parity)
1218 errctl |= ERRCTL_L2P;
1219 } else {
1220 /* No parity available */
1221 }
1222
1223 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1224
1225 write_c0_ecc(errctl);
1226 back_to_back_c0_hazard();
1227 errctl = read_c0_ecc();
1228 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1229
1230 if (l1parity_present)
1231 printk(KERN_INFO "Cache parity protection %sabled\n",
1232 (errctl & ERRCTL_PE) ? "en" : "dis");
1233
1234 if (l2parity_present) {
1235 if (l1parity_present && l1parity)
1236 errctl ^= ERRCTL_L2P;
1237 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1238 (errctl & ERRCTL_L2P) ? "en" : "dis");
1239 }
1240 }
1241 break;
1242
1243 case CPU_5KC:
1244 write_c0_ecc(0x80000000);
1245 back_to_back_c0_hazard();
1246 /* Set the PE bit (bit 31) in the c0_errctl register. */
1247 printk(KERN_INFO "Cache parity protection %sabled\n",
1248 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1249 break;
1250 case CPU_20KC:
1251 case CPU_25KF:
1252 /* Clear the DE bit (bit 16) in the c0_status register. */
1253 printk(KERN_INFO "Enable cache parity protection for "
1254 "MIPS 20KC/25KF CPUs.\n");
1255 clear_c0_status(ST0_DE);
1256 break;
1257 default:
1258 break;
1259 }
1260 }
1261
1262 asmlinkage void cache_parity_error(void)
1263 {
1264 const int field = 2 * sizeof(unsigned long);
1265 unsigned int reg_val;
1266
1267 /* For the moment, report the problem and hang. */
1268 printk("Cache error exception:\n");
1269 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1270 reg_val = read_c0_cacheerr();
1271 printk("c0_cacheerr == %08x\n", reg_val);
1272
1273 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1274 reg_val & (1<<30) ? "secondary" : "primary",
1275 reg_val & (1<<31) ? "data" : "insn");
1276 printk("Error bits: %s%s%s%s%s%s%s\n",
1277 reg_val & (1<<29) ? "ED " : "",
1278 reg_val & (1<<28) ? "ET " : "",
1279 reg_val & (1<<26) ? "EE " : "",
1280 reg_val & (1<<25) ? "EB " : "",
1281 reg_val & (1<<24) ? "EI " : "",
1282 reg_val & (1<<23) ? "E1 " : "",
1283 reg_val & (1<<22) ? "E0 " : "");
1284 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1285
1286 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1287 if (reg_val & (1<<22))
1288 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1289
1290 if (reg_val & (1<<23))
1291 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1292 #endif
1293
1294 panic("Can't handle the cache error!");
1295 }
1296
1297 /*
1298 * SDBBP EJTAG debug exception handler.
1299 * We skip the instruction and return to the next instruction.
1300 */
1301 void ejtag_exception_handler(struct pt_regs *regs)
1302 {
1303 const int field = 2 * sizeof(unsigned long);
1304 unsigned long depc, old_epc;
1305 unsigned int debug;
1306
1307 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1308 depc = read_c0_depc();
1309 debug = read_c0_debug();
1310 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1311 if (debug & 0x80000000) {
1312 /*
1313 * In branch delay slot.
1314 * We cheat a little bit here and use EPC to calculate the
1315 * debug return address (DEPC). EPC is restored after the
1316 * calculation.
1317 */
1318 old_epc = regs->cp0_epc;
1319 regs->cp0_epc = depc;
1320 __compute_return_epc(regs);
1321 depc = regs->cp0_epc;
1322 regs->cp0_epc = old_epc;
1323 } else
1324 depc += 4;
1325 write_c0_depc(depc);
1326
1327 #if 0
1328 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1329 write_c0_debug(debug | 0x100);
1330 #endif
1331 }
1332
1333 /*
1334 * NMI exception handler.
1335 */
1336 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1337 {
1338 bust_spinlocks(1);
1339 printk("NMI taken!!!!\n");
1340 die("NMI", regs);
1341 }
1342
1343 #define VECTORSPACING 0x100 /* for EI/VI mode */
1344
1345 unsigned long ebase;
1346 unsigned long exception_handlers[32];
1347 unsigned long vi_handlers[64];
1348
1349 void __init *set_except_vector(int n, void *addr)
1350 {
1351 unsigned long handler = (unsigned long) addr;
1352 unsigned long old_handler = exception_handlers[n];
1353
1354 exception_handlers[n] = handler;
1355 if (n == 0 && cpu_has_divec) {
1356 unsigned long jump_mask = ~((1 << 28) - 1);
1357 u32 *buf = (u32 *)(ebase + 0x200);
1358 unsigned int k0 = 26;
1359 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1360 uasm_i_j(&buf, handler & ~jump_mask);
1361 uasm_i_nop(&buf);
1362 } else {
1363 UASM_i_LA(&buf, k0, handler);
1364 uasm_i_jr(&buf, k0);
1365 uasm_i_nop(&buf);
1366 }
1367 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1368 }
1369 return (void *)old_handler;
1370 }
1371
1372 static asmlinkage void do_default_vi(void)
1373 {
1374 show_regs(get_irq_regs());
1375 panic("Caught unexpected vectored interrupt.");
1376 }
1377
1378 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1379 {
1380 unsigned long handler;
1381 unsigned long old_handler = vi_handlers[n];
1382 int srssets = current_cpu_data.srsets;
1383 u32 *w;
1384 unsigned char *b;
1385
1386 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1387
1388 if (addr == NULL) {
1389 handler = (unsigned long) do_default_vi;
1390 srs = 0;
1391 } else
1392 handler = (unsigned long) addr;
1393 vi_handlers[n] = (unsigned long) addr;
1394
1395 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1396
1397 if (srs >= srssets)
1398 panic("Shadow register set %d not supported", srs);
1399
1400 if (cpu_has_veic) {
1401 if (board_bind_eic_interrupt)
1402 board_bind_eic_interrupt(n, srs);
1403 } else if (cpu_has_vint) {
1404 /* SRSMap is only defined if shadow sets are implemented */
1405 if (srssets > 1)
1406 change_c0_srsmap(0xf << n*4, srs << n*4);
1407 }
1408
1409 if (srs == 0) {
1410 /*
1411 * If no shadow set is selected then use the default handler
1412 * that does normal register saving and a standard interrupt exit
1413 */
1414
1415 extern char except_vec_vi, except_vec_vi_lui;
1416 extern char except_vec_vi_ori, except_vec_vi_end;
1417 extern char rollback_except_vec_vi;
1418 char *vec_start = (cpu_wait == r4k_wait) ?
1419 &rollback_except_vec_vi : &except_vec_vi;
1420 #ifdef CONFIG_MIPS_MT_SMTC
1421 /*
1422 * We need to provide the SMTC vectored interrupt handler
1423 * not only with the address of the handler, but with the
1424 * Status.IM bit to be masked before going there.
1425 */
1426 extern char except_vec_vi_mori;
1427 const int mori_offset = &except_vec_vi_mori - vec_start;
1428 #endif /* CONFIG_MIPS_MT_SMTC */
1429 const int handler_len = &except_vec_vi_end - vec_start;
1430 const int lui_offset = &except_vec_vi_lui - vec_start;
1431 const int ori_offset = &except_vec_vi_ori - vec_start;
1432
1433 if (handler_len > VECTORSPACING) {
1434 /*
1435 * Sigh... panicing won't help as the console
1436 * is probably not configured :(
1437 */
1438 panic("VECTORSPACING too small");
1439 }
1440
1441 memcpy(b, vec_start, handler_len);
1442 #ifdef CONFIG_MIPS_MT_SMTC
1443 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1444
1445 w = (u32 *)(b + mori_offset);
1446 *w = (*w & 0xffff0000) | (0x100 << n);
1447 #endif /* CONFIG_MIPS_MT_SMTC */
1448 w = (u32 *)(b + lui_offset);
1449 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1450 w = (u32 *)(b + ori_offset);
1451 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1452 local_flush_icache_range((unsigned long)b,
1453 (unsigned long)(b+handler_len));
1454 }
1455 else {
1456 /*
1457 * In other cases jump directly to the interrupt handler
1458 *
1459 * It is the handlers responsibility to save registers if required
1460 * (eg hi/lo) and return from the exception using "eret"
1461 */
1462 w = (u32 *)b;
1463 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1464 *w = 0;
1465 local_flush_icache_range((unsigned long)b,
1466 (unsigned long)(b+8));
1467 }
1468
1469 return (void *)old_handler;
1470 }
1471
1472 void *set_vi_handler(int n, vi_handler_t addr)
1473 {
1474 return set_vi_srs_handler(n, addr, 0);
1475 }
1476
1477 extern void cpu_cache_init(void);
1478 extern void tlb_init(void);
1479 extern void flush_tlb_handlers(void);
1480
1481 /*
1482 * Timer interrupt
1483 */
1484 int cp0_compare_irq;
1485 int cp0_compare_irq_shift;
1486
1487 /*
1488 * Performance counter IRQ or -1 if shared with timer
1489 */
1490 int cp0_perfcount_irq;
1491 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1492
1493 static int __cpuinitdata noulri;
1494
1495 static int __init ulri_disable(char *s)
1496 {
1497 pr_info("Disabling ulri\n");
1498 noulri = 1;
1499
1500 return 1;
1501 }
1502 __setup("noulri", ulri_disable);
1503
1504 void __cpuinit per_cpu_trap_init(void)
1505 {
1506 unsigned int cpu = smp_processor_id();
1507 unsigned int status_set = ST0_CU0;
1508 unsigned int hwrena = cpu_hwrena_impl_bits;
1509 #ifdef CONFIG_MIPS_MT_SMTC
1510 int secondaryTC = 0;
1511 int bootTC = (cpu == 0);
1512
1513 /*
1514 * Only do per_cpu_trap_init() for first TC of Each VPE.
1515 * Note that this hack assumes that the SMTC init code
1516 * assigns TCs consecutively and in ascending order.
1517 */
1518
1519 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1520 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1521 secondaryTC = 1;
1522 #endif /* CONFIG_MIPS_MT_SMTC */
1523
1524 /*
1525 * Disable coprocessors and select 32-bit or 64-bit addressing
1526 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1527 * flag that some firmware may have left set and the TS bit (for
1528 * IP27). Set XX for ISA IV code to work.
1529 */
1530 #ifdef CONFIG_64BIT
1531 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1532 #endif
1533 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1534 status_set |= ST0_XX;
1535 if (cpu_has_dsp)
1536 status_set |= ST0_MX;
1537
1538 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1539 status_set);
1540
1541 if (cpu_has_mips_r2)
1542 hwrena |= 0x0000000f;
1543
1544 if (!noulri && cpu_has_userlocal)
1545 hwrena |= (1 << 29);
1546
1547 if (hwrena)
1548 write_c0_hwrena(hwrena);
1549
1550 #ifdef CONFIG_MIPS_MT_SMTC
1551 if (!secondaryTC) {
1552 #endif /* CONFIG_MIPS_MT_SMTC */
1553
1554 if (cpu_has_veic || cpu_has_vint) {
1555 unsigned long sr = set_c0_status(ST0_BEV);
1556 write_c0_ebase(ebase);
1557 write_c0_status(sr);
1558 /* Setting vector spacing enables EI/VI mode */
1559 change_c0_intctl(0x3e0, VECTORSPACING);
1560 }
1561 if (cpu_has_divec) {
1562 if (cpu_has_mipsmt) {
1563 unsigned int vpflags = dvpe();
1564 set_c0_cause(CAUSEF_IV);
1565 evpe(vpflags);
1566 } else
1567 set_c0_cause(CAUSEF_IV);
1568 }
1569
1570 /*
1571 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1572 *
1573 * o read IntCtl.IPTI to determine the timer interrupt
1574 * o read IntCtl.IPPCI to determine the performance counter interrupt
1575 */
1576 if (cpu_has_mips_r2) {
1577 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1578 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1579 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1580 if (cp0_perfcount_irq == cp0_compare_irq)
1581 cp0_perfcount_irq = -1;
1582 } else {
1583 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1584 cp0_compare_irq_shift = cp0_compare_irq;
1585 cp0_perfcount_irq = -1;
1586 }
1587
1588 #ifdef CONFIG_MIPS_MT_SMTC
1589 }
1590 #endif /* CONFIG_MIPS_MT_SMTC */
1591
1592 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1593
1594 atomic_inc(&init_mm.mm_count);
1595 current->active_mm = &init_mm;
1596 BUG_ON(current->mm);
1597 enter_lazy_tlb(&init_mm, current);
1598
1599 #ifdef CONFIG_MIPS_MT_SMTC
1600 if (bootTC) {
1601 #endif /* CONFIG_MIPS_MT_SMTC */
1602 cpu_cache_init();
1603 tlb_init();
1604 #ifdef CONFIG_MIPS_MT_SMTC
1605 } else if (!secondaryTC) {
1606 /*
1607 * First TC in non-boot VPE must do subset of tlb_init()
1608 * for MMU countrol registers.
1609 */
1610 write_c0_pagemask(PM_DEFAULT_MASK);
1611 write_c0_wired(0);
1612 }
1613 #endif /* CONFIG_MIPS_MT_SMTC */
1614 TLBMISS_HANDLER_SETUP();
1615 }
1616
1617 /* Install CPU exception handler */
1618 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1619 {
1620 memcpy((void *)(ebase + offset), addr, size);
1621 local_flush_icache_range(ebase + offset, ebase + offset + size);
1622 }
1623
1624 static char panic_null_cerr[] __cpuinitdata =
1625 "Trying to set NULL cache error exception handler";
1626
1627 /*
1628 * Install uncached CPU exception handler.
1629 * This is suitable only for the cache error exception which is the only
1630 * exception handler that is being run uncached.
1631 */
1632 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1633 unsigned long size)
1634 {
1635 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1636
1637 if (!addr)
1638 panic(panic_null_cerr);
1639
1640 memcpy((void *)(uncached_ebase + offset), addr, size);
1641 }
1642
1643 static int __initdata rdhwr_noopt;
1644 static int __init set_rdhwr_noopt(char *str)
1645 {
1646 rdhwr_noopt = 1;
1647 return 1;
1648 }
1649
1650 __setup("rdhwr_noopt", set_rdhwr_noopt);
1651
1652 void __init trap_init(void)
1653 {
1654 extern char except_vec3_generic, except_vec3_r4000;
1655 extern char except_vec4;
1656 unsigned long i;
1657 int rollback;
1658
1659 check_wait();
1660 rollback = (cpu_wait == r4k_wait);
1661
1662 #if defined(CONFIG_KGDB)
1663 if (kgdb_early_setup)
1664 return; /* Already done */
1665 #endif
1666
1667 if (cpu_has_veic || cpu_has_vint) {
1668 unsigned long size = 0x200 + VECTORSPACING*64;
1669 ebase = (unsigned long)
1670 __alloc_bootmem(size, 1 << fls(size), 0);
1671 } else {
1672 ebase = CKSEG0;
1673 if (cpu_has_mips_r2)
1674 ebase += (read_c0_ebase() & 0x3ffff000);
1675 }
1676
1677 per_cpu_trap_init();
1678
1679 /*
1680 * Copy the generic exception handlers to their final destination.
1681 * This will be overriden later as suitable for a particular
1682 * configuration.
1683 */
1684 set_handler(0x180, &except_vec3_generic, 0x80);
1685
1686 /*
1687 * Setup default vectors
1688 */
1689 for (i = 0; i <= 31; i++)
1690 set_except_vector(i, handle_reserved);
1691
1692 /*
1693 * Copy the EJTAG debug exception vector handler code to it's final
1694 * destination.
1695 */
1696 if (cpu_has_ejtag && board_ejtag_handler_setup)
1697 board_ejtag_handler_setup();
1698
1699 /*
1700 * Only some CPUs have the watch exceptions.
1701 */
1702 if (cpu_has_watch)
1703 set_except_vector(23, handle_watch);
1704
1705 /*
1706 * Initialise interrupt handlers
1707 */
1708 if (cpu_has_veic || cpu_has_vint) {
1709 int nvec = cpu_has_veic ? 64 : 8;
1710 for (i = 0; i < nvec; i++)
1711 set_vi_handler(i, NULL);
1712 }
1713 else if (cpu_has_divec)
1714 set_handler(0x200, &except_vec4, 0x8);
1715
1716 /*
1717 * Some CPUs can enable/disable for cache parity detection, but does
1718 * it different ways.
1719 */
1720 parity_protection_init();
1721
1722 /*
1723 * The Data Bus Errors / Instruction Bus Errors are signaled
1724 * by external hardware. Therefore these two exceptions
1725 * may have board specific handlers.
1726 */
1727 if (board_be_init)
1728 board_be_init();
1729
1730 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1731 set_except_vector(1, handle_tlbm);
1732 set_except_vector(2, handle_tlbl);
1733 set_except_vector(3, handle_tlbs);
1734
1735 set_except_vector(4, handle_adel);
1736 set_except_vector(5, handle_ades);
1737
1738 set_except_vector(6, handle_ibe);
1739 set_except_vector(7, handle_dbe);
1740
1741 set_except_vector(8, handle_sys);
1742 set_except_vector(9, handle_bp);
1743 set_except_vector(10, rdhwr_noopt ? handle_ri :
1744 (cpu_has_vtag_icache ?
1745 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1746 set_except_vector(11, handle_cpu);
1747 set_except_vector(12, handle_ov);
1748 set_except_vector(13, handle_tr);
1749
1750 if (current_cpu_type() == CPU_R6000 ||
1751 current_cpu_type() == CPU_R6000A) {
1752 /*
1753 * The R6000 is the only R-series CPU that features a machine
1754 * check exception (similar to the R4000 cache error) and
1755 * unaligned ldc1/sdc1 exception. The handlers have not been
1756 * written yet. Well, anyway there is no R6000 machine on the
1757 * current list of targets for Linux/MIPS.
1758 * (Duh, crap, there is someone with a triple R6k machine)
1759 */
1760 //set_except_vector(14, handle_mc);
1761 //set_except_vector(15, handle_ndc);
1762 }
1763
1764
1765 if (board_nmi_handler_setup)
1766 board_nmi_handler_setup();
1767
1768 if (cpu_has_fpu && !cpu_has_nofpuex)
1769 set_except_vector(15, handle_fpe);
1770
1771 set_except_vector(22, handle_mdmx);
1772
1773 if (cpu_has_mcheck)
1774 set_except_vector(24, handle_mcheck);
1775
1776 if (cpu_has_mipsmt)
1777 set_except_vector(25, handle_mt);
1778
1779 set_except_vector(26, handle_dsp);
1780
1781 if (cpu_has_vce)
1782 /* Special exception: R4[04]00 uses also the divec space. */
1783 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1784 else if (cpu_has_4kex)
1785 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1786 else
1787 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1788
1789 local_flush_icache_range(ebase, ebase + 0x400);
1790 flush_tlb_handlers();
1791
1792 sort_extable(__start___dbe_table, __stop___dbe_table);
1793
1794 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1795 }
Linux Btrfs Development