arch/sh/kernel/cpu/sh3/setup-sh770x.c

   1 /*
   2  * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
   3  *
   4  *  Copyright (C) 2007  Magnus Damm
   5  *  Copyright (C) 2009  Paul Mundt
   6  *
   7  * Based on setup-sh7709.c
   8  *
   9  *  Copyright (C) 2006  Paul Mundt
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/serial.h>
  20 #include <linux/serial_sci.h>
  21 #include <linux/sh_timer.h>
  22 #include <cpu/serial.h>
  23
  24 enum {
  25         UNUSED = 0,
  26
  27         /* interrupt sources */
  28         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  29         PINT07, PINT815,
  30         DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
  31         LCDC, PCC0, PCC1,
  32         TMU0, TMU1, TMU2,
  33         RTC, WDT, REF,
  34 };
  35
  36 static struct intc_vect vectors[] __initdata = {
  37         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  38         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  39         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  40         INTC_VECT(RTC, 0x4c0),
  41         INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
  42         INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
  43         INTC_VECT(WDT, 0x560),
  44         INTC_VECT(REF, 0x580),
  45         INTC_VECT(REF, 0x5a0),
  46 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  47     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  48     defined(CONFIG_CPU_SUBTYPE_SH7709)
  49         /* IRQ0->5 are handled in setup-sh3.c */
  50         INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
  51         INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
  52         INTC_VECT(ADC_ADI, 0x980),
  53         INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
  54         INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
  55 #endif
  56 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  57     defined(CONFIG_CPU_SUBTYPE_SH7709)
  58         INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
  59         INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
  60         INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
  61 #endif
  62 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  63         INTC_VECT(LCDC, 0x9a0),
  64         INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
  65 #endif
  66 };
  67
  68 static struct intc_prio_reg prio_registers[] __initdata = {
  69         { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  70         { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
  71 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  72     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  73     defined(CONFIG_CPU_SUBTYPE_SH7709)
  74         { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  75         { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
  76         { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
  77 #endif
  78 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  79     defined(CONFIG_CPU_SUBTYPE_SH7709)
  80         { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
  81         { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
  82 #endif
  83 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  84         { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
  85 #endif
  86 };
  87
  88 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
  89                          NULL, prio_registers, NULL);
  90
  91 static struct resource rtc_resources[] = {
  92         [0] =   {
  93                 .start  = 0xfffffec0,
  94                 .end    = 0xfffffec0 + 0x1e,
  95                 .flags  = IORESOURCE_IO,
  96         },
  97         [1] =   {
  98                 .start  = 20,
  99                 .flags  = IORESOURCE_IRQ,
 100         },
 101 };
 102
 103 static struct platform_device rtc_device = {
 104         .name           = "sh-rtc",
 105         .id             = -1,
 106         .num_resources  = ARRAY_SIZE(rtc_resources),
 107         .resource       = rtc_resources,
 108 };
 109
 110 static struct plat_sci_port scif0_platform_data = {
 111         .mapbase        = 0xfffffe80,
 112         .port_reg       = 0xa4000136,
 113         .flags          = UPF_BOOT_AUTOCONF,
 114         .scscr          = SCSCR_TE | SCSCR_RE,
 115         .scbrr_algo_id  = SCBRR_ALGO_2,
 116         .type           = PORT_SCI,
 117         .irqs           = { 23, 23, 23, 0 },
 118         .ops            = &sh770x_sci_port_ops,
 119         .regshift       = 1,
 120 };
 121
 122 static struct platform_device scif0_device = {
 123         .name           = "sh-sci",
 124         .id             = 0,
 125         .dev            = {
 126                 .platform_data  = &scif0_platform_data,
 127         },
 128 };
 129 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 130     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 131     defined(CONFIG_CPU_SUBTYPE_SH7709)
 132 static struct plat_sci_port scif1_platform_data = {
 133         .mapbase        = 0xa4000150,
 134         .flags          = UPF_BOOT_AUTOCONF,
 135         .scscr          = SCSCR_TE | SCSCR_RE,
 136         .scbrr_algo_id  = SCBRR_ALGO_2,
 137         .type           = PORT_SCIF,
 138         .irqs           = { 56, 56, 56, 56 },
 139         .ops            = &sh770x_sci_port_ops,
 140         .regtype        = SCIx_SH3_SCIF_REGTYPE,
 141 };
 142
 143 static struct platform_device scif1_device = {
 144         .name           = "sh-sci",
 145         .id             = 1,
 146         .dev            = {
 147                 .platform_data  = &scif1_platform_data,
 148         },
 149 };
 150 #endif
 151 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 152     defined(CONFIG_CPU_SUBTYPE_SH7709)
 153 static struct plat_sci_port scif2_platform_data = {
 154         .mapbase        = 0xa4000140,
 155         .port_reg       = SCIx_NOT_SUPPORTED,
 156         .flags          = UPF_BOOT_AUTOCONF,
 157         .scscr          = SCSCR_TE | SCSCR_RE,
 158         .scbrr_algo_id  = SCBRR_ALGO_2,
 159         .type           = PORT_IRDA,
 160         .irqs           = { 52, 52, 52, 52 },
 161         .ops            = &sh770x_sci_port_ops,
 162         .regshift       = 1,
 163 };
 164
 165 static struct platform_device scif2_device = {
 166         .name           = "sh-sci",
 167         .id             = 2,
 168         .dev            = {
 169                 .platform_data  = &scif2_platform_data,
 170         },
 171 };
 172 #endif
 173
 174 static struct sh_timer_config tmu0_platform_data = {
 175         .channel_offset = 0x02,
 176         .timer_bit = 0,
 177         .clockevent_rating = 200,
 178 };
 179
 180 static struct resource tmu0_resources[] = {
 181         [0] = {
 182                 .start  = 0xfffffe94,
 183                 .end    = 0xfffffe9f,
 184                 .flags  = IORESOURCE_MEM,
 185         },
 186         [1] = {
 187                 .start  = 16,
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct platform_device tmu0_device = {
 193         .name           = "sh_tmu",
 194         .id             = 0,
 195         .dev = {
 196                 .platform_data  = &tmu0_platform_data,
 197         },
 198         .resource       = tmu0_resources,
 199         .num_resources  = ARRAY_SIZE(tmu0_resources),
 200 };
 201
 202 static struct sh_timer_config tmu1_platform_data = {
 203         .channel_offset = 0xe,
 204         .timer_bit = 1,
 205         .clocksource_rating = 200,
 206 };
 207
 208 static struct resource tmu1_resources[] = {
 209         [0] = {
 210                 .start  = 0xfffffea0,
 211                 .end    = 0xfffffeab,
 212                 .flags  = IORESOURCE_MEM,
 213         },
 214         [1] = {
 215                 .start  = 17,
 216                 .flags  = IORESOURCE_IRQ,
 217         },
 218 };
 219
 220 static struct platform_device tmu1_device = {
 221         .name           = "sh_tmu",
 222         .id             = 1,
 223         .dev = {
 224                 .platform_data  = &tmu1_platform_data,
 225         },
 226         .resource       = tmu1_resources,
 227         .num_resources  = ARRAY_SIZE(tmu1_resources),
 228 };
 229
 230 static struct sh_timer_config tmu2_platform_data = {
 231         .channel_offset = 0x1a,
 232         .timer_bit = 2,
 233 };
 234
 235 static struct resource tmu2_resources[] = {
 236         [0] = {
 237                 .start  = 0xfffffeac,
 238                 .end    = 0xfffffebb,
 239                 .flags  = IORESOURCE_MEM,
 240         },
 241         [1] = {
 242                 .start  = 18,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 static struct platform_device tmu2_device = {
 248         .name           = "sh_tmu",
 249         .id             = 2,
 250         .dev = {
 251                 .platform_data  = &tmu2_platform_data,
 252         },
 253         .resource       = tmu2_resources,
 254         .num_resources  = ARRAY_SIZE(tmu2_resources),
 255 };
 256
 257 static struct platform_device *sh770x_devices[] __initdata = {
 258         &scif0_device,
 259 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 260     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 261     defined(CONFIG_CPU_SUBTYPE_SH7709)
 262         &scif1_device,
 263 #endif
 264 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 265     defined(CONFIG_CPU_SUBTYPE_SH7709)
 266         &scif2_device,
 267 #endif
 268         &tmu0_device,
 269         &tmu1_device,
 270         &tmu2_device,
 271         &rtc_device,
 272 };
 273
 274 static int __init sh770x_devices_setup(void)
 275 {
 276         return platform_add_devices(sh770x_devices,
 277                 ARRAY_SIZE(sh770x_devices));
 278 }
 279 arch_initcall(sh770x_devices_setup);
 280
 281 static struct platform_device *sh770x_early_devices[] __initdata = {
 282         &scif0_device,
 283 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 284     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 285     defined(CONFIG_CPU_SUBTYPE_SH7709)
 286         &scif1_device,
 287 #endif
 288 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 289     defined(CONFIG_CPU_SUBTYPE_SH7709)
 290         &scif2_device,
 291 #endif
 292         &tmu0_device,
 293         &tmu1_device,
 294         &tmu2_device,
 295 };
 296
 297 void __init plat_early_device_setup(void)
 298 {
 299         early_platform_add_devices(sh770x_early_devices,
 300                                    ARRAY_SIZE(sh770x_early_devices));
 301 }
 302
 303 void __init plat_irq_setup(void)
 304 {
 305         register_intc_controller(&intc_desc);
 306 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 307     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 308     defined(CONFIG_CPU_SUBTYPE_SH7709)
 309         plat_irq_setup_sh3();
 310 #endif
 311 }