2 * SH5-101/SH5-103 CPU Setup
4 * Copyright (C) 2009 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
16 #include <linux/sh_timer.h>
17 #include <asm/addrspace.h>
19 static struct plat_sci_port scif0_platform_data
= {
20 .mapbase
= PHYS_PERIPHERAL_BLOCK
+ 0x01030000,
21 .flags
= UPF_BOOT_AUTOCONF
| UPF_IOREMAP
,
22 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
,
23 .scbrr_algo_id
= SCBRR_ALGO_2
,
25 .irqs
= { 39, 40, 42, 0 },
28 static struct platform_device scif0_device
= {
32 .platform_data
= &scif0_platform_data
,
36 static struct resource rtc_resources
[] = {
38 .start
= PHYS_PERIPHERAL_BLOCK
+ 0x01040000,
39 .end
= PHYS_PERIPHERAL_BLOCK
+ 0x01040000 + 0x58 - 1,
40 .flags
= IORESOURCE_IO
,
45 .flags
= IORESOURCE_IRQ
,
50 .flags
= IORESOURCE_IRQ
,
55 .flags
= IORESOURCE_IRQ
,
59 static struct platform_device rtc_device
= {
62 .num_resources
= ARRAY_SIZE(rtc_resources
),
63 .resource
= rtc_resources
,
66 #define TMU_BLOCK_OFF 0x01020000
67 #define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
68 #define TMU0_BASE (TMU_BASE + 0x8 + (0xc * 0x0))
69 #define TMU1_BASE (TMU_BASE + 0x8 + (0xc * 0x1))
70 #define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
72 static struct sh_timer_config tmu0_platform_data
= {
73 .channel_offset
= 0x04,
75 .clockevent_rating
= 200,
78 static struct resource tmu0_resources
[] = {
81 .end
= TMU0_BASE
+ 0xc - 1,
82 .flags
= IORESOURCE_MEM
,
86 .flags
= IORESOURCE_IRQ
,
90 static struct platform_device tmu0_device
= {
94 .platform_data
= &tmu0_platform_data
,
96 .resource
= tmu0_resources
,
97 .num_resources
= ARRAY_SIZE(tmu0_resources
),
100 static struct sh_timer_config tmu1_platform_data
= {
101 .channel_offset
= 0x10,
103 .clocksource_rating
= 200,
106 static struct resource tmu1_resources
[] = {
109 .end
= TMU1_BASE
+ 0xc - 1,
110 .flags
= IORESOURCE_MEM
,
114 .flags
= IORESOURCE_IRQ
,
118 static struct platform_device tmu1_device
= {
122 .platform_data
= &tmu1_platform_data
,
124 .resource
= tmu1_resources
,
125 .num_resources
= ARRAY_SIZE(tmu1_resources
),
128 static struct sh_timer_config tmu2_platform_data
= {
129 .channel_offset
= 0x1c,
133 static struct resource tmu2_resources
[] = {
136 .end
= TMU2_BASE
+ 0xc - 1,
137 .flags
= IORESOURCE_MEM
,
141 .flags
= IORESOURCE_IRQ
,
145 static struct platform_device tmu2_device
= {
149 .platform_data
= &tmu2_platform_data
,
151 .resource
= tmu2_resources
,
152 .num_resources
= ARRAY_SIZE(tmu2_resources
),
155 static struct platform_device
*sh5_early_devices
[] __initdata
= {
162 static struct platform_device
*sh5_devices
[] __initdata
= {
166 static int __init
sh5_devices_setup(void)
170 ret
= platform_add_devices(sh5_early_devices
,
171 ARRAY_SIZE(sh5_early_devices
));
172 if (unlikely(ret
!= 0))
175 return platform_add_devices(sh5_devices
,
176 ARRAY_SIZE(sh5_devices
));
178 arch_initcall(sh5_devices_setup
);
180 void __init
plat_early_device_setup(void)
182 early_platform_add_devices(sh5_early_devices
,
183 ARRAY_SIZE(sh5_early_devices
));