arch/sparc/include/asm/io_64.h

   1 #ifndef __SPARC64_IO_H
   2 #define __SPARC64_IO_H
   3
   4 #include <linux/kernel.h>
   5 #include <linux/compiler.h>
   6 #include <linux/types.h>
   7
   8 #include <asm/page.h>      /* IO address mapping routines need this */
   9 #include <asm/system.h>
  10 #include <asm/asi.h>
  11
  12 /* PC crapola... */
  13 #define __SLOW_DOWN_IO  do { } while (0)
  14 #define SLOW_DOWN_IO    do { } while (0)
  15
  16 /* BIO layer definitions. */
  17 extern unsigned long kern_base, kern_size;
  18 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
  19
  20 static inline u8 _inb(unsigned long addr)
  21 {
  22         u8 ret;
  23
  24         __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
  25                              : "=r" (ret)
  26                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  27                              : "memory");
  28
  29         return ret;
  30 }
  31
  32 static inline u16 _inw(unsigned long addr)
  33 {
  34         u16 ret;
  35
  36         __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
  37                              : "=r" (ret)
  38                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  39                              : "memory");
  40
  41         return ret;
  42 }
  43
  44 static inline u32 _inl(unsigned long addr)
  45 {
  46         u32 ret;
  47
  48         __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
  49                              : "=r" (ret)
  50                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  51                              : "memory");
  52
  53         return ret;
  54 }
  55
  56 static inline void _outb(u8 b, unsigned long addr)
  57 {
  58         __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
  59                              : /* no outputs */
  60                              : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  61                              : "memory");
  62 }
  63
  64 static inline void _outw(u16 w, unsigned long addr)
  65 {
  66         __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
  67                              : /* no outputs */
  68                              : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  69                              : "memory");
  70 }
  71
  72 static inline void _outl(u32 l, unsigned long addr)
  73 {
  74         __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
  75                              : /* no outputs */
  76                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  77                              : "memory");
  78 }
  79
  80 #define inb(__addr)             (_inb((unsigned long)(__addr)))
  81 #define inw(__addr)             (_inw((unsigned long)(__addr)))
  82 #define inl(__addr)             (_inl((unsigned long)(__addr)))
  83 #define outb(__b, __addr)       (_outb((u8)(__b), (unsigned long)(__addr)))
  84 #define outw(__w, __addr)       (_outw((u16)(__w), (unsigned long)(__addr)))
  85 #define outl(__l, __addr)       (_outl((u32)(__l), (unsigned long)(__addr)))
  86
  87 #define inb_p(__addr)           inb(__addr)
  88 #define outb_p(__b, __addr)     outb(__b, __addr)
  89 #define inw_p(__addr)           inw(__addr)
  90 #define outw_p(__w, __addr)     outw(__w, __addr)
  91 #define inl_p(__addr)           inl(__addr)
  92 #define outl_p(__l, __addr)     outl(__l, __addr)
  93
  94 extern void outsb(unsigned long, const void *, unsigned long);
  95 extern void outsw(unsigned long, const void *, unsigned long);
  96 extern void outsl(unsigned long, const void *, unsigned long);
  97 extern void insb(unsigned long, void *, unsigned long);
  98 extern void insw(unsigned long, void *, unsigned long);
  99 extern void insl(unsigned long, void *, unsigned long);
 100
 101 static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
 102 {
 103         insb((unsigned long __force)port, buf, count);
 104 }
 105 static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
 106 {
 107         insw((unsigned long __force)port, buf, count);
 108 }
 109
 110 static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
 111 {
 112         insl((unsigned long __force)port, buf, count);
 113 }
 114
 115 static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
 116 {
 117         outsb((unsigned long __force)port, buf, count);
 118 }
 119
 120 static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
 121 {
 122         outsw((unsigned long __force)port, buf, count);
 123 }
 124
 125 static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
 126 {
 127         outsl((unsigned long __force)port, buf, count);
 128 }
 129
 130 /* Memory functions, same as I/O accesses on Ultra. */
 131 static inline u8 _readb(const volatile void __iomem *addr)
 132 {       u8 ret;
 133
 134         __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
 135                              : "=r" (ret)
 136                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 137                              : "memory");
 138         return ret;
 139 }
 140
 141 static inline u16 _readw(const volatile void __iomem *addr)
 142 {       u16 ret;
 143
 144         __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
 145                              : "=r" (ret)
 146                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 147                              : "memory");
 148
 149         return ret;
 150 }
 151
 152 static inline u32 _readl(const volatile void __iomem *addr)
 153 {       u32 ret;
 154
 155         __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
 156                              : "=r" (ret)
 157                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 158                              : "memory");
 159
 160         return ret;
 161 }
 162
 163 static inline u64 _readq(const volatile void __iomem *addr)
 164 {       u64 ret;
 165
 166         __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
 167                              : "=r" (ret)
 168                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 169                              : "memory");
 170
 171         return ret;
 172 }
 173
 174 static inline void _writeb(u8 b, volatile void __iomem *addr)
 175 {
 176         __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
 177                              : /* no outputs */
 178                              : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 179                              : "memory");
 180 }
 181
 182 static inline void _writew(u16 w, volatile void __iomem *addr)
 183 {
 184         __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
 185                              : /* no outputs */
 186                              : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 187                              : "memory");
 188 }
 189
 190 static inline void _writel(u32 l, volatile void __iomem *addr)
 191 {
 192         __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
 193                              : /* no outputs */
 194                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 195                              : "memory");
 196 }
 197
 198 static inline void _writeq(u64 q, volatile void __iomem *addr)
 199 {
 200         __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
 201                              : /* no outputs */
 202                              : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 203                              : "memory");
 204 }
 205
 206 #define readb(__addr)           _readb(__addr)
 207 #define readw(__addr)           _readw(__addr)
 208 #define readl(__addr)           _readl(__addr)
 209 #define readq(__addr)           _readq(__addr)
 210 #define readb_relaxed(__addr)   _readb(__addr)
 211 #define readw_relaxed(__addr)   _readw(__addr)
 212 #define readl_relaxed(__addr)   _readl(__addr)
 213 #define readq_relaxed(__addr)   _readq(__addr)
 214 #define writeb(__b, __addr)     _writeb(__b, __addr)
 215 #define writew(__w, __addr)     _writew(__w, __addr)
 216 #define writel(__l, __addr)     _writel(__l, __addr)
 217 #define writeq(__q, __addr)     _writeq(__q, __addr)
 218
 219 /* Now versions without byte-swapping. */
 220 static inline u8 _raw_readb(unsigned long addr)
 221 {
 222         u8 ret;
 223
 224         __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
 225                              : "=r" (ret)
 226                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 227
 228         return ret;
 229 }
 230
 231 static inline u16 _raw_readw(unsigned long addr)
 232 {
 233         u16 ret;
 234
 235         __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
 236                              : "=r" (ret)
 237                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 238
 239         return ret;
 240 }
 241
 242 static inline u32 _raw_readl(unsigned long addr)
 243 {
 244         u32 ret;
 245
 246         __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
 247                              : "=r" (ret)
 248                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 249
 250         return ret;
 251 }
 252
 253 static inline u64 _raw_readq(unsigned long addr)
 254 {
 255         u64 ret;
 256
 257         __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
 258                              : "=r" (ret)
 259                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 260
 261         return ret;
 262 }
 263
 264 static inline void _raw_writeb(u8 b, unsigned long addr)
 265 {
 266         __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
 267                              : /* no outputs */
 268                              : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 269 }
 270
 271 static inline void _raw_writew(u16 w, unsigned long addr)
 272 {
 273         __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
 274                              : /* no outputs */
 275                              : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 276 }
 277
 278 static inline void _raw_writel(u32 l, unsigned long addr)
 279 {
 280         __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
 281                              : /* no outputs */
 282                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 283 }
 284
 285 static inline void _raw_writeq(u64 q, unsigned long addr)
 286 {
 287         __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
 288                              : /* no outputs */
 289                              : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 290 }
 291
 292 #define __raw_readb(__addr)             (_raw_readb((unsigned long)(__addr)))
 293 #define __raw_readw(__addr)             (_raw_readw((unsigned long)(__addr)))
 294 #define __raw_readl(__addr)             (_raw_readl((unsigned long)(__addr)))
 295 #define __raw_readq(__addr)             (_raw_readq((unsigned long)(__addr)))
 296 #define __raw_writeb(__b, __addr)       (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
 297 #define __raw_writew(__w, __addr)       (_raw_writew((u16)(__w), (unsigned long)(__addr)))
 298 #define __raw_writel(__l, __addr)       (_raw_writel((u32)(__l), (unsigned long)(__addr)))
 299 #define __raw_writeq(__q, __addr)       (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
 300
 301 /* Valid I/O Space regions are anywhere, because each PCI bus supported
 302  * can live in an arbitrary area of the physical address range.
 303  */
 304 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
 305
 306 /* Now, SBUS variants, only difference from PCI is that we do
 307  * not use little-endian ASIs.
 308  */
 309 static inline u8 _sbus_readb(const volatile void __iomem *addr)
 310 {
 311         u8 ret;
 312
 313         __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
 314                              : "=r" (ret)
 315                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 316                              : "memory");
 317
 318         return ret;
 319 }
 320
 321 static inline u16 _sbus_readw(const volatile void __iomem *addr)
 322 {
 323         u16 ret;
 324
 325         __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
 326                              : "=r" (ret)
 327                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 328                              : "memory");
 329
 330         return ret;
 331 }
 332
 333 static inline u32 _sbus_readl(const volatile void __iomem *addr)
 334 {
 335         u32 ret;
 336
 337         __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
 338                              : "=r" (ret)
 339                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 340                              : "memory");
 341
 342         return ret;
 343 }
 344
 345 static inline u64 _sbus_readq(const volatile void __iomem *addr)
 346 {
 347         u64 ret;
 348
 349         __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
 350                              : "=r" (ret)
 351                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 352                              : "memory");
 353
 354         return ret;
 355 }
 356
 357 static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
 358 {
 359         __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
 360                              : /* no outputs */
 361                              : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 362                              : "memory");
 363 }
 364
 365 static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
 366 {
 367         __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
 368                              : /* no outputs */
 369                              : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 370                              : "memory");
 371 }
 372
 373 static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
 374 {
 375         __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
 376                              : /* no outputs */
 377                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 378                              : "memory");
 379 }
 380
 381 static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
 382 {
 383         __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
 384                              : /* no outputs */
 385                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
 386                              : "memory");
 387 }
 388
 389 #define sbus_readb(__addr)              _sbus_readb(__addr)
 390 #define sbus_readw(__addr)              _sbus_readw(__addr)
 391 #define sbus_readl(__addr)              _sbus_readl(__addr)
 392 #define sbus_readq(__addr)              _sbus_readq(__addr)
 393 #define sbus_writeb(__b, __addr)        _sbus_writeb(__b, __addr)
 394 #define sbus_writew(__w, __addr)        _sbus_writew(__w, __addr)
 395 #define sbus_writel(__l, __addr)        _sbus_writel(__l, __addr)
 396 #define sbus_writeq(__l, __addr)        _sbus_writeq(__l, __addr)
 397
 398 static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
 399 {
 400         while(n--) {
 401                 sbus_writeb(c, dst);
 402                 dst++;
 403         }
 404 }
 405
 406 #define sbus_memset_io(d,c,sz)  _sbus_memset_io(d,c,sz)
 407
 408 static inline void
 409 _memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
 410 {
 411         volatile void __iomem *d = dst;
 412
 413         while (n--) {
 414                 writeb(c, d);
 415                 d++;
 416         }
 417 }
 418
 419 #define memset_io(d,c,sz)       _memset_io(d,c,sz)
 420
 421 static inline void
 422 _sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
 423                     __kernel_size_t n)
 424 {
 425         char *d = dst;
 426
 427         while (n--) {
 428                 char tmp = sbus_readb(src);
 429                 *d++ = tmp;
 430                 src++;
 431         }
 432 }
 433
 434 #define sbus_memcpy_fromio(d, s, sz)    _sbus_memcpy_fromio(d, s, sz)
 435
 436 static inline void
 437 _memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
 438 {
 439         char *d = dst;
 440
 441         while (n--) {
 442                 char tmp = readb(src);
 443                 *d++ = tmp;
 444                 src++;
 445         }
 446 }
 447
 448 #define memcpy_fromio(d,s,sz)   _memcpy_fromio(d,s,sz)
 449
 450 static inline void
 451 _sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
 452                   __kernel_size_t n)
 453 {
 454         const char *s = src;
 455         volatile void __iomem *d = dst;
 456
 457         while (n--) {
 458                 char tmp = *s++;
 459                 sbus_writeb(tmp, d);
 460                 d++;
 461         }
 462 }
 463
 464 #define sbus_memcpy_toio(d, s, sz)      _sbus_memcpy_toio(d, s, sz)
 465
 466 static inline void
 467 _memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
 468 {
 469         const char *s = src;
 470         volatile void __iomem *d = dst;
 471
 472         while (n--) {
 473                 char tmp = *s++;
 474                 writeb(tmp, d);
 475                 d++;
 476         }
 477 }
 478
 479 #define memcpy_toio(d,s,sz)     _memcpy_toio(d,s,sz)
 480
 481 #define mmiowb()
 482
 483 #ifdef __KERNEL__
 484
 485 /* On sparc64 we have the whole physical IO address space accessible
 486  * using physically addressed loads and stores, so this does nothing.
 487  */
 488 static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
 489 {
 490         return (void __iomem *)offset;
 491 }
 492
 493 #define ioremap_nocache(X,Y)            ioremap((X),(Y))
 494 #define ioremap_wc(X,Y)                 ioremap((X),(Y))
 495
 496 static inline void iounmap(volatile void __iomem *addr)
 497 {
 498 }
 499
 500 #define ioread8(X)                      readb(X)
 501 #define ioread16(X)                     readw(X)
 502 #define ioread16be(X)                   __raw_readw(X)
 503 #define ioread32(X)                     readl(X)
 504 #define ioread32be(X)                   __raw_readl(X)
 505 #define iowrite8(val,X)                 writeb(val,X)
 506 #define iowrite16(val,X)                writew(val,X)
 507 #define iowrite16be(val,X)              __raw_writew(val,X)
 508 #define iowrite32(val,X)                writel(val,X)
 509 #define iowrite32be(val,X)              __raw_writel(val,X)
 510
 511 /* Create a virtual mapping cookie for an IO port range */
 512 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 513 extern void ioport_unmap(void __iomem *);
 514
 515 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 516 struct pci_dev;
 517 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 518 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 519
 520 static inline int sbus_can_dma_64bit(void)
 521 {
 522         return 1;
 523 }
 524 static inline int sbus_can_burst64(void)
 525 {
 526         return 1;
 527 }
 528 struct device;
 529 extern void sbus_set_sbus64(struct device *, int);
 530
 531 /*
 532  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 533  * access
 534  */
 535 #define xlate_dev_mem_ptr(p)    __va(p)
 536
 537 /*
 538  * Convert a virtual cached pointer to an uncached pointer
 539  */
 540 #define xlate_dev_kmem_ptr(p)   p
 541
 542 #endif
 543
 544 #endif /* !(__SPARC64_IO_H) */