Merge branch 'for-linus' of git://git.infradead.org/users/sameo/mfd-2.6
[linux-btrfs-devel.git] / drivers / net / bmac.c
blob45e45e8d3d66f86f2c886a88678c56a27302f032
1 /*
2 * Network device driver for the BMAC ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 * Copyright (C) 1998 Randy Gobbel.
7 * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
8 * dynamic procfs inode.
9 */
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/timer.h>
18 #include <linux/proc_fs.h>
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/crc32.h>
22 #include <linux/bitrev.h>
23 #include <linux/ethtool.h>
24 #include <linux/slab.h>
25 #include <asm/prom.h>
26 #include <asm/dbdma.h>
27 #include <asm/io.h>
28 #include <asm/page.h>
29 #include <asm/pgtable.h>
30 #include <asm/machdep.h>
31 #include <asm/pmac_feature.h>
32 #include <asm/macio.h>
33 #include <asm/irq.h>
35 #include "bmac.h"
37 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
38 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
41 * CRC polynomial - used in working out multicast filter bits.
43 #define ENET_CRCPOLY 0x04c11db7
45 /* switch to use multicast code lifted from sunhme driver */
46 #define SUNHME_MULTICAST
48 #define N_RX_RING 64
49 #define N_TX_RING 32
50 #define MAX_TX_ACTIVE 1
51 #define ETHERCRC 4
52 #define ETHERMINPACKET 64
53 #define ETHERMTU 1500
54 #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
55 #define TX_TIMEOUT HZ /* 1 second */
57 /* Bits in transmit DMA status */
58 #define TX_DMA_ERR 0x80
60 #define XXDEBUG(args)
62 struct bmac_data {
63 /* volatile struct bmac *bmac; */
64 struct sk_buff_head *queue;
65 volatile struct dbdma_regs __iomem *tx_dma;
66 int tx_dma_intr;
67 volatile struct dbdma_regs __iomem *rx_dma;
68 int rx_dma_intr;
69 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
70 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
71 struct macio_dev *mdev;
72 int is_bmac_plus;
73 struct sk_buff *rx_bufs[N_RX_RING];
74 int rx_fill;
75 int rx_empty;
76 struct sk_buff *tx_bufs[N_TX_RING];
77 int tx_fill;
78 int tx_empty;
79 unsigned char tx_fullup;
80 struct timer_list tx_timeout;
81 int timeout_active;
82 int sleeping;
83 int opened;
84 unsigned short hash_use_count[64];
85 unsigned short hash_table_mask[4];
86 spinlock_t lock;
89 #if 0 /* Move that to ethtool */
91 typedef struct bmac_reg_entry {
92 char *name;
93 unsigned short reg_offset;
94 } bmac_reg_entry_t;
96 #define N_REG_ENTRIES 31
98 static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
99 {"MEMADD", MEMADD},
100 {"MEMDATAHI", MEMDATAHI},
101 {"MEMDATALO", MEMDATALO},
102 {"TXPNTR", TXPNTR},
103 {"RXPNTR", RXPNTR},
104 {"IPG1", IPG1},
105 {"IPG2", IPG2},
106 {"ALIMIT", ALIMIT},
107 {"SLOT", SLOT},
108 {"PALEN", PALEN},
109 {"PAPAT", PAPAT},
110 {"TXSFD", TXSFD},
111 {"JAM", JAM},
112 {"TXCFG", TXCFG},
113 {"TXMAX", TXMAX},
114 {"TXMIN", TXMIN},
115 {"PAREG", PAREG},
116 {"DCNT", DCNT},
117 {"NCCNT", NCCNT},
118 {"NTCNT", NTCNT},
119 {"EXCNT", EXCNT},
120 {"LTCNT", LTCNT},
121 {"TXSM", TXSM},
122 {"RXCFG", RXCFG},
123 {"RXMAX", RXMAX},
124 {"RXMIN", RXMIN},
125 {"FRCNT", FRCNT},
126 {"AECNT", AECNT},
127 {"FECNT", FECNT},
128 {"RXSM", RXSM},
129 {"RXCV", RXCV}
132 #endif
134 static unsigned char *bmac_emergency_rxbuf;
137 * Number of bytes of private data per BMAC: allow enough for
138 * the rx and tx dma commands plus a branch dma command each,
139 * and another 16 bytes to allow us to align the dma command
140 * buffers on a 16 byte boundary.
142 #define PRIV_BYTES (sizeof(struct bmac_data) \
143 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
144 + sizeof(struct sk_buff_head))
146 static int bmac_open(struct net_device *dev);
147 static int bmac_close(struct net_device *dev);
148 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
149 static void bmac_set_multicast(struct net_device *dev);
150 static void bmac_reset_and_enable(struct net_device *dev);
151 static void bmac_start_chip(struct net_device *dev);
152 static void bmac_init_chip(struct net_device *dev);
153 static void bmac_init_registers(struct net_device *dev);
154 static void bmac_enable_and_reset_chip(struct net_device *dev);
155 static int bmac_set_address(struct net_device *dev, void *addr);
156 static irqreturn_t bmac_misc_intr(int irq, void *dev_id);
157 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id);
158 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id);
159 static void bmac_set_timeout(struct net_device *dev);
160 static void bmac_tx_timeout(unsigned long data);
161 static int bmac_output(struct sk_buff *skb, struct net_device *dev);
162 static void bmac_start(struct net_device *dev);
164 #define DBDMA_SET(x) ( ((x) | (x) << 16) )
165 #define DBDMA_CLEAR(x) ( (x) << 16)
167 static inline void
168 dbdma_st32(volatile __u32 __iomem *a, unsigned long x)
170 __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
173 static inline unsigned long
174 dbdma_ld32(volatile __u32 __iomem *a)
176 __u32 swap;
177 __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
178 return swap;
181 static void
182 dbdma_continue(volatile struct dbdma_regs __iomem *dmap)
184 dbdma_st32(&dmap->control,
185 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
186 eieio();
189 static void
190 dbdma_reset(volatile struct dbdma_regs __iomem *dmap)
192 dbdma_st32(&dmap->control,
193 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
194 eieio();
195 while (dbdma_ld32(&dmap->status) & RUN)
196 eieio();
199 static void
200 dbdma_setcmd(volatile struct dbdma_cmd *cp,
201 unsigned short cmd, unsigned count, unsigned long addr,
202 unsigned long cmd_dep)
204 out_le16(&cp->command, cmd);
205 out_le16(&cp->req_count, count);
206 out_le32(&cp->phy_addr, addr);
207 out_le32(&cp->cmd_dep, cmd_dep);
208 out_le16(&cp->xfer_status, 0);
209 out_le16(&cp->res_count, 0);
212 static inline
213 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
215 out_le16((void __iomem *)dev->base_addr + reg_offset, data);
219 static inline
220 unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
222 return in_le16((void __iomem *)dev->base_addr + reg_offset);
225 static void
226 bmac_enable_and_reset_chip(struct net_device *dev)
228 struct bmac_data *bp = netdev_priv(dev);
229 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
230 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
232 if (rd)
233 dbdma_reset(rd);
234 if (td)
235 dbdma_reset(td);
237 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1);
240 #define MIFDELAY udelay(10)
242 static unsigned int
243 bmac_mif_readbits(struct net_device *dev, int nb)
245 unsigned int val = 0;
247 while (--nb >= 0) {
248 bmwrite(dev, MIFCSR, 0);
249 MIFDELAY;
250 if (bmread(dev, MIFCSR) & 8)
251 val |= 1 << nb;
252 bmwrite(dev, MIFCSR, 1);
253 MIFDELAY;
255 bmwrite(dev, MIFCSR, 0);
256 MIFDELAY;
257 bmwrite(dev, MIFCSR, 1);
258 MIFDELAY;
259 return val;
262 static void
263 bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
265 int b;
267 while (--nb >= 0) {
268 b = (val & (1 << nb))? 6: 4;
269 bmwrite(dev, MIFCSR, b);
270 MIFDELAY;
271 bmwrite(dev, MIFCSR, b|1);
272 MIFDELAY;
276 static unsigned int
277 bmac_mif_read(struct net_device *dev, unsigned int addr)
279 unsigned int val;
281 bmwrite(dev, MIFCSR, 4);
282 MIFDELAY;
283 bmac_mif_writebits(dev, ~0U, 32);
284 bmac_mif_writebits(dev, 6, 4);
285 bmac_mif_writebits(dev, addr, 10);
286 bmwrite(dev, MIFCSR, 2);
287 MIFDELAY;
288 bmwrite(dev, MIFCSR, 1);
289 MIFDELAY;
290 val = bmac_mif_readbits(dev, 17);
291 bmwrite(dev, MIFCSR, 4);
292 MIFDELAY;
293 return val;
296 static void
297 bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
299 bmwrite(dev, MIFCSR, 4);
300 MIFDELAY;
301 bmac_mif_writebits(dev, ~0U, 32);
302 bmac_mif_writebits(dev, 5, 4);
303 bmac_mif_writebits(dev, addr, 10);
304 bmac_mif_writebits(dev, 2, 2);
305 bmac_mif_writebits(dev, val, 16);
306 bmac_mif_writebits(dev, 3, 2);
309 static void
310 bmac_init_registers(struct net_device *dev)
312 struct bmac_data *bp = netdev_priv(dev);
313 volatile unsigned short regValue;
314 unsigned short *pWord16;
315 int i;
317 /* XXDEBUG(("bmac: enter init_registers\n")); */
319 bmwrite(dev, RXRST, RxResetValue);
320 bmwrite(dev, TXRST, TxResetBit);
322 i = 100;
323 do {
324 --i;
325 udelay(10000);
326 regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
327 } while ((regValue & TxResetBit) && i > 0);
329 if (!bp->is_bmac_plus) {
330 regValue = bmread(dev, XCVRIF);
331 regValue |= ClkBit | SerialMode | COLActiveLow;
332 bmwrite(dev, XCVRIF, regValue);
333 udelay(10000);
336 bmwrite(dev, RSEED, (unsigned short)0x1968);
338 regValue = bmread(dev, XIFC);
339 regValue |= TxOutputEnable;
340 bmwrite(dev, XIFC, regValue);
342 bmread(dev, PAREG);
344 /* set collision counters to 0 */
345 bmwrite(dev, NCCNT, 0);
346 bmwrite(dev, NTCNT, 0);
347 bmwrite(dev, EXCNT, 0);
348 bmwrite(dev, LTCNT, 0);
350 /* set rx counters to 0 */
351 bmwrite(dev, FRCNT, 0);
352 bmwrite(dev, LECNT, 0);
353 bmwrite(dev, AECNT, 0);
354 bmwrite(dev, FECNT, 0);
355 bmwrite(dev, RXCV, 0);
357 /* set tx fifo information */
358 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
360 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
361 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
363 /* set rx fifo information */
364 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
365 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
367 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
368 bmread(dev, STATUS); /* read it just to clear it */
370 /* zero out the chip Hash Filter registers */
371 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
372 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
373 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
374 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
375 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
377 pWord16 = (unsigned short *)dev->dev_addr;
378 bmwrite(dev, MADD0, *pWord16++);
379 bmwrite(dev, MADD1, *pWord16++);
380 bmwrite(dev, MADD2, *pWord16);
382 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
384 bmwrite(dev, INTDISABLE, EnableNormal);
387 #if 0
388 static void
389 bmac_disable_interrupts(struct net_device *dev)
391 bmwrite(dev, INTDISABLE, DisableAll);
394 static void
395 bmac_enable_interrupts(struct net_device *dev)
397 bmwrite(dev, INTDISABLE, EnableNormal);
399 #endif
402 static void
403 bmac_start_chip(struct net_device *dev)
405 struct bmac_data *bp = netdev_priv(dev);
406 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
407 unsigned short oldConfig;
409 /* enable rx dma channel */
410 dbdma_continue(rd);
412 oldConfig = bmread(dev, TXCFG);
413 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
415 /* turn on rx plus any other bits already on (promiscuous possibly) */
416 oldConfig = bmread(dev, RXCFG);
417 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
418 udelay(20000);
421 static void
422 bmac_init_phy(struct net_device *dev)
424 unsigned int addr;
425 struct bmac_data *bp = netdev_priv(dev);
427 printk(KERN_DEBUG "phy registers:");
428 for (addr = 0; addr < 32; ++addr) {
429 if ((addr & 7) == 0)
430 printk(KERN_DEBUG);
431 printk(KERN_CONT " %.4x", bmac_mif_read(dev, addr));
433 printk(KERN_CONT "\n");
435 if (bp->is_bmac_plus) {
436 unsigned int capable, ctrl;
438 ctrl = bmac_mif_read(dev, 0);
439 capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
440 if (bmac_mif_read(dev, 4) != capable ||
441 (ctrl & 0x1000) == 0) {
442 bmac_mif_write(dev, 4, capable);
443 bmac_mif_write(dev, 0, 0x1200);
444 } else
445 bmac_mif_write(dev, 0, 0x1000);
449 static void bmac_init_chip(struct net_device *dev)
451 bmac_init_phy(dev);
452 bmac_init_registers(dev);
455 #ifdef CONFIG_PM
456 static int bmac_suspend(struct macio_dev *mdev, pm_message_t state)
458 struct net_device* dev = macio_get_drvdata(mdev);
459 struct bmac_data *bp = netdev_priv(dev);
460 unsigned long flags;
461 unsigned short config;
462 int i;
464 netif_device_detach(dev);
465 /* prolly should wait for dma to finish & turn off the chip */
466 spin_lock_irqsave(&bp->lock, flags);
467 if (bp->timeout_active) {
468 del_timer(&bp->tx_timeout);
469 bp->timeout_active = 0;
471 disable_irq(dev->irq);
472 disable_irq(bp->tx_dma_intr);
473 disable_irq(bp->rx_dma_intr);
474 bp->sleeping = 1;
475 spin_unlock_irqrestore(&bp->lock, flags);
476 if (bp->opened) {
477 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
478 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
480 config = bmread(dev, RXCFG);
481 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
482 config = bmread(dev, TXCFG);
483 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
484 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
485 /* disable rx and tx dma */
486 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
487 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
488 /* free some skb's */
489 for (i=0; i<N_RX_RING; i++) {
490 if (bp->rx_bufs[i] != NULL) {
491 dev_kfree_skb(bp->rx_bufs[i]);
492 bp->rx_bufs[i] = NULL;
495 for (i = 0; i<N_TX_RING; i++) {
496 if (bp->tx_bufs[i] != NULL) {
497 dev_kfree_skb(bp->tx_bufs[i]);
498 bp->tx_bufs[i] = NULL;
502 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
503 return 0;
506 static int bmac_resume(struct macio_dev *mdev)
508 struct net_device* dev = macio_get_drvdata(mdev);
509 struct bmac_data *bp = netdev_priv(dev);
511 /* see if this is enough */
512 if (bp->opened)
513 bmac_reset_and_enable(dev);
515 enable_irq(dev->irq);
516 enable_irq(bp->tx_dma_intr);
517 enable_irq(bp->rx_dma_intr);
518 netif_device_attach(dev);
520 return 0;
522 #endif /* CONFIG_PM */
524 static int bmac_set_address(struct net_device *dev, void *addr)
526 struct bmac_data *bp = netdev_priv(dev);
527 unsigned char *p = addr;
528 unsigned short *pWord16;
529 unsigned long flags;
530 int i;
532 XXDEBUG(("bmac: enter set_address\n"));
533 spin_lock_irqsave(&bp->lock, flags);
535 for (i = 0; i < 6; ++i) {
536 dev->dev_addr[i] = p[i];
538 /* load up the hardware address */
539 pWord16 = (unsigned short *)dev->dev_addr;
540 bmwrite(dev, MADD0, *pWord16++);
541 bmwrite(dev, MADD1, *pWord16++);
542 bmwrite(dev, MADD2, *pWord16);
544 spin_unlock_irqrestore(&bp->lock, flags);
545 XXDEBUG(("bmac: exit set_address\n"));
546 return 0;
549 static inline void bmac_set_timeout(struct net_device *dev)
551 struct bmac_data *bp = netdev_priv(dev);
552 unsigned long flags;
554 spin_lock_irqsave(&bp->lock, flags);
555 if (bp->timeout_active)
556 del_timer(&bp->tx_timeout);
557 bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
558 bp->tx_timeout.function = bmac_tx_timeout;
559 bp->tx_timeout.data = (unsigned long) dev;
560 add_timer(&bp->tx_timeout);
561 bp->timeout_active = 1;
562 spin_unlock_irqrestore(&bp->lock, flags);
565 static void
566 bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
568 void *vaddr;
569 unsigned long baddr;
570 unsigned long len;
572 len = skb->len;
573 vaddr = skb->data;
574 baddr = virt_to_bus(vaddr);
576 dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
579 static void
580 bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
582 unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf;
584 dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN,
585 virt_to_bus(addr), 0);
588 static void
589 bmac_init_tx_ring(struct bmac_data *bp)
591 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
593 memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
595 bp->tx_empty = 0;
596 bp->tx_fill = 0;
597 bp->tx_fullup = 0;
599 /* put a branch at the end of the tx command list */
600 dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
601 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
603 /* reset tx dma */
604 dbdma_reset(td);
605 out_le32(&td->wait_sel, 0x00200020);
606 out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
609 static int
610 bmac_init_rx_ring(struct bmac_data *bp)
612 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
613 int i;
614 struct sk_buff *skb;
616 /* initialize list of sk_buffs for receiving and set up recv dma */
617 memset((char *)bp->rx_cmds, 0,
618 (N_RX_RING + 1) * sizeof(struct dbdma_cmd));
619 for (i = 0; i < N_RX_RING; i++) {
620 if ((skb = bp->rx_bufs[i]) == NULL) {
621 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
622 if (skb != NULL)
623 skb_reserve(skb, 2);
625 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
628 bp->rx_empty = 0;
629 bp->rx_fill = i;
631 /* Put a branch back to the beginning of the receive command list */
632 dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
633 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
635 /* start rx dma */
636 dbdma_reset(rd);
637 out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
639 return 1;
643 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
645 struct bmac_data *bp = netdev_priv(dev);
646 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
647 int i;
649 /* see if there's a free slot in the tx ring */
650 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
651 /* bp->tx_empty, bp->tx_fill)); */
652 i = bp->tx_fill + 1;
653 if (i >= N_TX_RING)
654 i = 0;
655 if (i == bp->tx_empty) {
656 netif_stop_queue(dev);
657 bp->tx_fullup = 1;
658 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
659 return -1; /* can't take it at the moment */
662 dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
664 bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
666 bp->tx_bufs[bp->tx_fill] = skb;
667 bp->tx_fill = i;
669 dev->stats.tx_bytes += skb->len;
671 dbdma_continue(td);
673 return 0;
676 static int rxintcount;
678 static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id)
680 struct net_device *dev = (struct net_device *) dev_id;
681 struct bmac_data *bp = netdev_priv(dev);
682 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
683 volatile struct dbdma_cmd *cp;
684 int i, nb, stat;
685 struct sk_buff *skb;
686 unsigned int residual;
687 int last;
688 unsigned long flags;
690 spin_lock_irqsave(&bp->lock, flags);
692 if (++rxintcount < 10) {
693 XXDEBUG(("bmac_rxdma_intr\n"));
696 last = -1;
697 i = bp->rx_empty;
699 while (1) {
700 cp = &bp->rx_cmds[i];
701 stat = ld_le16(&cp->xfer_status);
702 residual = ld_le16(&cp->res_count);
703 if ((stat & ACTIVE) == 0)
704 break;
705 nb = RX_BUFLEN - residual - 2;
706 if (nb < (ETHERMINPACKET - ETHERCRC)) {
707 skb = NULL;
708 dev->stats.rx_length_errors++;
709 dev->stats.rx_errors++;
710 } else {
711 skb = bp->rx_bufs[i];
712 bp->rx_bufs[i] = NULL;
714 if (skb != NULL) {
715 nb -= ETHERCRC;
716 skb_put(skb, nb);
717 skb->protocol = eth_type_trans(skb, dev);
718 netif_rx(skb);
719 ++dev->stats.rx_packets;
720 dev->stats.rx_bytes += nb;
721 } else {
722 ++dev->stats.rx_dropped;
724 if ((skb = bp->rx_bufs[i]) == NULL) {
725 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
726 if (skb != NULL)
727 skb_reserve(bp->rx_bufs[i], 2);
729 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
730 st_le16(&cp->res_count, 0);
731 st_le16(&cp->xfer_status, 0);
732 last = i;
733 if (++i >= N_RX_RING) i = 0;
736 if (last != -1) {
737 bp->rx_fill = last;
738 bp->rx_empty = i;
741 dbdma_continue(rd);
742 spin_unlock_irqrestore(&bp->lock, flags);
744 if (rxintcount < 10) {
745 XXDEBUG(("bmac_rxdma_intr done\n"));
747 return IRQ_HANDLED;
750 static int txintcount;
752 static irqreturn_t bmac_txdma_intr(int irq, void *dev_id)
754 struct net_device *dev = (struct net_device *) dev_id;
755 struct bmac_data *bp = netdev_priv(dev);
756 volatile struct dbdma_cmd *cp;
757 int stat;
758 unsigned long flags;
760 spin_lock_irqsave(&bp->lock, flags);
762 if (txintcount++ < 10) {
763 XXDEBUG(("bmac_txdma_intr\n"));
766 /* del_timer(&bp->tx_timeout); */
767 /* bp->timeout_active = 0; */
769 while (1) {
770 cp = &bp->tx_cmds[bp->tx_empty];
771 stat = ld_le16(&cp->xfer_status);
772 if (txintcount < 10) {
773 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
775 if (!(stat & ACTIVE)) {
777 * status field might not have been filled by DBDMA
779 if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
780 break;
783 if (bp->tx_bufs[bp->tx_empty]) {
784 ++dev->stats.tx_packets;
785 dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]);
787 bp->tx_bufs[bp->tx_empty] = NULL;
788 bp->tx_fullup = 0;
789 netif_wake_queue(dev);
790 if (++bp->tx_empty >= N_TX_RING)
791 bp->tx_empty = 0;
792 if (bp->tx_empty == bp->tx_fill)
793 break;
796 spin_unlock_irqrestore(&bp->lock, flags);
798 if (txintcount < 10) {
799 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
802 bmac_start(dev);
803 return IRQ_HANDLED;
806 #ifndef SUNHME_MULTICAST
807 /* Real fast bit-reversal algorithm, 6-bit values */
808 static int reverse6[64] = {
809 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
810 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
811 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
812 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
813 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
814 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
815 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
816 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
819 static unsigned int
820 crc416(unsigned int curval, unsigned short nxtval)
822 register unsigned int counter, cur = curval, next = nxtval;
823 register int high_crc_set, low_data_set;
825 /* Swap bytes */
826 next = ((next & 0x00FF) << 8) | (next >> 8);
828 /* Compute bit-by-bit */
829 for (counter = 0; counter < 16; ++counter) {
830 /* is high CRC bit set? */
831 if ((cur & 0x80000000) == 0) high_crc_set = 0;
832 else high_crc_set = 1;
834 cur = cur << 1;
836 if ((next & 0x0001) == 0) low_data_set = 0;
837 else low_data_set = 1;
839 next = next >> 1;
841 /* do the XOR */
842 if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY;
844 return cur;
847 static unsigned int
848 bmac_crc(unsigned short *address)
850 unsigned int newcrc;
852 XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2]));
853 newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */
854 newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */
855 newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */
857 return(newcrc);
861 * Add requested mcast addr to BMac's hash table filter.
865 static void
866 bmac_addhash(struct bmac_data *bp, unsigned char *addr)
868 unsigned int crc;
869 unsigned short mask;
871 if (!(*addr)) return;
872 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
873 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
874 if (bp->hash_use_count[crc]++) return; /* This bit is already set */
875 mask = crc % 16;
876 mask = (unsigned char)1 << mask;
877 bp->hash_use_count[crc/16] |= mask;
880 static void
881 bmac_removehash(struct bmac_data *bp, unsigned char *addr)
883 unsigned int crc;
884 unsigned char mask;
886 /* Now, delete the address from the filter copy, as indicated */
887 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
888 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
889 if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
890 if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
891 mask = crc % 16;
892 mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
893 bp->hash_table_mask[crc/16] &= mask;
897 * Sync the adapter with the software copy of the multicast mask
898 * (logical address filter).
901 static void
902 bmac_rx_off(struct net_device *dev)
904 unsigned short rx_cfg;
906 rx_cfg = bmread(dev, RXCFG);
907 rx_cfg &= ~RxMACEnable;
908 bmwrite(dev, RXCFG, rx_cfg);
909 do {
910 rx_cfg = bmread(dev, RXCFG);
911 } while (rx_cfg & RxMACEnable);
914 unsigned short
915 bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
917 unsigned short rx_cfg;
919 rx_cfg = bmread(dev, RXCFG);
920 rx_cfg |= RxMACEnable;
921 if (hash_enable) rx_cfg |= RxHashFilterEnable;
922 else rx_cfg &= ~RxHashFilterEnable;
923 if (promisc_enable) rx_cfg |= RxPromiscEnable;
924 else rx_cfg &= ~RxPromiscEnable;
925 bmwrite(dev, RXRST, RxResetValue);
926 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
927 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
928 bmwrite(dev, RXCFG, rx_cfg );
929 return rx_cfg;
932 static void
933 bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
935 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
936 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
937 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
938 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
941 #if 0
942 static void
943 bmac_add_multi(struct net_device *dev,
944 struct bmac_data *bp, unsigned char *addr)
946 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
947 bmac_addhash(bp, addr);
948 bmac_rx_off(dev);
949 bmac_update_hash_table_mask(dev, bp);
950 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
951 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
954 static void
955 bmac_remove_multi(struct net_device *dev,
956 struct bmac_data *bp, unsigned char *addr)
958 bmac_removehash(bp, addr);
959 bmac_rx_off(dev);
960 bmac_update_hash_table_mask(dev, bp);
961 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
963 #endif
965 /* Set or clear the multicast filter for this adaptor.
966 num_addrs == -1 Promiscuous mode, receive all packets
967 num_addrs == 0 Normal mode, clear multicast list
968 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
969 best-effort filtering.
971 static void bmac_set_multicast(struct net_device *dev)
973 struct netdev_hw_addr *ha;
974 struct bmac_data *bp = netdev_priv(dev);
975 int num_addrs = netdev_mc_count(dev);
976 unsigned short rx_cfg;
977 int i;
979 if (bp->sleeping)
980 return;
982 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
984 if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
985 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
986 bmac_update_hash_table_mask(dev, bp);
987 rx_cfg = bmac_rx_on(dev, 1, 0);
988 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
989 } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
990 rx_cfg = bmread(dev, RXCFG);
991 rx_cfg |= RxPromiscEnable;
992 bmwrite(dev, RXCFG, rx_cfg);
993 rx_cfg = bmac_rx_on(dev, 0, 1);
994 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
995 } else {
996 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
997 for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
998 if (num_addrs == 0) {
999 rx_cfg = bmac_rx_on(dev, 0, 0);
1000 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
1001 } else {
1002 netdev_for_each_mc_addr(ha, dev)
1003 bmac_addhash(bp, ha->addr);
1004 bmac_update_hash_table_mask(dev, bp);
1005 rx_cfg = bmac_rx_on(dev, 1, 0);
1006 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
1009 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
1011 #else /* ifdef SUNHME_MULTICAST */
1013 /* The version of set_multicast below was lifted from sunhme.c */
1015 static void bmac_set_multicast(struct net_device *dev)
1017 struct netdev_hw_addr *ha;
1018 int i;
1019 unsigned short rx_cfg;
1020 u32 crc;
1022 if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
1023 bmwrite(dev, BHASH0, 0xffff);
1024 bmwrite(dev, BHASH1, 0xffff);
1025 bmwrite(dev, BHASH2, 0xffff);
1026 bmwrite(dev, BHASH3, 0xffff);
1027 } else if(dev->flags & IFF_PROMISC) {
1028 rx_cfg = bmread(dev, RXCFG);
1029 rx_cfg |= RxPromiscEnable;
1030 bmwrite(dev, RXCFG, rx_cfg);
1031 } else {
1032 u16 hash_table[4];
1034 rx_cfg = bmread(dev, RXCFG);
1035 rx_cfg &= ~RxPromiscEnable;
1036 bmwrite(dev, RXCFG, rx_cfg);
1038 for(i = 0; i < 4; i++) hash_table[i] = 0;
1040 netdev_for_each_mc_addr(ha, dev) {
1041 crc = ether_crc_le(6, ha->addr);
1042 crc >>= 26;
1043 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1045 bmwrite(dev, BHASH0, hash_table[0]);
1046 bmwrite(dev, BHASH1, hash_table[1]);
1047 bmwrite(dev, BHASH2, hash_table[2]);
1048 bmwrite(dev, BHASH3, hash_table[3]);
1051 #endif /* SUNHME_MULTICAST */
1053 static int miscintcount;
1055 static irqreturn_t bmac_misc_intr(int irq, void *dev_id)
1057 struct net_device *dev = (struct net_device *) dev_id;
1058 unsigned int status = bmread(dev, STATUS);
1059 if (miscintcount++ < 10) {
1060 XXDEBUG(("bmac_misc_intr\n"));
1062 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
1063 /* bmac_txdma_intr_inner(irq, dev_id); */
1064 /* if (status & FrameReceived) dev->stats.rx_dropped++; */
1065 if (status & RxErrorMask) dev->stats.rx_errors++;
1066 if (status & RxCRCCntExp) dev->stats.rx_crc_errors++;
1067 if (status & RxLenCntExp) dev->stats.rx_length_errors++;
1068 if (status & RxOverFlow) dev->stats.rx_over_errors++;
1069 if (status & RxAlignCntExp) dev->stats.rx_frame_errors++;
1071 /* if (status & FrameSent) dev->stats.tx_dropped++; */
1072 if (status & TxErrorMask) dev->stats.tx_errors++;
1073 if (status & TxUnderrun) dev->stats.tx_fifo_errors++;
1074 if (status & TxNormalCollExp) dev->stats.collisions++;
1075 return IRQ_HANDLED;
1079 * Procedure for reading EEPROM
1081 #define SROMAddressLength 5
1082 #define DataInOn 0x0008
1083 #define DataInOff 0x0000
1084 #define Clk 0x0002
1085 #define ChipSelect 0x0001
1086 #define SDIShiftCount 3
1087 #define SD0ShiftCount 2
1088 #define DelayValue 1000 /* number of microseconds */
1089 #define SROMStartOffset 10 /* this is in words */
1090 #define SROMReadCount 3 /* number of words to read from SROM */
1091 #define SROMAddressBits 6
1092 #define EnetAddressOffset 20
1094 static unsigned char
1095 bmac_clock_out_bit(struct net_device *dev)
1097 unsigned short data;
1098 unsigned short val;
1100 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1101 udelay(DelayValue);
1103 data = bmread(dev, SROMCSR);
1104 udelay(DelayValue);
1105 val = (data >> SD0ShiftCount) & 1;
1107 bmwrite(dev, SROMCSR, ChipSelect);
1108 udelay(DelayValue);
1110 return val;
1113 static void
1114 bmac_clock_in_bit(struct net_device *dev, unsigned int val)
1116 unsigned short data;
1118 if (val != 0 && val != 1) return;
1120 data = (val << SDIShiftCount);
1121 bmwrite(dev, SROMCSR, data | ChipSelect );
1122 udelay(DelayValue);
1124 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1125 udelay(DelayValue);
1127 bmwrite(dev, SROMCSR, data | ChipSelect);
1128 udelay(DelayValue);
1131 static void
1132 reset_and_select_srom(struct net_device *dev)
1134 /* first reset */
1135 bmwrite(dev, SROMCSR, 0);
1136 udelay(DelayValue);
1138 /* send it the read command (110) */
1139 bmac_clock_in_bit(dev, 1);
1140 bmac_clock_in_bit(dev, 1);
1141 bmac_clock_in_bit(dev, 0);
1144 static unsigned short
1145 read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
1147 unsigned short data, val;
1148 int i;
1150 /* send out the address we want to read from */
1151 for (i = 0; i < addr_len; i++) {
1152 val = addr >> (addr_len-i-1);
1153 bmac_clock_in_bit(dev, val & 1);
1156 /* Now read in the 16-bit data */
1157 data = 0;
1158 for (i = 0; i < 16; i++) {
1159 val = bmac_clock_out_bit(dev);
1160 data <<= 1;
1161 data |= val;
1163 bmwrite(dev, SROMCSR, 0);
1165 return data;
1169 * It looks like Cogent and SMC use different methods for calculating
1170 * checksums. What a pain..
1173 static int
1174 bmac_verify_checksum(struct net_device *dev)
1176 unsigned short data, storedCS;
1178 reset_and_select_srom(dev);
1179 data = read_srom(dev, 3, SROMAddressBits);
1180 storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
1182 return 0;
1186 static void
1187 bmac_get_station_address(struct net_device *dev, unsigned char *ea)
1189 int i;
1190 unsigned short data;
1192 for (i = 0; i < 6; i++)
1194 reset_and_select_srom(dev);
1195 data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
1196 ea[2*i] = bitrev8(data & 0x0ff);
1197 ea[2*i+1] = bitrev8((data >> 8) & 0x0ff);
1201 static void bmac_reset_and_enable(struct net_device *dev)
1203 struct bmac_data *bp = netdev_priv(dev);
1204 unsigned long flags;
1205 struct sk_buff *skb;
1206 unsigned char *data;
1208 spin_lock_irqsave(&bp->lock, flags);
1209 bmac_enable_and_reset_chip(dev);
1210 bmac_init_tx_ring(bp);
1211 bmac_init_rx_ring(bp);
1212 bmac_init_chip(dev);
1213 bmac_start_chip(dev);
1214 bmwrite(dev, INTDISABLE, EnableNormal);
1215 bp->sleeping = 0;
1218 * It seems that the bmac can't receive until it's transmitted
1219 * a packet. So we give it a dummy packet to transmit.
1221 skb = dev_alloc_skb(ETHERMINPACKET);
1222 if (skb != NULL) {
1223 data = skb_put(skb, ETHERMINPACKET);
1224 memset(data, 0, ETHERMINPACKET);
1225 memcpy(data, dev->dev_addr, 6);
1226 memcpy(data+6, dev->dev_addr, 6);
1227 bmac_transmit_packet(skb, dev);
1229 spin_unlock_irqrestore(&bp->lock, flags);
1232 static const struct ethtool_ops bmac_ethtool_ops = {
1233 .get_link = ethtool_op_get_link,
1236 static const struct net_device_ops bmac_netdev_ops = {
1237 .ndo_open = bmac_open,
1238 .ndo_stop = bmac_close,
1239 .ndo_start_xmit = bmac_output,
1240 .ndo_set_multicast_list = bmac_set_multicast,
1241 .ndo_set_mac_address = bmac_set_address,
1242 .ndo_change_mtu = eth_change_mtu,
1243 .ndo_validate_addr = eth_validate_addr,
1246 static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
1248 int j, rev, ret;
1249 struct bmac_data *bp;
1250 const unsigned char *prop_addr;
1251 unsigned char addr[6];
1252 struct net_device *dev;
1253 int is_bmac_plus = ((int)match->data) != 0;
1255 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
1256 printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n");
1257 return -ENODEV;
1259 prop_addr = of_get_property(macio_get_of_node(mdev),
1260 "mac-address", NULL);
1261 if (prop_addr == NULL) {
1262 prop_addr = of_get_property(macio_get_of_node(mdev),
1263 "local-mac-address", NULL);
1264 if (prop_addr == NULL) {
1265 printk(KERN_ERR "BMAC: Can't get mac-address\n");
1266 return -ENODEV;
1269 memcpy(addr, prop_addr, sizeof(addr));
1271 dev = alloc_etherdev(PRIV_BYTES);
1272 if (!dev) {
1273 printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n");
1274 return -ENOMEM;
1277 bp = netdev_priv(dev);
1278 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
1279 macio_set_drvdata(mdev, dev);
1281 bp->mdev = mdev;
1282 spin_lock_init(&bp->lock);
1284 if (macio_request_resources(mdev, "bmac")) {
1285 printk(KERN_ERR "BMAC: can't request IO resource !\n");
1286 goto out_free;
1289 dev->base_addr = (unsigned long)
1290 ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0));
1291 if (dev->base_addr == 0)
1292 goto out_release;
1294 dev->irq = macio_irq(mdev, 0);
1296 bmac_enable_and_reset_chip(dev);
1297 bmwrite(dev, INTDISABLE, DisableAll);
1299 rev = addr[0] == 0 && addr[1] == 0xA0;
1300 for (j = 0; j < 6; ++j)
1301 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
1303 /* Enable chip without interrupts for now */
1304 bmac_enable_and_reset_chip(dev);
1305 bmwrite(dev, INTDISABLE, DisableAll);
1307 dev->netdev_ops = &bmac_netdev_ops;
1308 dev->ethtool_ops = &bmac_ethtool_ops;
1310 bmac_get_station_address(dev, addr);
1311 if (bmac_verify_checksum(dev) != 0)
1312 goto err_out_iounmap;
1314 bp->is_bmac_plus = is_bmac_plus;
1315 bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1));
1316 if (!bp->tx_dma)
1317 goto err_out_iounmap;
1318 bp->tx_dma_intr = macio_irq(mdev, 1);
1319 bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2));
1320 if (!bp->rx_dma)
1321 goto err_out_iounmap_tx;
1322 bp->rx_dma_intr = macio_irq(mdev, 2);
1324 bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
1325 bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
1327 bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
1328 skb_queue_head_init(bp->queue);
1330 init_timer(&bp->tx_timeout);
1332 ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev);
1333 if (ret) {
1334 printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
1335 goto err_out_iounmap_rx;
1337 ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev);
1338 if (ret) {
1339 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr);
1340 goto err_out_irq0;
1342 ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev);
1343 if (ret) {
1344 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr);
1345 goto err_out_irq1;
1348 /* Mask chip interrupts and disable chip, will be
1349 * re-enabled on open()
1351 disable_irq(dev->irq);
1352 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1354 if (register_netdev(dev) != 0) {
1355 printk(KERN_ERR "BMAC: Ethernet registration failed\n");
1356 goto err_out_irq2;
1359 printk(KERN_INFO "%s: BMAC%s at %pM",
1360 dev->name, (is_bmac_plus ? "+" : ""), dev->dev_addr);
1361 XXDEBUG((", base_addr=%#0lx", dev->base_addr));
1362 printk("\n");
1364 return 0;
1366 err_out_irq2:
1367 free_irq(bp->rx_dma_intr, dev);
1368 err_out_irq1:
1369 free_irq(bp->tx_dma_intr, dev);
1370 err_out_irq0:
1371 free_irq(dev->irq, dev);
1372 err_out_iounmap_rx:
1373 iounmap(bp->rx_dma);
1374 err_out_iounmap_tx:
1375 iounmap(bp->tx_dma);
1376 err_out_iounmap:
1377 iounmap((void __iomem *)dev->base_addr);
1378 out_release:
1379 macio_release_resources(mdev);
1380 out_free:
1381 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1382 free_netdev(dev);
1384 return -ENODEV;
1387 static int bmac_open(struct net_device *dev)
1389 struct bmac_data *bp = netdev_priv(dev);
1390 /* XXDEBUG(("bmac: enter open\n")); */
1391 /* reset the chip */
1392 bp->opened = 1;
1393 bmac_reset_and_enable(dev);
1394 enable_irq(dev->irq);
1395 return 0;
1398 static int bmac_close(struct net_device *dev)
1400 struct bmac_data *bp = netdev_priv(dev);
1401 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1402 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1403 unsigned short config;
1404 int i;
1406 bp->sleeping = 1;
1408 /* disable rx and tx */
1409 config = bmread(dev, RXCFG);
1410 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1412 config = bmread(dev, TXCFG);
1413 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1415 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1417 /* disable rx and tx dma */
1418 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1419 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1421 /* free some skb's */
1422 XXDEBUG(("bmac: free rx bufs\n"));
1423 for (i=0; i<N_RX_RING; i++) {
1424 if (bp->rx_bufs[i] != NULL) {
1425 dev_kfree_skb(bp->rx_bufs[i]);
1426 bp->rx_bufs[i] = NULL;
1429 XXDEBUG(("bmac: free tx bufs\n"));
1430 for (i = 0; i<N_TX_RING; i++) {
1431 if (bp->tx_bufs[i] != NULL) {
1432 dev_kfree_skb(bp->tx_bufs[i]);
1433 bp->tx_bufs[i] = NULL;
1436 XXDEBUG(("bmac: all bufs freed\n"));
1438 bp->opened = 0;
1439 disable_irq(dev->irq);
1440 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1442 return 0;
1445 static void
1446 bmac_start(struct net_device *dev)
1448 struct bmac_data *bp = netdev_priv(dev);
1449 int i;
1450 struct sk_buff *skb;
1451 unsigned long flags;
1453 if (bp->sleeping)
1454 return;
1456 spin_lock_irqsave(&bp->lock, flags);
1457 while (1) {
1458 i = bp->tx_fill + 1;
1459 if (i >= N_TX_RING)
1460 i = 0;
1461 if (i == bp->tx_empty)
1462 break;
1463 skb = skb_dequeue(bp->queue);
1464 if (skb == NULL)
1465 break;
1466 bmac_transmit_packet(skb, dev);
1468 spin_unlock_irqrestore(&bp->lock, flags);
1471 static int
1472 bmac_output(struct sk_buff *skb, struct net_device *dev)
1474 struct bmac_data *bp = netdev_priv(dev);
1475 skb_queue_tail(bp->queue, skb);
1476 bmac_start(dev);
1477 return NETDEV_TX_OK;
1480 static void bmac_tx_timeout(unsigned long data)
1482 struct net_device *dev = (struct net_device *) data;
1483 struct bmac_data *bp = netdev_priv(dev);
1484 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1485 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1486 volatile struct dbdma_cmd *cp;
1487 unsigned long flags;
1488 unsigned short config, oldConfig;
1489 int i;
1491 XXDEBUG(("bmac: tx_timeout called\n"));
1492 spin_lock_irqsave(&bp->lock, flags);
1493 bp->timeout_active = 0;
1495 /* update various counters */
1496 /* bmac_handle_misc_intrs(bp, 0); */
1498 cp = &bp->tx_cmds[bp->tx_empty];
1499 /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1500 /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
1501 /* mb->pr, mb->xmtfs, mb->fifofc)); */
1503 /* turn off both tx and rx and reset the chip */
1504 config = bmread(dev, RXCFG);
1505 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1506 config = bmread(dev, TXCFG);
1507 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1508 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1509 printk(KERN_ERR "bmac: transmit timeout - resetting\n");
1510 bmac_enable_and_reset_chip(dev);
1512 /* restart rx dma */
1513 cp = bus_to_virt(ld_le32(&rd->cmdptr));
1514 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1515 out_le16(&cp->xfer_status, 0);
1516 out_le32(&rd->cmdptr, virt_to_bus(cp));
1517 out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
1519 /* fix up the transmit side */
1520 XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
1521 bp->tx_empty, bp->tx_fill, bp->tx_fullup));
1522 i = bp->tx_empty;
1523 ++dev->stats.tx_errors;
1524 if (i != bp->tx_fill) {
1525 dev_kfree_skb(bp->tx_bufs[i]);
1526 bp->tx_bufs[i] = NULL;
1527 if (++i >= N_TX_RING) i = 0;
1528 bp->tx_empty = i;
1530 bp->tx_fullup = 0;
1531 netif_wake_queue(dev);
1532 if (i != bp->tx_fill) {
1533 cp = &bp->tx_cmds[i];
1534 out_le16(&cp->xfer_status, 0);
1535 out_le16(&cp->command, OUTPUT_LAST);
1536 out_le32(&td->cmdptr, virt_to_bus(cp));
1537 out_le32(&td->control, DBDMA_SET(RUN));
1538 /* bmac_set_timeout(dev); */
1539 XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
1542 /* turn it back on */
1543 oldConfig = bmread(dev, RXCFG);
1544 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1545 oldConfig = bmread(dev, TXCFG);
1546 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
1548 spin_unlock_irqrestore(&bp->lock, flags);
1551 #if 0
1552 static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
1554 int i,*ip;
1556 for (i=0;i< count;i++) {
1557 ip = (int*)(cp+i);
1559 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1560 ld_le32(ip+0),
1561 ld_le32(ip+1),
1562 ld_le32(ip+2),
1563 ld_le32(ip+3));
1567 #endif
1569 #if 0
1570 static int
1571 bmac_proc_info(char *buffer, char **start, off_t offset, int length)
1573 int len = 0;
1574 off_t pos = 0;
1575 off_t begin = 0;
1576 int i;
1578 if (bmac_devs == NULL)
1579 return -ENOSYS;
1581 len += sprintf(buffer, "BMAC counters & registers\n");
1583 for (i = 0; i<N_REG_ENTRIES; i++) {
1584 len += sprintf(buffer + len, "%s: %#08x\n",
1585 reg_entries[i].name,
1586 bmread(bmac_devs, reg_entries[i].reg_offset));
1587 pos = begin + len;
1589 if (pos < offset) {
1590 len = 0;
1591 begin = pos;
1594 if (pos > offset+length) break;
1597 *start = buffer + (offset - begin);
1598 len -= (offset - begin);
1600 if (len > length) len = length;
1602 return len;
1604 #endif
1606 static int __devexit bmac_remove(struct macio_dev *mdev)
1608 struct net_device *dev = macio_get_drvdata(mdev);
1609 struct bmac_data *bp = netdev_priv(dev);
1611 unregister_netdev(dev);
1613 free_irq(dev->irq, dev);
1614 free_irq(bp->tx_dma_intr, dev);
1615 free_irq(bp->rx_dma_intr, dev);
1617 iounmap((void __iomem *)dev->base_addr);
1618 iounmap(bp->tx_dma);
1619 iounmap(bp->rx_dma);
1621 macio_release_resources(mdev);
1623 free_netdev(dev);
1625 return 0;
1628 static struct of_device_id bmac_match[] =
1631 .name = "bmac",
1632 .data = (void *)0,
1635 .type = "network",
1636 .compatible = "bmac+",
1637 .data = (void *)1,
1641 MODULE_DEVICE_TABLE (of, bmac_match);
1643 static struct macio_driver bmac_driver =
1645 .driver = {
1646 .name = "bmac",
1647 .owner = THIS_MODULE,
1648 .of_match_table = bmac_match,
1650 .probe = bmac_probe,
1651 .remove = bmac_remove,
1652 #ifdef CONFIG_PM
1653 .suspend = bmac_suspend,
1654 .resume = bmac_resume,
1655 #endif
1659 static int __init bmac_init(void)
1661 if (bmac_emergency_rxbuf == NULL) {
1662 bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL);
1663 if (bmac_emergency_rxbuf == NULL) {
1664 printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n");
1665 return -ENOMEM;
1669 return macio_register_driver(&bmac_driver);
1672 static void __exit bmac_exit(void)
1674 macio_unregister_driver(&bmac_driver);
1676 kfree(bmac_emergency_rxbuf);
1677 bmac_emergency_rxbuf = NULL;
1680 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1681 MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1682 MODULE_LICENSE("GPL");
1684 module_init(bmac_init);
1685 module_exit(bmac_exit);